1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 5 * Copyright (c) 2010 The FreeBSD Foundation 6 * Copyright (c) 2010-2015 Semihalf 7 * All rights reserved. 8 * 9 * Developed by Semihalf. 10 * 11 * Portions of this software were developed by Semihalf 12 * under sponsorship from the FreeBSD Foundation. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. Neither the name of MARVELL nor the names of contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Marvell integrated PCI/PCI-Express controller driver. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/malloc.h> 48 #include <sys/module.h> 49 #include <sys/mutex.h> 50 #include <sys/queue.h> 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <sys/endian.h> 54 #include <sys/devmap.h> 55 56 #include <machine/fdt.h> 57 #include <machine/intr.h> 58 59 #include <vm/vm.h> 60 #include <vm/pmap.h> 61 62 #include <dev/fdt/fdt_common.h> 63 #include <dev/ofw/ofw_bus.h> 64 #include <dev/ofw/ofw_bus_subr.h> 65 #include <dev/ofw/ofw_pci.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcib_private.h> 69 70 #include "ofw_bus_if.h" 71 #include "pcib_if.h" 72 73 #include <machine/resource.h> 74 #include <machine/bus.h> 75 76 #include <arm/mv/mvreg.h> 77 #include <arm/mv/mvvar.h> 78 #include <arm/mv/mvwin.h> 79 80 #ifdef DEBUG 81 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 82 #else 83 #define debugf(fmt, args...) 84 #endif 85 86 /* 87 * Code and data related to fdt-based PCI configuration. 88 * 89 * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was 90 * always Marvell-specific so that was deleted and the code now lives here. 91 */ 92 93 struct mv_pci_range { 94 u_long base_pci; 95 u_long base_parent; 96 u_long len; 97 }; 98 99 #define FDT_RANGES_CELLS ((3 + 3 + 2) * 2) 100 #define PCI_SPACE_LEN 0x00400000 101 102 static void 103 mv_pci_range_dump(struct mv_pci_range *range) 104 { 105 #ifdef DEBUG 106 printf("\n"); 107 printf(" base_pci = 0x%08lx\n", range->base_pci); 108 printf(" base_par = 0x%08lx\n", range->base_parent); 109 printf(" len = 0x%08lx\n", range->len); 110 #endif 111 } 112 113 static int 114 mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space, 115 struct mv_pci_range *mem_space) 116 { 117 pcell_t ranges[FDT_RANGES_CELLS]; 118 struct mv_pci_range *pci_space; 119 pcell_t addr_cells, size_cells, par_addr_cells; 120 pcell_t *rangesptr; 121 pcell_t cell0, cell2; 122 int tuple_size, tuples, i, rv, offset_cells, len; 123 int portid, is_io_space; 124 125 /* 126 * Retrieve 'ranges' property. 127 */ 128 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 129 return (EINVAL); 130 if (addr_cells != 3 || size_cells != 2) 131 return (ERANGE); 132 133 par_addr_cells = fdt_parent_addr_cells(node); 134 if (par_addr_cells > 3) 135 return (ERANGE); 136 137 len = OF_getproplen(node, "ranges"); 138 if (len > sizeof(ranges)) 139 return (ENOMEM); 140 141 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) 142 return (EINVAL); 143 144 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 145 size_cells); 146 tuples = len / tuple_size; 147 148 /* 149 * Initialize the ranges so that we don't have to worry about 150 * having them all defined in the FDT. In particular, it is 151 * perfectly fine not to want I/O space on PCI buses. 152 */ 153 bzero(io_space, sizeof(*io_space)); 154 bzero(mem_space, sizeof(*mem_space)); 155 156 rangesptr = &ranges[0]; 157 offset_cells = 0; 158 for (i = 0; i < tuples; i++) { 159 cell0 = fdt_data_get((void *)rangesptr, 1); 160 rangesptr++; 161 /* cell1 */ 162 rangesptr++; 163 cell2 = fdt_data_get((void *)rangesptr, 1); 164 rangesptr++; 165 portid = fdt_data_get((void *)(rangesptr+1), 1); 166 167 if (cell0 & 0x02000000) { 168 pci_space = mem_space; 169 is_io_space = 0; 170 } else if (cell0 & 0x01000000) { 171 pci_space = io_space; 172 is_io_space = 1; 173 } else { 174 rv = ERANGE; 175 goto out; 176 } 177 178 if (par_addr_cells == 3) { 179 /* 180 * This is a PCI subnode 'ranges'. Skip cell0 and 181 * cell1 of this entry and only use cell2. 182 */ 183 offset_cells = 2; 184 rangesptr += offset_cells; 185 } 186 187 if ((par_addr_cells - offset_cells) > 2) { 188 rv = ERANGE; 189 goto out; 190 } 191 pci_space->base_parent = fdt_data_get((void *)rangesptr, 192 par_addr_cells - offset_cells); 193 rangesptr += par_addr_cells - offset_cells; 194 195 if (size_cells > 2) { 196 rv = ERANGE; 197 goto out; 198 } 199 pci_space->len = fdt_data_get((void *)rangesptr, size_cells); 200 rangesptr += size_cells; 201 202 pci_space->base_pci = cell2; 203 204 if (pci_space->len == 0) { 205 pci_space->len = PCI_SPACE_LEN; 206 pci_space->base_parent = fdt_immr_va + 207 PCI_SPACE_LEN * ( 2 * portid + is_io_space); 208 } 209 } 210 rv = 0; 211 out: 212 return (rv); 213 } 214 215 static int 216 mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space, 217 struct mv_pci_range *mem_space) 218 { 219 int err; 220 221 debugf("Processing PCI node: %x\n", node); 222 if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) { 223 debugf("could not decode parent PCI node 'ranges'\n"); 224 return (err); 225 } 226 227 debugf("Post fixup dump:\n"); 228 mv_pci_range_dump(io_space); 229 mv_pci_range_dump(mem_space); 230 return (0); 231 } 232 233 int 234 mv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va, 235 vm_offset_t mem_va) 236 { 237 struct mv_pci_range io_space, mem_space; 238 int error; 239 240 if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0) 241 return (error); 242 243 devmap->pd_va = (io_va ? io_va : io_space.base_parent); 244 devmap->pd_pa = io_space.base_parent; 245 devmap->pd_size = io_space.len; 246 devmap++; 247 248 devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent); 249 devmap->pd_pa = mem_space.base_parent; 250 devmap->pd_size = mem_space.len; 251 return (0); 252 } 253 254 /* 255 * Code and data related to the Marvell pcib driver. 256 */ 257 258 #define PCI_CFG_ENA (1U << 31) 259 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 260 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 261 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 262 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 263 264 #define PCI_REG_CFG_ADDR 0x0C78 265 #define PCI_REG_CFG_DATA 0x0C7C 266 267 #define PCIE_REG_CFG_ADDR 0x18F8 268 #define PCIE_REG_CFG_DATA 0x18FC 269 #define PCIE_REG_CONTROL 0x1A00 270 #define PCIE_CTRL_LINK1X 0x00000001 271 #define PCIE_REG_STATUS 0x1A04 272 #define PCIE_REG_IRQ_MASK 0x1910 273 274 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1) 275 #define PCIE_CONTROL_HOT_RESET (1 << 24) 276 277 #define PCIE_LINK_TIMEOUT 1000000 278 279 #define PCIE_STATUS_LINK_DOWN 1 280 #define PCIE_STATUS_DEV_OFFS 16 281 282 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */ 283 #define PCI_MIN_IO_ALLOC 4 284 #define PCI_MIN_MEM_ALLOC 16 285 286 #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 287 288 struct mv_pcib_softc { 289 device_t sc_dev; 290 291 struct rman sc_mem_rman; 292 bus_addr_t sc_mem_base; 293 bus_addr_t sc_mem_size; 294 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE / 295 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 296 int sc_win_target; 297 int sc_mem_win_attr; 298 299 struct rman sc_io_rman; 300 bus_addr_t sc_io_base; 301 bus_addr_t sc_io_size; 302 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE / 303 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 304 int sc_io_win_attr; 305 306 struct resource *sc_res; 307 bus_space_handle_t sc_bsh; 308 bus_space_tag_t sc_bst; 309 int sc_rid; 310 311 struct mtx sc_msi_mtx; 312 uint32_t sc_msi_bitmap; 313 314 int sc_busnr; /* Host bridge bus number */ 315 int sc_devnr; /* Host bridge device number */ 316 int sc_type; 317 int sc_mode; /* Endpoint / Root Complex */ 318 319 int sc_msi_supported; 320 int sc_skip_enable_procedure; 321 int sc_enable_find_root_slot; 322 struct ofw_bus_iinfo sc_pci_iinfo; 323 324 int ap_segment; /* PCI domain */ 325 }; 326 327 /* Local forward prototypes */ 328 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 329 static void mv_pcib_hw_cfginit(void); 330 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 331 u_int, u_int, int); 332 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 333 u_int, u_int, uint32_t, int); 334 static int mv_pcib_init(struct mv_pcib_softc *, int, int); 335 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 336 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 337 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 338 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t); 339 static int mv_pcib_mem_init(struct mv_pcib_softc *); 340 341 /* Forward prototypes */ 342 static int mv_pcib_probe(device_t); 343 static int mv_pcib_attach(device_t); 344 345 static struct rman *mv_pcib_get_rman(device_t, int, u_int); 346 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 347 rman_res_t, rman_res_t, rman_res_t, u_int); 348 static int mv_pcib_adjust_resource(device_t, device_t, int, struct resource *, 349 rman_res_t, rman_res_t); 350 static int mv_pcib_release_resource(device_t, device_t, int, int, 351 struct resource *); 352 static int mv_pcib_activate_resource(device_t, device_t, int, int, 353 struct resource *r); 354 static int mv_pcib_deactivate_resource(device_t, device_t, int, int, 355 struct resource *r); 356 static int mv_pcib_map_resource(device_t, device_t, int, struct resource *, 357 struct resource_map_request *, struct resource_map *); 358 static int mv_pcib_unmap_resource(device_t, device_t, int, struct resource *, 359 struct resource_map *); 360 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 361 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 362 363 static int mv_pcib_maxslots(device_t); 364 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 365 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 366 uint32_t, int); 367 static int mv_pcib_route_interrupt(device_t, device_t, int); 368 369 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *); 370 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 371 static int mv_pcib_release_msi(device_t, device_t, int, int *); 372 373 /* 374 * Bus interface definitions. 375 */ 376 static device_method_t mv_pcib_methods[] = { 377 /* Device interface */ 378 DEVMETHOD(device_probe, mv_pcib_probe), 379 DEVMETHOD(device_attach, mv_pcib_attach), 380 381 /* Bus interface */ 382 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 383 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 384 DEVMETHOD(bus_get_rman, mv_pcib_get_rman), 385 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 386 DEVMETHOD(bus_adjust_resource, mv_pcib_adjust_resource), 387 DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 388 DEVMETHOD(bus_activate_resource, mv_pcib_activate_resource), 389 DEVMETHOD(bus_deactivate_resource, mv_pcib_deactivate_resource), 390 DEVMETHOD(bus_map_resource, mv_pcib_map_resource), 391 DEVMETHOD(bus_unmap_resource, mv_pcib_unmap_resource), 392 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 393 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 394 395 /* pcib interface */ 396 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 397 DEVMETHOD(pcib_read_config, mv_pcib_read_config), 398 DEVMETHOD(pcib_write_config, mv_pcib_write_config), 399 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 400 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 401 402 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi), 403 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi), 404 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi), 405 406 /* OFW bus interface */ 407 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 408 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 409 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 410 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 411 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 412 413 DEVMETHOD_END 414 }; 415 416 static driver_t mv_pcib_driver = { 417 "pcib", 418 mv_pcib_methods, 419 sizeof(struct mv_pcib_softc), 420 }; 421 422 DRIVER_MODULE(mv_pcib, ofwbus, mv_pcib_driver, 0, 0); 423 DRIVER_MODULE(mv_pcib, pcib_ctrl, mv_pcib_driver, 0, 0); 424 425 static struct mtx pcicfg_mtx; 426 427 static int 428 mv_pcib_probe(device_t self) 429 { 430 phandle_t node; 431 432 node = ofw_bus_get_node(self); 433 if (!mv_fdt_is_type(node, "pci")) 434 return (ENXIO); 435 436 if (!(ofw_bus_is_compatible(self, "mrvl,pcie") || 437 ofw_bus_is_compatible(self, "mrvl,pci") || 438 ofw_bus_node_is_compatible( 439 OF_parent(node), "marvell,armada-370-pcie"))) 440 return (ENXIO); 441 442 if (!ofw_bus_status_okay(self)) 443 return (ENXIO); 444 445 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 446 return (BUS_PROBE_DEFAULT); 447 } 448 449 static int 450 mv_pcib_attach(device_t self) 451 { 452 struct mv_pcib_softc *sc; 453 phandle_t node, parnode; 454 uint32_t val, reg0; 455 int err, bus, devfn, port_id; 456 457 sc = device_get_softc(self); 458 sc->sc_dev = self; 459 460 node = ofw_bus_get_node(self); 461 parnode = OF_parent(node); 462 463 if (OF_getencprop(node, "marvell,pcie-port", &(port_id), 464 sizeof(port_id)) <= 0) { 465 /* If port ID does not exist in the FDT set value to 0 */ 466 if (!OF_hasprop(node, "marvell,pcie-port")) 467 port_id = 0; 468 else 469 return(ENXIO); 470 } 471 472 sc->ap_segment = port_id; 473 474 if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) { 475 sc->sc_type = MV_TYPE_PCIE; 476 sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id); 477 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id); 478 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id); 479 sc->sc_skip_enable_procedure = 1; 480 } else if (ofw_bus_node_is_compatible(parnode, "marvell,armada-370-pcie")) { 481 sc->sc_type = MV_TYPE_PCIE; 482 sc->sc_win_target = MV_WIN_PCIE_TARGET_ARMADA38X(port_id); 483 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR_ARMADA38X(port_id); 484 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR_ARMADA38X(port_id); 485 sc->sc_enable_find_root_slot = 1; 486 } else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) { 487 sc->sc_type = MV_TYPE_PCI; 488 sc->sc_win_target = MV_WIN_PCI_TARGET; 489 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 490 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 491 } else 492 return (ENXIO); 493 494 /* 495 * Retrieve our mem-mapped registers range. 496 */ 497 sc->sc_rid = 0; 498 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 499 RF_ACTIVE); 500 if (sc->sc_res == NULL) { 501 device_printf(self, "could not map memory\n"); 502 return (ENXIO); 503 } 504 sc->sc_bst = rman_get_bustag(sc->sc_res); 505 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 506 507 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); 508 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : 509 MV_MODE_ENDPOINT); 510 511 /* 512 * Get PCI interrupt info. 513 */ 514 if (sc->sc_mode == MV_MODE_ROOT) 515 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t)); 516 517 /* 518 * Configure decode windows for PCI(E) access. 519 */ 520 if (mv_pcib_decode_win(node, sc) != 0) 521 return (ENXIO); 522 523 mv_pcib_hw_cfginit(); 524 525 /* 526 * Enable PCIE device. 527 */ 528 mv_pcib_enable(sc, port_id); 529 530 /* 531 * Memory management. 532 */ 533 err = mv_pcib_mem_init(sc); 534 if (err) 535 return (err); 536 537 /* 538 * Preliminary bus enumeration to find first linked devices and set 539 * appropriate bus number from which should start the actual enumeration 540 */ 541 for (bus = 0; bus < PCI_BUSMAX; bus++) { 542 for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) { 543 reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4); 544 if (reg0 == (~0U)) 545 continue; /* no device */ 546 else { 547 sc->sc_busnr = bus; /* update bus number */ 548 break; 549 } 550 } 551 } 552 553 if (sc->sc_mode == MV_MODE_ROOT) { 554 err = mv_pcib_init(sc, sc->sc_busnr, 555 mv_pcib_maxslots(sc->sc_dev)); 556 if (err) 557 goto error; 558 559 device_add_child(self, "pci", -1); 560 } else { 561 sc->sc_devnr = 1; 562 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 563 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS); 564 device_add_child(self, "pci_ep", -1); 565 } 566 567 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); 568 return (bus_generic_attach(self)); 569 570 error: 571 /* XXX SYS_RES_ should be released here */ 572 rman_fini(&sc->sc_mem_rman); 573 rman_fini(&sc->sc_io_rman); 574 575 return (err); 576 } 577 578 static void 579 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit) 580 { 581 uint32_t val; 582 int timeout; 583 584 if (sc->sc_skip_enable_procedure) 585 goto pcib_enable_root_mode; 586 587 /* 588 * Check if PCIE device is enabled. 589 */ 590 if ((sc->sc_skip_enable_procedure == 0) && 591 (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit))) { 592 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) & 593 ~(CPU_CONTROL_PCIE_DISABLE(unit))); 594 595 timeout = PCIE_LINK_TIMEOUT; 596 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 597 PCIE_REG_STATUS); 598 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) { 599 DELAY(1000); 600 timeout -= 1000; 601 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 602 PCIE_REG_STATUS); 603 } 604 } 605 606 pcib_enable_root_mode: 607 if (sc->sc_mode == MV_MODE_ROOT) { 608 /* 609 * Enable PCI bridge. 610 */ 611 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); 612 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | 613 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 614 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); 615 } 616 } 617 618 static int 619 mv_pcib_mem_init(struct mv_pcib_softc *sc) 620 { 621 int err; 622 623 /* 624 * Memory management. 625 */ 626 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 627 err = rman_init(&sc->sc_mem_rman); 628 if (err) 629 return (err); 630 631 sc->sc_io_rman.rm_type = RMAN_ARRAY; 632 err = rman_init(&sc->sc_io_rman); 633 if (err) { 634 rman_fini(&sc->sc_mem_rman); 635 return (err); 636 } 637 638 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 639 sc->sc_mem_base + sc->sc_mem_size - 1); 640 if (err) 641 goto error; 642 643 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 644 sc->sc_io_base + sc->sc_io_size - 1); 645 if (err) 646 goto error; 647 648 return (0); 649 650 error: 651 rman_fini(&sc->sc_mem_rman); 652 rman_fini(&sc->sc_io_rman); 653 654 return (err); 655 } 656 657 static inline uint32_t 658 pcib_bit_get(uint32_t *map, uint32_t bit) 659 { 660 uint32_t n = bit / BITS_PER_UINT32; 661 662 bit = bit % BITS_PER_UINT32; 663 return (map[n] & (1 << bit)); 664 } 665 666 static inline void 667 pcib_bit_set(uint32_t *map, uint32_t bit) 668 { 669 uint32_t n = bit / BITS_PER_UINT32; 670 671 bit = bit % BITS_PER_UINT32; 672 map[n] |= (1 << bit); 673 } 674 675 static inline uint32_t 676 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits) 677 { 678 uint32_t i; 679 680 for (i = start; i < start + bits; i++) 681 if (pcib_bit_get(map, i)) 682 return (0); 683 684 return (1); 685 } 686 687 static inline void 688 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits) 689 { 690 uint32_t i; 691 692 for (i = start; i < start + bits; i++) 693 pcib_bit_set(map, i); 694 } 695 696 /* 697 * The idea of this allocator is taken from ARM No-Cache memory 698 * management code (sys/arm/arm/vm_machdep.c). 699 */ 700 static bus_addr_t 701 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask) 702 { 703 uint32_t bits, bits_limit, i, *map, min_alloc, size; 704 bus_addr_t addr = 0; 705 bus_addr_t base; 706 707 if (smask & 1) { 708 base = sc->sc_io_base; 709 min_alloc = PCI_MIN_IO_ALLOC; 710 bits_limit = sc->sc_io_size / min_alloc; 711 map = sc->sc_io_map; 712 smask &= ~0x3; 713 } else { 714 base = sc->sc_mem_base; 715 min_alloc = PCI_MIN_MEM_ALLOC; 716 bits_limit = sc->sc_mem_size / min_alloc; 717 map = sc->sc_mem_map; 718 smask &= ~0xF; 719 } 720 721 size = ~smask + 1; 722 bits = size / min_alloc; 723 724 for (i = 0; i + bits <= bits_limit; i += bits) 725 if (pcib_map_check(map, i, bits)) { 726 pcib_map_set(map, i, bits); 727 addr = base + (i * min_alloc); 728 return (addr); 729 } 730 731 return (addr); 732 } 733 734 static int 735 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 736 int barno) 737 { 738 uint32_t addr, bar; 739 int reg, width; 740 741 reg = PCIR_BAR(barno); 742 743 /* 744 * Need to init the BAR register with 0xffffffff before correct 745 * value can be read. 746 */ 747 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 748 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 749 if (bar == 0) 750 return (1); 751 752 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 753 width = ((bar & 7) == 4) ? 2 : 1; 754 755 addr = pcib_alloc(sc, bar); 756 if (!addr) 757 return (-1); 758 759 if (bootverbose) 760 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", 761 bus, slot, func, reg, bar, addr); 762 763 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 764 if (width == 2) 765 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 766 0, 4); 767 768 return (width); 769 } 770 771 static void 772 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 773 { 774 bus_addr_t io_base, mem_base; 775 uint32_t io_limit, mem_limit; 776 int secbus; 777 778 io_base = sc->sc_io_base; 779 io_limit = io_base + sc->sc_io_size - 1; 780 mem_base = sc->sc_mem_base; 781 mem_limit = mem_base + sc->sc_mem_size - 1; 782 783 /* Configure I/O decode registers */ 784 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 785 io_base >> 8, 1); 786 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 787 io_base >> 16, 2); 788 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 789 io_limit >> 8, 1); 790 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 791 io_limit >> 16, 2); 792 793 /* Configure memory decode registers */ 794 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 795 mem_base >> 16, 2); 796 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 797 mem_limit >> 16, 2); 798 799 /* Disable memory prefetch decode */ 800 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 801 0x10, 2); 802 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 803 0x0, 4); 804 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 805 0xF, 2); 806 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 807 0x0, 4); 808 809 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 810 PCIR_SECBUS_1, 1); 811 812 /* Configure buses behind the bridge */ 813 mv_pcib_init(sc, secbus, PCI_SLOTMAX); 814 } 815 816 static int 817 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 818 { 819 int slot, func, maxfunc, error; 820 uint8_t hdrtype, command, class, subclass; 821 822 for (slot = 0; slot <= maxslot; slot++) { 823 maxfunc = 0; 824 for (func = 0; func <= maxfunc; func++) { 825 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 826 func, PCIR_HDRTYPE, 1); 827 828 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 829 continue; 830 831 if (func == 0 && (hdrtype & PCIM_MFDEV)) 832 maxfunc = PCI_FUNCMAX; 833 834 command = mv_pcib_read_config(sc->sc_dev, bus, slot, 835 func, PCIR_COMMAND, 1); 836 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 837 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 838 PCIR_COMMAND, command, 1); 839 840 error = mv_pcib_init_all_bars(sc, bus, slot, func, 841 hdrtype); 842 843 if (error) 844 return (error); 845 846 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 847 PCIM_CMD_PORTEN; 848 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 849 PCIR_COMMAND, command, 1); 850 851 /* Handle PCI-PCI bridges */ 852 class = mv_pcib_read_config(sc->sc_dev, bus, slot, 853 func, PCIR_CLASS, 1); 854 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 855 func, PCIR_SUBCLASS, 1); 856 857 if (class != PCIC_BRIDGE || 858 subclass != PCIS_BRIDGE_PCI) 859 continue; 860 861 mv_pcib_init_bridge(sc, bus, slot, func); 862 } 863 } 864 865 /* Enable all ABCD interrupts */ 866 pcib_write_irq_mask(sc, (0xF << 24)); 867 868 return (0); 869 } 870 871 static int 872 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 873 int func, int hdrtype) 874 { 875 int maxbar, bar, i; 876 877 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 878 bar = 0; 879 880 /* Program the base address registers */ 881 while (bar < maxbar) { 882 i = mv_pcib_init_bar(sc, bus, slot, func, bar); 883 bar += i; 884 if (i < 0) { 885 device_printf(sc->sc_dev, 886 "PCI IO/Memory space exhausted\n"); 887 return (ENOMEM); 888 } 889 } 890 891 return (0); 892 } 893 894 static struct rman * 895 mv_pcib_get_rman(device_t dev, int type, u_int flags) 896 { 897 struct mv_pcib_softc *sc = device_get_softc(dev); 898 899 switch (type) { 900 case SYS_RES_IOPORT: 901 return (&sc->sc_io_rman); 902 case SYS_RES_MEMORY: 903 return (&sc->sc_mem_rman); 904 default: 905 return (NULL); 906 } 907 } 908 909 static struct resource * 910 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 911 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 912 { 913 struct mv_pcib_softc *sc = device_get_softc(dev); 914 915 switch (type) { 916 case SYS_RES_IOPORT: 917 case SYS_RES_MEMORY: 918 break; 919 #ifdef PCI_RES_BUS 920 case PCI_RES_BUS: 921 return (pci_domain_alloc_bus(sc->ap_segment, child, rid, start, 922 end, count, flags)); 923 #endif 924 default: 925 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 926 type, rid, start, end, count, flags)); 927 } 928 929 if (RMAN_IS_DEFAULT_RANGE(start, end)) { 930 start = sc->sc_mem_base; 931 end = sc->sc_mem_base + sc->sc_mem_size - 1; 932 count = sc->sc_mem_size; 933 } 934 935 if ((start < sc->sc_mem_base) || (start + count - 1 != end) || 936 (end > sc->sc_mem_base + sc->sc_mem_size - 1)) 937 return (NULL); 938 939 return (bus_generic_rman_alloc_resource(dev, child, type, rid, 940 start, end, count, flags)); 941 } 942 943 static int 944 mv_pcib_adjust_resource(device_t dev, device_t child, int type, 945 struct resource *r, rman_res_t start, rman_res_t end) 946 { 947 #ifdef PCI_RES_BUS 948 struct mv_pcib_softc *sc = device_get_softc(dev); 949 #endif 950 951 switch (type) { 952 case SYS_RES_IOPORT: 953 case SYS_RES_MEMORY: 954 return (bus_generic_rman_adjust_resource(dev, child, type, r, 955 start, end)); 956 #ifdef PCI_RES_BUS 957 case PCI_RES_BUS: 958 return (pci_domain_adjust_bus(sc->ap_segment, child, r, start, 959 end)); 960 #endif 961 default: 962 return (bus_generic_adjust_resource(dev, child, type, r, 963 start, end)); 964 } 965 } 966 967 static int 968 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid, 969 struct resource *res) 970 { 971 #ifdef PCI_RES_BUS 972 struct mv_pcib_softc *sc = device_get_softc(dev); 973 #endif 974 975 switch (type) { 976 case SYS_RES_IOPORT: 977 case SYS_RES_MEMORY: 978 return (bus_generic_rman_release_resource(dev, child, type, 979 rid, res)); 980 #ifdef PCI_RES_BUS 981 case PCI_RES_BUS: 982 return (pci_domain_release_bus(sc->ap_segment, child, rid, res)); 983 #endif 984 default: 985 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 986 type, rid, res)); 987 } 988 } 989 990 static int 991 mv_pcib_activate_resource(device_t dev, device_t child, int type, int rid, 992 struct resource *r) 993 { 994 #ifdef PCI_RES_BUS 995 struct mv_pcib_softc *sc = device_get_softc(dev); 996 #endif 997 998 switch (type) { 999 case SYS_RES_IOPORT: 1000 case SYS_RES_MEMORY: 1001 return (bus_generic_rman_activate_resource(dev, child, type, 1002 rid, r)); 1003 #ifdef PCI_RES_BUS 1004 case PCI_RES_BUS: 1005 return (pci_domain_activate_bus(sc->ap_segment, child, rid, r)); 1006 #endif 1007 default: 1008 return (bus_generic_activate_resource(dev, child, type, rid, 1009 r)); 1010 } 1011 } 1012 1013 static int 1014 mv_pcib_deactivate_resource(device_t dev, device_t child, int type, int rid, 1015 struct resource *r) 1016 { 1017 #ifdef PCI_RES_BUS 1018 struct mv_pcib_softc *sc = device_get_softc(dev); 1019 #endif 1020 1021 switch (type) { 1022 case SYS_RES_IOPORT: 1023 case SYS_RES_MEMORY: 1024 return (bus_generic_rman_deactivate_resource(dev, child, type, 1025 rid, r)); 1026 #ifdef PCI_RES_BUS 1027 case PCI_RES_BUS: 1028 return (pci_domain_deactivate_bus(sc->ap_segment, child, rid, 1029 r)); 1030 #endif 1031 default: 1032 return (bus_generic_deactivate_resource(dev, child, type, rid, 1033 r)); 1034 } 1035 } 1036 1037 static int 1038 mv_pcib_map_resource(device_t dev, device_t child, int type, struct resource *r, 1039 struct resource_map_request *argsp, struct resource_map *map) 1040 { 1041 struct resource_map_request args; 1042 rman_res_t length, start; 1043 int error; 1044 1045 /* Resources must be active to be mapped. */ 1046 if (!(rman_get_flags(r) & RF_ACTIVE)) 1047 return (ENXIO); 1048 1049 /* Mappings are only supported on I/O and memory resources. */ 1050 switch (type) { 1051 case SYS_RES_IOPORT: 1052 case SYS_RES_MEMORY: 1053 break; 1054 default: 1055 return (EINVAL); 1056 } 1057 1058 resource_init_map_request(&args); 1059 error = resource_validate_map_request(r, argsp, &args, &start, &length); 1060 if (error) 1061 return (error); 1062 1063 map->r_bustag = fdtbus_bs_tag; 1064 map->r_bushandle = start; 1065 map->r_size = length; 1066 return (0); 1067 } 1068 1069 static int 1070 mv_pcib_unmap_resource(device_t dev, device_t child, int type, 1071 struct resource *r, struct resource_map *map) 1072 { 1073 switch (type) { 1074 case SYS_RES_IOPORT: 1075 case SYS_RES_MEMORY: 1076 return (0); 1077 default: 1078 return (EINVAL); 1079 } 1080 } 1081 1082 static int 1083 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1084 { 1085 struct mv_pcib_softc *sc = device_get_softc(dev); 1086 1087 switch (which) { 1088 case PCIB_IVAR_BUS: 1089 *result = sc->sc_busnr; 1090 return (0); 1091 case PCIB_IVAR_DOMAIN: 1092 *result = device_get_unit(dev); 1093 return (0); 1094 } 1095 1096 return (ENOENT); 1097 } 1098 1099 static int 1100 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1101 { 1102 struct mv_pcib_softc *sc = device_get_softc(dev); 1103 1104 switch (which) { 1105 case PCIB_IVAR_BUS: 1106 sc->sc_busnr = value; 1107 return (0); 1108 } 1109 1110 return (ENOENT); 1111 } 1112 1113 static inline void 1114 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 1115 { 1116 1117 if (sc->sc_type != MV_TYPE_PCIE) 1118 return; 1119 1120 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 1121 } 1122 1123 static void 1124 mv_pcib_hw_cfginit(void) 1125 { 1126 static int opened = 0; 1127 1128 if (opened) 1129 return; 1130 1131 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 1132 opened = 1; 1133 } 1134 1135 static uint32_t 1136 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 1137 u_int func, u_int reg, int bytes) 1138 { 1139 uint32_t addr, data, ca, cd; 1140 1141 ca = (sc->sc_type != MV_TYPE_PCI) ? 1142 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 1143 cd = (sc->sc_type != MV_TYPE_PCI) ? 1144 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 1145 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 1146 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 1147 1148 mtx_lock_spin(&pcicfg_mtx); 1149 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 1150 1151 data = ~0; 1152 switch (bytes) { 1153 case 1: 1154 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 1155 cd + (reg & 3)); 1156 break; 1157 case 2: 1158 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 1159 cd + (reg & 2))); 1160 break; 1161 case 4: 1162 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 1163 cd)); 1164 break; 1165 } 1166 mtx_unlock_spin(&pcicfg_mtx); 1167 return (data); 1168 } 1169 1170 static void 1171 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 1172 u_int func, u_int reg, uint32_t data, int bytes) 1173 { 1174 uint32_t addr, ca, cd; 1175 1176 ca = (sc->sc_type != MV_TYPE_PCI) ? 1177 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 1178 cd = (sc->sc_type != MV_TYPE_PCI) ? 1179 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 1180 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 1181 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 1182 1183 mtx_lock_spin(&pcicfg_mtx); 1184 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 1185 1186 switch (bytes) { 1187 case 1: 1188 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1189 cd + (reg & 3), data); 1190 break; 1191 case 2: 1192 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 1193 cd + (reg & 2), htole16(data)); 1194 break; 1195 case 4: 1196 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 1197 cd, htole32(data)); 1198 break; 1199 } 1200 mtx_unlock_spin(&pcicfg_mtx); 1201 } 1202 1203 static int 1204 mv_pcib_maxslots(device_t dev) 1205 { 1206 struct mv_pcib_softc *sc = device_get_softc(dev); 1207 1208 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 1209 } 1210 1211 static int 1212 mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func) 1213 { 1214 struct mv_pcib_softc *sc = device_get_softc(dev); 1215 uint32_t vendor, device; 1216 1217 /* On platforms other than Armada38x, root link is always at slot 0 */ 1218 if (!sc->sc_enable_find_root_slot) 1219 return (slot == 0); 1220 1221 vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR, 1222 PCIR_VENDOR_LENGTH); 1223 device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE, 1224 PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK; 1225 1226 return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X); 1227 } 1228 1229 static uint32_t 1230 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 1231 u_int reg, int bytes) 1232 { 1233 struct mv_pcib_softc *sc = device_get_softc(dev); 1234 1235 /* Return ~0 if link is inactive or trying to read from Root */ 1236 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1237 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1238 return (~0U); 1239 1240 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 1241 } 1242 1243 static void 1244 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1245 u_int reg, uint32_t val, int bytes) 1246 { 1247 struct mv_pcib_softc *sc = device_get_softc(dev); 1248 1249 /* Return if link is inactive or trying to write to Root */ 1250 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1251 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1252 return; 1253 1254 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 1255 } 1256 1257 static int 1258 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin) 1259 { 1260 struct mv_pcib_softc *sc; 1261 struct ofw_pci_register reg; 1262 uint32_t pintr, mintr[4]; 1263 int icells; 1264 phandle_t iparent; 1265 1266 sc = device_get_softc(bus); 1267 pintr = pin; 1268 1269 /* Fabricate imap information in case this isn't an OFW device */ 1270 bzero(®, sizeof(reg)); 1271 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 1272 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 1273 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 1274 1275 icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1276 ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr), 1277 &iparent); 1278 if (icells > 0) 1279 return (ofw_bus_map_intr(dev, iparent, icells, mintr)); 1280 1281 /* Maybe it's a real interrupt, not an intpin */ 1282 if (pin > 4) 1283 return (pin); 1284 1285 device_printf(bus, "could not route pin %d for device %d.%d\n", 1286 pin, pci_get_slot(dev), pci_get_function(dev)); 1287 return (PCI_INVALID_IRQ); 1288 } 1289 1290 static int 1291 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 1292 { 1293 struct mv_pci_range io_space, mem_space; 1294 device_t dev; 1295 int error; 1296 1297 dev = sc->sc_dev; 1298 1299 if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) { 1300 device_printf(dev, "could not retrieve 'ranges' data\n"); 1301 return (error); 1302 } 1303 1304 /* Configure CPU decoding windows */ 1305 error = decode_win_cpu_set(sc->sc_win_target, 1306 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); 1307 if (error < 0) { 1308 device_printf(dev, "could not set up CPU decode " 1309 "window for PCI IO\n"); 1310 return (ENXIO); 1311 } 1312 error = decode_win_cpu_set(sc->sc_win_target, 1313 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, 1314 mem_space.base_parent); 1315 if (error < 0) { 1316 device_printf(dev, "could not set up CPU decode " 1317 "windows for PCI MEM\n"); 1318 return (ENXIO); 1319 } 1320 1321 sc->sc_io_base = io_space.base_parent; 1322 sc->sc_io_size = io_space.len; 1323 1324 sc->sc_mem_base = mem_space.base_parent; 1325 sc->sc_mem_size = mem_space.len; 1326 1327 return (0); 1328 } 1329 1330 static int 1331 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 1332 uint32_t *data) 1333 { 1334 struct mv_pcib_softc *sc; 1335 1336 sc = device_get_softc(dev); 1337 if (!sc->sc_msi_supported) 1338 return (ENOTSUP); 1339 1340 irq = irq - MSI_IRQ; 1341 1342 /* validate parameters */ 1343 if (isclr(&sc->sc_msi_bitmap, irq)) { 1344 device_printf(dev, "invalid MSI 0x%x\n", irq); 1345 return (EINVAL); 1346 } 1347 1348 mv_msi_data(irq, addr, data); 1349 1350 debugf("%s: irq: %d addr: %jx data: %x\n", 1351 __func__, irq, *addr, *data); 1352 1353 return (0); 1354 } 1355 1356 static int 1357 mv_pcib_alloc_msi(device_t dev, device_t child, int count, 1358 int maxcount __unused, int *irqs) 1359 { 1360 struct mv_pcib_softc *sc; 1361 u_int start = 0, i; 1362 1363 sc = device_get_softc(dev); 1364 if (!sc->sc_msi_supported) 1365 return (ENOTSUP); 1366 1367 if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 1368 return (EINVAL); 1369 1370 mtx_lock(&sc->sc_msi_mtx); 1371 1372 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 1373 for (i = start; i < start + count; i++) { 1374 if (isset(&sc->sc_msi_bitmap, i)) 1375 break; 1376 } 1377 if (i == start + count) 1378 break; 1379 } 1380 1381 if ((start + count) == MSI_IRQ_NUM) { 1382 mtx_unlock(&sc->sc_msi_mtx); 1383 return (ENXIO); 1384 } 1385 1386 for (i = start; i < start + count; i++) { 1387 setbit(&sc->sc_msi_bitmap, i); 1388 *irqs++ = MSI_IRQ + i; 1389 } 1390 debugf("%s: start: %x count: %x\n", __func__, start, count); 1391 1392 mtx_unlock(&sc->sc_msi_mtx); 1393 return (0); 1394 } 1395 1396 static int 1397 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 1398 { 1399 struct mv_pcib_softc *sc; 1400 u_int i; 1401 1402 sc = device_get_softc(dev); 1403 if(!sc->sc_msi_supported) 1404 return (ENOTSUP); 1405 1406 mtx_lock(&sc->sc_msi_mtx); 1407 1408 for (i = 0; i < count; i++) 1409 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); 1410 1411 mtx_unlock(&sc->sc_msi_mtx); 1412 return (0); 1413 } 1414