1 /*- 2 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 3 * Copyright (c) 2010 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Developed by Semihalf. 7 * 8 * Portions of this software were developed by Semihalf 9 * under sponsorship from the FreeBSD Foundation. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of MARVELL nor the names of contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 /* 37 * Marvell integrated PCI/PCI-Express controller driver. 38 */ 39 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD$"); 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/malloc.h> 48 #include <sys/module.h> 49 #include <sys/mutex.h> 50 #include <sys/queue.h> 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <sys/endian.h> 54 55 #include <vm/vm.h> 56 #include <vm/pmap.h> 57 58 #include <dev/fdt/fdt_common.h> 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcib_private.h> 64 65 #include "ofw_bus_if.h" 66 #include "pcib_if.h" 67 68 #include <machine/resource.h> 69 #include <machine/bus.h> 70 71 #include <arm/mv/mvreg.h> 72 #include <arm/mv/mvvar.h> 73 #include <arm/mv/mvwin.h> 74 75 #define PCI_CFG_ENA (1 << 31) 76 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 77 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 78 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 79 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 80 81 #define PCI_REG_CFG_ADDR 0x0C78 82 #define PCI_REG_CFG_DATA 0x0C7C 83 #define PCI_REG_P2P_CONF 0x1D14 84 85 #define PCIE_REG_CFG_ADDR 0x18F8 86 #define PCIE_REG_CFG_DATA 0x18FC 87 #define PCIE_REG_CONTROL 0x1A00 88 #define PCIE_CTRL_LINK1X 0x00000001 89 #define PCIE_REG_STATUS 0x1A04 90 #define PCIE_REG_IRQ_MASK 0x1910 91 92 #define STATUS_LINK_DOWN 1 93 #define STATUS_BUS_OFFS 8 94 #define STATUS_BUS_MASK (0xFF << STATUS_BUS_OFFS) 95 #define STATUS_DEV_OFFS 16 96 #define STATUS_DEV_MASK (0x1F << STATUS_DEV_OFFS) 97 98 #define P2P_CONF_BUS_OFFS 16 99 #define P2P_CONF_BUS_MASK (0xFF << P2P_CONF_BUS_OFFS) 100 #define P2P_CONF_DEV_OFFS 24 101 #define P2P_CONF_DEV_MASK (0x1F << P2P_CONF_DEV_OFFS) 102 103 #define PCI_VENDORID_MRVL 0x11AB 104 105 struct mv_pcib_softc { 106 device_t sc_dev; 107 108 struct rman sc_mem_rman; 109 bus_addr_t sc_mem_base; 110 bus_addr_t sc_mem_size; 111 bus_addr_t sc_mem_alloc; /* Next allocation. */ 112 int sc_mem_win_target; 113 int sc_mem_win_attr; 114 115 struct rman sc_io_rman; 116 bus_addr_t sc_io_base; 117 bus_addr_t sc_io_size; 118 bus_addr_t sc_io_alloc; /* Next allocation. */ 119 int sc_io_win_target; 120 int sc_io_win_attr; 121 122 struct resource *sc_res; 123 bus_space_handle_t sc_bsh; 124 bus_space_tag_t sc_bst; 125 int sc_rid; 126 127 int sc_busnr; /* Host bridge bus number */ 128 int sc_devnr; /* Host bridge device number */ 129 int sc_type; 130 131 struct fdt_pci_intr sc_intr_info; 132 }; 133 134 /* Local forward prototypes */ 135 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 136 static void mv_pcib_hw_cfginit(void); 137 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 138 u_int, u_int, int); 139 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 140 u_int, u_int, uint32_t, int); 141 static int mv_pcib_init(struct mv_pcib_softc *, int, int); 142 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 143 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 144 static int mv_pcib_intr_info(phandle_t, struct mv_pcib_softc *); 145 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 146 147 148 /* Forward prototypes */ 149 static int mv_pcib_probe(device_t); 150 static int mv_pcib_attach(device_t); 151 152 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 153 u_long, u_long, u_long, u_int); 154 static int mv_pcib_release_resource(device_t, device_t, int, int, 155 struct resource *); 156 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 157 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 158 159 static int mv_pcib_maxslots(device_t); 160 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 161 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 162 uint32_t, int); 163 static int mv_pcib_route_interrupt(device_t, device_t, int); 164 165 /* 166 * Bus interface definitions. 167 */ 168 static device_method_t mv_pcib_methods[] = { 169 /* Device interface */ 170 DEVMETHOD(device_probe, mv_pcib_probe), 171 DEVMETHOD(device_attach, mv_pcib_attach), 172 173 /* Bus interface */ 174 DEVMETHOD(bus_print_child, bus_generic_print_child), 175 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 176 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 177 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 178 DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 179 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 180 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 181 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 182 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 183 184 /* pcib interface */ 185 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 186 DEVMETHOD(pcib_read_config, mv_pcib_read_config), 187 DEVMETHOD(pcib_write_config, mv_pcib_write_config), 188 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 189 190 /* OFW bus interface */ 191 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 192 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 193 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 194 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 195 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 196 197 { 0, 0 } 198 }; 199 200 static driver_t mv_pcib_driver = { 201 "pcib", 202 mv_pcib_methods, 203 sizeof(struct mv_pcib_softc), 204 }; 205 206 devclass_t pcib_devclass; 207 208 DRIVER_MODULE(pcib, fdtbus, mv_pcib_driver, pcib_devclass, 0, 0); 209 210 static struct mtx pcicfg_mtx; 211 212 static int 213 mv_pcib_probe(device_t self) 214 { 215 phandle_t parnode; 216 217 /* 218 * The PCI subnode does not have the 'compatible' property, so we need 219 * to check in the parent PCI node. However the parent is not 220 * represented by a separate ofw_bus child, and therefore 221 * ofw_bus_is_compatible() cannot be used, but direct fdt equivalent. 222 */ 223 parnode = OF_parent(ofw_bus_get_node(self)); 224 if (parnode == 0) 225 return (ENXIO); 226 if (!(fdt_is_compatible(parnode, "mrvl,pcie") || 227 fdt_is_compatible(parnode, "mrvl,pci"))) 228 return (ENXIO); 229 230 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 231 232 return (BUS_PROBE_DEFAULT); 233 } 234 235 static int 236 mv_pcib_attach(device_t self) 237 { 238 struct mv_pcib_softc *sc; 239 phandle_t node, parnode; 240 uint32_t val; 241 int err; 242 243 sc = device_get_softc(self); 244 sc->sc_dev = self; 245 246 parnode = OF_parent(ofw_bus_get_node(self)); 247 if (fdt_is_compatible(parnode, "mrvl,pcie")) { 248 sc->sc_type = MV_TYPE_PCIE; 249 sc->sc_mem_win_target = MV_WIN_PCIE_MEM_TARGET; 250 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR; 251 sc->sc_io_win_target = MV_WIN_PCIE_IO_TARGET; 252 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR; 253 #ifdef SOC_MV_ORION 254 } else if (fdt_is_compatible(parnode, "mrvl,pci")) { 255 sc->sc_type = MV_TYPE_PCI; 256 sc->sc_mem_win_target = MV_WIN_PCI_MEM_TARGET; 257 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 258 sc->sc_io_win_target = MV_WIN_PCI_IO_TARGET; 259 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 260 #endif 261 } else 262 return (ENXIO); 263 264 node = ofw_bus_get_node(self); 265 266 /* 267 * Get PCI interrupt info. 268 */ 269 if (mv_pcib_intr_info(node, sc) != 0) { 270 device_printf(self, "could not retrieve interrupt info\n"); 271 return (ENXIO); 272 } 273 274 /* 275 * Retrieve our mem-mapped registers range. 276 */ 277 sc->sc_rid = 0; 278 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 279 RF_ACTIVE); 280 if (sc->sc_res == NULL) { 281 device_printf(self, "could not map memory\n"); 282 return (ENXIO); 283 } 284 sc->sc_bst = rman_get_bustag(sc->sc_res); 285 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 286 287 /* 288 * Configure decode windows for PCI(E) access. 289 */ 290 if (mv_pcib_decode_win(node, sc) != 0) 291 return (ENXIO); 292 293 mv_pcib_hw_cfginit(); 294 295 /* 296 * Enable PCI bridge. 297 */ 298 val = mv_pcib_hw_cfgread(sc, sc->sc_busnr, sc->sc_devnr, 0, 299 PCIR_COMMAND, 2); 300 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 301 PCIM_CMD_PORTEN; 302 mv_pcib_hw_cfgwrite(sc, sc->sc_busnr, sc->sc_devnr, 0, 303 PCIR_COMMAND, val, 2); 304 305 sc->sc_mem_alloc = sc->sc_mem_base; 306 sc->sc_io_alloc = sc->sc_io_base; 307 308 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 309 err = rman_init(&sc->sc_mem_rman); 310 if (err) 311 return (err); 312 313 sc->sc_io_rman.rm_type = RMAN_ARRAY; 314 err = rman_init(&sc->sc_io_rman); 315 if (err) { 316 rman_fini(&sc->sc_mem_rman); 317 return (err); 318 } 319 320 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 321 sc->sc_mem_base + sc->sc_mem_size - 1); 322 if (err) 323 goto error; 324 325 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 326 sc->sc_io_base + sc->sc_io_size - 1); 327 if (err) 328 goto error; 329 330 err = mv_pcib_init(sc, sc->sc_busnr, mv_pcib_maxslots(sc->sc_dev)); 331 if (err) 332 goto error; 333 334 device_add_child(self, "pci", -1); 335 return (bus_generic_attach(self)); 336 337 error: 338 /* XXX SYS_RES_ should be released here */ 339 rman_fini(&sc->sc_mem_rman); 340 rman_fini(&sc->sc_io_rman); 341 return (err); 342 } 343 344 static int 345 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 346 int barno) 347 { 348 bus_addr_t *allocp, limit; 349 uint32_t addr, bar, mask, size; 350 int reg, width; 351 352 reg = PCIR_BAR(barno); 353 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 354 if (bar == 0) 355 return (1); 356 357 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 358 width = ((bar & 7) == 4) ? 2 : 1; 359 360 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 361 size = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 362 363 /* Get BAR type and size */ 364 if (bar & 1) { 365 /* I/O port */ 366 allocp = &sc->sc_io_alloc; 367 limit = sc->sc_io_base + sc->sc_io_size; 368 size &= ~0x3; 369 if ((size & 0xffff0000) == 0) 370 size |= 0xffff0000; 371 } else { 372 /* Memory */ 373 allocp = &sc->sc_mem_alloc; 374 limit = sc->sc_mem_base + sc->sc_mem_size; 375 size &= ~0xF; 376 } 377 mask = ~size; 378 size = mask + 1; 379 380 /* Sanity check (must be a power of 2) */ 381 if (size & mask) 382 return (width); 383 384 addr = (*allocp + mask) & ~mask; 385 if ((*allocp = addr + size) > limit) 386 return (-1); 387 388 if (bootverbose) 389 printf("PCI %u:%u:%u: reg %x: size=%08x: addr=%08x\n", 390 bus, slot, func, reg, size, addr); 391 392 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 393 if (width == 2) 394 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 395 0, 4); 396 397 return (width); 398 } 399 400 static void 401 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 402 { 403 bus_addr_t io_base, mem_base; 404 uint32_t io_limit, mem_limit; 405 int secbus; 406 407 io_base = sc->sc_io_base; 408 io_limit = io_base + sc->sc_io_size - 1; 409 mem_base = sc->sc_mem_base; 410 mem_limit = mem_base + sc->sc_mem_size - 1; 411 412 /* Configure I/O decode registers */ 413 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 414 io_base >> 8, 1); 415 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 416 io_base >> 16, 2); 417 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 418 io_limit >> 8, 1); 419 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 420 io_limit >> 16, 2); 421 422 /* Configure memory decode registers */ 423 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 424 mem_base >> 16, 2); 425 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 426 mem_limit >> 16, 2); 427 428 /* Disable memory prefetch decode */ 429 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 430 0x10, 2); 431 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 432 0x0, 4); 433 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 434 0xF, 2); 435 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 436 0x0, 4); 437 438 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 439 PCIR_SECBUS_1, 1); 440 441 /* Configure buses behind the bridge */ 442 mv_pcib_init(sc, secbus, PCI_SLOTMAX); 443 } 444 445 static int 446 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 447 { 448 int slot, func, maxfunc, error; 449 uint8_t hdrtype, command, class, subclass; 450 451 for (slot = 0; slot <= maxslot; slot++) { 452 maxfunc = 0; 453 for (func = 0; func <= maxfunc; func++) { 454 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 455 func, PCIR_HDRTYPE, 1); 456 457 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 458 continue; 459 460 if (func == 0 && (hdrtype & PCIM_MFDEV)) 461 maxfunc = PCI_FUNCMAX; 462 463 command = mv_pcib_read_config(sc->sc_dev, bus, slot, 464 func, PCIR_COMMAND, 1); 465 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 466 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 467 PCIR_COMMAND, command, 1); 468 469 error = mv_pcib_init_all_bars(sc, bus, slot, func, 470 hdrtype); 471 472 if (error) 473 return (error); 474 475 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 476 PCIM_CMD_PORTEN; 477 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 478 PCIR_COMMAND, command, 1); 479 480 /* Handle PCI-PCI bridges */ 481 class = mv_pcib_read_config(sc->sc_dev, bus, slot, 482 func, PCIR_CLASS, 1); 483 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 484 func, PCIR_SUBCLASS, 1); 485 486 if (class != PCIC_BRIDGE || 487 subclass != PCIS_BRIDGE_PCI) 488 continue; 489 490 mv_pcib_init_bridge(sc, bus, slot, func); 491 } 492 } 493 494 /* Enable all ABCD interrupts */ 495 pcib_write_irq_mask(sc, (0xF << 24)); 496 497 return (0); 498 } 499 500 static int 501 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 502 int func, int hdrtype) 503 { 504 int maxbar, bar, i; 505 506 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 507 bar = 0; 508 509 /* Program the base address registers */ 510 while (bar < maxbar) { 511 i = mv_pcib_init_bar(sc, bus, slot, func, bar); 512 bar += i; 513 if (i < 0) { 514 device_printf(sc->sc_dev, 515 "PCI IO/Memory space exhausted\n"); 516 return (ENOMEM); 517 } 518 } 519 520 return (0); 521 } 522 523 static struct resource * 524 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 525 u_long start, u_long end, u_long count, u_int flags) 526 { 527 struct mv_pcib_softc *sc = device_get_softc(dev); 528 struct rman *rm = NULL; 529 struct resource *res; 530 531 switch (type) { 532 case SYS_RES_IOPORT: 533 rm = &sc->sc_io_rman; 534 break; 535 case SYS_RES_MEMORY: 536 rm = &sc->sc_mem_rman; 537 break; 538 default: 539 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 540 type, rid, start, end, count, flags)); 541 }; 542 543 res = rman_reserve_resource(rm, start, end, count, flags, child); 544 if (res == NULL) 545 return (NULL); 546 547 rman_set_rid(res, *rid); 548 rman_set_bustag(res, fdtbus_bs_tag); 549 rman_set_bushandle(res, start); 550 551 if (flags & RF_ACTIVE) 552 if (bus_activate_resource(child, type, *rid, res)) { 553 rman_release_resource(res); 554 return (NULL); 555 } 556 557 return (res); 558 } 559 560 static int 561 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid, 562 struct resource *res) 563 { 564 565 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY) 566 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 567 type, rid, res)); 568 569 return (rman_release_resource(res)); 570 } 571 572 static int 573 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 574 { 575 struct mv_pcib_softc *sc = device_get_softc(dev); 576 577 switch (which) { 578 case PCIB_IVAR_BUS: 579 *result = sc->sc_busnr; 580 return (0); 581 case PCIB_IVAR_DOMAIN: 582 *result = device_get_unit(dev); 583 return (0); 584 } 585 586 return (ENOENT); 587 } 588 589 static int 590 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 591 { 592 struct mv_pcib_softc *sc = device_get_softc(dev); 593 594 switch (which) { 595 case PCIB_IVAR_BUS: 596 sc->sc_busnr = value; 597 return (0); 598 } 599 600 return (ENOENT); 601 } 602 603 static inline void 604 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 605 { 606 607 if (!sc->sc_type != MV_TYPE_PCI) 608 return; 609 610 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 611 } 612 613 static void 614 mv_pcib_hw_cfginit(void) 615 { 616 static int opened = 0; 617 618 if (opened) 619 return; 620 621 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 622 opened = 1; 623 } 624 625 static uint32_t 626 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 627 u_int func, u_int reg, int bytes) 628 { 629 uint32_t addr, data, ca, cd; 630 631 ca = (sc->sc_type != MV_TYPE_PCI) ? 632 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 633 cd = (sc->sc_type != MV_TYPE_PCI) ? 634 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 635 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 636 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 637 638 mtx_lock_spin(&pcicfg_mtx); 639 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 640 641 data = ~0; 642 switch (bytes) { 643 case 1: 644 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 645 cd + (reg & 3)); 646 break; 647 case 2: 648 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 649 cd + (reg & 2))); 650 break; 651 case 4: 652 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 653 cd)); 654 break; 655 } 656 mtx_unlock_spin(&pcicfg_mtx); 657 return (data); 658 } 659 660 static void 661 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 662 u_int func, u_int reg, uint32_t data, int bytes) 663 { 664 uint32_t addr, ca, cd; 665 666 ca = (sc->sc_type != MV_TYPE_PCI) ? 667 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 668 cd = (sc->sc_type != MV_TYPE_PCI) ? 669 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 670 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 671 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 672 673 mtx_lock_spin(&pcicfg_mtx); 674 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 675 676 switch (bytes) { 677 case 1: 678 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 679 cd + (reg & 3), data); 680 break; 681 case 2: 682 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 683 cd + (reg & 2), htole16(data)); 684 break; 685 case 4: 686 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 687 cd, htole32(data)); 688 break; 689 } 690 mtx_unlock_spin(&pcicfg_mtx); 691 } 692 693 static int 694 mv_pcib_maxslots(device_t dev) 695 { 696 struct mv_pcib_softc *sc = device_get_softc(dev); 697 698 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 699 } 700 701 static uint32_t 702 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 703 u_int reg, int bytes) 704 { 705 struct mv_pcib_softc *sc = device_get_softc(dev); 706 707 /* Skip self */ 708 if (bus == sc->sc_busnr && slot == sc->sc_devnr) 709 return (~0U); 710 711 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 712 } 713 714 static void 715 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 716 u_int reg, uint32_t val, int bytes) 717 { 718 struct mv_pcib_softc *sc = device_get_softc(dev); 719 720 /* Skip self */ 721 if (bus == sc->sc_busnr && slot == sc->sc_devnr) 722 return; 723 724 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 725 } 726 727 static int 728 mv_pcib_route_interrupt(device_t pcib, device_t dev, int pin) 729 { 730 struct mv_pcib_softc *sc; 731 int err, interrupt; 732 733 sc = device_get_softc(pcib); 734 735 err = fdt_pci_route_intr(pci_get_bus(dev), pci_get_slot(dev), 736 pci_get_function(dev), pin, &sc->sc_intr_info, &interrupt); 737 if (err == 0) 738 return (interrupt); 739 740 device_printf(pcib, "could not route pin %d for device %d.%d\n", 741 pin, pci_get_slot(dev), pci_get_function(dev)); 742 return (PCI_INVALID_IRQ); 743 } 744 745 static int 746 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 747 { 748 struct fdt_pci_range io_space, mem_space; 749 device_t dev; 750 int error; 751 752 dev = sc->sc_dev; 753 754 if ((error = fdt_pci_ranges(node, &io_space, &mem_space)) != 0) { 755 device_printf(dev, "could not retrieve 'ranges' data\n"); 756 return (error); 757 } 758 759 /* Configure CPU decoding windows */ 760 error = decode_win_cpu_set(sc->sc_io_win_target, 761 sc->sc_io_win_attr, io_space.base_parent, io_space.len, -1); 762 if (error < 0) { 763 device_printf(dev, "could not set up CPU decode " 764 "window for PCI IO\n"); 765 return (ENXIO); 766 } 767 error = decode_win_cpu_set(sc->sc_mem_win_target, 768 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, -1); 769 if (error < 0) { 770 device_printf(dev, "could not set up CPU decode " 771 "windows for PCI MEM\n"); 772 return (ENXIO); 773 } 774 775 sc->sc_io_base = io_space.base_parent; 776 sc->sc_io_size = io_space.len; 777 778 sc->sc_mem_base = mem_space.base_parent; 779 sc->sc_mem_size = mem_space.len; 780 781 return (0); 782 } 783 784 static int 785 mv_pcib_intr_info(phandle_t node, struct mv_pcib_softc *sc) 786 { 787 int error; 788 789 if ((error = fdt_pci_intr_info(node, &sc->sc_intr_info)) != 0) 790 return (error); 791 792 return (0); 793 } 794 795 #if 0 796 control = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 797 PCIE_REG_CONTROL); 798 799 /* 800 * If this PCI-E port (controller) is configured (by the 801 * underlying firmware) with lane width other than 1x, there 802 * are auxiliary resources defined for aggregating more width 803 * on our lane. Skip all such entries as they are not 804 * standalone ports and must not have a device object 805 * instantiated. 806 */ 807 if ((control & PCIE_CTRL_LINK1X) == 0) 808 while (info->op_base && 809 info->op_type == MV_TYPE_PCIE_AGGR_LANE) 810 info++; 811 812 mv_pcib_add_child(driver, parent, sc); 813 #endif 814