1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 5 * Copyright (c) 2010 The FreeBSD Foundation 6 * Copyright (c) 2010-2015 Semihalf 7 * All rights reserved. 8 * 9 * Developed by Semihalf. 10 * 11 * Portions of this software were developed by Semihalf 12 * under sponsorship from the FreeBSD Foundation. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. Neither the name of MARVELL nor the names of contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Marvell integrated PCI/PCI-Express controller driver. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/malloc.h> 48 #include <sys/module.h> 49 #include <sys/mutex.h> 50 #include <sys/queue.h> 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <sys/endian.h> 54 #include <sys/devmap.h> 55 56 #include <machine/fdt.h> 57 #include <machine/intr.h> 58 59 #include <vm/vm.h> 60 #include <vm/pmap.h> 61 62 #include <dev/fdt/fdt_common.h> 63 #include <dev/ofw/ofw_bus.h> 64 #include <dev/ofw/ofw_bus_subr.h> 65 #include <dev/ofw/ofw_pci.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcib_private.h> 69 70 #include "ofw_bus_if.h" 71 #include "pcib_if.h" 72 73 #include <machine/resource.h> 74 #include <machine/bus.h> 75 76 #include <arm/mv/mvreg.h> 77 #include <arm/mv/mvvar.h> 78 #include <arm/mv/mvwin.h> 79 80 #ifdef DEBUG 81 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 82 #else 83 #define debugf(fmt, args...) 84 #endif 85 86 /* 87 * Code and data related to fdt-based PCI configuration. 88 * 89 * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was 90 * always Marvell-specific so that was deleted and the code now lives here. 91 */ 92 93 struct mv_pci_range { 94 u_long base_pci; 95 u_long base_parent; 96 u_long len; 97 }; 98 99 #define FDT_RANGES_CELLS ((3 + 3 + 2) * 2) 100 #define PCI_SPACE_LEN 0x00400000 101 102 static void 103 mv_pci_range_dump(struct mv_pci_range *range) 104 { 105 #ifdef DEBUG 106 printf("\n"); 107 printf(" base_pci = 0x%08lx\n", range->base_pci); 108 printf(" base_par = 0x%08lx\n", range->base_parent); 109 printf(" len = 0x%08lx\n", range->len); 110 #endif 111 } 112 113 static int 114 mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space, 115 struct mv_pci_range *mem_space) 116 { 117 pcell_t ranges[FDT_RANGES_CELLS]; 118 struct mv_pci_range *pci_space; 119 pcell_t addr_cells, size_cells, par_addr_cells; 120 pcell_t *rangesptr; 121 pcell_t cell0, cell2; 122 int tuple_size, tuples, i, rv, offset_cells, len; 123 int portid, is_io_space; 124 125 /* 126 * Retrieve 'ranges' property. 127 */ 128 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 129 return (EINVAL); 130 if (addr_cells != 3 || size_cells != 2) 131 return (ERANGE); 132 133 par_addr_cells = fdt_parent_addr_cells(node); 134 if (par_addr_cells > 3) 135 return (ERANGE); 136 137 len = OF_getproplen(node, "ranges"); 138 if (len > sizeof(ranges)) 139 return (ENOMEM); 140 141 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) 142 return (EINVAL); 143 144 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 145 size_cells); 146 tuples = len / tuple_size; 147 148 /* 149 * Initialize the ranges so that we don't have to worry about 150 * having them all defined in the FDT. In particular, it is 151 * perfectly fine not to want I/O space on PCI buses. 152 */ 153 bzero(io_space, sizeof(*io_space)); 154 bzero(mem_space, sizeof(*mem_space)); 155 156 rangesptr = &ranges[0]; 157 offset_cells = 0; 158 for (i = 0; i < tuples; i++) { 159 cell0 = fdt_data_get((void *)rangesptr, 1); 160 rangesptr++; 161 /* cell1 */ 162 rangesptr++; 163 cell2 = fdt_data_get((void *)rangesptr, 1); 164 rangesptr++; 165 portid = fdt_data_get((void *)(rangesptr+1), 1); 166 167 if (cell0 & 0x02000000) { 168 pci_space = mem_space; 169 is_io_space = 0; 170 } else if (cell0 & 0x01000000) { 171 pci_space = io_space; 172 is_io_space = 1; 173 } else { 174 rv = ERANGE; 175 goto out; 176 } 177 178 if (par_addr_cells == 3) { 179 /* 180 * This is a PCI subnode 'ranges'. Skip cell0 and 181 * cell1 of this entry and only use cell2. 182 */ 183 offset_cells = 2; 184 rangesptr += offset_cells; 185 } 186 187 if ((par_addr_cells - offset_cells) > 2) { 188 rv = ERANGE; 189 goto out; 190 } 191 pci_space->base_parent = fdt_data_get((void *)rangesptr, 192 par_addr_cells - offset_cells); 193 rangesptr += par_addr_cells - offset_cells; 194 195 if (size_cells > 2) { 196 rv = ERANGE; 197 goto out; 198 } 199 pci_space->len = fdt_data_get((void *)rangesptr, size_cells); 200 rangesptr += size_cells; 201 202 pci_space->base_pci = cell2; 203 204 if (pci_space->len == 0) { 205 pci_space->len = PCI_SPACE_LEN; 206 pci_space->base_parent = fdt_immr_va + 207 PCI_SPACE_LEN * ( 2 * portid + is_io_space); 208 } 209 } 210 rv = 0; 211 out: 212 return (rv); 213 } 214 215 static int 216 mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space, 217 struct mv_pci_range *mem_space) 218 { 219 int err; 220 221 debugf("Processing PCI node: %x\n", node); 222 if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) { 223 debugf("could not decode parent PCI node 'ranges'\n"); 224 return (err); 225 } 226 227 debugf("Post fixup dump:\n"); 228 mv_pci_range_dump(io_space); 229 mv_pci_range_dump(mem_space); 230 return (0); 231 } 232 233 int 234 mv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va, 235 vm_offset_t mem_va) 236 { 237 struct mv_pci_range io_space, mem_space; 238 int error; 239 240 if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0) 241 return (error); 242 243 devmap->pd_va = (io_va ? io_va : io_space.base_parent); 244 devmap->pd_pa = io_space.base_parent; 245 devmap->pd_size = io_space.len; 246 devmap++; 247 248 devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent); 249 devmap->pd_pa = mem_space.base_parent; 250 devmap->pd_size = mem_space.len; 251 return (0); 252 } 253 254 /* 255 * Code and data related to the Marvell pcib driver. 256 */ 257 258 #define PCI_CFG_ENA (1U << 31) 259 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 260 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 261 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 262 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 263 264 #define PCI_REG_CFG_ADDR 0x0C78 265 #define PCI_REG_CFG_DATA 0x0C7C 266 267 #define PCIE_REG_CFG_ADDR 0x18F8 268 #define PCIE_REG_CFG_DATA 0x18FC 269 #define PCIE_REG_CONTROL 0x1A00 270 #define PCIE_CTRL_LINK1X 0x00000001 271 #define PCIE_REG_STATUS 0x1A04 272 #define PCIE_REG_IRQ_MASK 0x1910 273 274 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1) 275 #define PCIE_CONTROL_HOT_RESET (1 << 24) 276 277 #define PCIE_LINK_TIMEOUT 1000000 278 279 #define PCIE_STATUS_LINK_DOWN 1 280 #define PCIE_STATUS_DEV_OFFS 16 281 282 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */ 283 #define PCI_MIN_IO_ALLOC 4 284 #define PCI_MIN_MEM_ALLOC 16 285 286 #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 287 288 struct mv_pcib_softc { 289 device_t sc_dev; 290 291 struct rman sc_mem_rman; 292 bus_addr_t sc_mem_base; 293 bus_addr_t sc_mem_size; 294 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE / 295 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 296 int sc_win_target; 297 int sc_mem_win_attr; 298 299 struct rman sc_io_rman; 300 bus_addr_t sc_io_base; 301 bus_addr_t sc_io_size; 302 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE / 303 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 304 int sc_io_win_attr; 305 306 struct resource *sc_res; 307 bus_space_handle_t sc_bsh; 308 bus_space_tag_t sc_bst; 309 int sc_rid; 310 311 struct mtx sc_msi_mtx; 312 uint32_t sc_msi_bitmap; 313 314 int sc_busnr; /* Host bridge bus number */ 315 int sc_devnr; /* Host bridge device number */ 316 int sc_type; 317 int sc_mode; /* Endpoint / Root Complex */ 318 319 int sc_msi_supported; 320 int sc_skip_enable_procedure; 321 int sc_enable_find_root_slot; 322 struct ofw_bus_iinfo sc_pci_iinfo; 323 324 int ap_segment; /* PCI domain */ 325 }; 326 327 /* Local forward prototypes */ 328 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 329 static void mv_pcib_hw_cfginit(void); 330 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 331 u_int, u_int, int); 332 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 333 u_int, u_int, uint32_t, int); 334 static int mv_pcib_init(struct mv_pcib_softc *, int, int); 335 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 336 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 337 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 338 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t); 339 static int mv_pcib_mem_init(struct mv_pcib_softc *); 340 341 /* Forward prototypes */ 342 static int mv_pcib_probe(device_t); 343 static int mv_pcib_attach(device_t); 344 345 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 346 rman_res_t, rman_res_t, rman_res_t, u_int); 347 static int mv_pcib_release_resource(device_t, device_t, int, int, 348 struct resource *); 349 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 350 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 351 352 static int mv_pcib_maxslots(device_t); 353 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 354 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 355 uint32_t, int); 356 static int mv_pcib_route_interrupt(device_t, device_t, int); 357 358 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *); 359 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 360 static int mv_pcib_release_msi(device_t, device_t, int, int *); 361 362 /* 363 * Bus interface definitions. 364 */ 365 static device_method_t mv_pcib_methods[] = { 366 /* Device interface */ 367 DEVMETHOD(device_probe, mv_pcib_probe), 368 DEVMETHOD(device_attach, mv_pcib_attach), 369 370 /* Bus interface */ 371 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 372 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 373 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 374 DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 375 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 376 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 377 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 378 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 379 380 /* pcib interface */ 381 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 382 DEVMETHOD(pcib_read_config, mv_pcib_read_config), 383 DEVMETHOD(pcib_write_config, mv_pcib_write_config), 384 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 385 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 386 387 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi), 388 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi), 389 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi), 390 391 /* OFW bus interface */ 392 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 393 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 394 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 395 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 396 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 397 398 DEVMETHOD_END 399 }; 400 401 static driver_t mv_pcib_driver = { 402 "pcib", 403 mv_pcib_methods, 404 sizeof(struct mv_pcib_softc), 405 }; 406 407 DRIVER_MODULE(mv_pcib, ofwbus, mv_pcib_driver, 0, 0); 408 DRIVER_MODULE(mv_pcib, pcib_ctrl, mv_pcib_driver, 0, 0); 409 410 static struct mtx pcicfg_mtx; 411 412 static int 413 mv_pcib_probe(device_t self) 414 { 415 phandle_t node; 416 417 node = ofw_bus_get_node(self); 418 if (!mv_fdt_is_type(node, "pci")) 419 return (ENXIO); 420 421 if (!(ofw_bus_is_compatible(self, "mrvl,pcie") || 422 ofw_bus_is_compatible(self, "mrvl,pci") || 423 ofw_bus_node_is_compatible( 424 OF_parent(node), "marvell,armada-370-pcie"))) 425 return (ENXIO); 426 427 if (!ofw_bus_status_okay(self)) 428 return (ENXIO); 429 430 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 431 return (BUS_PROBE_DEFAULT); 432 } 433 434 static int 435 mv_pcib_attach(device_t self) 436 { 437 struct mv_pcib_softc *sc; 438 phandle_t node, parnode; 439 uint32_t val, reg0; 440 int err, bus, devfn, port_id; 441 442 sc = device_get_softc(self); 443 sc->sc_dev = self; 444 445 node = ofw_bus_get_node(self); 446 parnode = OF_parent(node); 447 448 if (OF_getencprop(node, "marvell,pcie-port", &(port_id), 449 sizeof(port_id)) <= 0) { 450 /* If port ID does not exist in the FDT set value to 0 */ 451 if (!OF_hasprop(node, "marvell,pcie-port")) 452 port_id = 0; 453 else 454 return(ENXIO); 455 } 456 457 sc->ap_segment = port_id; 458 459 if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) { 460 sc->sc_type = MV_TYPE_PCIE; 461 sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id); 462 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id); 463 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id); 464 sc->sc_skip_enable_procedure = 1; 465 } else if (ofw_bus_node_is_compatible(parnode, "marvell,armada-370-pcie")) { 466 sc->sc_type = MV_TYPE_PCIE; 467 sc->sc_win_target = MV_WIN_PCIE_TARGET_ARMADA38X(port_id); 468 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR_ARMADA38X(port_id); 469 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR_ARMADA38X(port_id); 470 sc->sc_enable_find_root_slot = 1; 471 } else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) { 472 sc->sc_type = MV_TYPE_PCI; 473 sc->sc_win_target = MV_WIN_PCI_TARGET; 474 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 475 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 476 } else 477 return (ENXIO); 478 479 /* 480 * Retrieve our mem-mapped registers range. 481 */ 482 sc->sc_rid = 0; 483 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 484 RF_ACTIVE); 485 if (sc->sc_res == NULL) { 486 device_printf(self, "could not map memory\n"); 487 return (ENXIO); 488 } 489 sc->sc_bst = rman_get_bustag(sc->sc_res); 490 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 491 492 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); 493 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : 494 MV_MODE_ENDPOINT); 495 496 /* 497 * Get PCI interrupt info. 498 */ 499 if (sc->sc_mode == MV_MODE_ROOT) 500 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t)); 501 502 /* 503 * Configure decode windows for PCI(E) access. 504 */ 505 if (mv_pcib_decode_win(node, sc) != 0) 506 return (ENXIO); 507 508 mv_pcib_hw_cfginit(); 509 510 /* 511 * Enable PCIE device. 512 */ 513 mv_pcib_enable(sc, port_id); 514 515 /* 516 * Memory management. 517 */ 518 err = mv_pcib_mem_init(sc); 519 if (err) 520 return (err); 521 522 /* 523 * Preliminary bus enumeration to find first linked devices and set 524 * appropriate bus number from which should start the actual enumeration 525 */ 526 for (bus = 0; bus < PCI_BUSMAX; bus++) { 527 for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) { 528 reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4); 529 if (reg0 == (~0U)) 530 continue; /* no device */ 531 else { 532 sc->sc_busnr = bus; /* update bus number */ 533 break; 534 } 535 } 536 } 537 538 if (sc->sc_mode == MV_MODE_ROOT) { 539 err = mv_pcib_init(sc, sc->sc_busnr, 540 mv_pcib_maxslots(sc->sc_dev)); 541 if (err) 542 goto error; 543 544 device_add_child(self, "pci", -1); 545 } else { 546 sc->sc_devnr = 1; 547 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 548 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS); 549 device_add_child(self, "pci_ep", -1); 550 } 551 552 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); 553 return (bus_generic_attach(self)); 554 555 error: 556 /* XXX SYS_RES_ should be released here */ 557 rman_fini(&sc->sc_mem_rman); 558 rman_fini(&sc->sc_io_rman); 559 560 return (err); 561 } 562 563 static void 564 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit) 565 { 566 uint32_t val; 567 int timeout; 568 569 if (sc->sc_skip_enable_procedure) 570 goto pcib_enable_root_mode; 571 572 /* 573 * Check if PCIE device is enabled. 574 */ 575 if ((sc->sc_skip_enable_procedure == 0) && 576 (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit))) { 577 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) & 578 ~(CPU_CONTROL_PCIE_DISABLE(unit))); 579 580 timeout = PCIE_LINK_TIMEOUT; 581 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 582 PCIE_REG_STATUS); 583 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) { 584 DELAY(1000); 585 timeout -= 1000; 586 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 587 PCIE_REG_STATUS); 588 } 589 } 590 591 pcib_enable_root_mode: 592 if (sc->sc_mode == MV_MODE_ROOT) { 593 /* 594 * Enable PCI bridge. 595 */ 596 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); 597 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | 598 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 599 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); 600 } 601 } 602 603 static int 604 mv_pcib_mem_init(struct mv_pcib_softc *sc) 605 { 606 int err; 607 608 /* 609 * Memory management. 610 */ 611 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 612 err = rman_init(&sc->sc_mem_rman); 613 if (err) 614 return (err); 615 616 sc->sc_io_rman.rm_type = RMAN_ARRAY; 617 err = rman_init(&sc->sc_io_rman); 618 if (err) { 619 rman_fini(&sc->sc_mem_rman); 620 return (err); 621 } 622 623 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 624 sc->sc_mem_base + sc->sc_mem_size - 1); 625 if (err) 626 goto error; 627 628 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 629 sc->sc_io_base + sc->sc_io_size - 1); 630 if (err) 631 goto error; 632 633 return (0); 634 635 error: 636 rman_fini(&sc->sc_mem_rman); 637 rman_fini(&sc->sc_io_rman); 638 639 return (err); 640 } 641 642 static inline uint32_t 643 pcib_bit_get(uint32_t *map, uint32_t bit) 644 { 645 uint32_t n = bit / BITS_PER_UINT32; 646 647 bit = bit % BITS_PER_UINT32; 648 return (map[n] & (1 << bit)); 649 } 650 651 static inline void 652 pcib_bit_set(uint32_t *map, uint32_t bit) 653 { 654 uint32_t n = bit / BITS_PER_UINT32; 655 656 bit = bit % BITS_PER_UINT32; 657 map[n] |= (1 << bit); 658 } 659 660 static inline uint32_t 661 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits) 662 { 663 uint32_t i; 664 665 for (i = start; i < start + bits; i++) 666 if (pcib_bit_get(map, i)) 667 return (0); 668 669 return (1); 670 } 671 672 static inline void 673 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits) 674 { 675 uint32_t i; 676 677 for (i = start; i < start + bits; i++) 678 pcib_bit_set(map, i); 679 } 680 681 /* 682 * The idea of this allocator is taken from ARM No-Cache memory 683 * management code (sys/arm/arm/vm_machdep.c). 684 */ 685 static bus_addr_t 686 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask) 687 { 688 uint32_t bits, bits_limit, i, *map, min_alloc, size; 689 bus_addr_t addr = 0; 690 bus_addr_t base; 691 692 if (smask & 1) { 693 base = sc->sc_io_base; 694 min_alloc = PCI_MIN_IO_ALLOC; 695 bits_limit = sc->sc_io_size / min_alloc; 696 map = sc->sc_io_map; 697 smask &= ~0x3; 698 } else { 699 base = sc->sc_mem_base; 700 min_alloc = PCI_MIN_MEM_ALLOC; 701 bits_limit = sc->sc_mem_size / min_alloc; 702 map = sc->sc_mem_map; 703 smask &= ~0xF; 704 } 705 706 size = ~smask + 1; 707 bits = size / min_alloc; 708 709 for (i = 0; i + bits <= bits_limit; i += bits) 710 if (pcib_map_check(map, i, bits)) { 711 pcib_map_set(map, i, bits); 712 addr = base + (i * min_alloc); 713 return (addr); 714 } 715 716 return (addr); 717 } 718 719 static int 720 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 721 int barno) 722 { 723 uint32_t addr, bar; 724 int reg, width; 725 726 reg = PCIR_BAR(barno); 727 728 /* 729 * Need to init the BAR register with 0xffffffff before correct 730 * value can be read. 731 */ 732 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 733 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 734 if (bar == 0) 735 return (1); 736 737 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 738 width = ((bar & 7) == 4) ? 2 : 1; 739 740 addr = pcib_alloc(sc, bar); 741 if (!addr) 742 return (-1); 743 744 if (bootverbose) 745 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", 746 bus, slot, func, reg, bar, addr); 747 748 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 749 if (width == 2) 750 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 751 0, 4); 752 753 return (width); 754 } 755 756 static void 757 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 758 { 759 bus_addr_t io_base, mem_base; 760 uint32_t io_limit, mem_limit; 761 int secbus; 762 763 io_base = sc->sc_io_base; 764 io_limit = io_base + sc->sc_io_size - 1; 765 mem_base = sc->sc_mem_base; 766 mem_limit = mem_base + sc->sc_mem_size - 1; 767 768 /* Configure I/O decode registers */ 769 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 770 io_base >> 8, 1); 771 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 772 io_base >> 16, 2); 773 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 774 io_limit >> 8, 1); 775 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 776 io_limit >> 16, 2); 777 778 /* Configure memory decode registers */ 779 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 780 mem_base >> 16, 2); 781 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 782 mem_limit >> 16, 2); 783 784 /* Disable memory prefetch decode */ 785 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 786 0x10, 2); 787 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 788 0x0, 4); 789 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 790 0xF, 2); 791 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 792 0x0, 4); 793 794 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 795 PCIR_SECBUS_1, 1); 796 797 /* Configure buses behind the bridge */ 798 mv_pcib_init(sc, secbus, PCI_SLOTMAX); 799 } 800 801 static int 802 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 803 { 804 int slot, func, maxfunc, error; 805 uint8_t hdrtype, command, class, subclass; 806 807 for (slot = 0; slot <= maxslot; slot++) { 808 maxfunc = 0; 809 for (func = 0; func <= maxfunc; func++) { 810 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 811 func, PCIR_HDRTYPE, 1); 812 813 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 814 continue; 815 816 if (func == 0 && (hdrtype & PCIM_MFDEV)) 817 maxfunc = PCI_FUNCMAX; 818 819 command = mv_pcib_read_config(sc->sc_dev, bus, slot, 820 func, PCIR_COMMAND, 1); 821 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 822 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 823 PCIR_COMMAND, command, 1); 824 825 error = mv_pcib_init_all_bars(sc, bus, slot, func, 826 hdrtype); 827 828 if (error) 829 return (error); 830 831 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 832 PCIM_CMD_PORTEN; 833 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 834 PCIR_COMMAND, command, 1); 835 836 /* Handle PCI-PCI bridges */ 837 class = mv_pcib_read_config(sc->sc_dev, bus, slot, 838 func, PCIR_CLASS, 1); 839 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 840 func, PCIR_SUBCLASS, 1); 841 842 if (class != PCIC_BRIDGE || 843 subclass != PCIS_BRIDGE_PCI) 844 continue; 845 846 mv_pcib_init_bridge(sc, bus, slot, func); 847 } 848 } 849 850 /* Enable all ABCD interrupts */ 851 pcib_write_irq_mask(sc, (0xF << 24)); 852 853 return (0); 854 } 855 856 static int 857 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 858 int func, int hdrtype) 859 { 860 int maxbar, bar, i; 861 862 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 863 bar = 0; 864 865 /* Program the base address registers */ 866 while (bar < maxbar) { 867 i = mv_pcib_init_bar(sc, bus, slot, func, bar); 868 bar += i; 869 if (i < 0) { 870 device_printf(sc->sc_dev, 871 "PCI IO/Memory space exhausted\n"); 872 return (ENOMEM); 873 } 874 } 875 876 return (0); 877 } 878 879 static struct resource * 880 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 881 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 882 { 883 struct mv_pcib_softc *sc = device_get_softc(dev); 884 struct rman *rm = NULL; 885 struct resource *res; 886 887 switch (type) { 888 case SYS_RES_IOPORT: 889 rm = &sc->sc_io_rman; 890 break; 891 case SYS_RES_MEMORY: 892 rm = &sc->sc_mem_rman; 893 break; 894 #ifdef PCI_RES_BUS 895 case PCI_RES_BUS: 896 return (pci_domain_alloc_bus(sc->ap_segment, child, rid, start, 897 end, count, flags)); 898 #endif 899 default: 900 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 901 type, rid, start, end, count, flags)); 902 } 903 904 if (RMAN_IS_DEFAULT_RANGE(start, end)) { 905 start = sc->sc_mem_base; 906 end = sc->sc_mem_base + sc->sc_mem_size - 1; 907 count = sc->sc_mem_size; 908 } 909 910 if ((start < sc->sc_mem_base) || (start + count - 1 != end) || 911 (end > sc->sc_mem_base + sc->sc_mem_size - 1)) 912 return (NULL); 913 914 res = rman_reserve_resource(rm, start, end, count, flags, child); 915 if (res == NULL) 916 return (NULL); 917 918 rman_set_rid(res, *rid); 919 rman_set_bustag(res, fdtbus_bs_tag); 920 rman_set_bushandle(res, start); 921 922 if (flags & RF_ACTIVE) 923 if (bus_activate_resource(child, type, *rid, res)) { 924 rman_release_resource(res); 925 return (NULL); 926 } 927 928 return (res); 929 } 930 931 static int 932 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid, 933 struct resource *res) 934 { 935 #ifdef PCI_RES_BUS 936 struct mv_pcib_softc *sc = device_get_softc(dev); 937 938 if (type == PCI_RES_BUS) 939 return (pci_domain_release_bus(sc->ap_segment, child, rid, res)); 940 #endif 941 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY) 942 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 943 type, rid, res)); 944 945 return (rman_release_resource(res)); 946 } 947 948 static int 949 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 950 { 951 struct mv_pcib_softc *sc = device_get_softc(dev); 952 953 switch (which) { 954 case PCIB_IVAR_BUS: 955 *result = sc->sc_busnr; 956 return (0); 957 case PCIB_IVAR_DOMAIN: 958 *result = device_get_unit(dev); 959 return (0); 960 } 961 962 return (ENOENT); 963 } 964 965 static int 966 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 967 { 968 struct mv_pcib_softc *sc = device_get_softc(dev); 969 970 switch (which) { 971 case PCIB_IVAR_BUS: 972 sc->sc_busnr = value; 973 return (0); 974 } 975 976 return (ENOENT); 977 } 978 979 static inline void 980 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 981 { 982 983 if (sc->sc_type != MV_TYPE_PCIE) 984 return; 985 986 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 987 } 988 989 static void 990 mv_pcib_hw_cfginit(void) 991 { 992 static int opened = 0; 993 994 if (opened) 995 return; 996 997 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 998 opened = 1; 999 } 1000 1001 static uint32_t 1002 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 1003 u_int func, u_int reg, int bytes) 1004 { 1005 uint32_t addr, data, ca, cd; 1006 1007 ca = (sc->sc_type != MV_TYPE_PCI) ? 1008 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 1009 cd = (sc->sc_type != MV_TYPE_PCI) ? 1010 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 1011 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 1012 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 1013 1014 mtx_lock_spin(&pcicfg_mtx); 1015 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 1016 1017 data = ~0; 1018 switch (bytes) { 1019 case 1: 1020 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 1021 cd + (reg & 3)); 1022 break; 1023 case 2: 1024 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 1025 cd + (reg & 2))); 1026 break; 1027 case 4: 1028 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 1029 cd)); 1030 break; 1031 } 1032 mtx_unlock_spin(&pcicfg_mtx); 1033 return (data); 1034 } 1035 1036 static void 1037 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 1038 u_int func, u_int reg, uint32_t data, int bytes) 1039 { 1040 uint32_t addr, ca, cd; 1041 1042 ca = (sc->sc_type != MV_TYPE_PCI) ? 1043 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 1044 cd = (sc->sc_type != MV_TYPE_PCI) ? 1045 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 1046 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 1047 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 1048 1049 mtx_lock_spin(&pcicfg_mtx); 1050 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 1051 1052 switch (bytes) { 1053 case 1: 1054 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1055 cd + (reg & 3), data); 1056 break; 1057 case 2: 1058 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 1059 cd + (reg & 2), htole16(data)); 1060 break; 1061 case 4: 1062 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 1063 cd, htole32(data)); 1064 break; 1065 } 1066 mtx_unlock_spin(&pcicfg_mtx); 1067 } 1068 1069 static int 1070 mv_pcib_maxslots(device_t dev) 1071 { 1072 struct mv_pcib_softc *sc = device_get_softc(dev); 1073 1074 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 1075 } 1076 1077 static int 1078 mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func) 1079 { 1080 struct mv_pcib_softc *sc = device_get_softc(dev); 1081 uint32_t vendor, device; 1082 1083 /* On platforms other than Armada38x, root link is always at slot 0 */ 1084 if (!sc->sc_enable_find_root_slot) 1085 return (slot == 0); 1086 1087 vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR, 1088 PCIR_VENDOR_LENGTH); 1089 device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE, 1090 PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK; 1091 1092 return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X); 1093 } 1094 1095 static uint32_t 1096 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 1097 u_int reg, int bytes) 1098 { 1099 struct mv_pcib_softc *sc = device_get_softc(dev); 1100 1101 /* Return ~0 if link is inactive or trying to read from Root */ 1102 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1103 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1104 return (~0U); 1105 1106 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 1107 } 1108 1109 static void 1110 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1111 u_int reg, uint32_t val, int bytes) 1112 { 1113 struct mv_pcib_softc *sc = device_get_softc(dev); 1114 1115 /* Return if link is inactive or trying to write to Root */ 1116 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1117 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1118 return; 1119 1120 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 1121 } 1122 1123 static int 1124 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin) 1125 { 1126 struct mv_pcib_softc *sc; 1127 struct ofw_pci_register reg; 1128 uint32_t pintr, mintr[4]; 1129 int icells; 1130 phandle_t iparent; 1131 1132 sc = device_get_softc(bus); 1133 pintr = pin; 1134 1135 /* Fabricate imap information in case this isn't an OFW device */ 1136 bzero(®, sizeof(reg)); 1137 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 1138 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 1139 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 1140 1141 icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1142 ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr), 1143 &iparent); 1144 if (icells > 0) 1145 return (ofw_bus_map_intr(dev, iparent, icells, mintr)); 1146 1147 /* Maybe it's a real interrupt, not an intpin */ 1148 if (pin > 4) 1149 return (pin); 1150 1151 device_printf(bus, "could not route pin %d for device %d.%d\n", 1152 pin, pci_get_slot(dev), pci_get_function(dev)); 1153 return (PCI_INVALID_IRQ); 1154 } 1155 1156 static int 1157 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 1158 { 1159 struct mv_pci_range io_space, mem_space; 1160 device_t dev; 1161 int error; 1162 1163 dev = sc->sc_dev; 1164 1165 if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) { 1166 device_printf(dev, "could not retrieve 'ranges' data\n"); 1167 return (error); 1168 } 1169 1170 /* Configure CPU decoding windows */ 1171 error = decode_win_cpu_set(sc->sc_win_target, 1172 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); 1173 if (error < 0) { 1174 device_printf(dev, "could not set up CPU decode " 1175 "window for PCI IO\n"); 1176 return (ENXIO); 1177 } 1178 error = decode_win_cpu_set(sc->sc_win_target, 1179 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, 1180 mem_space.base_parent); 1181 if (error < 0) { 1182 device_printf(dev, "could not set up CPU decode " 1183 "windows for PCI MEM\n"); 1184 return (ENXIO); 1185 } 1186 1187 sc->sc_io_base = io_space.base_parent; 1188 sc->sc_io_size = io_space.len; 1189 1190 sc->sc_mem_base = mem_space.base_parent; 1191 sc->sc_mem_size = mem_space.len; 1192 1193 return (0); 1194 } 1195 1196 static int 1197 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 1198 uint32_t *data) 1199 { 1200 struct mv_pcib_softc *sc; 1201 1202 sc = device_get_softc(dev); 1203 if (!sc->sc_msi_supported) 1204 return (ENOTSUP); 1205 1206 irq = irq - MSI_IRQ; 1207 1208 /* validate parameters */ 1209 if (isclr(&sc->sc_msi_bitmap, irq)) { 1210 device_printf(dev, "invalid MSI 0x%x\n", irq); 1211 return (EINVAL); 1212 } 1213 1214 mv_msi_data(irq, addr, data); 1215 1216 debugf("%s: irq: %d addr: %jx data: %x\n", 1217 __func__, irq, *addr, *data); 1218 1219 return (0); 1220 } 1221 1222 static int 1223 mv_pcib_alloc_msi(device_t dev, device_t child, int count, 1224 int maxcount __unused, int *irqs) 1225 { 1226 struct mv_pcib_softc *sc; 1227 u_int start = 0, i; 1228 1229 sc = device_get_softc(dev); 1230 if (!sc->sc_msi_supported) 1231 return (ENOTSUP); 1232 1233 if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 1234 return (EINVAL); 1235 1236 mtx_lock(&sc->sc_msi_mtx); 1237 1238 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 1239 for (i = start; i < start + count; i++) { 1240 if (isset(&sc->sc_msi_bitmap, i)) 1241 break; 1242 } 1243 if (i == start + count) 1244 break; 1245 } 1246 1247 if ((start + count) == MSI_IRQ_NUM) { 1248 mtx_unlock(&sc->sc_msi_mtx); 1249 return (ENXIO); 1250 } 1251 1252 for (i = start; i < start + count; i++) { 1253 setbit(&sc->sc_msi_bitmap, i); 1254 *irqs++ = MSI_IRQ + i; 1255 } 1256 debugf("%s: start: %x count: %x\n", __func__, start, count); 1257 1258 mtx_unlock(&sc->sc_msi_mtx); 1259 return (0); 1260 } 1261 1262 static int 1263 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 1264 { 1265 struct mv_pcib_softc *sc; 1266 u_int i; 1267 1268 sc = device_get_softc(dev); 1269 if(!sc->sc_msi_supported) 1270 return (ENOTSUP); 1271 1272 mtx_lock(&sc->sc_msi_mtx); 1273 1274 for (i = 0; i < count; i++) 1275 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); 1276 1277 mtx_unlock(&sc->sc_msi_mtx); 1278 return (0); 1279 } 1280