1 /*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef _MVWIN_H_ 35 #define _MVWIN_H_ 36 37 /* 38 * Decode windows addresses. 39 * 40 * All decoding windows must be aligned to their size, which has to be 41 * a power of 2. 42 */ 43 44 /* 45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA) 46 */ 47 48 /* SoC Regs */ 49 #define MV_PHYS_BASE 0xF1000000 50 #define MV_SIZE (1024 * 1024) /* 1 MB */ 51 52 /* SRAM */ 53 #define MV_CESA_SRAM_BASE 0xF1100000 54 55 /* 56 * External devices: 0x80000000, 1 GB (VA == PA) 57 * Includes Device Bus, PCI and PCIE. 58 */ 59 #if defined(SOC_MV_ORION) 60 #define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */ 61 #elif defined(SOC_MV_KIRKWOOD) 62 #define MV_PCI_PORTS 1 /* 1x PCIE */ 63 #elif defined(SOC_MV_DISCOVERY) 64 #define MV_PCI_PORTS 8 /* 8x PCIE */ 65 #elif defined(SOC_MV_ARMADAXP) 66 #define MV_PCI_PORTS 3 /* 3x PCIE */ 67 #elif defined(SOC_MV_ARMADA38X) 68 #define MV_PCI_PORTS 4 /* 4x PCIE */ 69 #else 70 #error "MV_PCI_PORTS not configured !" 71 #endif 72 73 /* PCI/PCIE Memory */ 74 #define MV_PCI_MEM_PHYS_BASE 0x80000000 75 #define MV_PCI_MEM_SIZE (512 * 1024 * 1024) /* 512 MB */ 76 #define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 77 #define MV_PCI_MEM_SLICE_SIZE (MV_PCI_MEM_SIZE / MV_PCI_PORTS) 78 #define MV_PCI_MEM_SLICE(n) (MV_PCI_MEM_BASE + ((n) * \ 79 MV_PCI_MEM_SLICE_SIZE)) 80 /* PCI/PCIE I/O */ 81 #define MV_PCI_IO_PHYS_BASE 0xBF000000 82 #define MV_PCI_IO_SIZE (16 * 1024 * 1024) /* 16 MB */ 83 #define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 84 #define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS) 85 #define MV_PCI_IO_SLICE(n) (MV_PCI_IO_BASE + ((n) * MV_PCI_IO_SLICE_SIZE)) 86 87 #define MV_PCI_VA_MEM_BASE 0 88 #define MV_PCI_VA_IO_BASE 0 89 90 /* 91 * Device Bus (VA == PA) 92 */ 93 #define MV_DEV_BOOT_BASE 0xF9300000 94 #define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */ 95 96 #define MV_DEV_CS0_BASE 0xF9400000 97 #define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */ 98 99 #define MV_DEV_CS1_BASE 0xF9500000 100 #define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */ 101 102 #define MV_DEV_CS2_BASE 0xFB500000 103 #define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */ 104 105 106 /* 107 * Integrated SoC peripherals addresses 108 */ 109 #define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 110 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 111 #define MV_DDR_CADR_BASE (MV_BASE + 0x20180) 112 #else 113 #define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 114 #endif 115 #define MV_MPP_BASE (MV_BASE + 0x10000) 116 117 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 118 #define MV_MISC_BASE (MV_BASE + 0x18200) 119 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 120 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 121 #define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700) 122 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x1800) 123 #else 124 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 125 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 126 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 127 #endif 128 129 #define MV_PCI_BASE (MV_BASE + 0x30000) 130 #define MV_PCI_SIZE 0x2000 131 132 #if defined(SOC_MV_ARMADA38X) 133 #define MV_PCIE_BASE (MV_BASE + 0x80000) 134 #else 135 #define MV_PCIE_BASE (MV_BASE + 0x40000) 136 #endif 137 #define MV_PCIE_SIZE 0x2000 138 139 #define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) 140 #define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 141 #define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 142 #define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 143 #define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 144 #define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 145 #define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 146 #define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 147 148 #define MV_SDIO_BASE (MV_BASE + 0x90000) 149 #define MV_SDIO_SIZE 0x10000 150 151 /* 152 * Decode windows definitions and macros 153 */ 154 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 155 #define MV_WIN_CPU_CTRL(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) 156 #define MV_WIN_CPU_BASE(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4) 157 #define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + 0x008) 158 #define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + 0x00C) 159 #else 160 #define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 161 #define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 162 #define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 163 #define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 164 #endif 165 166 #if defined(SOC_MV_DISCOVERY) 167 #define MV_WIN_CPU_MAX 14 168 #elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 169 #define MV_WIN_CPU_MAX 20 170 #else 171 #define MV_WIN_CPU_MAX 8 172 #endif 173 174 #define MV_WIN_CPU_ATTR_SHIFT 8 175 #define MV_WIN_CPU_TARGET_SHIFT 4 176 #define MV_WIN_CPU_ENABLE_BIT 1 177 178 #define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 179 #define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 180 #define MV_WIN_DDR_MAX 4 181 182 /* 183 * These values are valid only for peripherals decoding windows 184 * Bit in ATTR is zeroed according to CS bank number 185 */ 186 #define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs))) 187 #define MV_WIN_DDR_TARGET 0x0 188 189 #if defined(SOC_MV_DISCOVERY) 190 #define MV_WIN_CESA_TARGET 9 191 #define MV_WIN_CESA_ATTR(eng_sel) 1 192 #elif defined(SOC_MV_ARMADAXP) 193 #define MV_WIN_CESA_TARGET 9 194 /* 195 * Bits [2:3] of cesa attribute select engine: 196 * eng_sel: 197 * 1: engine1 198 * 2: engine0 199 */ 200 #define MV_WIN_CESA_ATTR(eng_sel) (1 | ((eng_sel) << 2)) 201 #elif defined(SOC_MV_ARMADA38X) 202 #define MV_WIN_CESA_TARGET 9 203 /* 204 * Bits [1:0] = Data swapping 205 * 0x0 = Byte swap 206 * 0x1 = No swap 207 * 0x2 = Byte and word swap 208 * 0x3 = Word swap 209 * Bits [4:2] = CESA select: 210 * 0x6 = CESA0 211 * 0x5 = CESA1 212 */ 213 #define MV_WIN_CESA_ATTR(eng_sel) (0x11 | (1 << (3 - (eng_sel)))) 214 #else 215 #define MV_WIN_CESA_TARGET 3 216 #define MV_WIN_CESA_ATTR(eng_sel) 0 217 #endif 218 219 #define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320) 220 #define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324) 221 #define MV_WIN_USB_MAX 4 222 223 #define MV_WIN_USB3_CTRL(n) (0x8 * (n)) 224 #define MV_WIN_USB3_BASE(n) (0x8 * (n) + 0x4) 225 #define MV_WIN_USB3_MAX 8 226 227 #define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 228 #define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 229 #define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 230 #define MV_WIN_ETH_MAX 6 231 232 #define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 233 #define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 234 #define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 235 #define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 236 #define MV_WIN_IDMA_MAX 8 237 #define MV_IDMA_CHAN_MAX 4 238 239 #define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) 240 #define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) 241 #define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) 242 #define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) 243 #define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) 244 #define MV_WIN_XOR_MAX 8 245 #define MV_XOR_CHAN_MAX 2 246 #define MV_XOR_NON_REMAP 4 247 248 #if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD) 249 #define MV_WIN_PCIE_TARGET(n) 4 250 #define MV_WIN_PCIE_MEM_ATTR(n) 0xE8 251 #define MV_WIN_PCIE_IO_ATTR(n) 0xE0 252 #elif defined(SOC_MV_ARMADAXP) 253 #define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2))) 254 #define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2))) 255 #define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2))) 256 #elif defined(SOC_MV_ARMADA38X) 257 #define MV_WIN_PCIE_TARGET(n) ((n) == 0 ? 8 : 4) 258 #define MV_WIN_PCIE_MEM_ATTR(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20))) 259 #define MV_WIN_PCIE_IO_ATTR(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20))) 260 #elif defined(SOC_MV_ORION) 261 #define MV_WIN_PCIE_TARGET(n) 4 262 #define MV_WIN_PCIE_MEM_ATTR(n) 0x59 263 #define MV_WIN_PCIE_IO_ATTR(n) 0x51 264 #endif 265 266 #define MV_WIN_PCI_TARGET 3 267 #define MV_WIN_PCI_MEM_ATTR 0x59 268 #define MV_WIN_PCI_IO_ATTR 0x51 269 270 #define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 271 (n) + 1) + 0x1820) 272 #define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 273 (n) + 1) + 0x1824) 274 #define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 275 (n) + 1) + 0x182C) 276 #define MV_WIN_PCIE_MAX 6 277 278 #define MV_PCIE_BAR_CTRL(n) (0x04 * (n) + 0x1800) 279 #define MV_PCIE_BAR_BASE(n) (0x08 * ((n) < 3 ? (n) : 4) + 0x0010) 280 #define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014) 281 #define MV_PCIE_BAR_MAX 4 282 #define MV_PCIE_BAR_64BIT (0x4) 283 #define MV_PCIE_BAR_PREFETCH_EN (0x8) 284 285 #define MV_PCIE_CONTROL (0x1a00) 286 #define MV_PCIE_ROOT_CMPLX (1 << 1) 287 288 #if defined(SOC_MV_ARMADA38X) 289 #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x60) 290 #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x64) 291 #define MV_WIN_SATA_SIZE(n) (0x10 * (n) + 0x68) 292 #define MV_WIN_SATA_MAX 4 293 #else 294 #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) 295 #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) 296 #define MV_WIN_SATA_MAX 4 297 #endif 298 299 #if defined(SOC_MV_ARMADA38X) 300 #define MV_BOOTROM_MEM_ADDR 0xFFF00000 301 #define MV_BOOTROM_WIN_SIZE 0xF 302 #define MV_CPU_SUBSYS_REGS_LEN 0x100 303 304 /* IO Window Control Register fields */ 305 #define IO_WIN_SIZE_SHIFT 16 306 #define IO_WIN_SIZE_MASK 0xFFFF 307 #define IO_WIN_ATTR_SHIFT 8 308 #define IO_WIN_ATTR_MASK 0xFF 309 #define IO_WIN_TGT_SHIFT 4 310 #define IO_WIN_TGT_MASK 0xF 311 #define IO_WIN_SYNC_SHIFT 1 312 #define IO_WIN_SYNC_MASK 0x1 313 #define IO_WIN_ENA_SHIFT 0 314 #define IO_WIN_ENA_MASK 0x1 315 316 #define IO_WIN_9_CTRL_OFFSET 0x98 317 #define IO_WIN_9_BASE_OFFSET 0x9C 318 319 /* Mbus decoding unit IDs and attributes */ 320 #define MBUS_BOOTROM_TGT_ID 0x1 321 #define MBUS_BOOTROM_ATTR 0x1D 322 323 /* Internal Units Sync Barrier Control Register */ 324 #define MV_SYNC_BARRIER_CTRL 0x84 325 #define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF 326 #endif 327 328 #define WIN_REG_IDX_RD(pre,reg,off,base) \ 329 static __inline uint32_t \ 330 pre ## _ ## reg ## _read(int i) \ 331 { \ 332 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 333 } 334 335 #define WIN_REG_IDX_RD2(pre,reg,off,base) \ 336 static __inline uint32_t \ 337 pre ## _ ## reg ## _read(int i, int j) \ 338 { \ 339 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 340 } \ 341 342 #define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 343 static __inline uint32_t \ 344 pre ## _ ## reg ## _read(uint32_t base, int i) \ 345 { \ 346 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 347 } 348 349 #define WIN_REG_BASE_IDX_RD2(pre,reg,off) \ 350 static __inline uint32_t \ 351 pre ## _ ## reg ## _read(uint32_t base, int i, int j) \ 352 { \ 353 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 354 } 355 356 #define WIN_REG_IDX_WR(pre,reg,off,base) \ 357 static __inline void \ 358 pre ## _ ## reg ## _write(int i, uint32_t val) \ 359 { \ 360 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 361 } 362 363 #define WIN_REG_IDX_WR2(pre,reg,off,base) \ 364 static __inline void \ 365 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ 366 { \ 367 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 368 } 369 370 #define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 371 static __inline void \ 372 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 373 { \ 374 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 375 } 376 377 #define WIN_REG_BASE_IDX_WR2(pre,reg,off) \ 378 static __inline void \ 379 pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \ 380 { \ 381 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 382 } 383 384 #define WIN_REG_RD(pre,reg,off,base) \ 385 static __inline uint32_t \ 386 pre ## _ ## reg ## _read(void) \ 387 { \ 388 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 389 } 390 391 #define WIN_REG_BASE_RD(pre,reg,off) \ 392 static __inline uint32_t \ 393 pre ## _ ## reg ## _read(uint32_t base) \ 394 { \ 395 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 396 } 397 398 #define WIN_REG_WR(pre,reg,off,base) \ 399 static __inline void \ 400 pre ## _ ## reg ## _write(uint32_t val) \ 401 { \ 402 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 403 } 404 405 #define WIN_REG_BASE_WR(pre,reg,off) \ 406 static __inline void \ 407 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 408 { \ 409 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 410 } 411 412 #endif /* _MVWIN_H_ */ 413