1 /*- 2 * Copyright (c) 2015 Michal Meloun 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/clock.h> 32 #include <sys/kernel.h> 33 #include <sys/limits.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/module.h> 37 #include <sys/resource.h> 38 #include <sys/rman.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 43 #include <dev/extres/clk/clk.h> 44 #include <dev/extres/hwreset/hwreset.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <arm/nvidia/tegra_efuse.h> 49 50 #define FUSES_START 0x100 51 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (FUSES_START + (_r))) 52 53 struct efuse_soc; 54 struct tegra_efuse_softc { 55 device_t dev; 56 struct resource *mem_res; 57 58 struct efuse_soc *soc; 59 clk_t clk; 60 hwreset_t reset; 61 }; 62 63 struct tegra_efuse_softc *dev_sc; 64 struct tegra_sku_info tegra_sku_info; 65 static char *tegra_rev_name[] = { 66 [TEGRA_REVISION_UNKNOWN] = "unknown", 67 [TEGRA_REVISION_A01] = "A01", 68 [TEGRA_REVISION_A02] = "A02", 69 [TEGRA_REVISION_A03] = "A03", 70 [TEGRA_REVISION_A03p] = "A03 prime", 71 [TEGRA_REVISION_A04] = "A04", 72 }; 73 74 struct efuse_soc { 75 void (*init)(struct tegra_efuse_softc *sc, 76 struct tegra_sku_info *sku); 77 }; 78 79 static void tegra124_init(struct tegra_efuse_softc *sc, 80 struct tegra_sku_info *sku); 81 struct efuse_soc tegra124_efuse_soc = { 82 .init = tegra124_init, 83 }; 84 85 static void tegra210_init(struct tegra_efuse_softc *sc, 86 struct tegra_sku_info *sku); 87 struct efuse_soc tegra210_efuse_soc = { 88 .init = tegra210_init, 89 }; 90 91 static struct ofw_compat_data compat_data[] = { 92 {"nvidia,tegra124-efuse", (intptr_t)&tegra124_efuse_soc}, 93 {"nvidia,tegra210-efuse", (intptr_t)&tegra210_efuse_soc}, 94 {NULL, 0} 95 }; 96 97 /* ---------------------- Tegra 124 specific code & data --------------- */ 98 #define TEGRA124_CPU_PROCESS_CORNERS 2 99 #define TEGRA124_GPU_PROCESS_CORNERS 2 100 #define TEGRA124_SOC_PROCESS_CORNERS 2 101 102 #define TEGRA124_FUSE_SKU_INFO 0x10 103 #define TEGRA124_FUSE_CPU_SPEEDO_0 0x14 104 #define TEGRA124_FUSE_CPU_IDDQ 0x18 105 #define TEGRA124_FUSE_FT_REV 0x28 106 #define TEGRA124_FUSE_CPU_SPEEDO_1 0x2c 107 #define TEGRA124_FUSE_CPU_SPEEDO_2 0x30 108 #define TEGRA124_FUSE_SOC_SPEEDO_0 0x34 109 #define TEGRA124_FUSE_SOC_SPEEDO_1 0x38 110 #define TEGRA124_FUSE_SOC_SPEEDO_2 0x3c 111 #define TEGRA124_FUSE_SOC_IDDQ 0x40 112 #define TEGRA124_FUSE_GPU_IDDQ 0x128 113 114 enum { 115 TEGRA124_THRESHOLD_INDEX_0, 116 TEGRA124_THRESHOLD_INDEX_1, 117 TEGRA124_THRESHOLD_INDEX_COUNT, 118 }; 119 120 static uint32_t tegra124_cpu_process_speedos[][TEGRA124_CPU_PROCESS_CORNERS] = 121 { 122 {2190, UINT_MAX}, 123 {0, UINT_MAX}, 124 }; 125 126 static uint32_t tegra124_gpu_process_speedos[][TEGRA124_GPU_PROCESS_CORNERS] = 127 { 128 {1965, UINT_MAX}, 129 {0, UINT_MAX}, 130 }; 131 132 static uint32_t tegra124_soc_process_speedos[][TEGRA124_SOC_PROCESS_CORNERS] = 133 { 134 {2101, UINT_MAX}, 135 {0, UINT_MAX}, 136 }; 137 138 139 static void 140 tegra124_rev_sku_to_speedo_ids(struct tegra_efuse_softc *sc, 141 struct tegra_sku_info *sku, int *threshold) 142 { 143 144 /* Set default */ 145 sku->cpu_speedo_id = 0; 146 sku->soc_speedo_id = 0; 147 sku->gpu_speedo_id = 0; 148 *threshold = TEGRA124_THRESHOLD_INDEX_0; 149 150 switch (sku->sku_id) { 151 case 0x00: /* Eng sku */ 152 case 0x0F: 153 case 0x23: 154 /* Using the default */ 155 break; 156 case 0x83: 157 sku->cpu_speedo_id = 2; 158 break; 159 160 case 0x1F: 161 case 0x87: 162 case 0x27: 163 sku->cpu_speedo_id = 2; 164 sku->soc_speedo_id = 0; 165 sku->gpu_speedo_id = 1; 166 *threshold = TEGRA124_THRESHOLD_INDEX_0; 167 break; 168 case 0x81: 169 case 0x21: 170 case 0x07: 171 sku->cpu_speedo_id = 1; 172 sku->soc_speedo_id = 1; 173 sku->gpu_speedo_id = 1; 174 *threshold = TEGRA124_THRESHOLD_INDEX_1; 175 break; 176 case 0x49: 177 case 0x4A: 178 case 0x48: 179 sku->cpu_speedo_id = 4; 180 sku->soc_speedo_id = 2; 181 sku->gpu_speedo_id = 3; 182 *threshold = TEGRA124_THRESHOLD_INDEX_1; 183 break; 184 default: 185 device_printf(sc->dev, " Unknown SKU ID %d\n", sku->sku_id); 186 break; 187 } 188 } 189 190 static void 191 tegra124_init(struct tegra_efuse_softc *sc, struct tegra_sku_info *sku) 192 { 193 int i, threshold; 194 195 sku->sku_id = RD4(sc, TEGRA124_FUSE_SKU_INFO); 196 sku->soc_iddq_value = RD4(sc, TEGRA124_FUSE_SOC_IDDQ); 197 sku->cpu_iddq_value = RD4(sc, TEGRA124_FUSE_CPU_IDDQ); 198 sku->gpu_iddq_value = RD4(sc, TEGRA124_FUSE_GPU_IDDQ); 199 sku->soc_speedo_value = RD4(sc, TEGRA124_FUSE_SOC_SPEEDO_0); 200 sku->cpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_0); 201 sku->gpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_2); 202 203 if (sku->cpu_speedo_value == 0) { 204 device_printf(sc->dev, "CPU Speedo value is not fused.\n"); 205 return; 206 } 207 208 tegra124_rev_sku_to_speedo_ids(sc, sku, &threshold); 209 210 for (i = 0; i < TEGRA124_SOC_PROCESS_CORNERS; i++) { 211 if (sku->soc_speedo_value < 212 tegra124_soc_process_speedos[threshold][i]) 213 break; 214 } 215 sku->soc_process_id = i; 216 217 for (i = 0; i < TEGRA124_CPU_PROCESS_CORNERS; i++) { 218 if (sku->cpu_speedo_value < 219 tegra124_cpu_process_speedos[threshold][i]) 220 break; 221 } 222 sku->cpu_process_id = i; 223 224 for (i = 0; i < TEGRA124_GPU_PROCESS_CORNERS; i++) { 225 if (sku->gpu_speedo_value < 226 tegra124_gpu_process_speedos[threshold][i]) 227 break; 228 } 229 sku->gpu_process_id = i; 230 231 } 232 /* ----------------- End of Tegra 124 specific code & data --------------- */ 233 234 /* -------------------- Tegra 201 specific code & data ------------------- */ 235 #define TEGRA210_CPU_PROCESS_CORNERS 2 236 #define TEGRA210_GPU_PROCESS_CORNERS 2 237 #define TEGRA210_SOC_PROCESS_CORNERS 3 238 239 #define TEGRA210_FUSE_SKU_INFO 0x010 240 #define TEGRA210_FUSE_CPU_SPEEDO_0 0x014 241 #define TEGRA210_FUSE_CPU_IDDQ 0x018 242 #define TEGRA210_FUSE_FT_REV 0x028 243 #define TEGRA210_FUSE_CPU_SPEEDO_1 0x02c 244 #define TEGRA210_FUSE_CPU_SPEEDO_2 0x030 245 #define TEGRA210_FUSE_SOC_SPEEDO_0 0x034 246 #define TEGRA210_FUSE_SOC_SPEEDO_1 0x038 247 #define TEGRA210_FUSE_SOC_SPEEDO_2 0x03c 248 #define TEGRA210_FUSE_SOC_IDDQ 0x040 249 #define TEGRA210_FUSE_GPU_IDDQ 0x128 250 #define TEGRA210_FUSE_SPARE 0x270 251 252 enum { 253 TEGRA210_THRESHOLD_INDEX_0, 254 TEGRA210_THRESHOLD_INDEX_1, 255 TEGRA210_THRESHOLD_INDEX_COUNT, 256 }; 257 258 static uint32_t tegra210_cpu_process_speedos[][TEGRA210_CPU_PROCESS_CORNERS] = 259 { 260 {2119, UINT_MAX}, 261 {2119, UINT_MAX}, 262 }; 263 264 static uint32_t tegra210_gpu_process_speedos[][TEGRA210_GPU_PROCESS_CORNERS] = 265 { 266 {UINT_MAX, UINT_MAX}, 267 {UINT_MAX, UINT_MAX}, 268 }; 269 270 static uint32_t tegra210_soc_process_speedos[][TEGRA210_SOC_PROCESS_CORNERS] = 271 { 272 {1950, 2100, UINT_MAX}, 273 {1950, 2100, UINT_MAX}, 274 }; 275 276 static uint32_t 277 tegra210_get_speedo_revision(struct tegra_efuse_softc *sc) 278 { 279 uint32_t reg; 280 uint32_t val; 281 282 val = 0; 283 284 /* Revision i encoded in spare fields */ 285 reg = RD4(sc, TEGRA210_FUSE_SPARE + 2 * 4); 286 val |= (reg & 1) << 0; 287 reg = RD4(sc, TEGRA210_FUSE_SPARE + 3 * 4); 288 val |= (reg & 1) << 1; 289 reg = RD4(sc, TEGRA210_FUSE_SPARE + 4 * 4); 290 val |= (reg & 1) << 2; 291 292 return (val); 293 } 294 295 296 static void 297 tegra210_rev_sku_to_speedo_ids(struct tegra_efuse_softc *sc, 298 struct tegra_sku_info *sku, int speedo_rev, int *threshold) 299 { 300 301 /* Set defaults */ 302 sku->cpu_speedo_id = 0; 303 sku->soc_speedo_id = 0; 304 sku->gpu_speedo_id = 0; 305 *threshold = TEGRA210_THRESHOLD_INDEX_0; 306 307 switch (sku->sku_id) { 308 case 0x00: /* Eng sku */ 309 case 0x01: /* Eng sku */ 310 case 0x07: 311 case 0x17: 312 case 0x27: 313 /* Use defaults */ 314 if (speedo_rev >= 2) 315 sku->gpu_speedo_id = 1; 316 break; 317 case 0x13: 318 if (speedo_rev >= 2) 319 sku->gpu_speedo_id = 1; 320 sku->cpu_speedo_id = 1; 321 break; 322 323 default: 324 device_printf(sc->dev, " Unknown SKU ID %d\n", sku->sku_id); 325 break; 326 } 327 } 328 329 330 static void 331 tegra210_init(struct tegra_efuse_softc *sc, struct tegra_sku_info *sku) 332 { 333 int i, threshold, speedo_rev; 334 uint32_t cpu_speedo[3], soc_speedo[3]; 335 336 cpu_speedo[0] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_0); 337 cpu_speedo[1] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_1); 338 cpu_speedo[2] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_2); 339 soc_speedo[0] = RD4(sc, TEGRA210_FUSE_SOC_SPEEDO_0); 340 soc_speedo[1] = RD4(sc, TEGRA210_FUSE_SOC_SPEEDO_1); 341 soc_speedo[2] = RD4(sc, TEGRA210_FUSE_SOC_SPEEDO_2); 342 343 344 sku->cpu_iddq_value = RD4(sc, TEGRA210_FUSE_CPU_IDDQ); 345 sku->soc_iddq_value = RD4(sc, TEGRA210_FUSE_SOC_IDDQ); 346 sku->gpu_iddq_value = RD4(sc, TEGRA210_FUSE_GPU_IDDQ); 347 348 speedo_rev = tegra210_get_speedo_revision(sc); 349 device_printf(sc->dev, " Speedo revision: %u\n", speedo_rev); 350 351 if (speedo_rev >= 3) { 352 sku->cpu_speedo_value = cpu_speedo[0]; 353 sku->gpu_speedo_value = cpu_speedo[2]; 354 sku->soc_speedo_value = soc_speedo[0]; 355 } else if (speedo_rev == 2) { 356 sku->cpu_speedo_value = 357 (-1938 + (1095 * cpu_speedo[0] / 100)) / 10; 358 sku->gpu_speedo_value = 359 (-1662 + (1082 * cpu_speedo[2] / 100)) / 10; 360 sku->soc_speedo_value = 361 ( -705 + (1037 * soc_speedo[0] / 100)) / 10; 362 } else { 363 sku->cpu_speedo_value = 2100; 364 sku->gpu_speedo_value = cpu_speedo[2] - 75; 365 sku->soc_speedo_value = 1900; 366 } 367 368 tegra210_rev_sku_to_speedo_ids(sc, sku, speedo_rev, &threshold); 369 370 for (i = 0; i < TEGRA210_SOC_PROCESS_CORNERS; i++) { 371 if (sku->soc_speedo_value < 372 tegra210_soc_process_speedos[threshold][i]) 373 break; 374 } 375 sku->soc_process_id = i; 376 377 for (i = 0; i < TEGRA210_CPU_PROCESS_CORNERS; i++) { 378 if (sku->cpu_speedo_value < 379 tegra210_cpu_process_speedos[threshold][i]) 380 break; 381 } 382 sku->cpu_process_id = i; 383 384 for (i = 0; i < TEGRA210_GPU_PROCESS_CORNERS; i++) { 385 if (sku->gpu_speedo_value < 386 tegra210_gpu_process_speedos[threshold][i]) 387 break; 388 } 389 sku->gpu_process_id = i; 390 391 } 392 393 /* ----------------- End of Tegra 210 specific code & data --------------- */ 394 395 396 uint32_t 397 tegra_fuse_read_4(int addr) { 398 if (dev_sc == NULL) 399 panic("tegra_fuse_read_4 called too early"); 400 return (RD4(dev_sc, addr)); 401 } 402 403 static void 404 tegra_efuse_dump_sku(void) 405 { 406 printf(" TEGRA SKU Info:\n"); 407 printf(" chip_id: %u\n", tegra_sku_info.chip_id); 408 printf(" sku_id: %u\n", tegra_sku_info.sku_id); 409 printf(" cpu_process_id: %u\n", tegra_sku_info.cpu_process_id); 410 printf(" cpu_speedo_id: %u\n", tegra_sku_info.cpu_speedo_id); 411 printf(" cpu_speedo_value: %u\n", tegra_sku_info.cpu_speedo_value); 412 printf(" cpu_iddq_value: %u\n", tegra_sku_info.cpu_iddq_value); 413 printf(" soc_process_id: %u\n", tegra_sku_info.soc_process_id); 414 printf(" soc_speedo_id: %u\n", tegra_sku_info.soc_speedo_id); 415 printf(" soc_speedo_value: %u\n", tegra_sku_info.soc_speedo_value); 416 printf(" soc_iddq_value: %u\n", tegra_sku_info.soc_iddq_value); 417 printf(" gpu_process_id: %u\n", tegra_sku_info.gpu_process_id); 418 printf(" gpu_speedo_id: %u\n", tegra_sku_info.gpu_speedo_id); 419 printf(" gpu_speedo_value: %u\n", tegra_sku_info.gpu_speedo_value); 420 printf(" gpu_iddq_value: %u\n", tegra_sku_info.gpu_iddq_value); 421 printf(" revision: %s\n", tegra_rev_name[tegra_sku_info.revision]); 422 } 423 424 static int 425 tegra_efuse_probe(device_t dev) 426 { 427 if (!ofw_bus_status_okay(dev)) 428 return (ENXIO); 429 430 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 431 return (ENXIO); 432 433 return (BUS_PROBE_DEFAULT); 434 } 435 436 static int 437 tegra_efuse_attach(device_t dev) 438 { 439 int rv, rid; 440 struct tegra_efuse_softc *sc; 441 442 sc = device_get_softc(dev); 443 sc->dev = dev; 444 sc->soc = (struct efuse_soc *)ofw_bus_search_compatible(dev, 445 compat_data)->ocd_data; 446 447 /* Get the memory resource for the register mapping. */ 448 rid = 0; 449 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 450 RF_ACTIVE); 451 if (sc->mem_res == NULL) { 452 device_printf(dev, "Cannot map registers.\n"); 453 rv = ENXIO; 454 goto fail; 455 } 456 457 /* OFW resources. */ 458 rv = clk_get_by_ofw_name(dev, 0, "fuse", &sc->clk); 459 if (rv != 0) { 460 device_printf(dev, "Cannot get fuse clock: %d\n", rv); 461 goto fail; 462 } 463 rv = clk_enable(sc->clk); 464 if (rv != 0) { 465 device_printf(dev, "Cannot enable clock: %d\n", rv); 466 goto fail; 467 } 468 rv = hwreset_get_by_ofw_name(sc->dev, 0, "fuse", &sc->reset); 469 if (rv != 0) { 470 device_printf(dev, "Cannot get fuse reset\n"); 471 goto fail; 472 } 473 rv = hwreset_deassert(sc->reset); 474 if (rv != 0) { 475 device_printf(sc->dev, "Cannot clear reset\n"); 476 goto fail; 477 } 478 479 sc->soc->init(sc, &tegra_sku_info); 480 481 dev_sc = sc; 482 483 if (bootverbose) 484 tegra_efuse_dump_sku(); 485 return (bus_generic_attach(dev)); 486 487 fail: 488 dev_sc = NULL; 489 if (sc->clk != NULL) 490 clk_release(sc->clk); 491 if (sc->reset != NULL) 492 hwreset_release(sc->reset); 493 if (sc->mem_res != NULL) 494 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 495 496 return (rv); 497 } 498 499 static int 500 tegra_efuse_detach(device_t dev) 501 { 502 struct tegra_efuse_softc *sc; 503 504 sc = device_get_softc(dev); 505 dev_sc = NULL; 506 if (sc->clk != NULL) 507 clk_release(sc->clk); 508 if (sc->reset != NULL) 509 hwreset_release(sc->reset); 510 if (sc->mem_res != NULL) 511 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 512 513 return (bus_generic_detach(dev)); 514 } 515 516 static device_method_t tegra_efuse_methods[] = { 517 /* Device interface */ 518 DEVMETHOD(device_probe, tegra_efuse_probe), 519 DEVMETHOD(device_attach, tegra_efuse_attach), 520 DEVMETHOD(device_detach, tegra_efuse_detach), 521 522 DEVMETHOD_END 523 }; 524 525 static DEFINE_CLASS_0(efuse, tegra_efuse_driver, tegra_efuse_methods, 526 sizeof(struct tegra_efuse_softc)); 527 EARLY_DRIVER_MODULE(tegra_efuse, simplebus, tegra_efuse_driver, NULL, NULL, 528 BUS_PASS_TIMER); 529