1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 31 /* 32 * USB phy driver for Tegra SoCs. 33 */ 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/rman.h> 41 42 #include <machine/bus.h> 43 #include <machine/fdt.h> 44 45 #include <dev/extres/clk/clk.h> 46 #include <dev/extres/hwreset/hwreset.h> 47 #include <dev/extres/phy/phy.h> 48 #include <dev/extres/regulator/regulator.h> 49 #include <dev/fdt/fdt_pinctrl.h> 50 #include <dev/ofw/openfirm.h> 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 54 #include "phynode_if.h" 55 56 #define CTRL_ICUSB_CTRL 0x15c 57 #define ICUSB_CTR_IC_ENB1 (1 << 3) 58 59 #define CTRL_USB_USBMODE 0x1f8 60 #define USB_USBMODE_MASK (3 << 0) 61 #define USB_USBMODE_HOST (3 << 0) 62 #define USB_USBMODE_DEVICE (2 << 0) 63 64 #define CTRL_USB_HOSTPC1_DEVLC 0x1b4 65 #define USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29) 66 #define USB_HOSTPC1_DEVLC_STS (1 << 28) 67 #define USB_HOSTPC1_DEVLC_PHCD (1 << 22) 68 69 70 #define IF_USB_SUSP_CTRL 0x400 71 #define FAST_WAKEUP_RESP (1 << 26) 72 #define UTMIP_SUSPL1_SET (1 << 25) 73 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) 74 #define USB_SUSP_SET (1 << 14) 75 #define UTMIP_PHY_ENB (1 << 12) 76 #define UTMIP_RESET (1 << 11) 77 #define USB_SUSP_POL (1 << 10) 78 #define USB_PHY_CLK_VALID_INT_ENB (1 << 9) 79 #define USB_PHY_CLK_VALID_INT_STS (1 << 8) 80 #define USB_PHY_CLK_VALID (1 << 7) 81 #define USB_CLKEN (1 << 6) 82 #define USB_SUSP_CLR (1 << 5) 83 #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4) 84 #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3) 85 #define USB_WAKE_ON_RESUME_EN (1 << 2) 86 #define USB_WAKEUP_INT_ENB (1 << 1) 87 #define USB_WAKEUP_INT_STS (1 << 0) 88 89 #define IF_USB_PHY_VBUS_SENSORS 0x404 90 #define B_SESS_END_SW_VALUE (1 << 4) 91 #define B_SESS_END_SW_EN (1 << 3) 92 93 94 #define UTMIP_XCVR_CFG0 0x808 95 #define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25) 96 #define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22) 97 #define UTMIP_XCVR_LSBIAS_SEL (1 << 21) 98 #define UTMIP_XCVR_DISCON_METHOD (1 << 20) 99 #define UTMIP_FORCE_PDZI_POWERUP (1 << 19) 100 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) 101 #define UTMIP_FORCE_PD2_POWERUP (1 << 17) 102 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) 103 #define UTMIP_FORCE_PD_POWERUP (1 << 15) 104 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) 105 #define UTMIP_XCVR_TERMEN (1 << 13) 106 #define UTMIP_XCVR_HSLOOPBACK (1 << 12) 107 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) 108 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) 109 #define UTMIP_XCVR_FSSLEW(x) (((x) & 0x3) << 6) 110 #define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4) 111 #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) 112 113 #define UTMIP_BIAS_CFG0 0x80C 114 #define UTMIP_IDDIG_C_VAL (1 << 30) 115 #define UTMIP_IDDIG_C_SEL (1 << 29) 116 #define UTMIP_IDDIG_B_VAL (1 << 28) 117 #define UTMIP_IDDIG_B_SEL (1 << 27) 118 #define UTMIP_IDDIG_A_VAL (1 << 26) 119 #define UTMIP_IDDIG_A_SEL (1 << 25) 120 #define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24) 121 #define UTMIP_IDPD_VAL (1 << 23) 122 #define UTMIP_IDPD_SEL (1 << 22) 123 #define UTMIP_IDDIG_VAL (1 << 21) 124 #define UTMIP_IDDIG_SEL (1 << 20) 125 #define UTMIP_GPI_VAL (1 << 19) 126 #define UTMIP_GPI_SEL (1 << 18) 127 #define UTMIP_ACTIVE_TERM_OFFSET(x) (((x) & 0x7) << 15) 128 #define UTMIP_ACTIVE_PULLUP_OFFSET(x) (((x) & 0x7) << 12) 129 #define UTMIP_OTGPD (1 << 11) 130 #define UTMIP_BIASPD (1 << 10) 131 #define UTMIP_VBUS_LEVEL_LEVEL(x) (((x) & 0x3) << 8) 132 #define UTMIP_SESS_LEVEL_LEVEL(x) (((x) & 0x3) << 6) 133 #define UTMIP_HSCHIRP_LEVEL(x) (((x) & 0x3) << 4) 134 #define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2) 135 #define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0) 136 137 138 #define UTMIP_HSRX_CFG0 0x810 139 #define UTMIP_KEEP_PATT_ON_ACTIVE(x) (((x) & 0x3) << 30) 140 #define UTMIP_ALLOW_CONSEC_UPDN (1 << 29) 141 #define UTMIP_REALIGN_ON_NEW_PKT (1 << 28) 142 #define UTMIP_PCOUNT_UPDN_DIV(x) (((x) & 0xf) << 24) 143 #define UTMIP_SQUELCH_EOP_DLY(x) (((x) & 0x7) << 21) 144 #define UTMIP_NO_STRIPPING (1 << 20) 145 #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) 146 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) 147 #define UTMIP_ELASTIC_OVERRUN_DISABLE (1 << 9) 148 #define UTMIP_ELASTIC_UNDERRUN_DISABLE (1 << 8) 149 #define UTMIP_PASS_CHIRP (1 << 7) 150 #define UTMIP_PASS_FEEDBACK (1 << 6) 151 #define UTMIP_PCOUNT_INERTIA(x) (((x) & 0x3) << 4) 152 #define UTMIP_PHASE_ADJUST(x) (((x) & 0x3) << 2) 153 #define UTMIP_THREE_SYNCBITS (1 << 1) 154 #define UTMIP_USE4SYNC_TRAN (1 << 0) 155 156 #define UTMIP_HSRX_CFG1 0x814 157 #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1F) << 1) 158 #define UTMIP_HS_ALLOW_KEEP_ALIVE (1 << 0) 159 160 #define UTMIP_TX_CFG0 0x820 161 #define UTMIP_FS_PREAMBLE_J (1 << 19) 162 #define UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE (1 << 18) 163 #define UTMIP_FS_PREAMBLE_OUTPUT_ENABLE (1 << 17) 164 #define UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR (1 << 16) 165 #define UTMIP_HS_READY_WAIT_FOR_VALID (1 << 15) 166 #define UTMIP_HS_TX_IPG_DLY(x) (((x) & 0x1f) << 10) 167 #define UTMIP_HS_DISCON_EOP_ONLY (1 << 9) 168 #define UTMIP_HS_DISCON_DISABLE (1 << 8) 169 #define UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE (1 << 7) 170 #define UTMIP_HS_PREAMBLE_OUTPUT_ENABLE (1 << 6) 171 #define UTMIP_SIE_RESUME_ON_LINESTATE (1 << 5) 172 #define UTMIP_SOF_ON_NO_STUFF (1 << 4) 173 #define UTMIP_SOF_ON_NO_ENCODE (1 << 3) 174 #define UTMIP_NO_STUFFING (1 << 2) 175 #define UTMIP_NO_ENCODING (1 << 1) 176 #define UTMIP_NO_SYNC_NO_EOP (1 << 0) 177 178 #define UTMIP_MISC_CFG0 0x824 179 #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) 180 #define UTMIP_DPDM_OBSERVE (1 << 26) 181 #define UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON (1 << 25) 182 #define UTMIP_ALLOW_LS_ON_SOFT_DISCON (1 << 24) 183 #define UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP (1 << 23) 184 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) 185 #define UTMIP_LS_TO_FS_SKIP_4MS (1 << 21) 186 #define UTMIP_INJECT_ERROR_TYPE(x) (((x) & 0x3) << 19) 187 #define UTMIP_FORCE_HS_CLOCK_ON (1 << 18) 188 #define UTMIP_DISABLE_HS_TERM (1 << 17) 189 #define UTMIP_FORCE_HS_TERM (1 << 16) 190 #define UTMIP_DISABLE_PULLUP_DP (1 << 15) 191 #define UTMIP_DISABLE_PULLUP_DM (1 << 14) 192 #define UTMIP_DISABLE_PULLDN_DP (1 << 13) 193 #define UTMIP_DISABLE_PULLDN_DM (1 << 12) 194 #define UTMIP_FORCE_PULLUP_DP (1 << 11) 195 #define UTMIP_FORCE_PULLUP_DM (1 << 10) 196 #define UTMIP_FORCE_PULLDN_DP (1 << 9) 197 #define UTMIP_FORCE_PULLDN_DM (1 << 8) 198 #define UTMIP_STABLE_COUNT(x) (((x) & 0x7) << 5) 199 #define UTMIP_STABLE_ALL (1 << 4) 200 #define UTMIP_NO_FREE_ON_SUSPEND (1 << 3) 201 #define UTMIP_NEVER_FREE_RUNNING_TERMS (1 << 2) 202 #define UTMIP_ALWAYS_FREE_RUNNING_TERMS (1 << 1) 203 #define UTMIP_COMB_TERMS (1 << 0) 204 205 #define UTMIP_MISC_CFG1 0x828 206 #define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) 207 208 #define UTMIP_DEBOUNCE_CFG0 0x82C 209 #define UTMIP_BIAS_DEBOUNCE_B(x) (((x) & 0xffff) << 16) 210 #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) 211 212 #define UTMIP_BAT_CHRG_CFG0 0x830 213 #define UTMIP_CHRG_DEBOUNCE_TIMESCALE(x) (((x) & 0x1f) << 8) 214 #define UTMIP_OP_I_SRC_ENG (1 << 5) 215 #define UTMIP_ON_SRC_ENG (1 << 4) 216 #define UTMIP_OP_SRC_ENG (1 << 3) 217 #define UTMIP_ON_SINK_ENG (1 << 2) 218 #define UTMIP_OP_SINK_ENG (1 << 1) 219 #define UTMIP_PD_CHRG (1 << 0) 220 221 #define UTMIP_SPARE_CFG0 0x834 222 #define FUSE_HS_IREF_CAP_CFG (1 << 7) 223 #define FUSE_HS_SQUELCH_LEVEL (1 << 6) 224 #define FUSE_SPARE (1 << 5) 225 #define FUSE_TERM_RANGE_ADJ_SEL (1 << 4) 226 #define FUSE_SETUP_SEL (1 << 3) 227 #define HS_RX_LATE_SQUELCH (1 << 2) 228 #define HS_RX_FLUSH_ALAP (1 << 1) 229 #define HS_RX_IPG_ERROR_ENABLE (1 << 0) 230 231 #define UTMIP_XCVR_CFG1 0x838 232 #define UTMIP_XCVR_RPU_RANGE_ADJ(x) (((x) & 0x3) << 26) 233 #define UTMIP_XCVR_HS_IREF_CAP(x) (((x) & 0x3) << 24) 234 #define UTMIP_XCVR_SPARE(x) (((x) & 0x3) << 22) 235 #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) 236 #define UTMIP_RCTRL_SW_SET (1 << 17) 237 #define UTMIP_RCTRL_SW_VAL(x) (((x) & 0x1f) << 12) 238 #define UTMIP_TCTRL_SW_SET (1 << 11) 239 #define UTMIP_TCTRL_SW_VAL(x) (((x) & 0x1f) << 6) 240 #define UTMIP_FORCE_PDDR_POWERUP (1 << 5) 241 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) 242 #define UTMIP_FORCE_PDCHRP_POWERUP (1 << 3) 243 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) 244 #define UTMIP_FORCE_PDDISC_POWERUP (1 << 1) 245 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) 246 247 #define UTMIP_BIAS_CFG1 0x83c 248 #define UTMIP_BIAS_DEBOUNCE_TIMESCALE(x) (((x) & 0x3f) << 8) 249 #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) 250 #define UTMIP_VBUS_WAKEUP_POWERDOWN (1 << 2) 251 #define UTMIP_FORCE_PDTRK_POWERUP (1 << 1) 252 #define UTMIP_FORCE_PDTRK_POWERDOWN (1 << 0) 253 254 static int usbpby_enable_cnt; 255 256 enum usb_ifc_type { 257 USB_IFC_TYPE_UNKNOWN = 0, 258 USB_IFC_TYPE_UTMI, 259 USB_IFC_TYPE_ULPI 260 }; 261 262 enum usb_dr_mode { 263 USB_DR_MODE_UNKNOWN = 0, 264 USB_DR_MODE_DEVICE, 265 USB_DR_MODE_HOST, 266 USB_DR_MODE_OTG 267 }; 268 269 struct usbphy_softc { 270 device_t dev; 271 struct resource *mem_res; 272 struct resource *pads_res; 273 clk_t clk_reg; 274 clk_t clk_pads; 275 clk_t clk_pllu; 276 regulator_t supply_vbus; 277 hwreset_t reset_usb; 278 hwreset_t reset_pads; 279 enum usb_ifc_type ifc_type; 280 enum usb_dr_mode dr_mode; 281 bool have_utmi_regs; 282 283 /* UTMI params */ 284 int hssync_start_delay; 285 int elastic_limit; 286 int idle_wait_delay; 287 int term_range_adj; 288 int xcvr_lsfslew; 289 int xcvr_lsrslew; 290 int xcvr_hsslew; 291 int hssquelch_level; 292 int hsdiscon_level; 293 int xcvr_setup; 294 int xcvr_setup_use_fuses; 295 }; 296 297 static struct ofw_compat_data compat_data[] = { 298 {"nvidia,tegra30-usb-phy", 1}, 299 {NULL, 0}, 300 }; 301 302 /* Phy controller class and methods. */ 303 static int usbphy_phy_enable(struct phynode *phy, bool enable); 304 static phynode_method_t usbphy_phynode_methods[] = { 305 PHYNODEMETHOD(phynode_enable, usbphy_phy_enable), 306 307 PHYNODEMETHOD_END 308 }; 309 DEFINE_CLASS_1(usbphy_phynode, usbphy_phynode_class, usbphy_phynode_methods, 310 0, phynode_class); 311 312 #define RD4(sc, offs) \ 313 bus_read_4(sc->mem_res, offs) 314 315 #define WR4(sc, offs, val) \ 316 bus_write_4(sc->mem_res, offs, val) 317 318 static int 319 reg_wait(struct usbphy_softc *sc, uint32_t reg, uint32_t mask, uint32_t val) 320 { 321 int i; 322 323 for (i = 0; i < 1000; i++) { 324 if ((RD4(sc, reg) & mask) == val) 325 return (0); 326 DELAY(10); 327 } 328 return (ETIMEDOUT); 329 } 330 331 static int 332 usbphy_utmi_phy_clk(struct usbphy_softc *sc, bool enable) 333 { 334 uint32_t val; 335 int rv; 336 337 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC); 338 if (enable) 339 val &= ~USB_HOSTPC1_DEVLC_PHCD; 340 else 341 val |= USB_HOSTPC1_DEVLC_PHCD; 342 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val); 343 344 rv = reg_wait(sc, IF_USB_SUSP_CTRL, USB_PHY_CLK_VALID, 345 enable ? USB_PHY_CLK_VALID: 0); 346 if (rv != 0) { 347 device_printf(sc->dev, "USB phy clock timeout.\n"); 348 return (ETIMEDOUT); 349 } 350 return (0); 351 } 352 353 static int 354 usbphy_utmi_enable(struct usbphy_softc *sc) 355 { 356 int rv; 357 uint32_t val; 358 359 /* Reset phy */ 360 val = RD4(sc, IF_USB_SUSP_CTRL); 361 val |= UTMIP_RESET; 362 WR4(sc, IF_USB_SUSP_CTRL, val); 363 364 365 val = RD4(sc, UTMIP_TX_CFG0); 366 val |= UTMIP_FS_PREAMBLE_J; 367 WR4(sc, UTMIP_TX_CFG0, val); 368 369 val = RD4(sc, UTMIP_HSRX_CFG0); 370 val &= ~UTMIP_IDLE_WAIT(~0); 371 val &= ~UTMIP_ELASTIC_LIMIT(~0); 372 val |= UTMIP_IDLE_WAIT(sc->idle_wait_delay); 373 val |= UTMIP_ELASTIC_LIMIT(sc->elastic_limit); 374 WR4(sc, UTMIP_HSRX_CFG0, val); 375 376 val = RD4(sc, UTMIP_HSRX_CFG1); 377 val &= ~UTMIP_HS_SYNC_START_DLY(~0); 378 val |= UTMIP_HS_SYNC_START_DLY(sc->hssync_start_delay); 379 WR4(sc, UTMIP_HSRX_CFG1, val); 380 381 val = RD4(sc, UTMIP_DEBOUNCE_CFG0); 382 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); 383 val |= UTMIP_BIAS_DEBOUNCE_A(0x7530); /* For 12MHz */ 384 WR4(sc, UTMIP_DEBOUNCE_CFG0, val); 385 386 val = RD4(sc, UTMIP_MISC_CFG0); 387 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; 388 WR4(sc, UTMIP_MISC_CFG0, val); 389 390 if (sc->dr_mode == USB_DR_MODE_DEVICE) { 391 val = RD4(sc,IF_USB_SUSP_CTRL); 392 val &= ~USB_WAKE_ON_CNNT_EN_DEV; 393 val &= ~USB_WAKE_ON_DISCON_EN_DEV; 394 WR4(sc, IF_USB_SUSP_CTRL, val); 395 396 val = RD4(sc, UTMIP_BAT_CHRG_CFG0); 397 val &= ~UTMIP_PD_CHRG; 398 WR4(sc, UTMIP_BAT_CHRG_CFG0, val); 399 } else { 400 val = RD4(sc, UTMIP_BAT_CHRG_CFG0); 401 val |= UTMIP_PD_CHRG; 402 WR4(sc, UTMIP_BAT_CHRG_CFG0, val); 403 } 404 405 usbpby_enable_cnt++; 406 if (usbpby_enable_cnt == 1) { 407 rv = hwreset_deassert(sc->reset_pads); 408 if (rv != 0) { 409 device_printf(sc->dev, 410 "Cannot unreset 'utmi-pads' reset\n"); 411 return (rv); 412 } 413 rv = clk_enable(sc->clk_pads); 414 if (rv != 0) { 415 device_printf(sc->dev, 416 "Cannot enable 'utmi-pads' clock\n"); 417 return (rv); 418 } 419 420 val = bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0); 421 val &= ~UTMIP_OTGPD; 422 val &= ~UTMIP_BIASPD; 423 val &= ~UTMIP_HSSQUELCH_LEVEL(~0); 424 val &= ~UTMIP_HSDISCON_LEVEL(~0); 425 val &= ~UTMIP_HSDISCON_LEVEL_MSB(~0); 426 val |= UTMIP_HSSQUELCH_LEVEL(sc->hssquelch_level); 427 val |= UTMIP_HSDISCON_LEVEL(sc->hsdiscon_level); 428 val |= UTMIP_HSDISCON_LEVEL_MSB(sc->hsdiscon_level); 429 bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val); 430 431 rv = clk_disable(sc->clk_pads); 432 if (rv != 0) { 433 device_printf(sc->dev, 434 "Cannot disable 'utmi-pads' clock\n"); 435 return (rv); 436 } 437 } 438 439 val = RD4(sc, UTMIP_XCVR_CFG0); 440 val &= ~UTMIP_FORCE_PD_POWERDOWN; 441 val &= ~UTMIP_FORCE_PD2_POWERDOWN ; 442 val &= ~UTMIP_FORCE_PDZI_POWERDOWN; 443 val &= ~UTMIP_XCVR_LSBIAS_SEL; 444 val &= ~UTMIP_XCVR_LSFSLEW(~0); 445 val &= ~UTMIP_XCVR_LSRSLEW(~0); 446 val &= ~UTMIP_XCVR_HSSLEW(~0); 447 val &= ~UTMIP_XCVR_HSSLEW_MSB(~0); 448 val |= UTMIP_XCVR_LSFSLEW(sc->xcvr_lsfslew); 449 val |= UTMIP_XCVR_LSRSLEW(sc->xcvr_lsrslew); 450 val |= UTMIP_XCVR_HSSLEW(sc->xcvr_hsslew); 451 val |= UTMIP_XCVR_HSSLEW_MSB(sc->xcvr_hsslew); 452 if (!sc->xcvr_setup_use_fuses) { 453 val &= ~UTMIP_XCVR_SETUP(~0); 454 val &= ~UTMIP_XCVR_SETUP_MSB(~0); 455 val |= UTMIP_XCVR_SETUP(sc->xcvr_setup); 456 val |= UTMIP_XCVR_SETUP_MSB(sc->xcvr_setup); 457 } 458 WR4(sc, UTMIP_XCVR_CFG0, val); 459 460 val = RD4(sc, UTMIP_XCVR_CFG1); 461 val &= ~UTMIP_FORCE_PDDISC_POWERDOWN; 462 val &= ~UTMIP_FORCE_PDCHRP_POWERDOWN; 463 val &= ~UTMIP_FORCE_PDDR_POWERDOWN; 464 val &= ~UTMIP_XCVR_TERM_RANGE_ADJ(~0); 465 val |= UTMIP_XCVR_TERM_RANGE_ADJ(sc->term_range_adj); 466 WR4(sc, UTMIP_XCVR_CFG1, val); 467 468 469 val = RD4(sc, UTMIP_BIAS_CFG1); 470 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); 471 val |= UTMIP_BIAS_PDTRK_COUNT(0x5); 472 WR4(sc, UTMIP_BIAS_CFG1, val); 473 474 val = RD4(sc, UTMIP_SPARE_CFG0); 475 if (sc->xcvr_setup_use_fuses) 476 val |= FUSE_SETUP_SEL; 477 else 478 val &= ~FUSE_SETUP_SEL; 479 WR4(sc, UTMIP_SPARE_CFG0, val); 480 481 val = RD4(sc, IF_USB_SUSP_CTRL); 482 val |= UTMIP_PHY_ENB; 483 WR4(sc, IF_USB_SUSP_CTRL, val); 484 485 val = RD4(sc, IF_USB_SUSP_CTRL); 486 val &= ~UTMIP_RESET; 487 WR4(sc, IF_USB_SUSP_CTRL, val); 488 489 usbphy_utmi_phy_clk(sc, true); 490 491 val = RD4(sc, CTRL_USB_USBMODE); 492 val &= ~USB_USBMODE_MASK; 493 if (sc->dr_mode == USB_DR_MODE_HOST) 494 val |= USB_USBMODE_HOST; 495 else 496 val |= USB_USBMODE_DEVICE; 497 WR4(sc, CTRL_USB_USBMODE, val); 498 499 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC); 500 val &= ~USB_HOSTPC1_DEVLC_PTS(~0); 501 val |= USB_HOSTPC1_DEVLC_PTS(0); 502 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val); 503 504 return (0); 505 } 506 507 static int 508 usbphy_utmi_disable(struct usbphy_softc *sc) 509 { 510 int rv; 511 uint32_t val; 512 513 usbphy_utmi_phy_clk(sc, false); 514 515 if (sc->dr_mode == USB_DR_MODE_DEVICE) { 516 val = RD4(sc, IF_USB_SUSP_CTRL); 517 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); 518 val |= USB_WAKE_ON_CNNT_EN_DEV; 519 val |= USB_WAKEUP_DEBOUNCE_COUNT(5); 520 WR4(sc, IF_USB_SUSP_CTRL, val); 521 } 522 523 val = RD4(sc, IF_USB_SUSP_CTRL); 524 val |= UTMIP_RESET; 525 WR4(sc, IF_USB_SUSP_CTRL, val); 526 527 val = RD4(sc, UTMIP_BAT_CHRG_CFG0); 528 val |= UTMIP_PD_CHRG; 529 WR4(sc, UTMIP_BAT_CHRG_CFG0, val); 530 531 val = RD4(sc, UTMIP_XCVR_CFG0); 532 val |= UTMIP_FORCE_PD_POWERDOWN; 533 val |= UTMIP_FORCE_PD2_POWERDOWN; 534 val |= UTMIP_FORCE_PDZI_POWERDOWN; 535 WR4(sc, UTMIP_XCVR_CFG0, val); 536 537 val = RD4(sc, UTMIP_XCVR_CFG1); 538 val |= UTMIP_FORCE_PDDISC_POWERDOWN; 539 val |= UTMIP_FORCE_PDCHRP_POWERDOWN; 540 val |= UTMIP_FORCE_PDDR_POWERDOWN; 541 WR4(sc, UTMIP_XCVR_CFG1, val); 542 543 usbpby_enable_cnt--; 544 if (usbpby_enable_cnt <= 0) { 545 rv = clk_enable(sc->clk_pads); 546 if (rv != 0) { 547 device_printf(sc->dev, 548 "Cannot enable 'utmi-pads' clock\n"); 549 return (rv); 550 } 551 val =bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0); 552 val |= UTMIP_OTGPD; 553 val |= UTMIP_BIASPD; 554 bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val); 555 556 rv = clk_disable(sc->clk_pads); 557 if (rv != 0) { 558 device_printf(sc->dev, 559 "Cannot disable 'utmi-pads' clock\n"); 560 return (rv); 561 } 562 } 563 return (0); 564 } 565 566 static int 567 usbphy_phy_enable(struct phynode *phy, bool enable) 568 { 569 device_t dev; 570 struct usbphy_softc *sc; 571 int rv = 0; 572 573 dev = phynode_get_device(phy); 574 sc = device_get_softc(dev); 575 576 if (sc->ifc_type != USB_IFC_TYPE_UTMI) { 577 device_printf(sc->dev, 578 "Only UTMI interface is supported.\n"); 579 return (ENXIO); 580 } 581 if (enable) 582 rv = usbphy_utmi_enable(sc); 583 else 584 rv = usbphy_utmi_disable(sc); 585 586 return (rv); 587 } 588 589 static enum usb_ifc_type 590 usb_get_ifc_mode(device_t dev, phandle_t node, char *name) 591 { 592 char *tmpstr; 593 int rv; 594 enum usb_ifc_type ret; 595 596 rv = OF_getprop_alloc(node, name, (void **)&tmpstr); 597 if (rv <= 0) 598 return (USB_IFC_TYPE_UNKNOWN); 599 600 ret = USB_IFC_TYPE_UNKNOWN; 601 if (strcmp(tmpstr, "utmi") == 0) 602 ret = USB_IFC_TYPE_UTMI; 603 else if (strcmp(tmpstr, "ulpi") == 0) 604 ret = USB_IFC_TYPE_ULPI; 605 else 606 device_printf(dev, "Unsupported phy type: %s\n", tmpstr); 607 OF_prop_free(tmpstr); 608 return (ret); 609 } 610 611 static enum usb_dr_mode 612 usb_get_dr_mode(device_t dev, phandle_t node, char *name) 613 { 614 char *tmpstr; 615 int rv; 616 enum usb_dr_mode ret; 617 618 rv = OF_getprop_alloc(node, name, (void **)&tmpstr); 619 if (rv <= 0) 620 return (USB_DR_MODE_UNKNOWN); 621 622 ret = USB_DR_MODE_UNKNOWN; 623 if (strcmp(tmpstr, "device") == 0) 624 ret = USB_DR_MODE_DEVICE; 625 else if (strcmp(tmpstr, "host") == 0) 626 ret = USB_DR_MODE_HOST; 627 else if (strcmp(tmpstr, "otg") == 0) 628 ret = USB_DR_MODE_OTG; 629 else 630 device_printf(dev, "Unknown dr mode: %s\n", tmpstr); 631 OF_prop_free(tmpstr); 632 return (ret); 633 } 634 635 static int 636 usbphy_utmi_read_params(struct usbphy_softc *sc, phandle_t node) 637 { 638 int rv; 639 640 rv = OF_getencprop(node, "nvidia,hssync-start-delay", 641 &sc->hssync_start_delay, sizeof (sc->hssync_start_delay)); 642 if (rv <= 0) 643 return (ENXIO); 644 645 rv = OF_getencprop(node, "nvidia,elastic-limit", 646 &sc->elastic_limit, sizeof (sc->elastic_limit)); 647 if (rv <= 0) 648 return (ENXIO); 649 650 rv = OF_getencprop(node, "nvidia,idle-wait-delay", 651 &sc->idle_wait_delay, sizeof (sc->idle_wait_delay)); 652 if (rv <= 0) 653 return (ENXIO); 654 655 rv = OF_getencprop(node, "nvidia,term-range-adj", 656 &sc->term_range_adj, sizeof (sc->term_range_adj)); 657 if (rv <= 0) 658 return (ENXIO); 659 660 rv = OF_getencprop(node, "nvidia,xcvr-lsfslew", 661 &sc->xcvr_lsfslew, sizeof (sc->xcvr_lsfslew)); 662 if (rv <= 0) 663 return (ENXIO); 664 665 rv = OF_getencprop(node, "nvidia,xcvr-lsrslew", 666 &sc->xcvr_lsrslew, sizeof (sc->xcvr_lsrslew)); 667 if (rv <= 0) 668 return (ENXIO); 669 670 rv = OF_getencprop(node, "nvidia,xcvr-hsslew", 671 &sc->xcvr_hsslew, sizeof (sc->xcvr_hsslew)); 672 if (rv <= 0) 673 return (ENXIO); 674 675 rv = OF_getencprop(node, "nvidia,hssquelch-level", 676 &sc->hssquelch_level, sizeof (sc->hssquelch_level)); 677 if (rv <= 0) 678 return (ENXIO); 679 680 rv = OF_getencprop(node, "nvidia,hsdiscon-level", 681 &sc->hsdiscon_level, sizeof (sc->hsdiscon_level)); 682 if (rv <= 0) 683 return (ENXIO); 684 685 rv = OF_getproplen(node, "nvidia,xcvr-setup-use-fuses"); 686 if (rv >= 1) { 687 sc->xcvr_setup_use_fuses = 1; 688 } else { 689 rv = OF_getencprop(node, "nvidia,xcvr-setup", 690 &sc->xcvr_setup, sizeof (sc->xcvr_setup)); 691 if (rv <= 0) 692 return (ENXIO); 693 } 694 695 return (0); 696 } 697 698 static int 699 usbphy_probe(device_t dev) 700 { 701 702 if (!ofw_bus_status_okay(dev)) 703 return (ENXIO); 704 705 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 706 return (ENXIO); 707 708 device_set_desc(dev, "Tegra USB phy"); 709 return (BUS_PROBE_DEFAULT); 710 } 711 712 static int 713 usbphy_attach(device_t dev) 714 { 715 struct usbphy_softc *sc; 716 int rid, rv; 717 phandle_t node; 718 struct phynode *phynode; 719 struct phynode_init_def phy_init; 720 721 sc = device_get_softc(dev); 722 sc->dev = dev; 723 724 rid = 0; 725 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 726 RF_ACTIVE | RF_SHAREABLE); 727 if (sc->mem_res == NULL) { 728 device_printf(dev, "Cannot allocate memory resources\n"); 729 return (ENXIO); 730 } 731 732 rid = 1; 733 sc->pads_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 734 RF_ACTIVE | RF_SHAREABLE); 735 if (sc->mem_res == NULL) { 736 device_printf(dev, "Cannot allocate memory resources\n"); 737 return (ENXIO); 738 } 739 740 node = ofw_bus_get_node(dev); 741 742 rv = hwreset_get_by_ofw_name(sc->dev, 0, "usb", &sc->reset_usb); 743 if (rv != 0) { 744 device_printf(dev, "Cannot get 'usb' reset\n"); 745 return (ENXIO); 746 } 747 rv = hwreset_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->reset_pads); 748 if (rv != 0) { 749 device_printf(dev, "Cannot get 'utmi-pads' reset\n"); 750 return (ENXIO); 751 } 752 753 rv = clk_get_by_ofw_name(sc->dev, 0, "reg", &sc->clk_reg); 754 if (rv != 0) { 755 device_printf(sc->dev, "Cannot get 'reg' clock\n"); 756 return (ENXIO); 757 } 758 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_u", &sc->clk_pllu); 759 if (rv != 0) { 760 device_printf(sc->dev, "Cannot get 'pll_u' clock\n"); 761 return (ENXIO); 762 } 763 rv = clk_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->clk_pads); 764 if (rv != 0) { 765 device_printf(sc->dev, "Cannot get 'utmi-pads' clock\n"); 766 return (ENXIO); 767 } 768 769 rv = hwreset_deassert(sc->reset_usb); 770 if (rv != 0) { 771 device_printf(dev, "Cannot unreset 'usb' reset\n"); 772 return (ENXIO); 773 } 774 775 rv = clk_enable(sc->clk_pllu); 776 if (rv != 0) { 777 device_printf(sc->dev, "Cannot enable 'pllu' clock\n"); 778 return (ENXIO); 779 } 780 rv = clk_enable(sc->clk_reg); 781 if (rv != 0) { 782 device_printf(sc->dev, "Cannot enable 'reg' clock\n"); 783 return (ENXIO); 784 } 785 if (OF_hasprop(node, "nvidia,has-utmi-pad-registers")) 786 sc->have_utmi_regs = true; 787 788 sc->dr_mode = usb_get_dr_mode(dev, node, "dr_mode"); 789 if (sc->dr_mode == USB_DR_MODE_UNKNOWN) 790 sc->dr_mode = USB_DR_MODE_HOST; 791 792 sc->ifc_type = usb_get_ifc_mode(dev, node, "phy_type"); 793 794 /* We supports only utmi phy mode for now .... */ 795 if (sc->ifc_type != USB_IFC_TYPE_UTMI) { 796 device_printf(dev, "Unsupported phy type\n"); 797 return (ENXIO); 798 } 799 rv = usbphy_utmi_read_params(sc, node); 800 if (rv < 0) 801 return rv; 802 803 if (OF_hasprop(node, "vbus-supply")) { 804 rv = regulator_get_by_ofw_property(sc->dev, 0, "vbus-supply", 805 &sc->supply_vbus); 806 if (rv != 0) { 807 device_printf(sc->dev, 808 "Cannot get \"vbus\" regulator\n"); 809 return (ENXIO); 810 } 811 rv = regulator_enable(sc->supply_vbus); 812 if (rv != 0) { 813 device_printf(sc->dev, 814 "Cannot enable \"vbus\" regulator\n"); 815 return (rv); 816 } 817 } 818 819 /* Create and register phy. */ 820 bzero(&phy_init, sizeof(phy_init)); 821 phy_init.id = 1; 822 phy_init.ofw_node = node; 823 phynode = phynode_create(dev, &usbphy_phynode_class, &phy_init); 824 if (phynode == NULL) { 825 device_printf(sc->dev, "Cannot create phy\n"); 826 return (ENXIO); 827 } 828 if (phynode_register(phynode) == NULL) { 829 device_printf(sc->dev, "Cannot create phy\n"); 830 return (ENXIO); 831 } 832 833 return (0); 834 } 835 836 static int 837 usbphy_detach(device_t dev) 838 { 839 840 /* This device is always present. */ 841 return (EBUSY); 842 } 843 844 static device_method_t tegra_usbphy_methods[] = { 845 /* Device interface */ 846 DEVMETHOD(device_probe, usbphy_probe), 847 DEVMETHOD(device_attach, usbphy_attach), 848 DEVMETHOD(device_detach, usbphy_detach), 849 850 DEVMETHOD_END 851 }; 852 853 static devclass_t tegra_usbphy_devclass; 854 static DEFINE_CLASS_0(usbphy, tegra_usbphy_driver, tegra_usbphy_methods, 855 sizeof(struct usbphy_softc)); 856 EARLY_DRIVER_MODULE(tegra_usbphy, simplebus, tegra_usbphy_driver, 857 tegra_usbphy_devclass, NULL, NULL, 79); 858