1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * XHCI driver for Tegra SoCs. 32 */ 33 #include "opt_bus.h" 34 #include "opt_platform.h" 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/clock.h> 39 #include <sys/condvar.h> 40 #include <sys/firmware.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/systm.h> 48 49 #include <vm/vm.h> 50 #include <vm/vm_extern.h> 51 #include <vm/vm_kern.h> 52 #include <vm/pmap.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 57 58 #include <dev/extres/clk/clk.h> 59 #include <dev/extres/hwreset/hwreset.h> 60 #include <dev/extres/phy/phy.h> 61 #include <dev/extres/regulator/regulator.h> 62 #include <dev/ofw/ofw_bus.h> 63 #include <dev/ofw/ofw_bus_subr.h> 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usb_busdma.h> 67 #include <dev/usb/usb_process.h> 68 #include <dev/usb/usb_controller.h> 69 #include <dev/usb/usb_bus.h> 70 #include <dev/usb/controller/xhci.h> 71 #include <dev/usb/controller/xhcireg.h> 72 73 #include <arm/nvidia/tegra_pmc.h> 74 75 #include "usbdevs.h" 76 77 /* FPCI address space */ 78 #define T_XUSB_CFG_0 0x000 79 #define T_XUSB_CFG_1 0x004 80 #define CFG_1_BUS_MASTER (1 << 2) 81 #define CFG_1_MEMORY_SPACE (1 << 1) 82 #define CFG_1_IO_SPACE (1 << 0) 83 84 #define T_XUSB_CFG_2 0x008 85 #define T_XUSB_CFG_3 0x00C 86 #define T_XUSB_CFG_4 0x010 87 #define CFG_4_BASE_ADDRESS(x) (((x) & 0x1FFFF) << 15) 88 89 #define T_XUSB_CFG_5 0x014 90 #define T_XUSB_CFG_ARU_MAILBOX_CMD 0x0E4 91 #define ARU_MAILBOX_CMD_INT_EN (1U << 31) 92 #define ARU_MAILBOX_CMD_DEST_XHCI (1 << 30) 93 #define ARU_MAILBOX_CMD_DEST_SMI (1 << 29) 94 #define ARU_MAILBOX_CMD_DEST_PME (1 << 28) 95 #define ARU_MAILBOX_CMD_DEST_FALC (1 << 27) 96 97 #define T_XUSB_CFG_ARU_MAILBOX_DATA_IN 0x0E8 98 #define ARU_MAILBOX_DATA_IN_DATA(x) (((x) & 0xFFFFFF) << 0) 99 #define ARU_MAILBOX_DATA_IN_TYPE(x) (((x) & 0x0000FF) << 24) 100 101 #define T_XUSB_CFG_ARU_MAILBOX_DATA_OUT 0x0EC 102 #define ARU_MAILBOX_DATA_OUT_DATA(x) (((x) >> 0) & 0xFFFFFF) 103 #define ARU_MAILBOX_DATA_OUT_TYPE(x) (((x) >> 24) & 0x0000FF) 104 105 #define T_XUSB_CFG_ARU_MAILBOX_OWNER 0x0F0 106 #define ARU_MAILBOX_OWNER_SW 2 107 #define ARU_MAILBOX_OWNER_FW 1 108 #define ARU_MAILBOX_OWNER_NONE 0 109 110 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41C /* ! UNDOCUMENTED ! */ 111 #define ARU_C11_CSBRANGE_PAGE(x) ((x) >> 9) 112 #define ARU_C11_CSBRANGE_ADDR(x) (0x800 + ((x) & 0x1FF)) 113 #define XUSB_CFG_ARU_SMI_INTR 0x428 /* ! UNDOCUMENTED ! */ 114 #define ARU_SMI_INTR_EN (1 << 3) 115 #define ARU_SMI_INTR_FW_HANG (1 << 1) 116 #define XUSB_CFG_ARU_RST 0x42C /* ! UNDOCUMENTED ! */ 117 #define ARU_RST_RESET (1 << 0) 118 119 #define XUSB_HOST_CONFIGURATION 0x180 120 #define CONFIGURATION_CLKEN_OVERRIDE (1U<< 31) 121 #define CONFIGURATION_PW_NO_DEVSEL_ERR_CYA (1 << 19) 122 #define CONFIGURATION_INITIATOR_READ_IDLE (1 << 18) 123 #define CONFIGURATION_INITIATOR_WRITE_IDLE (1 << 17) 124 #define CONFIGURATION_WDATA_LEAD_CYA (1 << 15) 125 #define CONFIGURATION_WR_INTRLV_CYA (1 << 14) 126 #define CONFIGURATION_TARGET_READ_IDLE (1 << 11) 127 #define CONFIGURATION_TARGET_WRITE_IDLE (1 << 10) 128 #define CONFIGURATION_MSI_VEC_EMPTY (1 << 9) 129 #define CONFIGURATION_UFPCI_MSIAW (1 << 7) 130 #define CONFIGURATION_UFPCI_PWPASSPW (1 << 6) 131 #define CONFIGURATION_UFPCI_PASSPW (1 << 5) 132 #define CONFIGURATION_UFPCI_PWPASSNPW (1 << 4) 133 #define CONFIGURATION_DFPCI_PWPASSNPW (1 << 3) 134 #define CONFIGURATION_DFPCI_RSPPASSPW (1 << 2) 135 #define CONFIGURATION_DFPCI_PASSPW (1 << 1) 136 #define CONFIGURATION_EN_FPCI (1 << 0) 137 138 /* IPFS address space */ 139 #define XUSB_HOST_FPCI_ERROR_MASKS 0x184 140 #define FPCI_ERROR_MASTER_ABORT (1 << 2) 141 #define FPCI_ERRORI_DATA_ERROR (1 << 1) 142 #define FPCI_ERROR_TARGET_ABORT (1 << 0) 143 144 #define XUSB_HOST_INTR_MASK 0x188 145 #define INTR_IP_INT_MASK (1 << 16) 146 #define INTR_MSI_MASK (1 << 8) 147 #define INTR_INT_MASK (1 << 0) 148 149 #define XUSB_HOST_CLKGATE_HYSTERESIS 0x1BC 150 151 /* CSB Falcon CPU */ 152 #define XUSB_FALCON_CPUCTL 0x100 153 #define CPUCTL_STOPPED (1 << 5) 154 #define CPUCTL_HALTED (1 << 4) 155 #define CPUCTL_HRESET (1 << 3) 156 #define CPUCTL_SRESET (1 << 2) 157 #define CPUCTL_STARTCPU (1 << 1) 158 #define CPUCTL_IINVAL (1 << 0) 159 160 #define XUSB_FALCON_BOOTVEC 0x104 161 #define XUSB_FALCON_DMACTL 0x10C 162 #define XUSB_FALCON_IMFILLRNG1 0x154 163 #define IMFILLRNG1_TAG_HI(x) (((x) & 0xFFF) << 16) 164 #define IMFILLRNG1_TAG_LO(x) (((x) & 0xFFF) << 0) 165 #define XUSB_FALCON_IMFILLCTL 0x158 166 167 /* CSB mempool */ 168 #define XUSB_CSB_MEMPOOL_APMAP 0x10181C 169 #define APMAP_BOOTPATH (1U << 31) 170 171 #define XUSB_CSB_MEMPOOL_ILOAD_ATTR 0x101A00 172 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_LO 0x101A04 173 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_HI 0x101A08 174 #define XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE 0x101A10 175 #define L2IMEMOP_SIZE_OFFSET(x) (((x) & 0x3FF) << 8) 176 #define L2IMEMOP_SIZE_SIZE(x) (((x) & 0x0FF) << 24) 177 178 #define XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG 0x101A14 179 #define L2IMEMOP_INVALIDATE_ALL (0x40 << 24) 180 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << 24) 181 182 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101A18 183 #define L2IMEMOP_RESULT_VLD (1U << 31) 184 185 #define XUSB_CSB_IMEM_BLOCK_SIZE 256 186 187 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000 188 #define TEGRA_XHCI_SS_LOW_SPEED 12000000 189 190 /* MBOX commands. */ 191 #define MBOX_CMD_MSG_ENABLED 1 192 #define MBOX_CMD_INC_FALC_CLOCK 2 193 #define MBOX_CMD_DEC_FALC_CLOCK 3 194 #define MBOX_CMD_INC_SSPI_CLOCK 4 195 #define MBOX_CMD_DEC_SSPI_CLOCK 5 196 #define MBOX_CMD_SET_BW 6 197 #define MBOX_CMD_SET_SS_PWR_GATING 7 198 #define MBOX_CMD_SET_SS_PWR_UNGATING 8 199 #define MBOX_CMD_SAVE_DFE_CTLE_CTX 9 200 #define MBOX_CMD_AIRPLANE_MODE_ENABLED 10 201 #define MBOX_CMD_AIRPLANE_MODE_DISABLED 11 202 #define MBOX_CMD_START_HSIC_IDLE 12 203 #define MBOX_CMD_STOP_HSIC_IDLE 13 204 #define MBOX_CMD_DBC_WAKE_STACK 14 205 #define MBOX_CMD_HSIC_PRETEND_CONNECT 15 206 #define MBOX_CMD_RESET_SSPI 16 207 #define MBOX_CMD_DISABLE_SS_LFPS_DETECTION 17 208 #define MBOX_CMD_ENABLE_SS_LFPS_DETECTION 18 209 210 /* MBOX responses. */ 211 #define MBOX_CMD_ACK (0x80 + 0) 212 #define MBOX_CMD_NAK (0x80 + 1) 213 214 215 #define IPFS_WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res_ipfs, (_r), (_v)) 216 #define IPFS_RD4(_sc, _r) bus_read_4((_sc)->mem_res_ipfs, (_r)) 217 #define FPCI_WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res_fpci, (_r), (_v)) 218 #define FPCI_RD4(_sc, _r) bus_read_4((_sc)->mem_res_fpci, (_r)) 219 220 #define LOCK(_sc) mtx_lock(&(_sc)->mtx) 221 #define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 222 #define SLEEP(_sc, timeout) \ 223 mtx_sleep(sc, &sc->mtx, 0, "tegra_xhci", timeout); 224 #define LOCK_INIT(_sc) \ 225 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_xhci", MTX_DEF) 226 #define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx) 227 #define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED) 228 #define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED) 229 230 struct tegra_xusb_fw_hdr { 231 uint32_t boot_loadaddr_in_imem; 232 uint32_t boot_codedfi_offset; 233 uint32_t boot_codetag; 234 uint32_t boot_codesize; 235 236 uint32_t phys_memaddr; 237 uint16_t reqphys_memsize; 238 uint16_t alloc_phys_memsize; 239 240 uint32_t rodata_img_offset; 241 uint32_t rodata_section_start; 242 uint32_t rodata_section_end; 243 uint32_t main_fnaddr; 244 245 uint32_t fwimg_cksum; 246 uint32_t fwimg_created_time; 247 248 uint32_t imem_resident_start; 249 uint32_t imem_resident_end; 250 uint32_t idirect_start; 251 uint32_t idirect_end; 252 uint32_t l2_imem_start; 253 uint32_t l2_imem_end; 254 uint32_t version_id; 255 uint8_t init_ddirect; 256 uint8_t reserved[3]; 257 uint32_t phys_addr_log_buffer; 258 uint32_t total_log_entries; 259 uint32_t dequeue_ptr; 260 uint32_t dummy[2]; 261 uint32_t fwimg_len; 262 uint8_t magic[8]; 263 uint32_t ss_low_power_entry_timeout; 264 uint8_t num_hsic_port; 265 uint8_t ss_portmap; 266 uint8_t build; 267 uint8_t padding[137]; /* Pad to 256 bytes */ 268 }; 269 270 /* Compatible devices. */ 271 static struct ofw_compat_data compat_data[] = { 272 {"nvidia,tegra124-xusb", 1}, 273 {NULL, 0} 274 }; 275 276 struct tegra_xhci_softc { 277 struct xhci_softc xhci_softc; 278 device_t dev; 279 struct mtx mtx; 280 struct resource *mem_res_fpci; 281 struct resource *mem_res_ipfs; 282 struct resource *irq_res_mbox; 283 void *irq_hdl_mbox; 284 285 clk_t clk_xusb_host; 286 clk_t clk_xusb_gate; 287 clk_t clk_xusb_falcon_src; 288 clk_t clk_xusb_ss; 289 clk_t clk_xusb_hs_src; 290 clk_t clk_xusb_fs_src; 291 hwreset_t hwreset_xusb_host; 292 hwreset_t hwreset_xusb_ss; 293 regulator_t supply_avddio_pex; 294 regulator_t supply_dvddio_pex; 295 regulator_t supply_avdd_usb; 296 regulator_t supply_avdd_pll_utmip; 297 regulator_t supply_avdd_pll_erefe; 298 regulator_t supply_avdd_usb_ss_pll; 299 regulator_t supply_hvdd_usb_ss; 300 regulator_t supply_hvdd_usb_ss_pll_e; 301 phy_t phy_usb2_0; 302 phy_t phy_usb2_1; 303 phy_t phy_usb2_2; 304 phy_t phy_usb3_0; 305 306 struct intr_config_hook irq_hook; 307 bool xhci_inited; 308 char *fw_name; 309 vm_offset_t fw_vaddr; 310 vm_size_t fw_size; 311 }; 312 313 static uint32_t 314 CSB_RD4(struct tegra_xhci_softc *sc, uint32_t addr) 315 { 316 317 FPCI_WR4(sc, XUSB_CFG_ARU_C11_CSBRANGE, ARU_C11_CSBRANGE_PAGE(addr)); 318 return (FPCI_RD4(sc, ARU_C11_CSBRANGE_ADDR(addr))); 319 } 320 321 static void 322 CSB_WR4(struct tegra_xhci_softc *sc, uint32_t addr, uint32_t val) 323 { 324 325 FPCI_WR4(sc, XUSB_CFG_ARU_C11_CSBRANGE, ARU_C11_CSBRANGE_PAGE(addr)); 326 FPCI_WR4(sc, ARU_C11_CSBRANGE_ADDR(addr), val); 327 } 328 329 static int 330 get_fdt_resources(struct tegra_xhci_softc *sc, phandle_t node) 331 { 332 int rv; 333 334 rv = regulator_get_by_ofw_property(sc->dev, 0, "avddio-pex-supply", 335 &sc->supply_avddio_pex); 336 if (rv != 0) { 337 device_printf(sc->dev, 338 "Cannot get 'avddio-pex' regulator\n"); 339 return (ENXIO); 340 } 341 rv = regulator_get_by_ofw_property(sc->dev, 0, "dvddio-pex-supply", 342 &sc->supply_dvddio_pex); 343 if (rv != 0) { 344 device_printf(sc->dev, 345 "Cannot get 'dvddio-pex' regulator\n"); 346 return (ENXIO); 347 } 348 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-usb-supply", 349 &sc->supply_avdd_usb); 350 if (rv != 0) { 351 device_printf(sc->dev, 352 "Cannot get 'avdd-usb' regulator\n"); 353 return (ENXIO); 354 } 355 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-utmip-supply", 356 &sc->supply_avdd_pll_utmip); 357 if (rv != 0) { 358 device_printf(sc->dev, 359 "Cannot get 'avdd-pll-utmip' regulator\n"); 360 return (ENXIO); 361 } 362 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-erefe-supply", 363 &sc->supply_avdd_pll_erefe); 364 if (rv != 0) { 365 device_printf(sc->dev, 366 "Cannot get 'avdd-pll-erefe' regulator\n"); 367 return (ENXIO); 368 } 369 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-usb-ss-pll-supply", 370 &sc->supply_avdd_usb_ss_pll); 371 if (rv != 0) { 372 device_printf(sc->dev, 373 "Cannot get 'avdd-usb-ss-pll' regulator\n"); 374 return (ENXIO); 375 } 376 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-usb-ss-supply", 377 &sc->supply_hvdd_usb_ss); 378 if (rv != 0) { 379 device_printf(sc->dev, 380 "Cannot get 'hvdd-usb-ss' regulator\n"); 381 return (ENXIO); 382 } 383 rv = regulator_get_by_ofw_property(sc->dev, 0, 384 "hvdd-usb-ss-pll-e-supply", &sc->supply_hvdd_usb_ss_pll_e); 385 if (rv != 0) { 386 device_printf(sc->dev, 387 "Cannot get 'hvdd-usb-ss-pll-e' regulator\n"); 388 return (ENXIO); 389 } 390 391 rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_host", 392 &sc->hwreset_xusb_host); 393 if (rv != 0) { 394 device_printf(sc->dev, "Cannot get 'xusb_host' reset\n"); 395 return (ENXIO); 396 } 397 rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_ss", 398 &sc->hwreset_xusb_ss); 399 if (rv != 0) { 400 device_printf(sc->dev, "Cannot get 'xusb_ss' reset\n"); 401 return (ENXIO); 402 } 403 404 rv = phy_get_by_ofw_name(sc->dev, 0, "usb2-0", &sc->phy_usb2_0); 405 if (rv != 0) { 406 device_printf(sc->dev, "Cannot get 'usb2-0' phy\n"); 407 return (ENXIO); 408 } 409 rv = phy_get_by_ofw_name(sc->dev, 0, "usb2-1", &sc->phy_usb2_1); 410 if (rv != 0) { 411 device_printf(sc->dev, "Cannot get 'usb2-1' phy\n"); 412 return (ENXIO); 413 } 414 rv = phy_get_by_ofw_name(sc->dev, 0, "usb2-2", &sc->phy_usb2_2); 415 if (rv != 0) { 416 device_printf(sc->dev, "Cannot get 'usb2-2' phy\n"); 417 return (ENXIO); 418 } 419 rv = phy_get_by_ofw_name(sc->dev, 0, "usb3-0", &sc->phy_usb3_0); 420 if (rv != 0) { 421 device_printf(sc->dev, "Cannot get 'usb3-0' phy\n"); 422 return (ENXIO); 423 } 424 425 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_host", 426 &sc->clk_xusb_host); 427 if (rv != 0) { 428 device_printf(sc->dev, "Cannot get 'xusb_host' clock\n"); 429 return (ENXIO); 430 } 431 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_falcon_src", 432 &sc->clk_xusb_falcon_src); 433 if (rv != 0) { 434 device_printf(sc->dev, "Cannot get 'xusb_falcon_src' clock\n"); 435 return (ENXIO); 436 } 437 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_ss", 438 &sc->clk_xusb_ss); 439 if (rv != 0) { 440 device_printf(sc->dev, "Cannot get 'xusb_ss' clock\n"); 441 return (ENXIO); 442 } 443 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_hs_src", 444 &sc->clk_xusb_hs_src); 445 if (rv != 0) { 446 device_printf(sc->dev, "Cannot get 'xusb_hs_src' clock\n"); 447 return (ENXIO); 448 } 449 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_fs_src", 450 &sc->clk_xusb_fs_src); 451 if (rv != 0) { 452 device_printf(sc->dev, "Cannot get 'xusb_fs_src' clock\n"); 453 return (ENXIO); 454 } 455 rv = clk_get_by_ofw_index_prop(sc->dev, 0, "freebsd,clock-xusb-gate", 0, 456 &sc->clk_xusb_gate); 457 if (rv != 0) { 458 device_printf(sc->dev, "Cannot get 'xusb_gate' clock\n"); 459 return (ENXIO); 460 } 461 return (0); 462 } 463 464 static int 465 enable_fdt_resources(struct tegra_xhci_softc *sc) 466 { 467 int rv; 468 469 rv = hwreset_assert(sc->hwreset_xusb_host); 470 if (rv != 0) { 471 device_printf(sc->dev, "Cannot reset 'xusb_host' reset\n"); 472 return (rv); 473 } 474 rv = hwreset_assert(sc->hwreset_xusb_ss); 475 if (rv != 0) { 476 device_printf(sc->dev, "Cannot reset 'xusb_ss' reset\n"); 477 return (rv); 478 } 479 480 rv = regulator_enable(sc->supply_avddio_pex); 481 if (rv != 0) { 482 device_printf(sc->dev, 483 "Cannot enable 'avddio_pex' regulator\n"); 484 return (rv); 485 } 486 rv = regulator_enable(sc->supply_dvddio_pex); 487 if (rv != 0) { 488 device_printf(sc->dev, 489 "Cannot enable 'dvddio_pex' regulator\n"); 490 return (rv); 491 } 492 rv = regulator_enable(sc->supply_avdd_usb); 493 if (rv != 0) { 494 device_printf(sc->dev, 495 "Cannot enable 'avdd_usb' regulator\n"); 496 return (rv); 497 } 498 rv = regulator_enable(sc->supply_avdd_pll_utmip); 499 if (rv != 0) { 500 device_printf(sc->dev, 501 "Cannot enable 'avdd_pll_utmip-5v' regulator\n"); 502 return (rv); 503 } 504 rv = regulator_enable(sc->supply_avdd_pll_erefe); 505 if (rv != 0) { 506 device_printf(sc->dev, 507 "Cannot enable 'avdd_pll_erefe' regulator\n"); 508 return (rv); 509 } 510 rv = regulator_enable(sc->supply_avdd_usb_ss_pll); 511 if (rv != 0) { 512 device_printf(sc->dev, 513 "Cannot enable 'avdd_usb_ss_pll' regulator\n"); 514 return (rv); 515 } 516 rv = regulator_enable(sc->supply_hvdd_usb_ss); 517 if (rv != 0) { 518 device_printf(sc->dev, 519 "Cannot enable 'hvdd_usb_ss' regulator\n"); 520 return (rv); 521 } 522 rv = regulator_enable(sc->supply_hvdd_usb_ss_pll_e); 523 if (rv != 0) { 524 device_printf(sc->dev, 525 "Cannot enable 'hvdd_usb_ss_pll_e' regulator\n"); 526 return (rv); 527 } 528 529 /* Power off XUSB host and XUSB SS domains. */ 530 rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 531 if (rv != 0) { 532 device_printf(sc->dev, "Cannot powerdown 'xusba' domain\n"); 533 return (rv); 534 } 535 rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); 536 if (rv != 0) { 537 device_printf(sc->dev, "Cannot powerdown 'xusbc' domain\n"); 538 return (rv); 539 } 540 541 /* Setup XUSB ss_src clock first */ 542 clk_set_freq(sc->clk_xusb_ss, TEGRA_XHCI_SS_HIGH_SPEED, 0); 543 if (rv != 0) 544 return (rv); 545 546 /* The XUSB gate clock must be enabled before XUSBA can be powered. */ 547 rv = clk_enable(sc->clk_xusb_gate); 548 if (rv != 0) { 549 device_printf(sc->dev, 550 "Cannot enable 'xusb_gate' clock\n"); 551 return (rv); 552 } 553 554 /* Power on XUSB host and XUSB SS domains. */ 555 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, 556 sc->clk_xusb_host, sc->hwreset_xusb_host); 557 if (rv != 0) { 558 device_printf(sc->dev, "Cannot powerup 'xusbc' domain\n"); 559 return (rv); 560 } 561 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA, 562 sc->clk_xusb_ss, sc->hwreset_xusb_ss); 563 if (rv != 0) { 564 device_printf(sc->dev, "Cannot powerup 'xusba' domain\n"); 565 return (rv); 566 } 567 568 /* Enable rest of clocks */ 569 rv = clk_enable(sc->clk_xusb_falcon_src); 570 if (rv != 0) { 571 device_printf(sc->dev, 572 "Cannot enable 'xusb_falcon_src' clock\n"); 573 return (rv); 574 } 575 rv = clk_enable(sc->clk_xusb_fs_src); 576 if (rv != 0) { 577 device_printf(sc->dev, 578 "Cannot enable 'xusb_fs_src' clock\n"); 579 return (rv); 580 } 581 rv = clk_enable(sc->clk_xusb_hs_src); 582 if (rv != 0) { 583 device_printf(sc->dev, 584 "Cannot enable 'xusb_hs_src' clock\n"); 585 return (rv); 586 } 587 588 rv = phy_enable(sc->phy_usb2_0); 589 if (rv != 0) { 590 device_printf(sc->dev, "Cannot enable USB2_0 phy\n"); 591 return (rv); 592 } 593 rv = phy_enable(sc->phy_usb2_1); 594 if (rv != 0) { 595 device_printf(sc->dev, "Cannot enable USB2_1 phy\n"); 596 return (rv); 597 } 598 rv = phy_enable(sc->phy_usb2_2); 599 if (rv != 0) { 600 device_printf(sc->dev, "Cannot enable USB2_2 phy\n"); 601 return (rv); 602 } 603 rv = phy_enable(sc->phy_usb3_0); 604 if (rv != 0) { 605 device_printf(sc->dev, "Cannot enable USB3_0 phy\n"); 606 return (rv); 607 } 608 609 return (0); 610 } 611 612 /* Respond by ACK/NAK back to FW */ 613 static void 614 mbox_send_ack(struct tegra_xhci_softc *sc, uint32_t cmd, uint32_t data) 615 { 616 uint32_t reg; 617 618 reg = ARU_MAILBOX_DATA_IN_TYPE(cmd) | ARU_MAILBOX_DATA_IN_DATA(data); 619 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg); 620 621 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD); 622 reg |= ARU_MAILBOX_CMD_DEST_FALC | ARU_MAILBOX_CMD_INT_EN; 623 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg); 624 } 625 626 /* Sent command to FW */ 627 static int 628 mbox_send_cmd(struct tegra_xhci_softc *sc, uint32_t cmd, uint32_t data) 629 { 630 uint32_t reg; 631 int i; 632 633 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER); 634 if (reg != ARU_MAILBOX_OWNER_NONE) { 635 device_printf(sc->dev, 636 "CPU mailbox is busy: 0x%08X\n", reg); 637 return (EBUSY); 638 } 639 /* XXX Is this right? Retry loop? Wait before send? */ 640 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER, ARU_MAILBOX_OWNER_SW); 641 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER); 642 if (reg != ARU_MAILBOX_OWNER_SW) { 643 device_printf(sc->dev, 644 "Cannot acquire CPU mailbox: 0x%08X\n", reg); 645 return (EBUSY); 646 } 647 reg = ARU_MAILBOX_DATA_IN_TYPE(cmd) | ARU_MAILBOX_DATA_IN_DATA(data); 648 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg); 649 650 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD); 651 reg |= ARU_MAILBOX_CMD_DEST_FALC | ARU_MAILBOX_CMD_INT_EN; 652 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg); 653 654 for (i = 250; i > 0; i--) { 655 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER); 656 if (reg == ARU_MAILBOX_OWNER_NONE) 657 break; 658 DELAY(100); 659 } 660 if (i <= 0) { 661 device_printf(sc->dev, 662 "Command response timeout: 0x%08X\n", reg); 663 return (ETIMEDOUT); 664 } 665 666 return(0); 667 } 668 669 static void 670 process_msg(struct tegra_xhci_softc *sc, uint32_t req_cmd, uint32_t req_data, 671 uint32_t *resp_cmd, uint32_t *resp_data) 672 { 673 uint64_t freq; 674 int rv; 675 676 /* In most cases, data are echoed back. */ 677 *resp_data = req_data; 678 switch (req_cmd) { 679 case MBOX_CMD_INC_FALC_CLOCK: 680 case MBOX_CMD_DEC_FALC_CLOCK: 681 rv = clk_set_freq(sc->clk_xusb_falcon_src, req_data * 1000ULL, 682 0); 683 if (rv == 0) { 684 rv = clk_get_freq(sc->clk_xusb_falcon_src, &freq); 685 *resp_data = (uint32_t)(freq / 1000); 686 } 687 *resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK; 688 break; 689 690 case MBOX_CMD_INC_SSPI_CLOCK: 691 case MBOX_CMD_DEC_SSPI_CLOCK: 692 rv = clk_set_freq(sc->clk_xusb_ss, req_data * 1000ULL, 693 0); 694 if (rv == 0) { 695 rv = clk_get_freq(sc->clk_xusb_ss, &freq); 696 *resp_data = (uint32_t)(freq / 1000); 697 } 698 *resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK; 699 break; 700 701 case MBOX_CMD_SET_BW: 702 /* No respense is expected. */ 703 *resp_cmd = 0; 704 break; 705 706 case MBOX_CMD_SET_SS_PWR_GATING: 707 case MBOX_CMD_SET_SS_PWR_UNGATING: 708 *resp_cmd = MBOX_CMD_NAK; 709 break; 710 711 case MBOX_CMD_SAVE_DFE_CTLE_CTX: 712 /* Not implemented yet. */ 713 *resp_cmd = MBOX_CMD_ACK; 714 break; 715 716 717 case MBOX_CMD_START_HSIC_IDLE: 718 case MBOX_CMD_STOP_HSIC_IDLE: 719 /* Not implemented yet. */ 720 *resp_cmd = MBOX_CMD_NAK; 721 break; 722 723 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: 724 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: 725 /* Not implemented yet. */ 726 *resp_cmd = MBOX_CMD_NAK; 727 break; 728 729 case MBOX_CMD_AIRPLANE_MODE_ENABLED: 730 case MBOX_CMD_AIRPLANE_MODE_DISABLED: 731 case MBOX_CMD_DBC_WAKE_STACK: 732 case MBOX_CMD_HSIC_PRETEND_CONNECT: 733 case MBOX_CMD_RESET_SSPI: 734 device_printf(sc->dev, 735 "Received unused/unexpected command: %u\n", req_cmd); 736 *resp_cmd = 0; 737 break; 738 739 default: 740 device_printf(sc->dev, 741 "Received unknown command: %u\n", req_cmd); 742 } 743 } 744 745 static void 746 intr_mbox(void *arg) 747 { 748 struct tegra_xhci_softc *sc; 749 uint32_t reg, msg, resp_cmd, resp_data; 750 751 sc = (struct tegra_xhci_softc *)arg; 752 753 /* Clear interrupt first */ 754 reg = FPCI_RD4(sc, XUSB_CFG_ARU_SMI_INTR); 755 FPCI_WR4(sc, XUSB_CFG_ARU_SMI_INTR, reg); 756 if (reg & ARU_SMI_INTR_FW_HANG) { 757 device_printf(sc->dev, 758 "XUSB CPU firmware hang!!! CPUCTL: 0x%08X\n", 759 CSB_RD4(sc, XUSB_FALCON_CPUCTL)); 760 } 761 762 msg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT); 763 resp_cmd = 0; 764 process_msg(sc, ARU_MAILBOX_DATA_OUT_TYPE(msg), 765 ARU_MAILBOX_DATA_OUT_DATA(msg), &resp_cmd, &resp_data); 766 if (resp_cmd != 0) 767 mbox_send_ack(sc, resp_cmd, resp_data); 768 else 769 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER, 770 ARU_MAILBOX_OWNER_NONE); 771 772 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD); 773 reg &= ~ARU_MAILBOX_CMD_DEST_SMI; 774 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg); 775 776 } 777 778 static int 779 load_fw(struct tegra_xhci_softc *sc) 780 { 781 const struct firmware *fw; 782 const struct tegra_xusb_fw_hdr *fw_hdr; 783 vm_paddr_t fw_paddr, fw_base; 784 vm_offset_t fw_vaddr; 785 vm_size_t fw_size; 786 uint32_t code_tags, code_size; 787 struct clocktime fw_clock; 788 struct timespec fw_timespec; 789 int i; 790 791 /* Reset ARU */ 792 FPCI_WR4(sc, XUSB_CFG_ARU_RST, ARU_RST_RESET); 793 DELAY(3000); 794 795 /* Check if FALCON already runs */ 796 if (CSB_RD4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO) != 0) { 797 device_printf(sc->dev, 798 "XUSB CPU is already loaded, CPUCTL: 0x%08X\n", 799 CSB_RD4(sc, XUSB_FALCON_CPUCTL)); 800 return (0); 801 } 802 803 fw = firmware_get(sc->fw_name); 804 if (fw == NULL) { 805 device_printf(sc->dev, "Cannot read xusb firmware\n"); 806 return (ENOENT); 807 } 808 809 /* Allocate uncached memory and copy firmware into. */ 810 fw_hdr = (const struct tegra_xusb_fw_hdr *)fw->data; 811 fw_size = fw_hdr->fwimg_len; 812 813 fw_vaddr = kmem_alloc_contig(fw_size, M_WAITOK, 0, -1UL, PAGE_SIZE, 0, 814 VM_MEMATTR_UNCACHEABLE); 815 fw_paddr = vtophys(fw_vaddr); 816 fw_hdr = (const struct tegra_xusb_fw_hdr *)fw_vaddr; 817 memcpy((void *)fw_vaddr, fw->data, fw_size); 818 819 firmware_put(fw, FIRMWARE_UNLOAD); 820 sc->fw_vaddr = fw_vaddr; 821 sc->fw_size = fw_size; 822 823 /* Setup firmware physical address and size. */ 824 fw_base = fw_paddr + sizeof(*fw_hdr); 825 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_ATTR, fw_size); 826 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO, fw_base & 0xFFFFFFFF); 827 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI, (uint64_t)fw_base >> 32); 828 CSB_WR4(sc, XUSB_CSB_MEMPOOL_APMAP, APMAP_BOOTPATH); 829 830 /* Invalidate full L2IMEM context. */ 831 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG, 832 L2IMEMOP_INVALIDATE_ALL); 833 834 /* Program load of L2IMEM by boot code. */ 835 code_tags = howmany(fw_hdr->boot_codetag, XUSB_CSB_IMEM_BLOCK_SIZE); 836 code_size = howmany(fw_hdr->boot_codesize, XUSB_CSB_IMEM_BLOCK_SIZE); 837 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE, 838 L2IMEMOP_SIZE_OFFSET(code_tags) | 839 L2IMEMOP_SIZE_SIZE(code_size)); 840 841 /* Execute L2IMEM boot code fetch. */ 842 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG, 843 L2IMEMOP_LOAD_LOCKED_RESULT); 844 845 /* Program FALCON auto-fill range and block count */ 846 CSB_WR4(sc, XUSB_FALCON_IMFILLCTL, code_size); 847 CSB_WR4(sc, XUSB_FALCON_IMFILLRNG1, 848 IMFILLRNG1_TAG_LO(code_tags) | 849 IMFILLRNG1_TAG_HI(code_tags + code_size)); 850 851 CSB_WR4(sc, XUSB_FALCON_DMACTL, 0); 852 /* Wait for CPU */ 853 for (i = 500; i > 0; i--) { 854 if (CSB_RD4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT) & 855 L2IMEMOP_RESULT_VLD) 856 break; 857 DELAY(100); 858 } 859 if (i <= 0) { 860 device_printf(sc->dev, "Timedout while wating for DMA, " 861 "state: 0x%08X\n", 862 CSB_RD4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT)); 863 return (ETIMEDOUT); 864 } 865 866 /* Boot FALCON cpu */ 867 CSB_WR4(sc, XUSB_FALCON_BOOTVEC, fw_hdr->boot_codetag); 868 CSB_WR4(sc, XUSB_FALCON_CPUCTL, CPUCTL_STARTCPU); 869 870 /* Wait for CPU */ 871 for (i = 50; i > 0; i--) { 872 if (CSB_RD4(sc, XUSB_FALCON_CPUCTL) == CPUCTL_STOPPED) 873 break; 874 DELAY(100); 875 } 876 if (i <= 0) { 877 device_printf(sc->dev, "Timedout while wating for FALCON cpu, " 878 "state: 0x%08X\n", CSB_RD4(sc, XUSB_FALCON_CPUCTL)); 879 return (ETIMEDOUT); 880 } 881 882 fw_timespec.tv_sec = fw_hdr->fwimg_created_time; 883 fw_timespec.tv_nsec = 0; 884 clock_ts_to_ct(&fw_timespec, &fw_clock); 885 device_printf(sc->dev, 886 " Falcon firmware version: %02X.%02X.%04X," 887 " (%d/%d/%d %d:%02d:%02d UTC)\n", 888 (fw_hdr->version_id >> 24) & 0xFF,(fw_hdr->version_id >> 15) & 0xFF, 889 fw_hdr->version_id & 0xFFFF, 890 fw_clock.day, fw_clock.mon, fw_clock.year, 891 fw_clock.hour, fw_clock.min, fw_clock.sec); 892 893 return (0); 894 } 895 896 static int 897 init_hw(struct tegra_xhci_softc *sc) 898 { 899 int rv; 900 uint32_t reg; 901 rman_res_t base_addr; 902 903 base_addr = rman_get_start(sc->xhci_softc.sc_io_res); 904 905 /* Enable FPCI access */ 906 reg = IPFS_RD4(sc, XUSB_HOST_CONFIGURATION); 907 reg |= CONFIGURATION_EN_FPCI; 908 IPFS_WR4(sc, XUSB_HOST_CONFIGURATION, reg); 909 IPFS_RD4(sc, XUSB_HOST_CONFIGURATION); 910 911 912 /* Program bar for XHCI base address */ 913 reg = FPCI_RD4(sc, T_XUSB_CFG_4); 914 reg &= ~CFG_4_BASE_ADDRESS(~0); 915 reg |= CFG_4_BASE_ADDRESS((uint32_t)base_addr >> 15); 916 FPCI_WR4(sc, T_XUSB_CFG_4, reg); 917 FPCI_WR4(sc, T_XUSB_CFG_5, (uint32_t)((uint64_t)(base_addr) >> 32)); 918 919 /* Enable bus master */ 920 reg = FPCI_RD4(sc, T_XUSB_CFG_1); 921 reg |= CFG_1_IO_SPACE; 922 reg |= CFG_1_MEMORY_SPACE; 923 reg |= CFG_1_BUS_MASTER; 924 FPCI_WR4(sc, T_XUSB_CFG_1, reg); 925 926 /* Enable Interrupts */ 927 reg = IPFS_RD4(sc, XUSB_HOST_INTR_MASK); 928 reg |= INTR_IP_INT_MASK; 929 IPFS_WR4(sc, XUSB_HOST_INTR_MASK, reg); 930 931 /* Set hysteresis */ 932 IPFS_WR4(sc, XUSB_HOST_CLKGATE_HYSTERESIS, 128); 933 934 rv = load_fw(sc); 935 if (rv != 0) 936 return rv; 937 return (0); 938 } 939 940 static int 941 tegra_xhci_probe(device_t dev) 942 { 943 944 if (!ofw_bus_status_okay(dev)) 945 return (ENXIO); 946 947 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 948 device_set_desc(dev, "Nvidia Tegra XHCI controller"); 949 return (BUS_PROBE_DEFAULT); 950 } 951 return (ENXIO); 952 } 953 954 static int 955 tegra_xhci_detach(device_t dev) 956 { 957 struct tegra_xhci_softc *sc; 958 struct xhci_softc *xsc; 959 960 sc = device_get_softc(dev); 961 xsc = &sc->xhci_softc; 962 963 /* during module unload there are lots of children leftover */ 964 device_delete_children(dev); 965 if (sc->xhci_inited) { 966 usb_callout_drain(&xsc->sc_callout); 967 xhci_halt_controller(xsc); 968 } 969 970 if (xsc->sc_irq_res && xsc->sc_intr_hdl) { 971 bus_teardown_intr(dev, xsc->sc_irq_res, xsc->sc_intr_hdl); 972 xsc->sc_intr_hdl = NULL; 973 } 974 if (xsc->sc_irq_res) { 975 bus_release_resource(dev, SYS_RES_IRQ, 976 rman_get_rid(xsc->sc_irq_res), xsc->sc_irq_res); 977 xsc->sc_irq_res = NULL; 978 } 979 if (xsc->sc_io_res != NULL) { 980 bus_release_resource(dev, SYS_RES_MEMORY, 981 rman_get_rid(xsc->sc_io_res), xsc->sc_io_res); 982 xsc->sc_io_res = NULL; 983 } 984 if (sc->xhci_inited) 985 xhci_uninit(xsc); 986 if (sc->irq_hdl_mbox != NULL) 987 bus_teardown_intr(dev, sc->irq_res_mbox, sc->irq_hdl_mbox); 988 if (sc->fw_vaddr != 0) 989 kmem_free(sc->fw_vaddr, sc->fw_size); 990 LOCK_DESTROY(sc); 991 return (0); 992 } 993 994 static int 995 tegra_xhci_attach(device_t dev) 996 { 997 struct tegra_xhci_softc *sc; 998 struct xhci_softc *xsc; 999 int rv, rid; 1000 phandle_t node; 1001 1002 sc = device_get_softc(dev); 1003 sc->dev = dev; 1004 sc->fw_name = "tegra124_xusb_fw"; 1005 node = ofw_bus_get_node(dev); 1006 xsc = &sc->xhci_softc; 1007 LOCK_INIT(sc); 1008 1009 rv = get_fdt_resources(sc, node); 1010 if (rv != 0) { 1011 rv = ENXIO; 1012 goto error; 1013 } 1014 rv = enable_fdt_resources(sc); 1015 if (rv != 0) { 1016 rv = ENXIO; 1017 goto error; 1018 } 1019 1020 /* Allocate resources. */ 1021 rid = 0; 1022 xsc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1023 RF_ACTIVE); 1024 if (xsc->sc_io_res == NULL) { 1025 device_printf(dev, 1026 "Could not allocate HCD memory resources\n"); 1027 rv = ENXIO; 1028 goto error; 1029 } 1030 rid = 1; 1031 sc->mem_res_fpci = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1032 RF_ACTIVE); 1033 if (sc->mem_res_fpci == NULL) { 1034 device_printf(dev, 1035 "Could not allocate FPCI memory resources\n"); 1036 rv = ENXIO; 1037 goto error; 1038 } 1039 rid = 2; 1040 sc->mem_res_ipfs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1041 RF_ACTIVE); 1042 if (sc->mem_res_ipfs == NULL) { 1043 device_printf(dev, 1044 "Could not allocate IPFS memory resources\n"); 1045 rv = ENXIO; 1046 goto error; 1047 } 1048 1049 rid = 0; 1050 xsc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1051 RF_ACTIVE); 1052 if (xsc->sc_irq_res == NULL) { 1053 device_printf(dev, "Could not allocate HCD IRQ resources\n"); 1054 rv = ENXIO; 1055 goto error; 1056 } 1057 rid = 1; 1058 sc->irq_res_mbox = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1059 RF_ACTIVE); 1060 if (sc->irq_res_mbox == NULL) { 1061 device_printf(dev, "Could not allocate MBOX IRQ resources\n"); 1062 rv = ENXIO; 1063 goto error; 1064 } 1065 1066 rv = init_hw(sc); 1067 if (rv != 0) { 1068 device_printf(dev, "Could not initialize XUSB hardware\n"); 1069 goto error; 1070 } 1071 1072 /* Wakeup and enable firmaware */ 1073 rv = mbox_send_cmd(sc, MBOX_CMD_MSG_ENABLED, 0); 1074 if (rv != 0) { 1075 device_printf(sc->dev, "Could not enable XUSB firmware\n"); 1076 goto error; 1077 } 1078 1079 /* Fill data for XHCI driver. */ 1080 xsc->sc_bus.parent = dev; 1081 xsc->sc_bus.devices = xsc->sc_devices; 1082 xsc->sc_bus.devices_max = XHCI_MAX_DEVICES; 1083 1084 xsc->sc_io_tag = rman_get_bustag(xsc->sc_io_res); 1085 xsc->sc_io_hdl = rman_get_bushandle(xsc->sc_io_res); 1086 xsc->sc_io_size = rman_get_size(xsc->sc_io_res); 1087 strlcpy(xsc->sc_vendor, "Nvidia", sizeof(xsc->sc_vendor)); 1088 1089 /* Add USB bus device. */ 1090 xsc->sc_bus.bdev = device_add_child(sc->dev, "usbus", -1); 1091 if (xsc->sc_bus.bdev == NULL) { 1092 device_printf(sc->dev, "Could not add USB device\n"); 1093 rv = ENXIO; 1094 goto error; 1095 } 1096 device_set_ivars(xsc->sc_bus.bdev, &xsc->sc_bus); 1097 device_set_desc(xsc->sc_bus.bdev, "Nvidia USB 3.0 controller"); 1098 1099 rv = xhci_init(xsc, sc->dev, 1); 1100 if (rv != 0) { 1101 device_printf(sc->dev, "USB init failed: %d\n", rv); 1102 goto error; 1103 } 1104 sc->xhci_inited = true; 1105 rv = xhci_start_controller(xsc); 1106 if (rv != 0) { 1107 device_printf(sc->dev, 1108 "Could not start XHCI controller: %d\n", rv); 1109 goto error; 1110 } 1111 1112 rv = bus_setup_intr(dev, sc->irq_res_mbox, INTR_TYPE_MISC | INTR_MPSAFE, 1113 NULL, intr_mbox, sc, &sc->irq_hdl_mbox); 1114 if (rv != 0) { 1115 device_printf(dev, "Could not setup error IRQ: %d\n",rv); 1116 xsc->sc_intr_hdl = NULL; 1117 goto error; 1118 } 1119 1120 rv = bus_setup_intr(dev, xsc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1121 NULL, (driver_intr_t *)xhci_interrupt, xsc, &xsc->sc_intr_hdl); 1122 if (rv != 0) { 1123 device_printf(dev, "Could not setup error IRQ: %d\n",rv); 1124 xsc->sc_intr_hdl = NULL; 1125 goto error; 1126 } 1127 1128 /* Probe the bus. */ 1129 rv = device_probe_and_attach(xsc->sc_bus.bdev); 1130 if (rv != 0) { 1131 device_printf(sc->dev, "Could not initialize USB: %d\n", rv); 1132 goto error; 1133 } 1134 1135 return (0); 1136 1137 error: 1138 panic("XXXXX"); 1139 tegra_xhci_detach(dev); 1140 return (rv); 1141 } 1142 1143 static device_method_t xhci_methods[] = { 1144 /* Device interface */ 1145 DEVMETHOD(device_probe, tegra_xhci_probe), 1146 DEVMETHOD(device_attach, tegra_xhci_attach), 1147 DEVMETHOD(device_detach, tegra_xhci_detach), 1148 DEVMETHOD(device_suspend, bus_generic_suspend), 1149 DEVMETHOD(device_resume, bus_generic_resume), 1150 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1151 1152 /* Bus interface */ 1153 DEVMETHOD(bus_print_child, bus_generic_print_child), 1154 1155 DEVMETHOD_END 1156 }; 1157 1158 static devclass_t xhci_devclass; 1159 static DEFINE_CLASS_0(xhci, xhci_driver, xhci_methods, 1160 sizeof(struct tegra_xhci_softc)); 1161 DRIVER_MODULE(tegra_xhci, simplebus, xhci_driver, xhci_devclass, NULL, NULL); 1162 MODULE_DEPEND(tegra_xhci, usb, 1, 1, 1); 1163