1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/conf.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/systm.h> 35 #include <sys/libkern.h> 36 37 #include <machine/bus.h> 38 #include <dev/fdt/simplebus.h> 39 40 #include <dev/extres/clk/clk_gate.h> 41 #include <dev/ofw/ofw_bus.h> 42 #include <dev/ofw/ofw_bus_subr.h> 43 44 #include "clock_common.h" 45 46 #define DEBUG_GATE 0 47 48 #if DEBUG_GATE 49 #define DPRINTF(dev, msg...) device_printf(dev, msg) 50 #else 51 #define DPRINTF(dev, msg...) 52 #endif 53 54 /* 55 * Devicetree description 56 * Documentation/devicetree/bindings/clock/ti/gate.txt 57 */ 58 59 struct ti_gate_softc { 60 device_t sc_dev; 61 bool attach_done; 62 uint8_t sc_type; 63 64 struct clk_gate_def gate_def; 65 struct clock_cell_info clock_cell; 66 struct clkdom *clkdom; 67 }; 68 69 static int ti_gate_probe(device_t dev); 70 static int ti_gate_attach(device_t dev); 71 static int ti_gate_detach(device_t dev); 72 73 #define TI_GATE_CLOCK 7 74 #define TI_WAIT_GATE_CLOCK 6 75 #define TI_DSS_GATE_CLOCK 5 76 #define TI_AM35XX_GATE_CLOCK 4 77 #define TI_CLKDM_GATE_CLOCK 3 78 #define TI_HSDIV_GATE_CLOCK 2 79 #define TI_COMPOSITE_NO_WAIT_GATE_CLOCK 1 80 #define TI_GATE_END 0 81 82 static struct ofw_compat_data compat_data[] = { 83 { "ti,gate-clock", TI_GATE_CLOCK }, 84 { "ti,wait-gate-clock", TI_WAIT_GATE_CLOCK }, 85 { "ti,dss-gate-clock", TI_DSS_GATE_CLOCK }, 86 { "ti,am35xx-gate-clock", TI_AM35XX_GATE_CLOCK }, 87 { "ti,clkdm-gate-clock", TI_CLKDM_GATE_CLOCK }, 88 { "ti,hsdiv-gate-cloc", TI_HSDIV_GATE_CLOCK }, 89 { "ti,composite-no-wait-gate-clock", TI_COMPOSITE_NO_WAIT_GATE_CLOCK }, 90 { NULL, TI_GATE_END } 91 }; 92 93 static int 94 ti_gate_probe(device_t dev) 95 { 96 if (!ofw_bus_status_okay(dev)) 97 return (ENXIO); 98 99 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 100 return (ENXIO); 101 102 device_set_desc(dev, "TI Gate Clock"); 103 104 return (BUS_PROBE_DEFAULT); 105 } 106 107 static int 108 register_clk(struct ti_gate_softc *sc) { 109 int err; 110 sc->clkdom = clkdom_create(sc->sc_dev); 111 if (sc->clkdom == NULL) { 112 DPRINTF(sc->sc_dev, "Failed to create clkdom\n"); 113 return ENXIO; 114 } 115 116 err = clknode_gate_register(sc->clkdom, &sc->gate_def); 117 if (err) { 118 DPRINTF(sc->sc_dev, "clknode_gate_register failed %x\n", err); 119 return ENXIO; 120 } 121 122 err = clkdom_finit(sc->clkdom); 123 if (err) { 124 DPRINTF(sc->sc_dev, "Clk domain finit fails %x.\n", err); 125 return ENXIO; 126 } 127 128 return (0); 129 } 130 131 static int 132 ti_gate_attach(device_t dev) 133 { 134 struct ti_gate_softc *sc; 135 phandle_t node; 136 int err; 137 cell_t value; 138 139 sc = device_get_softc(dev); 140 sc->sc_dev = dev; 141 node = ofw_bus_get_node(dev); 142 143 /* Get the compatible type */ 144 sc->sc_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 145 146 /* Get the content of reg properties */ 147 if (sc->sc_type != TI_CLKDM_GATE_CLOCK) { 148 OF_getencprop(node, "reg", &value, sizeof(value)); 149 sc->gate_def.offset = value; 150 } 151 #if DEBUG_GATE 152 else { 153 DPRINTF(sc->sc_dev, "no reg (TI_CLKDM_GATE_CLOCK)\n"); 154 } 155 #endif 156 157 if (OF_hasprop(node, "ti,bit-shift")) { 158 OF_getencprop(node, "ti,bit-shift", &value, sizeof(value)); 159 sc->gate_def.shift = value; 160 DPRINTF(sc->sc_dev, "ti,bit-shift => shift %x\n", sc->gate_def.shift); 161 } 162 if (OF_hasprop(node, "ti,set-bit-to-disable")) { 163 sc->gate_def.on_value = 0; 164 sc->gate_def.off_value = 1; 165 DPRINTF(sc->sc_dev, 166 "on_value = 0, off_value = 1 (ti,set-bit-to-disable)\n"); 167 } else { 168 sc->gate_def.on_value = 1; 169 sc->gate_def.off_value = 0; 170 DPRINTF(sc->sc_dev, "on_value = 1, off_value = 0\n"); 171 } 172 173 sc->gate_def.gate_flags = 0x0; 174 175 read_clock_cells(sc->sc_dev, &sc->clock_cell); 176 177 create_clkdef(sc->sc_dev, &sc->clock_cell, &sc->gate_def.clkdef); 178 179 /* Calculate mask */ 180 sc->gate_def.mask = (1 << fls(sc->clock_cell.num_real_clocks)) - 1; 181 DPRINTF(sc->sc_dev, "num_real_clocks %x gate_def.mask %x\n", 182 sc->clock_cell.num_real_clocks, sc->gate_def.mask); 183 184 err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->gate_def.clkdef); 185 186 if (err) { 187 /* free_clkdef will be called in ti_gate_new_pass */ 188 DPRINTF(sc->sc_dev, "find_parent_clock_names failed\n"); 189 return (bus_generic_attach(sc->sc_dev)); 190 } 191 192 err = register_clk(sc); 193 194 if (err) { 195 /* free_clkdef will be called in ti_gate_new_pass */ 196 DPRINTF(sc->sc_dev, "register_clk failed\n"); 197 return (bus_generic_attach(sc->sc_dev)); 198 } 199 200 sc->attach_done = true; 201 202 free_clkdef(&sc->gate_def.clkdef); 203 204 return (bus_generic_attach(sc->sc_dev)); 205 } 206 207 static int 208 ti_gate_detach(device_t dev) 209 { 210 return (EBUSY); 211 } 212 213 static void 214 ti_gate_new_pass(device_t dev) { 215 struct ti_gate_softc *sc; 216 int err; 217 218 sc = device_get_softc(dev); 219 220 if (sc->attach_done) { 221 return; 222 } 223 224 err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->gate_def.clkdef); 225 if (err) { 226 /* free_clkdef will be called in later call to ti_gate_new_pass */ 227 DPRINTF(sc->sc_dev, "new_pass find_parent_clock_names failed\n"); 228 return; 229 } 230 231 err = register_clk(sc); 232 if (err) { 233 /* free_clkdef will be called in later call to ti_gate_new_pass */ 234 DPRINTF(sc->sc_dev, "new_pass register_clk failed\n"); 235 return; 236 } 237 238 sc->attach_done = true; 239 240 free_clkdef(&sc->gate_def.clkdef); 241 } 242 243 static device_method_t ti_gate_methods[] = { 244 /* Device interface */ 245 DEVMETHOD(device_probe, ti_gate_probe), 246 DEVMETHOD(device_attach, ti_gate_attach), 247 DEVMETHOD(device_detach, ti_gate_detach), 248 249 /* Bus interface */ 250 DEVMETHOD(bus_new_pass, ti_gate_new_pass), 251 252 DEVMETHOD_END 253 }; 254 255 DEFINE_CLASS_0(ti_gate, ti_gate_driver, ti_gate_methods, 256 sizeof(struct ti_gate_softc)); 257 258 EARLY_DRIVER_MODULE(ti_gate, simplebus, ti_gate_driver, 0, 0, 259 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 260 MODULE_VERSION(ti_gate, 1); 261