1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 5 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * TI Common Platform Ethernet Switch (CPSW) Driver 32 * Found in TI8148 "DaVinci" and AM335x "Sitara" SoCs. 33 * 34 * This controller is documented in the AM335x Technical Reference 35 * Manual, in the TMS320DM814x DaVinci Digital Video Processors TRM 36 * and in the TMS320C6452 3 Port Switch Ethernet Subsystem TRM. 37 * 38 * It is basically a single Ethernet port (port 0) wired internally to 39 * a 3-port store-and-forward switch connected to two independent 40 * "sliver" controllers (port 1 and port 2). You can operate the 41 * controller in a variety of different ways by suitably configuring 42 * the slivers and the Address Lookup Engine (ALE) that routes packets 43 * between the ports. 44 * 45 * This code was developed and tested on a BeagleBone with 46 * an AM335x SoC. 47 */ 48 49 #include <sys/cdefs.h> 50 __FBSDID("$FreeBSD$"); 51 52 #include "opt_cpsw.h" 53 54 #include <sys/param.h> 55 #include <sys/bus.h> 56 #include <sys/kernel.h> 57 #include <sys/lock.h> 58 #include <sys/mbuf.h> 59 #include <sys/module.h> 60 #include <sys/mutex.h> 61 #include <sys/rman.h> 62 #include <sys/socket.h> 63 #include <sys/sockio.h> 64 #include <sys/sysctl.h> 65 66 #include <machine/bus.h> 67 #include <machine/resource.h> 68 #include <machine/stdarg.h> 69 70 #include <net/ethernet.h> 71 #include <net/bpf.h> 72 #include <net/if.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 #include <net/if_types.h> 76 77 #include <arm/ti/ti_scm.h> 78 #include <arm/ti/am335x/am335x_scm.h> 79 80 #include <dev/mii/mii.h> 81 #include <dev/mii/miivar.h> 82 83 #include <dev/ofw/ofw_bus.h> 84 #include <dev/ofw/ofw_bus_subr.h> 85 86 #include <dev/fdt/fdt_common.h> 87 88 #ifdef CPSW_ETHERSWITCH 89 #include <dev/etherswitch/etherswitch.h> 90 #include "etherswitch_if.h" 91 #endif 92 93 #include "if_cpswreg.h" 94 #include "if_cpswvar.h" 95 96 #include "miibus_if.h" 97 98 /* Device probe/attach/detach. */ 99 static int cpsw_probe(device_t); 100 static int cpsw_attach(device_t); 101 static int cpsw_detach(device_t); 102 static int cpswp_probe(device_t); 103 static int cpswp_attach(device_t); 104 static int cpswp_detach(device_t); 105 106 static phandle_t cpsw_get_node(device_t, device_t); 107 108 /* Device Init/shutdown. */ 109 static int cpsw_shutdown(device_t); 110 static void cpswp_init(void *); 111 static void cpswp_init_locked(void *); 112 static void cpswp_stop_locked(struct cpswp_softc *); 113 114 /* Device Suspend/Resume. */ 115 static int cpsw_suspend(device_t); 116 static int cpsw_resume(device_t); 117 118 /* Ioctl. */ 119 static int cpswp_ioctl(struct ifnet *, u_long command, caddr_t data); 120 121 static int cpswp_miibus_readreg(device_t, int phy, int reg); 122 static int cpswp_miibus_writereg(device_t, int phy, int reg, int value); 123 static void cpswp_miibus_statchg(device_t); 124 125 /* Send/Receive packets. */ 126 static void cpsw_intr_rx(void *arg); 127 static struct mbuf *cpsw_rx_dequeue(struct cpsw_softc *); 128 static void cpsw_rx_enqueue(struct cpsw_softc *); 129 static void cpswp_start(struct ifnet *); 130 static void cpsw_intr_tx(void *); 131 static void cpswp_tx_enqueue(struct cpswp_softc *); 132 static int cpsw_tx_dequeue(struct cpsw_softc *); 133 134 /* Misc interrupts and watchdog. */ 135 static void cpsw_intr_rx_thresh(void *); 136 static void cpsw_intr_misc(void *); 137 static void cpswp_tick(void *); 138 static void cpswp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 139 static int cpswp_ifmedia_upd(struct ifnet *); 140 static void cpsw_tx_watchdog(void *); 141 142 /* ALE support */ 143 static void cpsw_ale_read_entry(struct cpsw_softc *, uint16_t, uint32_t *); 144 static void cpsw_ale_write_entry(struct cpsw_softc *, uint16_t, uint32_t *); 145 static int cpsw_ale_mc_entry_set(struct cpsw_softc *, uint8_t, int, uint8_t *); 146 static void cpsw_ale_dump_table(struct cpsw_softc *); 147 static int cpsw_ale_update_vlan_table(struct cpsw_softc *, int, int, int, int, 148 int); 149 static int cpswp_ale_update_addresses(struct cpswp_softc *, int); 150 151 /* Statistics and sysctls. */ 152 static void cpsw_add_sysctls(struct cpsw_softc *); 153 static void cpsw_stats_collect(struct cpsw_softc *); 154 static int cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS); 155 156 #ifdef CPSW_ETHERSWITCH 157 static etherswitch_info_t *cpsw_getinfo(device_t); 158 static int cpsw_getport(device_t, etherswitch_port_t *); 159 static int cpsw_setport(device_t, etherswitch_port_t *); 160 static int cpsw_getconf(device_t, etherswitch_conf_t *); 161 static int cpsw_getvgroup(device_t, etherswitch_vlangroup_t *); 162 static int cpsw_setvgroup(device_t, etherswitch_vlangroup_t *); 163 static int cpsw_readreg(device_t, int); 164 static int cpsw_writereg(device_t, int, int); 165 static int cpsw_readphy(device_t, int, int); 166 static int cpsw_writephy(device_t, int, int, int); 167 #endif 168 169 /* 170 * Arbitrary limit on number of segments in an mbuf to be transmitted. 171 * Packets with more segments than this will be defragmented before 172 * they are queued. 173 */ 174 #define CPSW_TXFRAGS 16 175 176 /* Shared resources. */ 177 static device_method_t cpsw_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, cpsw_probe), 180 DEVMETHOD(device_attach, cpsw_attach), 181 DEVMETHOD(device_detach, cpsw_detach), 182 DEVMETHOD(device_shutdown, cpsw_shutdown), 183 DEVMETHOD(device_suspend, cpsw_suspend), 184 DEVMETHOD(device_resume, cpsw_resume), 185 /* Bus interface */ 186 DEVMETHOD(bus_add_child, device_add_child_ordered), 187 /* OFW methods */ 188 DEVMETHOD(ofw_bus_get_node, cpsw_get_node), 189 #ifdef CPSW_ETHERSWITCH 190 /* etherswitch interface */ 191 DEVMETHOD(etherswitch_getinfo, cpsw_getinfo), 192 DEVMETHOD(etherswitch_readreg, cpsw_readreg), 193 DEVMETHOD(etherswitch_writereg, cpsw_writereg), 194 DEVMETHOD(etherswitch_readphyreg, cpsw_readphy), 195 DEVMETHOD(etherswitch_writephyreg, cpsw_writephy), 196 DEVMETHOD(etherswitch_getport, cpsw_getport), 197 DEVMETHOD(etherswitch_setport, cpsw_setport), 198 DEVMETHOD(etherswitch_getvgroup, cpsw_getvgroup), 199 DEVMETHOD(etherswitch_setvgroup, cpsw_setvgroup), 200 DEVMETHOD(etherswitch_getconf, cpsw_getconf), 201 #endif 202 DEVMETHOD_END 203 }; 204 205 static driver_t cpsw_driver = { 206 "cpswss", 207 cpsw_methods, 208 sizeof(struct cpsw_softc), 209 }; 210 211 static devclass_t cpsw_devclass; 212 213 DRIVER_MODULE(cpswss, simplebus, cpsw_driver, cpsw_devclass, 0, 0); 214 215 /* Port/Slave resources. */ 216 static device_method_t cpswp_methods[] = { 217 /* Device interface */ 218 DEVMETHOD(device_probe, cpswp_probe), 219 DEVMETHOD(device_attach, cpswp_attach), 220 DEVMETHOD(device_detach, cpswp_detach), 221 /* MII interface */ 222 DEVMETHOD(miibus_readreg, cpswp_miibus_readreg), 223 DEVMETHOD(miibus_writereg, cpswp_miibus_writereg), 224 DEVMETHOD(miibus_statchg, cpswp_miibus_statchg), 225 DEVMETHOD_END 226 }; 227 228 static driver_t cpswp_driver = { 229 "cpsw", 230 cpswp_methods, 231 sizeof(struct cpswp_softc), 232 }; 233 234 static devclass_t cpswp_devclass; 235 236 #ifdef CPSW_ETHERSWITCH 237 DRIVER_MODULE(etherswitch, cpswss, etherswitch_driver, etherswitch_devclass, 0, 0); 238 MODULE_DEPEND(cpswss, etherswitch, 1, 1, 1); 239 #endif 240 241 DRIVER_MODULE(cpsw, cpswss, cpswp_driver, cpswp_devclass, 0, 0); 242 DRIVER_MODULE(miibus, cpsw, miibus_driver, miibus_devclass, 0, 0); 243 MODULE_DEPEND(cpsw, ether, 1, 1, 1); 244 MODULE_DEPEND(cpsw, miibus, 1, 1, 1); 245 246 #ifdef CPSW_ETHERSWITCH 247 static struct cpsw_vlangroups cpsw_vgroups[CPSW_VLANS]; 248 #endif 249 250 static uint32_t slave_mdio_addr[] = { 0x4a100200, 0x4a100300 }; 251 252 static struct resource_spec irq_res_spec[] = { 253 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 254 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_SHAREABLE }, 255 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_SHAREABLE }, 256 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_SHAREABLE }, 257 { -1, 0 } 258 }; 259 260 static struct { 261 void (*cb)(void *); 262 } cpsw_intr_cb[] = { 263 { cpsw_intr_rx_thresh }, 264 { cpsw_intr_rx }, 265 { cpsw_intr_tx }, 266 { cpsw_intr_misc }, 267 }; 268 269 /* Number of entries here must match size of stats 270 * array in struct cpswp_softc. */ 271 static struct cpsw_stat { 272 int reg; 273 char *oid; 274 } cpsw_stat_sysctls[CPSW_SYSCTL_COUNT] = { 275 {0x00, "GoodRxFrames"}, 276 {0x04, "BroadcastRxFrames"}, 277 {0x08, "MulticastRxFrames"}, 278 {0x0C, "PauseRxFrames"}, 279 {0x10, "RxCrcErrors"}, 280 {0x14, "RxAlignErrors"}, 281 {0x18, "OversizeRxFrames"}, 282 {0x1c, "RxJabbers"}, 283 {0x20, "ShortRxFrames"}, 284 {0x24, "RxFragments"}, 285 {0x30, "RxOctets"}, 286 {0x34, "GoodTxFrames"}, 287 {0x38, "BroadcastTxFrames"}, 288 {0x3c, "MulticastTxFrames"}, 289 {0x40, "PauseTxFrames"}, 290 {0x44, "DeferredTxFrames"}, 291 {0x48, "CollisionsTxFrames"}, 292 {0x4c, "SingleCollisionTxFrames"}, 293 {0x50, "MultipleCollisionTxFrames"}, 294 {0x54, "ExcessiveCollisions"}, 295 {0x58, "LateCollisions"}, 296 {0x5c, "TxUnderrun"}, 297 {0x60, "CarrierSenseErrors"}, 298 {0x64, "TxOctets"}, 299 {0x68, "RxTx64OctetFrames"}, 300 {0x6c, "RxTx65to127OctetFrames"}, 301 {0x70, "RxTx128to255OctetFrames"}, 302 {0x74, "RxTx256to511OctetFrames"}, 303 {0x78, "RxTx512to1024OctetFrames"}, 304 {0x7c, "RxTx1024upOctetFrames"}, 305 {0x80, "NetOctets"}, 306 {0x84, "RxStartOfFrameOverruns"}, 307 {0x88, "RxMiddleOfFrameOverruns"}, 308 {0x8c, "RxDmaOverruns"} 309 }; 310 311 /* 312 * Basic debug support. 313 */ 314 315 static void 316 cpsw_debugf_head(const char *funcname) 317 { 318 int t = (int)(time_second % (24 * 60 * 60)); 319 320 printf("%02d:%02d:%02d %s ", t / (60 * 60), (t / 60) % 60, t % 60, funcname); 321 } 322 323 static void 324 cpsw_debugf(const char *fmt, ...) 325 { 326 va_list ap; 327 328 va_start(ap, fmt); 329 vprintf(fmt, ap); 330 va_end(ap); 331 printf("\n"); 332 333 } 334 335 #define CPSW_DEBUGF(_sc, a) do { \ 336 if ((_sc)->debug) { \ 337 cpsw_debugf_head(__func__); \ 338 cpsw_debugf a; \ 339 } \ 340 } while (0) 341 342 /* 343 * Locking macros 344 */ 345 #define CPSW_TX_LOCK(sc) do { \ 346 mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \ 347 mtx_lock(&(sc)->tx.lock); \ 348 } while (0) 349 350 #define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock) 351 #define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED) 352 353 #define CPSW_RX_LOCK(sc) do { \ 354 mtx_assert(&(sc)->tx.lock, MA_NOTOWNED); \ 355 mtx_lock(&(sc)->rx.lock); \ 356 } while (0) 357 358 #define CPSW_RX_UNLOCK(sc) mtx_unlock(&(sc)->rx.lock) 359 #define CPSW_RX_LOCK_ASSERT(sc) mtx_assert(&(sc)->rx.lock, MA_OWNED) 360 361 #define CPSW_PORT_LOCK(_sc) do { \ 362 mtx_assert(&(_sc)->lock, MA_NOTOWNED); \ 363 mtx_lock(&(_sc)->lock); \ 364 } while (0) 365 366 #define CPSW_PORT_UNLOCK(_sc) mtx_unlock(&(_sc)->lock) 367 #define CPSW_PORT_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->lock, MA_OWNED) 368 369 /* 370 * Read/Write macros 371 */ 372 #define cpsw_read_4(_sc, _reg) bus_read_4((_sc)->mem_res, (_reg)) 373 #define cpsw_write_4(_sc, _reg, _val) \ 374 bus_write_4((_sc)->mem_res, (_reg), (_val)) 375 376 #define cpsw_cpdma_bd_offset(i) (CPSW_CPPI_RAM_OFFSET + ((i)*16)) 377 378 #define cpsw_cpdma_bd_paddr(sc, slot) \ 379 BUS_SPACE_PHYSADDR(sc->mem_res, slot->bd_offset) 380 #define cpsw_cpdma_read_bd(sc, slot, val) \ 381 bus_read_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4) 382 #define cpsw_cpdma_write_bd(sc, slot, val) \ 383 bus_write_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4) 384 #define cpsw_cpdma_write_bd_next(sc, slot, next_slot) \ 385 cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot)) 386 #define cpsw_cpdma_write_bd_flags(sc, slot, val) \ 387 bus_write_2(sc->mem_res, slot->bd_offset + 14, val) 388 #define cpsw_cpdma_read_bd_flags(sc, slot) \ 389 bus_read_2(sc->mem_res, slot->bd_offset + 14) 390 #define cpsw_write_hdp_slot(sc, queue, slot) \ 391 cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot)) 392 #define CP_OFFSET (CPSW_CPDMA_TX_CP(0) - CPSW_CPDMA_TX_HDP(0)) 393 #define cpsw_read_cp(sc, queue) \ 394 cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET) 395 #define cpsw_write_cp(sc, queue, val) \ 396 cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val)) 397 #define cpsw_write_cp_slot(sc, queue, slot) \ 398 cpsw_write_cp(sc, queue, cpsw_cpdma_bd_paddr(sc, slot)) 399 400 #if 0 401 /* XXX temporary function versions for debugging. */ 402 static void 403 cpsw_write_hdp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot) 404 { 405 uint32_t reg = queue->hdp_offset; 406 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot); 407 CPSW_DEBUGF(("HDP <=== 0x%08x (was 0x%08x)", v, cpsw_read_4(sc, reg))); 408 cpsw_write_4(sc, reg, v); 409 } 410 411 static void 412 cpsw_write_cp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot) 413 { 414 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot); 415 CPSW_DEBUGF(("CP <=== 0x%08x (expecting 0x%08x)", v, cpsw_read_cp(sc, queue))); 416 cpsw_write_cp(sc, queue, v); 417 } 418 #endif 419 420 /* 421 * Expanded dump routines for verbose debugging. 422 */ 423 static void 424 cpsw_dump_slot(struct cpsw_softc *sc, struct cpsw_slot *slot) 425 { 426 static const char *flags[] = {"SOP", "EOP", "Owner", "EOQ", 427 "TDownCmplt", "PassCRC", "Long", "Short", "MacCtl", "Overrun", 428 "PktErr1", "PortEn/PktErr0", "RxVlanEncap", "Port2", "Port1", 429 "Port0"}; 430 struct cpsw_cpdma_bd bd; 431 const char *sep; 432 int i; 433 434 cpsw_cpdma_read_bd(sc, slot, &bd); 435 printf("BD Addr : 0x%08x Next : 0x%08x\n", 436 cpsw_cpdma_bd_paddr(sc, slot), bd.next); 437 printf(" BufPtr: 0x%08x BufLen: 0x%08x\n", bd.bufptr, bd.buflen); 438 printf(" BufOff: 0x%08x PktLen: 0x%08x\n", bd.bufoff, bd.pktlen); 439 printf(" Flags: "); 440 sep = ""; 441 for (i = 0; i < 16; ++i) { 442 if (bd.flags & (1 << (15 - i))) { 443 printf("%s%s", sep, flags[i]); 444 sep = ","; 445 } 446 } 447 printf("\n"); 448 if (slot->mbuf) { 449 printf(" Ether: %14D\n", 450 (char *)(slot->mbuf->m_data), " "); 451 printf(" Packet: %16D\n", 452 (char *)(slot->mbuf->m_data) + 14, " "); 453 } 454 } 455 456 #define CPSW_DUMP_SLOT(cs, slot) do { \ 457 IF_DEBUG(sc) { \ 458 cpsw_dump_slot(sc, slot); \ 459 } \ 460 } while (0) 461 462 static void 463 cpsw_dump_queue(struct cpsw_softc *sc, struct cpsw_slots *q) 464 { 465 struct cpsw_slot *slot; 466 int i = 0; 467 int others = 0; 468 469 STAILQ_FOREACH(slot, q, next) { 470 if (i > CPSW_TXFRAGS) 471 ++others; 472 else 473 cpsw_dump_slot(sc, slot); 474 ++i; 475 } 476 if (others) 477 printf(" ... and %d more.\n", others); 478 printf("\n"); 479 } 480 481 #define CPSW_DUMP_QUEUE(sc, q) do { \ 482 IF_DEBUG(sc) { \ 483 cpsw_dump_queue(sc, q); \ 484 } \ 485 } while (0) 486 487 static void 488 cpsw_init_slots(struct cpsw_softc *sc) 489 { 490 struct cpsw_slot *slot; 491 int i; 492 493 STAILQ_INIT(&sc->avail); 494 495 /* Put the slot descriptors onto the global avail list. */ 496 for (i = 0; i < nitems(sc->_slots); i++) { 497 slot = &sc->_slots[i]; 498 slot->bd_offset = cpsw_cpdma_bd_offset(i); 499 STAILQ_INSERT_TAIL(&sc->avail, slot, next); 500 } 501 } 502 503 static int 504 cpsw_add_slots(struct cpsw_softc *sc, struct cpsw_queue *queue, int requested) 505 { 506 const int max_slots = nitems(sc->_slots); 507 struct cpsw_slot *slot; 508 int i; 509 510 if (requested < 0) 511 requested = max_slots; 512 513 for (i = 0; i < requested; ++i) { 514 slot = STAILQ_FIRST(&sc->avail); 515 if (slot == NULL) 516 return (0); 517 if (bus_dmamap_create(sc->mbuf_dtag, 0, &slot->dmamap)) { 518 device_printf(sc->dev, "failed to create dmamap\n"); 519 return (ENOMEM); 520 } 521 STAILQ_REMOVE_HEAD(&sc->avail, next); 522 STAILQ_INSERT_TAIL(&queue->avail, slot, next); 523 ++queue->avail_queue_len; 524 ++queue->queue_slots; 525 } 526 return (0); 527 } 528 529 static void 530 cpsw_free_slot(struct cpsw_softc *sc, struct cpsw_slot *slot) 531 { 532 int error; 533 534 if (slot->dmamap) { 535 if (slot->mbuf) 536 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 537 error = bus_dmamap_destroy(sc->mbuf_dtag, slot->dmamap); 538 KASSERT(error == 0, ("Mapping still active")); 539 slot->dmamap = NULL; 540 } 541 if (slot->mbuf) { 542 m_freem(slot->mbuf); 543 slot->mbuf = NULL; 544 } 545 } 546 547 static void 548 cpsw_reset(struct cpsw_softc *sc) 549 { 550 int i; 551 552 callout_stop(&sc->watchdog.callout); 553 554 /* Reset RMII/RGMII wrapper. */ 555 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 556 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 557 ; 558 559 /* Disable TX and RX interrupts for all cores. */ 560 for (i = 0; i < 3; ++i) { 561 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(i), 0x00); 562 cpsw_write_4(sc, CPSW_WR_C_TX_EN(i), 0x00); 563 cpsw_write_4(sc, CPSW_WR_C_RX_EN(i), 0x00); 564 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(i), 0x00); 565 } 566 567 /* Reset CPSW subsystem. */ 568 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 569 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 570 ; 571 572 /* Reset Sliver port 1 and 2 */ 573 for (i = 0; i < 2; i++) { 574 /* Reset */ 575 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 576 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 577 ; 578 } 579 580 /* Reset DMA controller. */ 581 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 582 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 583 ; 584 585 /* Disable TX & RX DMA */ 586 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 0); 587 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 0); 588 589 /* Clear all queues. */ 590 for (i = 0; i < 8; i++) { 591 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0); 592 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0); 593 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0); 594 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0); 595 } 596 597 /* Clear all interrupt Masks */ 598 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF); 599 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF); 600 } 601 602 static void 603 cpsw_init(struct cpsw_softc *sc) 604 { 605 struct cpsw_slot *slot; 606 uint32_t reg; 607 608 /* Disable the interrupt pacing. */ 609 reg = cpsw_read_4(sc, CPSW_WR_INT_CONTROL); 610 reg &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK); 611 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, reg); 612 613 /* Clear ALE */ 614 cpsw_write_4(sc, CPSW_ALE_CONTROL, CPSW_ALE_CTL_CLEAR_TBL); 615 616 /* Enable ALE */ 617 reg = CPSW_ALE_CTL_ENABLE; 618 if (sc->dualemac) 619 reg |= CPSW_ALE_CTL_VLAN_AWARE; 620 cpsw_write_4(sc, CPSW_ALE_CONTROL, reg); 621 622 /* Set Host Port Mapping. */ 623 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210); 624 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0); 625 626 /* Initialize ALE: set host port to forwarding(3). */ 627 cpsw_write_4(sc, CPSW_ALE_PORTCTL(0), 628 ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD); 629 630 cpsw_write_4(sc, CPSW_SS_PTYPE, 0); 631 632 /* Enable statistics for ports 0, 1 and 2 */ 633 cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7); 634 635 /* Turn off flow control. */ 636 cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0); 637 638 /* Make IP hdr aligned with 4 */ 639 cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, 2); 640 641 /* Initialize RX Buffer Descriptors */ 642 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), 0); 643 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0); 644 645 /* Enable TX & RX DMA */ 646 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1); 647 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1); 648 649 /* Enable Interrupts for core 0 */ 650 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(0), 0xFF); 651 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0xFF); 652 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0xFF); 653 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F); 654 655 /* Enable host Error Interrupt */ 656 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 3); 657 658 /* Enable interrupts for RX and TX on Channel 0 */ 659 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 660 CPSW_CPDMA_RX_INT(0) | CPSW_CPDMA_RX_INT_THRESH(0)); 661 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1); 662 663 /* Initialze MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */ 664 /* TODO Calculate MDCLK=CLK/(CLKDIV+1) */ 665 cpsw_write_4(sc, MDIOCONTROL, MDIOCTL_ENABLE | MDIOCTL_FAULTENB | 0xff); 666 667 /* Select MII in GMII_SEL, Internal Delay mode */ 668 //ti_scm_reg_write_4(0x650, 0); 669 670 /* Initialize active queues. */ 671 slot = STAILQ_FIRST(&sc->tx.active); 672 if (slot != NULL) 673 cpsw_write_hdp_slot(sc, &sc->tx, slot); 674 slot = STAILQ_FIRST(&sc->rx.active); 675 if (slot != NULL) 676 cpsw_write_hdp_slot(sc, &sc->rx, slot); 677 cpsw_rx_enqueue(sc); 678 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), sc->rx.active_queue_len); 679 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), CPSW_TXFRAGS); 680 681 /* Activate network interface. */ 682 sc->rx.running = 1; 683 sc->tx.running = 1; 684 sc->watchdog.timer = 0; 685 callout_init(&sc->watchdog.callout, 0); 686 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc); 687 } 688 689 /* 690 * 691 * Device Probe, Attach, Detach. 692 * 693 */ 694 695 static int 696 cpsw_probe(device_t dev) 697 { 698 699 if (!ofw_bus_status_okay(dev)) 700 return (ENXIO); 701 702 if (!ofw_bus_is_compatible(dev, "ti,cpsw")) 703 return (ENXIO); 704 705 device_set_desc(dev, "3-port Switch Ethernet Subsystem"); 706 return (BUS_PROBE_DEFAULT); 707 } 708 709 static int 710 cpsw_intr_attach(struct cpsw_softc *sc) 711 { 712 int i; 713 714 for (i = 0; i < CPSW_INTR_COUNT; i++) { 715 if (bus_setup_intr(sc->dev, sc->irq_res[i], 716 INTR_TYPE_NET | INTR_MPSAFE, NULL, 717 cpsw_intr_cb[i].cb, sc, &sc->ih_cookie[i]) != 0) { 718 return (-1); 719 } 720 } 721 722 return (0); 723 } 724 725 static void 726 cpsw_intr_detach(struct cpsw_softc *sc) 727 { 728 int i; 729 730 for (i = 0; i < CPSW_INTR_COUNT; i++) { 731 if (sc->ih_cookie[i]) { 732 bus_teardown_intr(sc->dev, sc->irq_res[i], 733 sc->ih_cookie[i]); 734 } 735 } 736 } 737 738 static int 739 cpsw_get_fdt_data(struct cpsw_softc *sc, int port) 740 { 741 char *name; 742 int len, phy, vlan; 743 pcell_t phy_id[3], vlan_id; 744 phandle_t child; 745 unsigned long mdio_child_addr; 746 747 /* Find any slave with phy-handle/phy_id */ 748 phy = -1; 749 vlan = -1; 750 for (child = OF_child(sc->node); child != 0; child = OF_peer(child)) { 751 if (OF_getprop_alloc(child, "name", (void **)&name) < 0) 752 continue; 753 if (sscanf(name, "slave@%lx", &mdio_child_addr) != 1) { 754 OF_prop_free(name); 755 continue; 756 } 757 OF_prop_free(name); 758 759 if (mdio_child_addr != slave_mdio_addr[port] && 760 mdio_child_addr != (slave_mdio_addr[port] & 0xFFF)) 761 continue; 762 763 if (fdt_get_phyaddr(child, NULL, &phy, NULL) != 0){ 764 /* Users with old DTB will have phy_id instead */ 765 phy = -1; 766 len = OF_getproplen(child, "phy_id"); 767 if (len / sizeof(pcell_t) == 2) { 768 /* Get phy address from fdt */ 769 if (OF_getencprop(child, "phy_id", phy_id, len) > 0) 770 phy = phy_id[1]; 771 } 772 } 773 774 len = OF_getproplen(child, "dual_emac_res_vlan"); 775 if (len / sizeof(pcell_t) == 1) { 776 /* Get phy address from fdt */ 777 if (OF_getencprop(child, "dual_emac_res_vlan", 778 &vlan_id, len) > 0) { 779 vlan = vlan_id; 780 } 781 } 782 783 break; 784 } 785 if (phy == -1) 786 return (ENXIO); 787 sc->port[port].phy = phy; 788 sc->port[port].vlan = vlan; 789 790 return (0); 791 } 792 793 static int 794 cpsw_attach(device_t dev) 795 { 796 int error, i; 797 struct cpsw_softc *sc; 798 uint32_t reg; 799 800 sc = device_get_softc(dev); 801 sc->dev = dev; 802 sc->node = ofw_bus_get_node(dev); 803 getbinuptime(&sc->attach_uptime); 804 805 if (OF_getencprop(sc->node, "active_slave", &sc->active_slave, 806 sizeof(sc->active_slave)) <= 0) { 807 sc->active_slave = 0; 808 } 809 if (sc->active_slave > 1) 810 sc->active_slave = 1; 811 812 if (OF_hasprop(sc->node, "dual_emac")) 813 sc->dualemac = 1; 814 815 for (i = 0; i < CPSW_PORTS; i++) { 816 if (!sc->dualemac && i != sc->active_slave) 817 continue; 818 if (cpsw_get_fdt_data(sc, i) != 0) { 819 device_printf(dev, 820 "failed to get PHY address from FDT\n"); 821 return (ENXIO); 822 } 823 } 824 825 /* Initialize mutexes */ 826 mtx_init(&sc->tx.lock, device_get_nameunit(dev), 827 "cpsw TX lock", MTX_DEF); 828 mtx_init(&sc->rx.lock, device_get_nameunit(dev), 829 "cpsw RX lock", MTX_DEF); 830 831 /* Allocate IRQ resources */ 832 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res); 833 if (error) { 834 device_printf(dev, "could not allocate IRQ resources\n"); 835 cpsw_detach(dev); 836 return (ENXIO); 837 } 838 839 sc->mem_rid = 0; 840 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 841 &sc->mem_rid, RF_ACTIVE); 842 if (sc->mem_res == NULL) { 843 device_printf(sc->dev, "failed to allocate memory resource\n"); 844 cpsw_detach(dev); 845 return (ENXIO); 846 } 847 848 reg = cpsw_read_4(sc, CPSW_SS_IDVER); 849 device_printf(dev, "CPSW SS Version %d.%d (%d)\n", (reg >> 8 & 0x7), 850 reg & 0xFF, (reg >> 11) & 0x1F); 851 852 cpsw_add_sysctls(sc); 853 854 /* Allocate a busdma tag and DMA safe memory for mbufs. */ 855 error = bus_dma_tag_create( 856 bus_get_dma_tag(sc->dev), /* parent */ 857 1, 0, /* alignment, boundary */ 858 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 859 BUS_SPACE_MAXADDR, /* highaddr */ 860 NULL, NULL, /* filtfunc, filtfuncarg */ 861 MCLBYTES, CPSW_TXFRAGS, /* maxsize, nsegments */ 862 MCLBYTES, 0, /* maxsegsz, flags */ 863 NULL, NULL, /* lockfunc, lockfuncarg */ 864 &sc->mbuf_dtag); /* dmatag */ 865 if (error) { 866 device_printf(dev, "bus_dma_tag_create failed\n"); 867 cpsw_detach(dev); 868 return (error); 869 } 870 871 /* Allocate a NULL buffer for padding. */ 872 sc->nullpad = malloc(ETHER_MIN_LEN, M_DEVBUF, M_WAITOK | M_ZERO); 873 874 cpsw_init_slots(sc); 875 876 /* Allocate slots to TX and RX queues. */ 877 STAILQ_INIT(&sc->rx.avail); 878 STAILQ_INIT(&sc->rx.active); 879 STAILQ_INIT(&sc->tx.avail); 880 STAILQ_INIT(&sc->tx.active); 881 // For now: 128 slots to TX, rest to RX. 882 // XXX TODO: start with 32/64 and grow dynamically based on demand. 883 if (cpsw_add_slots(sc, &sc->tx, 128) || 884 cpsw_add_slots(sc, &sc->rx, -1)) { 885 device_printf(dev, "failed to allocate dmamaps\n"); 886 cpsw_detach(dev); 887 return (ENOMEM); 888 } 889 device_printf(dev, "Initial queue size TX=%d RX=%d\n", 890 sc->tx.queue_slots, sc->rx.queue_slots); 891 892 sc->tx.hdp_offset = CPSW_CPDMA_TX_HDP(0); 893 sc->rx.hdp_offset = CPSW_CPDMA_RX_HDP(0); 894 895 if (cpsw_intr_attach(sc) == -1) { 896 device_printf(dev, "failed to setup interrupts\n"); 897 cpsw_detach(dev); 898 return (ENXIO); 899 } 900 901 #ifdef CPSW_ETHERSWITCH 902 for (i = 0; i < CPSW_VLANS; i++) 903 cpsw_vgroups[i].vid = -1; 904 #endif 905 906 /* Reset the controller. */ 907 cpsw_reset(sc); 908 cpsw_init(sc); 909 910 for (i = 0; i < CPSW_PORTS; i++) { 911 if (!sc->dualemac && i != sc->active_slave) 912 continue; 913 sc->port[i].dev = device_add_child(dev, "cpsw", i); 914 if (sc->port[i].dev == NULL) { 915 cpsw_detach(dev); 916 return (ENXIO); 917 } 918 } 919 bus_generic_probe(dev); 920 bus_generic_attach(dev); 921 922 return (0); 923 } 924 925 static int 926 cpsw_detach(device_t dev) 927 { 928 struct cpsw_softc *sc; 929 int error, i; 930 931 bus_generic_detach(dev); 932 sc = device_get_softc(dev); 933 934 for (i = 0; i < CPSW_PORTS; i++) { 935 if (sc->port[i].dev) 936 device_delete_child(dev, sc->port[i].dev); 937 } 938 939 if (device_is_attached(dev)) { 940 callout_stop(&sc->watchdog.callout); 941 callout_drain(&sc->watchdog.callout); 942 } 943 944 /* Stop and release all interrupts */ 945 cpsw_intr_detach(sc); 946 947 /* Free dmamaps and mbufs */ 948 for (i = 0; i < nitems(sc->_slots); ++i) 949 cpsw_free_slot(sc, &sc->_slots[i]); 950 951 /* Free null padding buffer. */ 952 if (sc->nullpad) 953 free(sc->nullpad, M_DEVBUF); 954 955 /* Free DMA tag */ 956 if (sc->mbuf_dtag) { 957 error = bus_dma_tag_destroy(sc->mbuf_dtag); 958 KASSERT(error == 0, ("Unable to destroy DMA tag")); 959 } 960 961 /* Free IO memory handler */ 962 if (sc->mem_res != NULL) 963 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); 964 bus_release_resources(dev, irq_res_spec, sc->irq_res); 965 966 /* Destroy mutexes */ 967 mtx_destroy(&sc->rx.lock); 968 mtx_destroy(&sc->tx.lock); 969 970 /* Detach the switch device, if present. */ 971 error = bus_generic_detach(dev); 972 if (error != 0) 973 return (error); 974 975 return (device_delete_children(dev)); 976 } 977 978 static phandle_t 979 cpsw_get_node(device_t bus, device_t dev) 980 { 981 982 /* Share controller node with port device. */ 983 return (ofw_bus_get_node(bus)); 984 } 985 986 static int 987 cpswp_probe(device_t dev) 988 { 989 990 if (device_get_unit(dev) > 1) { 991 device_printf(dev, "Only two ports are supported.\n"); 992 return (ENXIO); 993 } 994 device_set_desc(dev, "Ethernet Switch Port"); 995 996 return (BUS_PROBE_DEFAULT); 997 } 998 999 static int 1000 cpswp_attach(device_t dev) 1001 { 1002 int error; 1003 struct ifnet *ifp; 1004 struct cpswp_softc *sc; 1005 uint32_t reg; 1006 uint8_t mac_addr[ETHER_ADDR_LEN]; 1007 1008 sc = device_get_softc(dev); 1009 sc->dev = dev; 1010 sc->pdev = device_get_parent(dev); 1011 sc->swsc = device_get_softc(sc->pdev); 1012 sc->unit = device_get_unit(dev); 1013 sc->phy = sc->swsc->port[sc->unit].phy; 1014 sc->vlan = sc->swsc->port[sc->unit].vlan; 1015 if (sc->swsc->dualemac && sc->vlan == -1) 1016 sc->vlan = sc->unit + 1; 1017 1018 if (sc->unit == 0) { 1019 sc->physel = MDIOUSERPHYSEL0; 1020 sc->phyaccess = MDIOUSERACCESS0; 1021 } else { 1022 sc->physel = MDIOUSERPHYSEL1; 1023 sc->phyaccess = MDIOUSERACCESS1; 1024 } 1025 1026 mtx_init(&sc->lock, device_get_nameunit(dev), "cpsw port lock", 1027 MTX_DEF); 1028 1029 /* Allocate network interface */ 1030 ifp = sc->ifp = if_alloc(IFT_ETHER); 1031 if (ifp == NULL) { 1032 cpswp_detach(dev); 1033 return (ENXIO); 1034 } 1035 1036 if_initname(ifp, device_get_name(sc->dev), sc->unit); 1037 ifp->if_softc = sc; 1038 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 1039 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_HWCSUM; //FIXME VLAN? 1040 ifp->if_capenable = ifp->if_capabilities; 1041 1042 ifp->if_init = cpswp_init; 1043 ifp->if_start = cpswp_start; 1044 ifp->if_ioctl = cpswp_ioctl; 1045 1046 ifp->if_snd.ifq_drv_maxlen = sc->swsc->tx.queue_slots; 1047 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1048 IFQ_SET_READY(&ifp->if_snd); 1049 1050 /* Get high part of MAC address from control module (mac_id[0|1]_hi) */ 1051 ti_scm_reg_read_4(SCM_MAC_ID0_HI + sc->unit * 8, ®); 1052 mac_addr[0] = reg & 0xFF; 1053 mac_addr[1] = (reg >> 8) & 0xFF; 1054 mac_addr[2] = (reg >> 16) & 0xFF; 1055 mac_addr[3] = (reg >> 24) & 0xFF; 1056 1057 /* Get low part of MAC address from control module (mac_id[0|1]_lo) */ 1058 ti_scm_reg_read_4(SCM_MAC_ID0_LO + sc->unit * 8, ®); 1059 mac_addr[4] = reg & 0xFF; 1060 mac_addr[5] = (reg >> 8) & 0xFF; 1061 1062 error = mii_attach(dev, &sc->miibus, ifp, cpswp_ifmedia_upd, 1063 cpswp_ifmedia_sts, BMSR_DEFCAPMASK, sc->phy, MII_OFFSET_ANY, 0); 1064 if (error) { 1065 device_printf(dev, "attaching PHYs failed\n"); 1066 cpswp_detach(dev); 1067 return (error); 1068 } 1069 sc->mii = device_get_softc(sc->miibus); 1070 1071 /* Select PHY and enable interrupts */ 1072 cpsw_write_4(sc->swsc, sc->physel, 1073 MDIO_PHYSEL_LINKINTENB | (sc->phy & 0x1F)); 1074 1075 ether_ifattach(sc->ifp, mac_addr); 1076 callout_init(&sc->mii_callout, 0); 1077 1078 return (0); 1079 } 1080 1081 static int 1082 cpswp_detach(device_t dev) 1083 { 1084 struct cpswp_softc *sc; 1085 1086 sc = device_get_softc(dev); 1087 CPSW_DEBUGF(sc->swsc, ("")); 1088 if (device_is_attached(dev)) { 1089 ether_ifdetach(sc->ifp); 1090 CPSW_PORT_LOCK(sc); 1091 cpswp_stop_locked(sc); 1092 CPSW_PORT_UNLOCK(sc); 1093 callout_drain(&sc->mii_callout); 1094 } 1095 1096 bus_generic_detach(dev); 1097 1098 if_free(sc->ifp); 1099 mtx_destroy(&sc->lock); 1100 1101 return (0); 1102 } 1103 1104 /* 1105 * 1106 * Init/Shutdown. 1107 * 1108 */ 1109 1110 static int 1111 cpsw_ports_down(struct cpsw_softc *sc) 1112 { 1113 struct cpswp_softc *psc; 1114 struct ifnet *ifp1, *ifp2; 1115 1116 if (!sc->dualemac) 1117 return (1); 1118 psc = device_get_softc(sc->port[0].dev); 1119 ifp1 = psc->ifp; 1120 psc = device_get_softc(sc->port[1].dev); 1121 ifp2 = psc->ifp; 1122 if ((ifp1->if_flags & IFF_UP) == 0 && (ifp2->if_flags & IFF_UP) == 0) 1123 return (1); 1124 1125 return (0); 1126 } 1127 1128 static void 1129 cpswp_init(void *arg) 1130 { 1131 struct cpswp_softc *sc = arg; 1132 1133 CPSW_DEBUGF(sc->swsc, ("")); 1134 CPSW_PORT_LOCK(sc); 1135 cpswp_init_locked(arg); 1136 CPSW_PORT_UNLOCK(sc); 1137 } 1138 1139 static void 1140 cpswp_init_locked(void *arg) 1141 { 1142 #ifdef CPSW_ETHERSWITCH 1143 int i; 1144 #endif 1145 struct cpswp_softc *sc = arg; 1146 struct ifnet *ifp; 1147 uint32_t reg; 1148 1149 CPSW_DEBUGF(sc->swsc, ("")); 1150 CPSW_PORT_LOCK_ASSERT(sc); 1151 ifp = sc->ifp; 1152 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1153 return; 1154 1155 getbinuptime(&sc->init_uptime); 1156 1157 if (!sc->swsc->rx.running && !sc->swsc->tx.running) { 1158 /* Reset the controller. */ 1159 cpsw_reset(sc->swsc); 1160 cpsw_init(sc->swsc); 1161 } 1162 1163 /* Set Slave Mapping. */ 1164 cpsw_write_4(sc->swsc, CPSW_SL_RX_PRI_MAP(sc->unit), 0x76543210); 1165 cpsw_write_4(sc->swsc, CPSW_PORT_P_TX_PRI_MAP(sc->unit + 1), 1166 0x33221100); 1167 cpsw_write_4(sc->swsc, CPSW_SL_RX_MAXLEN(sc->unit), 0x5f2); 1168 /* Enable MAC RX/TX modules. */ 1169 /* TODO: Docs claim that IFCTL_B and IFCTL_A do the same thing? */ 1170 /* Huh? Docs call bit 0 "Loopback" some places, "FullDuplex" others. */ 1171 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit)); 1172 reg |= CPSW_SL_MACTL_GMII_ENABLE; 1173 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg); 1174 1175 /* Initialize ALE: set port to forwarding, initialize addrs */ 1176 cpsw_write_4(sc->swsc, CPSW_ALE_PORTCTL(sc->unit + 1), 1177 ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD); 1178 cpswp_ale_update_addresses(sc, 1); 1179 1180 if (sc->swsc->dualemac) { 1181 /* Set Port VID. */ 1182 cpsw_write_4(sc->swsc, CPSW_PORT_P_VLAN(sc->unit + 1), 1183 sc->vlan & 0xfff); 1184 cpsw_ale_update_vlan_table(sc->swsc, sc->vlan, 1185 (1 << (sc->unit + 1)) | (1 << 0), /* Member list */ 1186 (1 << (sc->unit + 1)) | (1 << 0), /* Untagged egress */ 1187 (1 << (sc->unit + 1)) | (1 << 0), 0); /* mcast reg flood */ 1188 #ifdef CPSW_ETHERSWITCH 1189 for (i = 0; i < CPSW_VLANS; i++) { 1190 if (cpsw_vgroups[i].vid != -1) 1191 continue; 1192 cpsw_vgroups[i].vid = sc->vlan; 1193 break; 1194 } 1195 #endif 1196 } 1197 1198 mii_mediachg(sc->mii); 1199 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc); 1200 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1201 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1202 } 1203 1204 static int 1205 cpsw_shutdown(device_t dev) 1206 { 1207 struct cpsw_softc *sc; 1208 struct cpswp_softc *psc; 1209 int i; 1210 1211 sc = device_get_softc(dev); 1212 CPSW_DEBUGF(sc, ("")); 1213 for (i = 0; i < CPSW_PORTS; i++) { 1214 if (!sc->dualemac && i != sc->active_slave) 1215 continue; 1216 psc = device_get_softc(sc->port[i].dev); 1217 CPSW_PORT_LOCK(psc); 1218 cpswp_stop_locked(psc); 1219 CPSW_PORT_UNLOCK(psc); 1220 } 1221 1222 return (0); 1223 } 1224 1225 static void 1226 cpsw_rx_teardown(struct cpsw_softc *sc) 1227 { 1228 int i = 0; 1229 1230 CPSW_RX_LOCK(sc); 1231 CPSW_DEBUGF(sc, ("starting RX teardown")); 1232 sc->rx.teardown = 1; 1233 cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0); 1234 CPSW_RX_UNLOCK(sc); 1235 while (sc->rx.running) { 1236 if (++i > 10) { 1237 device_printf(sc->dev, 1238 "Unable to cleanly shutdown receiver\n"); 1239 return; 1240 } 1241 DELAY(200); 1242 } 1243 if (!sc->rx.running) 1244 CPSW_DEBUGF(sc, ("finished RX teardown (%d retries)", i)); 1245 } 1246 1247 static void 1248 cpsw_tx_teardown(struct cpsw_softc *sc) 1249 { 1250 int i = 0; 1251 1252 CPSW_TX_LOCK(sc); 1253 CPSW_DEBUGF(sc, ("starting TX teardown")); 1254 /* Start the TX queue teardown if queue is not empty. */ 1255 if (STAILQ_FIRST(&sc->tx.active) != NULL) 1256 cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0); 1257 else 1258 sc->tx.teardown = 1; 1259 cpsw_tx_dequeue(sc); 1260 while (sc->tx.running && ++i < 10) { 1261 DELAY(200); 1262 cpsw_tx_dequeue(sc); 1263 } 1264 if (sc->tx.running) { 1265 device_printf(sc->dev, 1266 "Unable to cleanly shutdown transmitter\n"); 1267 } 1268 CPSW_DEBUGF(sc, 1269 ("finished TX teardown (%d retries, %d idle buffers)", i, 1270 sc->tx.active_queue_len)); 1271 CPSW_TX_UNLOCK(sc); 1272 } 1273 1274 static void 1275 cpswp_stop_locked(struct cpswp_softc *sc) 1276 { 1277 struct ifnet *ifp; 1278 uint32_t reg; 1279 1280 ifp = sc->ifp; 1281 CPSW_DEBUGF(sc->swsc, ("")); 1282 CPSW_PORT_LOCK_ASSERT(sc); 1283 1284 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1285 return; 1286 1287 /* Disable interface */ 1288 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1289 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1290 1291 /* Stop ticker */ 1292 callout_stop(&sc->mii_callout); 1293 1294 /* Tear down the RX/TX queues. */ 1295 if (cpsw_ports_down(sc->swsc)) { 1296 cpsw_rx_teardown(sc->swsc); 1297 cpsw_tx_teardown(sc->swsc); 1298 } 1299 1300 /* Stop MAC RX/TX modules. */ 1301 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit)); 1302 reg &= ~CPSW_SL_MACTL_GMII_ENABLE; 1303 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg); 1304 1305 if (cpsw_ports_down(sc->swsc)) { 1306 /* Capture stats before we reset controller. */ 1307 cpsw_stats_collect(sc->swsc); 1308 1309 cpsw_reset(sc->swsc); 1310 cpsw_init(sc->swsc); 1311 } 1312 } 1313 1314 /* 1315 * Suspend/Resume. 1316 */ 1317 1318 static int 1319 cpsw_suspend(device_t dev) 1320 { 1321 struct cpsw_softc *sc; 1322 struct cpswp_softc *psc; 1323 int i; 1324 1325 sc = device_get_softc(dev); 1326 CPSW_DEBUGF(sc, ("")); 1327 for (i = 0; i < CPSW_PORTS; i++) { 1328 if (!sc->dualemac && i != sc->active_slave) 1329 continue; 1330 psc = device_get_softc(sc->port[i].dev); 1331 CPSW_PORT_LOCK(psc); 1332 cpswp_stop_locked(psc); 1333 CPSW_PORT_UNLOCK(psc); 1334 } 1335 1336 return (0); 1337 } 1338 1339 static int 1340 cpsw_resume(device_t dev) 1341 { 1342 struct cpsw_softc *sc; 1343 1344 sc = device_get_softc(dev); 1345 CPSW_DEBUGF(sc, ("UNIMPLEMENTED")); 1346 1347 return (0); 1348 } 1349 1350 /* 1351 * 1352 * IOCTL 1353 * 1354 */ 1355 1356 static void 1357 cpsw_set_promisc(struct cpswp_softc *sc, int set) 1358 { 1359 uint32_t reg; 1360 1361 /* 1362 * Enabling promiscuous mode requires ALE_BYPASS to be enabled. 1363 * That disables the ALE forwarding logic and causes every 1364 * packet to be sent only to the host port. In bypass mode, 1365 * the ALE processes host port transmit packets the same as in 1366 * normal mode. 1367 */ 1368 reg = cpsw_read_4(sc->swsc, CPSW_ALE_CONTROL); 1369 reg &= ~CPSW_ALE_CTL_BYPASS; 1370 if (set) 1371 reg |= CPSW_ALE_CTL_BYPASS; 1372 cpsw_write_4(sc->swsc, CPSW_ALE_CONTROL, reg); 1373 } 1374 1375 static void 1376 cpsw_set_allmulti(struct cpswp_softc *sc, int set) 1377 { 1378 if (set) { 1379 printf("All-multicast mode unimplemented\n"); 1380 } 1381 } 1382 1383 static int 1384 cpswp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1385 { 1386 struct cpswp_softc *sc; 1387 struct ifreq *ifr; 1388 int error; 1389 uint32_t changed; 1390 1391 error = 0; 1392 sc = ifp->if_softc; 1393 ifr = (struct ifreq *)data; 1394 1395 switch (command) { 1396 case SIOCSIFCAP: 1397 changed = ifp->if_capenable ^ ifr->ifr_reqcap; 1398 if (changed & IFCAP_HWCSUM) { 1399 if ((ifr->ifr_reqcap & changed) & IFCAP_HWCSUM) 1400 ifp->if_capenable |= IFCAP_HWCSUM; 1401 else 1402 ifp->if_capenable &= ~IFCAP_HWCSUM; 1403 } 1404 error = 0; 1405 break; 1406 case SIOCSIFFLAGS: 1407 CPSW_PORT_LOCK(sc); 1408 if (ifp->if_flags & IFF_UP) { 1409 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1410 changed = ifp->if_flags ^ sc->if_flags; 1411 CPSW_DEBUGF(sc->swsc, 1412 ("SIOCSIFFLAGS: UP & RUNNING (changed=0x%x)", 1413 changed)); 1414 if (changed & IFF_PROMISC) 1415 cpsw_set_promisc(sc, 1416 ifp->if_flags & IFF_PROMISC); 1417 if (changed & IFF_ALLMULTI) 1418 cpsw_set_allmulti(sc, 1419 ifp->if_flags & IFF_ALLMULTI); 1420 } else { 1421 CPSW_DEBUGF(sc->swsc, 1422 ("SIOCSIFFLAGS: starting up")); 1423 cpswp_init_locked(sc); 1424 } 1425 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1426 CPSW_DEBUGF(sc->swsc, ("SIOCSIFFLAGS: shutting down")); 1427 cpswp_stop_locked(sc); 1428 } 1429 1430 sc->if_flags = ifp->if_flags; 1431 CPSW_PORT_UNLOCK(sc); 1432 break; 1433 case SIOCADDMULTI: 1434 cpswp_ale_update_addresses(sc, 0); 1435 break; 1436 case SIOCDELMULTI: 1437 /* Ugh. DELMULTI doesn't provide the specific address 1438 being removed, so the best we can do is remove 1439 everything and rebuild it all. */ 1440 cpswp_ale_update_addresses(sc, 1); 1441 break; 1442 case SIOCGIFMEDIA: 1443 case SIOCSIFMEDIA: 1444 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, command); 1445 break; 1446 default: 1447 error = ether_ioctl(ifp, command, data); 1448 } 1449 return (error); 1450 } 1451 1452 /* 1453 * 1454 * MIIBUS 1455 * 1456 */ 1457 static int 1458 cpswp_miibus_ready(struct cpsw_softc *sc, uint32_t reg) 1459 { 1460 uint32_t r, retries = CPSW_MIIBUS_RETRIES; 1461 1462 while (--retries) { 1463 r = cpsw_read_4(sc, reg); 1464 if ((r & MDIO_PHYACCESS_GO) == 0) 1465 return (1); 1466 DELAY(CPSW_MIIBUS_DELAY); 1467 } 1468 1469 return (0); 1470 } 1471 1472 static int 1473 cpswp_miibus_readreg(device_t dev, int phy, int reg) 1474 { 1475 struct cpswp_softc *sc; 1476 uint32_t cmd, r; 1477 1478 sc = device_get_softc(dev); 1479 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1480 device_printf(dev, "MDIO not ready to read\n"); 1481 return (0); 1482 } 1483 1484 /* Set GO, reg, phy */ 1485 cmd = MDIO_PHYACCESS_GO | (reg & 0x1F) << 21 | (phy & 0x1F) << 16; 1486 cpsw_write_4(sc->swsc, sc->phyaccess, cmd); 1487 1488 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1489 device_printf(dev, "MDIO timed out during read\n"); 1490 return (0); 1491 } 1492 1493 r = cpsw_read_4(sc->swsc, sc->phyaccess); 1494 if ((r & MDIO_PHYACCESS_ACK) == 0) { 1495 device_printf(dev, "Failed to read from PHY.\n"); 1496 r = 0; 1497 } 1498 return (r & 0xFFFF); 1499 } 1500 1501 static int 1502 cpswp_miibus_writereg(device_t dev, int phy, int reg, int value) 1503 { 1504 struct cpswp_softc *sc; 1505 uint32_t cmd; 1506 1507 sc = device_get_softc(dev); 1508 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1509 device_printf(dev, "MDIO not ready to write\n"); 1510 return (0); 1511 } 1512 1513 /* Set GO, WRITE, reg, phy, and value */ 1514 cmd = MDIO_PHYACCESS_GO | MDIO_PHYACCESS_WRITE | 1515 (reg & 0x1F) << 21 | (phy & 0x1F) << 16 | (value & 0xFFFF); 1516 cpsw_write_4(sc->swsc, sc->phyaccess, cmd); 1517 1518 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1519 device_printf(dev, "MDIO timed out during write\n"); 1520 return (0); 1521 } 1522 1523 return (0); 1524 } 1525 1526 static void 1527 cpswp_miibus_statchg(device_t dev) 1528 { 1529 struct cpswp_softc *sc; 1530 uint32_t mac_control, reg; 1531 1532 sc = device_get_softc(dev); 1533 CPSW_DEBUGF(sc->swsc, ("")); 1534 1535 reg = CPSW_SL_MACCONTROL(sc->unit); 1536 mac_control = cpsw_read_4(sc->swsc, reg); 1537 mac_control &= ~(CPSW_SL_MACTL_GIG | CPSW_SL_MACTL_IFCTL_A | 1538 CPSW_SL_MACTL_IFCTL_B | CPSW_SL_MACTL_FULLDUPLEX); 1539 1540 switch(IFM_SUBTYPE(sc->mii->mii_media_active)) { 1541 case IFM_1000_SX: 1542 case IFM_1000_LX: 1543 case IFM_1000_CX: 1544 case IFM_1000_T: 1545 mac_control |= CPSW_SL_MACTL_GIG; 1546 break; 1547 1548 case IFM_100_TX: 1549 mac_control |= CPSW_SL_MACTL_IFCTL_A; 1550 break; 1551 } 1552 if (sc->mii->mii_media_active & IFM_FDX) 1553 mac_control |= CPSW_SL_MACTL_FULLDUPLEX; 1554 1555 cpsw_write_4(sc->swsc, reg, mac_control); 1556 } 1557 1558 /* 1559 * 1560 * Transmit/Receive Packets. 1561 * 1562 */ 1563 static void 1564 cpsw_intr_rx(void *arg) 1565 { 1566 struct cpsw_softc *sc; 1567 struct ifnet *ifp; 1568 struct mbuf *received, *next; 1569 1570 sc = (struct cpsw_softc *)arg; 1571 CPSW_RX_LOCK(sc); 1572 if (sc->rx.teardown) { 1573 sc->rx.running = 0; 1574 sc->rx.teardown = 0; 1575 cpsw_write_cp(sc, &sc->rx, 0xfffffffc); 1576 } 1577 received = cpsw_rx_dequeue(sc); 1578 cpsw_rx_enqueue(sc); 1579 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 1); 1580 CPSW_RX_UNLOCK(sc); 1581 1582 while (received != NULL) { 1583 next = received->m_nextpkt; 1584 received->m_nextpkt = NULL; 1585 ifp = received->m_pkthdr.rcvif; 1586 (*ifp->if_input)(ifp, received); 1587 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1588 received = next; 1589 } 1590 } 1591 1592 static struct mbuf * 1593 cpsw_rx_dequeue(struct cpsw_softc *sc) 1594 { 1595 int nsegs, port, removed; 1596 struct cpsw_cpdma_bd bd; 1597 struct cpsw_slot *last, *slot; 1598 struct cpswp_softc *psc; 1599 struct mbuf *m, *m0, *mb_head, *mb_tail; 1600 uint16_t m0_flags; 1601 1602 nsegs = 0; 1603 m0 = NULL; 1604 last = NULL; 1605 mb_head = NULL; 1606 mb_tail = NULL; 1607 removed = 0; 1608 1609 /* Pull completed packets off hardware RX queue. */ 1610 while ((slot = STAILQ_FIRST(&sc->rx.active)) != NULL) { 1611 cpsw_cpdma_read_bd(sc, slot, &bd); 1612 1613 /* 1614 * Stop on packets still in use by hardware, but do not stop 1615 * on packets with the teardown complete flag, they will be 1616 * discarded later. 1617 */ 1618 if ((bd.flags & (CPDMA_BD_OWNER | CPDMA_BD_TDOWNCMPLT)) == 1619 CPDMA_BD_OWNER) 1620 break; 1621 1622 last = slot; 1623 ++removed; 1624 STAILQ_REMOVE_HEAD(&sc->rx.active, next); 1625 STAILQ_INSERT_TAIL(&sc->rx.avail, slot, next); 1626 1627 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTREAD); 1628 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1629 1630 m = slot->mbuf; 1631 slot->mbuf = NULL; 1632 1633 if (bd.flags & CPDMA_BD_TDOWNCMPLT) { 1634 CPSW_DEBUGF(sc, ("RX teardown is complete")); 1635 m_freem(m); 1636 sc->rx.running = 0; 1637 sc->rx.teardown = 0; 1638 break; 1639 } 1640 1641 port = (bd.flags & CPDMA_BD_PORT_MASK) - 1; 1642 KASSERT(port >= 0 && port <= 1, 1643 ("patcket received with invalid port: %d", port)); 1644 psc = device_get_softc(sc->port[port].dev); 1645 1646 /* Set up mbuf */ 1647 m->m_data += bd.bufoff; 1648 m->m_len = bd.buflen; 1649 if (bd.flags & CPDMA_BD_SOP) { 1650 m->m_pkthdr.len = bd.pktlen; 1651 m->m_pkthdr.rcvif = psc->ifp; 1652 m->m_flags |= M_PKTHDR; 1653 m0_flags = bd.flags; 1654 m0 = m; 1655 } 1656 nsegs++; 1657 m->m_next = NULL; 1658 m->m_nextpkt = NULL; 1659 if (bd.flags & CPDMA_BD_EOP && m0 != NULL) { 1660 if (m0_flags & CPDMA_BD_PASS_CRC) 1661 m_adj(m0, -ETHER_CRC_LEN); 1662 m0_flags = 0; 1663 m0 = NULL; 1664 if (nsegs > sc->rx.longest_chain) 1665 sc->rx.longest_chain = nsegs; 1666 nsegs = 0; 1667 } 1668 1669 if ((psc->ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1670 /* check for valid CRC by looking into pkt_err[5:4] */ 1671 if ((bd.flags & 1672 (CPDMA_BD_SOP | CPDMA_BD_PKT_ERR_MASK)) == 1673 CPDMA_BD_SOP) { 1674 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1675 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1676 m->m_pkthdr.csum_data = 0xffff; 1677 } 1678 } 1679 1680 if (STAILQ_FIRST(&sc->rx.active) != NULL && 1681 (bd.flags & (CPDMA_BD_EOP | CPDMA_BD_EOQ)) == 1682 (CPDMA_BD_EOP | CPDMA_BD_EOQ)) { 1683 cpsw_write_hdp_slot(sc, &sc->rx, 1684 STAILQ_FIRST(&sc->rx.active)); 1685 sc->rx.queue_restart++; 1686 } 1687 1688 /* Add mbuf to packet list to be returned. */ 1689 if (mb_tail != NULL && (bd.flags & CPDMA_BD_SOP)) { 1690 mb_tail->m_nextpkt = m; 1691 } else if (mb_tail != NULL) { 1692 mb_tail->m_next = m; 1693 } else if (mb_tail == NULL && (bd.flags & CPDMA_BD_SOP) == 0) { 1694 if (bootverbose) 1695 printf( 1696 "%s: %s: discanding fragment packet w/o header\n", 1697 __func__, psc->ifp->if_xname); 1698 m_freem(m); 1699 continue; 1700 } else { 1701 mb_head = m; 1702 } 1703 mb_tail = m; 1704 } 1705 1706 if (removed != 0) { 1707 cpsw_write_cp_slot(sc, &sc->rx, last); 1708 sc->rx.queue_removes += removed; 1709 sc->rx.avail_queue_len += removed; 1710 sc->rx.active_queue_len -= removed; 1711 if (sc->rx.avail_queue_len > sc->rx.max_avail_queue_len) 1712 sc->rx.max_avail_queue_len = sc->rx.avail_queue_len; 1713 CPSW_DEBUGF(sc, ("Removed %d received packet(s) from RX queue", removed)); 1714 } 1715 1716 return (mb_head); 1717 } 1718 1719 static void 1720 cpsw_rx_enqueue(struct cpsw_softc *sc) 1721 { 1722 bus_dma_segment_t seg[1]; 1723 struct cpsw_cpdma_bd bd; 1724 struct cpsw_slot *first_new_slot, *last_old_slot, *next, *slot; 1725 int error, nsegs, added = 0; 1726 1727 /* Register new mbufs with hardware. */ 1728 first_new_slot = NULL; 1729 last_old_slot = STAILQ_LAST(&sc->rx.active, cpsw_slot, next); 1730 while ((slot = STAILQ_FIRST(&sc->rx.avail)) != NULL) { 1731 if (first_new_slot == NULL) 1732 first_new_slot = slot; 1733 if (slot->mbuf == NULL) { 1734 slot->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1735 if (slot->mbuf == NULL) { 1736 device_printf(sc->dev, 1737 "Unable to fill RX queue\n"); 1738 break; 1739 } 1740 slot->mbuf->m_len = 1741 slot->mbuf->m_pkthdr.len = 1742 slot->mbuf->m_ext.ext_size; 1743 } 1744 1745 error = bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, slot->dmamap, 1746 slot->mbuf, seg, &nsegs, BUS_DMA_NOWAIT); 1747 1748 KASSERT(nsegs == 1, ("More than one segment (nsegs=%d)", nsegs)); 1749 KASSERT(error == 0, ("DMA error (error=%d)", error)); 1750 if (error != 0 || nsegs != 1) { 1751 device_printf(sc->dev, 1752 "%s: Can't prep RX buf for DMA (nsegs=%d, error=%d)\n", 1753 __func__, nsegs, error); 1754 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1755 m_freem(slot->mbuf); 1756 slot->mbuf = NULL; 1757 break; 1758 } 1759 1760 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_PREREAD); 1761 1762 /* Create and submit new rx descriptor. */ 1763 if ((next = STAILQ_NEXT(slot, next)) != NULL) 1764 bd.next = cpsw_cpdma_bd_paddr(sc, next); 1765 else 1766 bd.next = 0; 1767 bd.bufptr = seg->ds_addr; 1768 bd.bufoff = 0; 1769 bd.buflen = MCLBYTES - 1; 1770 bd.pktlen = bd.buflen; 1771 bd.flags = CPDMA_BD_OWNER; 1772 cpsw_cpdma_write_bd(sc, slot, &bd); 1773 ++added; 1774 1775 STAILQ_REMOVE_HEAD(&sc->rx.avail, next); 1776 STAILQ_INSERT_TAIL(&sc->rx.active, slot, next); 1777 } 1778 1779 if (added == 0 || first_new_slot == NULL) 1780 return; 1781 1782 CPSW_DEBUGF(sc, ("Adding %d buffers to RX queue", added)); 1783 1784 /* Link new entries to hardware RX queue. */ 1785 if (last_old_slot == NULL) { 1786 /* Start a fresh queue. */ 1787 cpsw_write_hdp_slot(sc, &sc->rx, first_new_slot); 1788 } else { 1789 /* Add buffers to end of current queue. */ 1790 cpsw_cpdma_write_bd_next(sc, last_old_slot, first_new_slot); 1791 } 1792 sc->rx.queue_adds += added; 1793 sc->rx.avail_queue_len -= added; 1794 sc->rx.active_queue_len += added; 1795 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), added); 1796 if (sc->rx.active_queue_len > sc->rx.max_active_queue_len) 1797 sc->rx.max_active_queue_len = sc->rx.active_queue_len; 1798 } 1799 1800 static void 1801 cpswp_start(struct ifnet *ifp) 1802 { 1803 struct cpswp_softc *sc; 1804 1805 sc = ifp->if_softc; 1806 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1807 sc->swsc->tx.running == 0) { 1808 return; 1809 } 1810 CPSW_TX_LOCK(sc->swsc); 1811 cpswp_tx_enqueue(sc); 1812 cpsw_tx_dequeue(sc->swsc); 1813 CPSW_TX_UNLOCK(sc->swsc); 1814 } 1815 1816 static void 1817 cpsw_intr_tx(void *arg) 1818 { 1819 struct cpsw_softc *sc; 1820 1821 sc = (struct cpsw_softc *)arg; 1822 CPSW_TX_LOCK(sc); 1823 if (cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)) == 0xfffffffc) 1824 cpsw_write_cp(sc, &sc->tx, 0xfffffffc); 1825 cpsw_tx_dequeue(sc); 1826 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 2); 1827 CPSW_TX_UNLOCK(sc); 1828 } 1829 1830 static void 1831 cpswp_tx_enqueue(struct cpswp_softc *sc) 1832 { 1833 bus_dma_segment_t segs[CPSW_TXFRAGS]; 1834 struct cpsw_cpdma_bd bd; 1835 struct cpsw_slot *first_new_slot, *last, *last_old_slot, *next, *slot; 1836 struct mbuf *m0; 1837 int error, nsegs, seg, added = 0, padlen; 1838 1839 /* Pull pending packets from IF queue and prep them for DMA. */ 1840 last = NULL; 1841 first_new_slot = NULL; 1842 last_old_slot = STAILQ_LAST(&sc->swsc->tx.active, cpsw_slot, next); 1843 while ((slot = STAILQ_FIRST(&sc->swsc->tx.avail)) != NULL) { 1844 IF_DEQUEUE(&sc->ifp->if_snd, m0); 1845 if (m0 == NULL) 1846 break; 1847 1848 slot->mbuf = m0; 1849 padlen = ETHER_MIN_LEN - ETHER_CRC_LEN - m0->m_pkthdr.len; 1850 if (padlen < 0) 1851 padlen = 0; 1852 else if (padlen > 0) 1853 m_append(slot->mbuf, padlen, sc->swsc->nullpad); 1854 1855 /* Create mapping in DMA memory */ 1856 error = bus_dmamap_load_mbuf_sg(sc->swsc->mbuf_dtag, 1857 slot->dmamap, slot->mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 1858 /* If the packet is too fragmented, try to simplify. */ 1859 if (error == EFBIG || 1860 (error == 0 && nsegs > sc->swsc->tx.avail_queue_len)) { 1861 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap); 1862 m0 = m_defrag(slot->mbuf, M_NOWAIT); 1863 if (m0 == NULL) { 1864 device_printf(sc->dev, 1865 "Can't defragment packet; dropping\n"); 1866 m_freem(slot->mbuf); 1867 } else { 1868 CPSW_DEBUGF(sc->swsc, 1869 ("Requeueing defragmented packet")); 1870 IF_PREPEND(&sc->ifp->if_snd, m0); 1871 } 1872 slot->mbuf = NULL; 1873 continue; 1874 } 1875 if (error != 0) { 1876 device_printf(sc->dev, 1877 "%s: Can't setup DMA (error=%d), dropping packet\n", 1878 __func__, error); 1879 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap); 1880 m_freem(slot->mbuf); 1881 slot->mbuf = NULL; 1882 break; 1883 } 1884 1885 bus_dmamap_sync(sc->swsc->mbuf_dtag, slot->dmamap, 1886 BUS_DMASYNC_PREWRITE); 1887 1888 CPSW_DEBUGF(sc->swsc, 1889 ("Queueing TX packet: %d segments + %d pad bytes", 1890 nsegs, padlen)); 1891 1892 if (first_new_slot == NULL) 1893 first_new_slot = slot; 1894 1895 /* Link from the previous descriptor. */ 1896 if (last != NULL) 1897 cpsw_cpdma_write_bd_next(sc->swsc, last, slot); 1898 1899 slot->ifp = sc->ifp; 1900 1901 /* If there is only one segment, the for() loop 1902 * gets skipped and the single buffer gets set up 1903 * as both SOP and EOP. */ 1904 if (nsegs > 1) { 1905 next = STAILQ_NEXT(slot, next); 1906 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next); 1907 } else 1908 bd.next = 0; 1909 /* Start by setting up the first buffer. */ 1910 bd.bufptr = segs[0].ds_addr; 1911 bd.bufoff = 0; 1912 bd.buflen = segs[0].ds_len; 1913 bd.pktlen = m_length(slot->mbuf, NULL); 1914 bd.flags = CPDMA_BD_SOP | CPDMA_BD_OWNER; 1915 if (sc->swsc->dualemac) { 1916 bd.flags |= CPDMA_BD_TO_PORT; 1917 bd.flags |= ((sc->unit + 1) & CPDMA_BD_PORT_MASK); 1918 } 1919 for (seg = 1; seg < nsegs; ++seg) { 1920 /* Save the previous buffer (which isn't EOP) */ 1921 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1922 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1923 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next); 1924 slot = STAILQ_FIRST(&sc->swsc->tx.avail); 1925 1926 /* Setup next buffer (which isn't SOP) */ 1927 if (nsegs > seg + 1) { 1928 next = STAILQ_NEXT(slot, next); 1929 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next); 1930 } else 1931 bd.next = 0; 1932 bd.bufptr = segs[seg].ds_addr; 1933 bd.bufoff = 0; 1934 bd.buflen = segs[seg].ds_len; 1935 bd.pktlen = 0; 1936 bd.flags = CPDMA_BD_OWNER; 1937 } 1938 1939 /* Save the final buffer. */ 1940 bd.flags |= CPDMA_BD_EOP; 1941 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1942 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1943 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next); 1944 1945 last = slot; 1946 added += nsegs; 1947 if (nsegs > sc->swsc->tx.longest_chain) 1948 sc->swsc->tx.longest_chain = nsegs; 1949 1950 BPF_MTAP(sc->ifp, m0); 1951 } 1952 1953 if (first_new_slot == NULL) 1954 return; 1955 1956 /* Attach the list of new buffers to the hardware TX queue. */ 1957 if (last_old_slot != NULL && 1958 (cpsw_cpdma_read_bd_flags(sc->swsc, last_old_slot) & 1959 CPDMA_BD_EOQ) == 0) { 1960 /* Add buffers to end of current queue. */ 1961 cpsw_cpdma_write_bd_next(sc->swsc, last_old_slot, 1962 first_new_slot); 1963 } else { 1964 /* Start a fresh queue. */ 1965 cpsw_write_hdp_slot(sc->swsc, &sc->swsc->tx, first_new_slot); 1966 } 1967 sc->swsc->tx.queue_adds += added; 1968 sc->swsc->tx.avail_queue_len -= added; 1969 sc->swsc->tx.active_queue_len += added; 1970 if (sc->swsc->tx.active_queue_len > sc->swsc->tx.max_active_queue_len) { 1971 sc->swsc->tx.max_active_queue_len = sc->swsc->tx.active_queue_len; 1972 } 1973 CPSW_DEBUGF(sc->swsc, ("Queued %d TX packet(s)", added)); 1974 } 1975 1976 static int 1977 cpsw_tx_dequeue(struct cpsw_softc *sc) 1978 { 1979 struct cpsw_slot *slot, *last_removed_slot = NULL; 1980 struct cpsw_cpdma_bd bd; 1981 uint32_t flags, removed = 0; 1982 1983 /* Pull completed buffers off the hardware TX queue. */ 1984 slot = STAILQ_FIRST(&sc->tx.active); 1985 while (slot != NULL) { 1986 flags = cpsw_cpdma_read_bd_flags(sc, slot); 1987 1988 /* TearDown complete is only marked on the SOP for the packet. */ 1989 if ((flags & (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) == 1990 (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) { 1991 sc->tx.teardown = 1; 1992 } 1993 1994 if ((flags & (CPDMA_BD_SOP | CPDMA_BD_OWNER)) == 1995 (CPDMA_BD_SOP | CPDMA_BD_OWNER) && sc->tx.teardown == 0) 1996 break; /* Hardware is still using this packet. */ 1997 1998 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 1999 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 2000 m_freem(slot->mbuf); 2001 slot->mbuf = NULL; 2002 2003 if (slot->ifp) { 2004 if (sc->tx.teardown == 0) 2005 if_inc_counter(slot->ifp, IFCOUNTER_OPACKETS, 1); 2006 else 2007 if_inc_counter(slot->ifp, IFCOUNTER_OQDROPS, 1); 2008 } 2009 2010 /* Dequeue any additional buffers used by this packet. */ 2011 while (slot != NULL && slot->mbuf == NULL) { 2012 STAILQ_REMOVE_HEAD(&sc->tx.active, next); 2013 STAILQ_INSERT_TAIL(&sc->tx.avail, slot, next); 2014 ++removed; 2015 last_removed_slot = slot; 2016 slot = STAILQ_FIRST(&sc->tx.active); 2017 } 2018 2019 cpsw_write_cp_slot(sc, &sc->tx, last_removed_slot); 2020 2021 /* Restart the TX queue if necessary. */ 2022 cpsw_cpdma_read_bd(sc, last_removed_slot, &bd); 2023 if (slot != NULL && bd.next != 0 && (bd.flags & 2024 (CPDMA_BD_EOP | CPDMA_BD_OWNER | CPDMA_BD_EOQ)) == 2025 (CPDMA_BD_EOP | CPDMA_BD_EOQ)) { 2026 cpsw_write_hdp_slot(sc, &sc->tx, slot); 2027 sc->tx.queue_restart++; 2028 break; 2029 } 2030 } 2031 2032 if (removed != 0) { 2033 sc->tx.queue_removes += removed; 2034 sc->tx.active_queue_len -= removed; 2035 sc->tx.avail_queue_len += removed; 2036 if (sc->tx.avail_queue_len > sc->tx.max_avail_queue_len) 2037 sc->tx.max_avail_queue_len = sc->tx.avail_queue_len; 2038 CPSW_DEBUGF(sc, ("TX removed %d completed packet(s)", removed)); 2039 } 2040 2041 if (sc->tx.teardown && STAILQ_EMPTY(&sc->tx.active)) { 2042 CPSW_DEBUGF(sc, ("TX teardown is complete")); 2043 sc->tx.teardown = 0; 2044 sc->tx.running = 0; 2045 } 2046 2047 return (removed); 2048 } 2049 2050 /* 2051 * 2052 * Miscellaneous interrupts. 2053 * 2054 */ 2055 2056 static void 2057 cpsw_intr_rx_thresh(void *arg) 2058 { 2059 struct cpsw_softc *sc; 2060 struct ifnet *ifp; 2061 struct mbuf *received, *next; 2062 2063 sc = (struct cpsw_softc *)arg; 2064 CPSW_RX_LOCK(sc); 2065 received = cpsw_rx_dequeue(sc); 2066 cpsw_rx_enqueue(sc); 2067 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 0); 2068 CPSW_RX_UNLOCK(sc); 2069 2070 while (received != NULL) { 2071 next = received->m_nextpkt; 2072 received->m_nextpkt = NULL; 2073 ifp = received->m_pkthdr.rcvif; 2074 (*ifp->if_input)(ifp, received); 2075 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2076 received = next; 2077 } 2078 } 2079 2080 static void 2081 cpsw_intr_misc_host_error(struct cpsw_softc *sc) 2082 { 2083 uint32_t intstat; 2084 uint32_t dmastat; 2085 int txerr, rxerr, txchan, rxchan; 2086 2087 printf("\n\n"); 2088 device_printf(sc->dev, 2089 "HOST ERROR: PROGRAMMING ERROR DETECTED BY HARDWARE\n"); 2090 printf("\n\n"); 2091 intstat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 2092 device_printf(sc->dev, "CPSW_CPDMA_DMA_INTSTAT_MASKED=0x%x\n", intstat); 2093 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS); 2094 device_printf(sc->dev, "CPSW_CPDMA_DMASTATUS=0x%x\n", dmastat); 2095 2096 txerr = (dmastat >> 20) & 15; 2097 txchan = (dmastat >> 16) & 7; 2098 rxerr = (dmastat >> 12) & 15; 2099 rxchan = (dmastat >> 8) & 7; 2100 2101 switch (txerr) { 2102 case 0: break; 2103 case 1: printf("SOP error on TX channel %d\n", txchan); 2104 break; 2105 case 2: printf("Ownership bit not set on SOP buffer on TX channel %d\n", txchan); 2106 break; 2107 case 3: printf("Zero Next Buffer but not EOP on TX channel %d\n", txchan); 2108 break; 2109 case 4: printf("Zero Buffer Pointer on TX channel %d\n", txchan); 2110 break; 2111 case 5: printf("Zero Buffer Length on TX channel %d\n", txchan); 2112 break; 2113 case 6: printf("Packet length error on TX channel %d\n", txchan); 2114 break; 2115 default: printf("Unknown error on TX channel %d\n", txchan); 2116 break; 2117 } 2118 2119 if (txerr != 0) { 2120 printf("CPSW_CPDMA_TX%d_HDP=0x%x\n", 2121 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(txchan))); 2122 printf("CPSW_CPDMA_TX%d_CP=0x%x\n", 2123 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_CP(txchan))); 2124 cpsw_dump_queue(sc, &sc->tx.active); 2125 } 2126 2127 switch (rxerr) { 2128 case 0: break; 2129 case 2: printf("Ownership bit not set on RX channel %d\n", rxchan); 2130 break; 2131 case 4: printf("Zero Buffer Pointer on RX channel %d\n", rxchan); 2132 break; 2133 case 5: printf("Zero Buffer Length on RX channel %d\n", rxchan); 2134 break; 2135 case 6: printf("Buffer offset too big on RX channel %d\n", rxchan); 2136 break; 2137 default: printf("Unknown RX error on RX channel %d\n", rxchan); 2138 break; 2139 } 2140 2141 if (rxerr != 0) { 2142 printf("CPSW_CPDMA_RX%d_HDP=0x%x\n", 2143 rxchan, cpsw_read_4(sc,CPSW_CPDMA_RX_HDP(rxchan))); 2144 printf("CPSW_CPDMA_RX%d_CP=0x%x\n", 2145 rxchan, cpsw_read_4(sc, CPSW_CPDMA_RX_CP(rxchan))); 2146 cpsw_dump_queue(sc, &sc->rx.active); 2147 } 2148 2149 printf("\nALE Table\n"); 2150 cpsw_ale_dump_table(sc); 2151 2152 // XXX do something useful here?? 2153 panic("CPSW HOST ERROR INTERRUPT"); 2154 2155 // Suppress this interrupt in the future. 2156 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, intstat); 2157 printf("XXX HOST ERROR INTERRUPT SUPPRESSED\n"); 2158 // The watchdog will probably reset the controller 2159 // in a little while. It will probably fail again. 2160 } 2161 2162 static void 2163 cpsw_intr_misc(void *arg) 2164 { 2165 struct cpsw_softc *sc = arg; 2166 uint32_t stat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0)); 2167 2168 if (stat & CPSW_WR_C_MISC_EVNT_PEND) 2169 CPSW_DEBUGF(sc, ("Time sync event interrupt unimplemented")); 2170 if (stat & CPSW_WR_C_MISC_STAT_PEND) 2171 cpsw_stats_collect(sc); 2172 if (stat & CPSW_WR_C_MISC_HOST_PEND) 2173 cpsw_intr_misc_host_error(sc); 2174 if (stat & CPSW_WR_C_MISC_MDIOLINK) { 2175 cpsw_write_4(sc, MDIOLINKINTMASKED, 2176 cpsw_read_4(sc, MDIOLINKINTMASKED)); 2177 } 2178 if (stat & CPSW_WR_C_MISC_MDIOUSER) { 2179 CPSW_DEBUGF(sc, 2180 ("MDIO operation completed interrupt unimplemented")); 2181 } 2182 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 3); 2183 } 2184 2185 /* 2186 * 2187 * Periodic Checks and Watchdog. 2188 * 2189 */ 2190 2191 static void 2192 cpswp_tick(void *msc) 2193 { 2194 struct cpswp_softc *sc = msc; 2195 2196 /* Check for media type change */ 2197 mii_tick(sc->mii); 2198 if (sc->media_status != sc->mii->mii_media.ifm_media) { 2199 printf("%s: media type changed (ifm_media=%x)\n", __func__, 2200 sc->mii->mii_media.ifm_media); 2201 cpswp_ifmedia_upd(sc->ifp); 2202 } 2203 2204 /* Schedule another timeout one second from now */ 2205 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc); 2206 } 2207 2208 static void 2209 cpswp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2210 { 2211 struct cpswp_softc *sc; 2212 struct mii_data *mii; 2213 2214 sc = ifp->if_softc; 2215 CPSW_DEBUGF(sc->swsc, ("")); 2216 CPSW_PORT_LOCK(sc); 2217 2218 mii = sc->mii; 2219 mii_pollstat(mii); 2220 2221 ifmr->ifm_active = mii->mii_media_active; 2222 ifmr->ifm_status = mii->mii_media_status; 2223 CPSW_PORT_UNLOCK(sc); 2224 } 2225 2226 static int 2227 cpswp_ifmedia_upd(struct ifnet *ifp) 2228 { 2229 struct cpswp_softc *sc; 2230 2231 sc = ifp->if_softc; 2232 CPSW_DEBUGF(sc->swsc, ("")); 2233 CPSW_PORT_LOCK(sc); 2234 mii_mediachg(sc->mii); 2235 sc->media_status = sc->mii->mii_media.ifm_media; 2236 CPSW_PORT_UNLOCK(sc); 2237 2238 return (0); 2239 } 2240 2241 static void 2242 cpsw_tx_watchdog_full_reset(struct cpsw_softc *sc) 2243 { 2244 struct cpswp_softc *psc; 2245 int i; 2246 2247 cpsw_debugf_head("CPSW watchdog"); 2248 device_printf(sc->dev, "watchdog timeout\n"); 2249 printf("CPSW_CPDMA_TX%d_HDP=0x%x\n", 0, 2250 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0))); 2251 printf("CPSW_CPDMA_TX%d_CP=0x%x\n", 0, 2252 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0))); 2253 cpsw_dump_queue(sc, &sc->tx.active); 2254 for (i = 0; i < CPSW_PORTS; i++) { 2255 if (!sc->dualemac && i != sc->active_slave) 2256 continue; 2257 psc = device_get_softc(sc->port[i].dev); 2258 CPSW_PORT_LOCK(psc); 2259 cpswp_stop_locked(psc); 2260 CPSW_PORT_UNLOCK(psc); 2261 } 2262 } 2263 2264 static void 2265 cpsw_tx_watchdog(void *msc) 2266 { 2267 struct cpsw_softc *sc; 2268 2269 sc = msc; 2270 CPSW_TX_LOCK(sc); 2271 if (sc->tx.active_queue_len == 0 || !sc->tx.running) { 2272 sc->watchdog.timer = 0; /* Nothing to do. */ 2273 } else if (sc->tx.queue_removes > sc->tx.queue_removes_at_last_tick) { 2274 sc->watchdog.timer = 0; /* Stuff done while we weren't looking. */ 2275 } else if (cpsw_tx_dequeue(sc) > 0) { 2276 sc->watchdog.timer = 0; /* We just did something. */ 2277 } else { 2278 /* There was something to do but it didn't get done. */ 2279 ++sc->watchdog.timer; 2280 if (sc->watchdog.timer > 5) { 2281 sc->watchdog.timer = 0; 2282 ++sc->watchdog.resets; 2283 cpsw_tx_watchdog_full_reset(sc); 2284 } 2285 } 2286 sc->tx.queue_removes_at_last_tick = sc->tx.queue_removes; 2287 CPSW_TX_UNLOCK(sc); 2288 2289 /* Schedule another timeout one second from now */ 2290 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc); 2291 } 2292 2293 /* 2294 * 2295 * ALE support routines. 2296 * 2297 */ 2298 2299 static void 2300 cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 2301 { 2302 cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023); 2303 ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0); 2304 ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1); 2305 ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2); 2306 } 2307 2308 static void 2309 cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 2310 { 2311 cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]); 2312 cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]); 2313 cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]); 2314 cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023)); 2315 } 2316 2317 static void 2318 cpsw_ale_remove_all_mc_entries(struct cpsw_softc *sc) 2319 { 2320 int i; 2321 uint32_t ale_entry[3]; 2322 2323 /* First four entries are link address and broadcast. */ 2324 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) { 2325 cpsw_ale_read_entry(sc, i, ale_entry); 2326 if ((ALE_TYPE(ale_entry) == ALE_TYPE_ADDR || 2327 ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) && 2328 ALE_MCAST(ale_entry) == 1) { /* MCast link addr */ 2329 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 2330 cpsw_ale_write_entry(sc, i, ale_entry); 2331 } 2332 } 2333 } 2334 2335 static int 2336 cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmap, int vlan, 2337 uint8_t *mac) 2338 { 2339 int free_index = -1, matching_index = -1, i; 2340 uint32_t ale_entry[3], ale_type; 2341 2342 /* Find a matching entry or a free entry. */ 2343 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) { 2344 cpsw_ale_read_entry(sc, i, ale_entry); 2345 2346 /* Entry Type[61:60] is 0 for free entry */ 2347 if (free_index < 0 && ALE_TYPE(ale_entry) == 0) 2348 free_index = i; 2349 2350 if ((((ale_entry[1] >> 8) & 0xFF) == mac[0]) && 2351 (((ale_entry[1] >> 0) & 0xFF) == mac[1]) && 2352 (((ale_entry[0] >>24) & 0xFF) == mac[2]) && 2353 (((ale_entry[0] >>16) & 0xFF) == mac[3]) && 2354 (((ale_entry[0] >> 8) & 0xFF) == mac[4]) && 2355 (((ale_entry[0] >> 0) & 0xFF) == mac[5])) { 2356 matching_index = i; 2357 break; 2358 } 2359 } 2360 2361 if (matching_index < 0) { 2362 if (free_index < 0) 2363 return (ENOMEM); 2364 i = free_index; 2365 } 2366 2367 if (vlan != -1) 2368 ale_type = ALE_TYPE_VLAN_ADDR << 28 | vlan << 16; 2369 else 2370 ale_type = ALE_TYPE_ADDR << 28; 2371 2372 /* Set MAC address */ 2373 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 2374 ale_entry[1] = mac[0] << 8 | mac[1]; 2375 2376 /* Entry type[61:60] and Mcast fwd state[63:62] is fw(3). */ 2377 ale_entry[1] |= ALE_MCAST_FWD | ale_type; 2378 2379 /* Set portmask [68:66] */ 2380 ale_entry[2] = (portmap & 7) << 2; 2381 2382 cpsw_ale_write_entry(sc, i, ale_entry); 2383 2384 return 0; 2385 } 2386 2387 static void 2388 cpsw_ale_dump_table(struct cpsw_softc *sc) { 2389 int i; 2390 uint32_t ale_entry[3]; 2391 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2392 cpsw_ale_read_entry(sc, i, ale_entry); 2393 switch (ALE_TYPE(ale_entry)) { 2394 case ALE_TYPE_VLAN: 2395 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2], 2396 ale_entry[1], ale_entry[0]); 2397 printf("type: %u ", ALE_TYPE(ale_entry)); 2398 printf("vlan: %u ", ALE_VLAN(ale_entry)); 2399 printf("untag: %u ", ALE_VLAN_UNTAG(ale_entry)); 2400 printf("reg flood: %u ", ALE_VLAN_REGFLOOD(ale_entry)); 2401 printf("unreg flood: %u ", ALE_VLAN_UNREGFLOOD(ale_entry)); 2402 printf("members: %u ", ALE_VLAN_MEMBERS(ale_entry)); 2403 printf("\n"); 2404 break; 2405 case ALE_TYPE_ADDR: 2406 case ALE_TYPE_VLAN_ADDR: 2407 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2], 2408 ale_entry[1], ale_entry[0]); 2409 printf("type: %u ", ALE_TYPE(ale_entry)); 2410 printf("mac: %02x:%02x:%02x:%02x:%02x:%02x ", 2411 (ale_entry[1] >> 8) & 0xFF, 2412 (ale_entry[1] >> 0) & 0xFF, 2413 (ale_entry[0] >>24) & 0xFF, 2414 (ale_entry[0] >>16) & 0xFF, 2415 (ale_entry[0] >> 8) & 0xFF, 2416 (ale_entry[0] >> 0) & 0xFF); 2417 printf(ALE_MCAST(ale_entry) ? "mcast " : "ucast "); 2418 if (ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) 2419 printf("vlan: %u ", ALE_VLAN(ale_entry)); 2420 printf("port: %u ", ALE_PORTS(ale_entry)); 2421 printf("\n"); 2422 break; 2423 } 2424 } 2425 printf("\n"); 2426 } 2427 2428 static u_int 2429 cpswp_set_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2430 { 2431 struct cpswp_softc *sc = arg; 2432 uint32_t portmask; 2433 2434 if (sc->swsc->dualemac) 2435 portmask = 1 << (sc->unit + 1) | 1 << 0; 2436 else 2437 portmask = 7; 2438 2439 cpsw_ale_mc_entry_set(sc->swsc, portmask, sc->vlan, LLADDR(sdl)); 2440 2441 return (1); 2442 } 2443 2444 static int 2445 cpswp_ale_update_addresses(struct cpswp_softc *sc, int purge) 2446 { 2447 uint8_t *mac; 2448 uint32_t ale_entry[3], ale_type, portmask; 2449 2450 if (sc->swsc->dualemac) { 2451 ale_type = ALE_TYPE_VLAN_ADDR << 28 | sc->vlan << 16; 2452 portmask = 1 << (sc->unit + 1) | 1 << 0; 2453 } else { 2454 ale_type = ALE_TYPE_ADDR << 28; 2455 portmask = 7; 2456 } 2457 2458 /* 2459 * Route incoming packets for our MAC address to Port 0 (host). 2460 * For simplicity, keep this entry at table index 0 for port 1 and 2461 * at index 2 for port 2 in the ALE. 2462 */ 2463 mac = LLADDR((struct sockaddr_dl *)sc->ifp->if_addr->ifa_addr); 2464 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 2465 ale_entry[1] = ale_type | mac[0] << 8 | mac[1]; /* addr entry + mac */ 2466 ale_entry[2] = 0; /* port = 0 */ 2467 cpsw_ale_write_entry(sc->swsc, 0 + 2 * sc->unit, ale_entry); 2468 2469 /* Set outgoing MAC Address for slave port. */ 2470 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_HI(sc->unit + 1), 2471 mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]); 2472 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_LO(sc->unit + 1), 2473 mac[5] << 8 | mac[4]); 2474 2475 /* Keep the broadcast address at table entry 1 (or 3). */ 2476 ale_entry[0] = 0xffffffff; /* Lower 32 bits of MAC */ 2477 /* ALE_MCAST_FWD, Addr type, upper 16 bits of Mac */ 2478 ale_entry[1] = ALE_MCAST_FWD | ale_type | 0xffff; 2479 ale_entry[2] = portmask << 2; 2480 cpsw_ale_write_entry(sc->swsc, 1 + 2 * sc->unit, ale_entry); 2481 2482 /* SIOCDELMULTI doesn't specify the particular address 2483 being removed, so we have to remove all and rebuild. */ 2484 if (purge) 2485 cpsw_ale_remove_all_mc_entries(sc->swsc); 2486 2487 /* Set other multicast addrs desired. */ 2488 if_foreach_llmaddr(sc->ifp, cpswp_set_maddr, sc); 2489 2490 return (0); 2491 } 2492 2493 static int 2494 cpsw_ale_update_vlan_table(struct cpsw_softc *sc, int vlan, int ports, 2495 int untag, int mcregflood, int mcunregflood) 2496 { 2497 int free_index, i, matching_index; 2498 uint32_t ale_entry[3]; 2499 2500 free_index = matching_index = -1; 2501 /* Find a matching entry or a free entry. */ 2502 for (i = 5; i < CPSW_MAX_ALE_ENTRIES; i++) { 2503 cpsw_ale_read_entry(sc, i, ale_entry); 2504 2505 /* Entry Type[61:60] is 0 for free entry */ 2506 if (free_index < 0 && ALE_TYPE(ale_entry) == 0) 2507 free_index = i; 2508 2509 if (ALE_VLAN(ale_entry) == vlan) { 2510 matching_index = i; 2511 break; 2512 } 2513 } 2514 2515 if (matching_index < 0) { 2516 if (free_index < 0) 2517 return (-1); 2518 i = free_index; 2519 } 2520 2521 ale_entry[0] = (untag & 7) << 24 | (mcregflood & 7) << 16 | 2522 (mcunregflood & 7) << 8 | (ports & 7); 2523 ale_entry[1] = ALE_TYPE_VLAN << 28 | vlan << 16; 2524 ale_entry[2] = 0; 2525 cpsw_ale_write_entry(sc, i, ale_entry); 2526 2527 return (0); 2528 } 2529 2530 /* 2531 * 2532 * Statistics and Sysctls. 2533 * 2534 */ 2535 2536 #if 0 2537 static void 2538 cpsw_stats_dump(struct cpsw_softc *sc) 2539 { 2540 int i; 2541 uint32_t r; 2542 2543 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2544 r = cpsw_read_4(sc, CPSW_STATS_OFFSET + 2545 cpsw_stat_sysctls[i].reg); 2546 CPSW_DEBUGF(sc, ("%s: %ju + %u = %ju", cpsw_stat_sysctls[i].oid, 2547 (intmax_t)sc->shadow_stats[i], r, 2548 (intmax_t)sc->shadow_stats[i] + r)); 2549 } 2550 } 2551 #endif 2552 2553 static void 2554 cpsw_stats_collect(struct cpsw_softc *sc) 2555 { 2556 int i; 2557 uint32_t r; 2558 2559 CPSW_DEBUGF(sc, ("Controller shadow statistics updated.")); 2560 2561 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2562 r = cpsw_read_4(sc, CPSW_STATS_OFFSET + 2563 cpsw_stat_sysctls[i].reg); 2564 sc->shadow_stats[i] += r; 2565 cpsw_write_4(sc, CPSW_STATS_OFFSET + cpsw_stat_sysctls[i].reg, 2566 r); 2567 } 2568 } 2569 2570 static int 2571 cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS) 2572 { 2573 struct cpsw_softc *sc; 2574 struct cpsw_stat *stat; 2575 uint64_t result; 2576 2577 sc = (struct cpsw_softc *)arg1; 2578 stat = &cpsw_stat_sysctls[oidp->oid_number]; 2579 result = sc->shadow_stats[oidp->oid_number]; 2580 result += cpsw_read_4(sc, CPSW_STATS_OFFSET + stat->reg); 2581 return (sysctl_handle_64(oidp, &result, 0, req)); 2582 } 2583 2584 static int 2585 cpsw_stat_attached(SYSCTL_HANDLER_ARGS) 2586 { 2587 struct cpsw_softc *sc; 2588 struct bintime t; 2589 unsigned result; 2590 2591 sc = (struct cpsw_softc *)arg1; 2592 getbinuptime(&t); 2593 bintime_sub(&t, &sc->attach_uptime); 2594 result = t.sec; 2595 return (sysctl_handle_int(oidp, &result, 0, req)); 2596 } 2597 2598 static int 2599 cpsw_intr_coalesce(SYSCTL_HANDLER_ARGS) 2600 { 2601 int error; 2602 struct cpsw_softc *sc; 2603 uint32_t ctrl, intr_per_ms; 2604 2605 sc = (struct cpsw_softc *)arg1; 2606 error = sysctl_handle_int(oidp, &sc->coal_us, 0, req); 2607 if (error != 0 || req->newptr == NULL) 2608 return (error); 2609 2610 ctrl = cpsw_read_4(sc, CPSW_WR_INT_CONTROL); 2611 ctrl &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK); 2612 if (sc->coal_us == 0) { 2613 /* Disable the interrupt pace hardware. */ 2614 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl); 2615 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), 0); 2616 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), 0); 2617 return (0); 2618 } 2619 2620 if (sc->coal_us > CPSW_WR_C_IMAX_US_MAX) 2621 sc->coal_us = CPSW_WR_C_IMAX_US_MAX; 2622 if (sc->coal_us < CPSW_WR_C_IMAX_US_MIN) 2623 sc->coal_us = CPSW_WR_C_IMAX_US_MIN; 2624 intr_per_ms = 1000 / sc->coal_us; 2625 /* Just to make sure... */ 2626 if (intr_per_ms > CPSW_WR_C_IMAX_MAX) 2627 intr_per_ms = CPSW_WR_C_IMAX_MAX; 2628 if (intr_per_ms < CPSW_WR_C_IMAX_MIN) 2629 intr_per_ms = CPSW_WR_C_IMAX_MIN; 2630 2631 /* Set the prescale to produce 4us pulses from the 125 Mhz clock. */ 2632 ctrl |= (125 * 4) & CPSW_WR_INT_PRESCALE_MASK; 2633 2634 /* Enable the interrupt pace hardware. */ 2635 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), intr_per_ms); 2636 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), intr_per_ms); 2637 ctrl |= CPSW_WR_INT_C0_RX_PULSE | CPSW_WR_INT_C0_TX_PULSE; 2638 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl); 2639 2640 return (0); 2641 } 2642 2643 static int 2644 cpsw_stat_uptime(SYSCTL_HANDLER_ARGS) 2645 { 2646 struct cpsw_softc *swsc; 2647 struct cpswp_softc *sc; 2648 struct bintime t; 2649 unsigned result; 2650 2651 swsc = arg1; 2652 sc = device_get_softc(swsc->port[arg2].dev); 2653 if (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) { 2654 getbinuptime(&t); 2655 bintime_sub(&t, &sc->init_uptime); 2656 result = t.sec; 2657 } else 2658 result = 0; 2659 return (sysctl_handle_int(oidp, &result, 0, req)); 2660 } 2661 2662 static void 2663 cpsw_add_queue_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node, 2664 struct cpsw_queue *queue) 2665 { 2666 struct sysctl_oid_list *parent; 2667 2668 parent = SYSCTL_CHILDREN(node); 2669 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "totalBuffers", 2670 CTLFLAG_RD, &queue->queue_slots, 0, 2671 "Total buffers currently assigned to this queue"); 2672 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "activeBuffers", 2673 CTLFLAG_RD, &queue->active_queue_len, 0, 2674 "Buffers currently registered with hardware controller"); 2675 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxActiveBuffers", 2676 CTLFLAG_RD, &queue->max_active_queue_len, 0, 2677 "Max value of activeBuffers since last driver reset"); 2678 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "availBuffers", 2679 CTLFLAG_RD, &queue->avail_queue_len, 0, 2680 "Buffers allocated to this queue but not currently " 2681 "registered with hardware controller"); 2682 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxAvailBuffers", 2683 CTLFLAG_RD, &queue->max_avail_queue_len, 0, 2684 "Max value of availBuffers since last driver reset"); 2685 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalEnqueued", 2686 CTLFLAG_RD, &queue->queue_adds, 0, 2687 "Total buffers added to queue"); 2688 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalDequeued", 2689 CTLFLAG_RD, &queue->queue_removes, 0, 2690 "Total buffers removed from queue"); 2691 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "queueRestart", 2692 CTLFLAG_RD, &queue->queue_restart, 0, 2693 "Total times the queue has been restarted"); 2694 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "longestChain", 2695 CTLFLAG_RD, &queue->longest_chain, 0, 2696 "Max buffers used for a single packet"); 2697 } 2698 2699 static void 2700 cpsw_add_watchdog_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node, 2701 struct cpsw_softc *sc) 2702 { 2703 struct sysctl_oid_list *parent; 2704 2705 parent = SYSCTL_CHILDREN(node); 2706 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "resets", 2707 CTLFLAG_RD, &sc->watchdog.resets, 0, 2708 "Total number of watchdog resets"); 2709 } 2710 2711 static void 2712 cpsw_add_sysctls(struct cpsw_softc *sc) 2713 { 2714 struct sysctl_ctx_list *ctx; 2715 struct sysctl_oid *stats_node, *queue_node, *node; 2716 struct sysctl_oid_list *parent, *stats_parent, *queue_parent; 2717 struct sysctl_oid_list *ports_parent, *port_parent; 2718 char port[16]; 2719 int i; 2720 2721 ctx = device_get_sysctl_ctx(sc->dev); 2722 parent = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2723 2724 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "debug", 2725 CTLFLAG_RW, &sc->debug, 0, "Enable switch debug messages"); 2726 2727 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "attachedSecs", 2728 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2729 sc, 0, cpsw_stat_attached, "IU", 2730 "Time since driver attach"); 2731 2732 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "intr_coalesce_us", 2733 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2734 sc, 0, cpsw_intr_coalesce, "IU", 2735 "minimum time between interrupts"); 2736 2737 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "ports", 2738 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CPSW Ports Statistics"); 2739 ports_parent = SYSCTL_CHILDREN(node); 2740 for (i = 0; i < CPSW_PORTS; i++) { 2741 if (!sc->dualemac && i != sc->active_slave) 2742 continue; 2743 port[0] = '0' + i; 2744 port[1] = '\0'; 2745 node = SYSCTL_ADD_NODE(ctx, ports_parent, OID_AUTO, 2746 port, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 2747 "CPSW Port Statistics"); 2748 port_parent = SYSCTL_CHILDREN(node); 2749 SYSCTL_ADD_PROC(ctx, port_parent, OID_AUTO, "uptime", 2750 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, i, 2751 cpsw_stat_uptime, "IU", "Seconds since driver init"); 2752 } 2753 2754 stats_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", 2755 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CPSW Statistics"); 2756 stats_parent = SYSCTL_CHILDREN(stats_node); 2757 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2758 SYSCTL_ADD_PROC(ctx, stats_parent, i, 2759 cpsw_stat_sysctls[i].oid, 2760 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2761 sc, 0, cpsw_stats_sysctl, "IU", 2762 cpsw_stat_sysctls[i].oid); 2763 } 2764 2765 queue_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "queue", 2766 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CPSW Queue Statistics"); 2767 queue_parent = SYSCTL_CHILDREN(queue_node); 2768 2769 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "tx", 2770 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Statistics"); 2771 cpsw_add_queue_sysctls(ctx, node, &sc->tx); 2772 2773 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "rx", 2774 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Statistics"); 2775 cpsw_add_queue_sysctls(ctx, node, &sc->rx); 2776 2777 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "watchdog", 2778 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Watchdog Statistics"); 2779 cpsw_add_watchdog_sysctls(ctx, node, sc); 2780 } 2781 2782 #ifdef CPSW_ETHERSWITCH 2783 static etherswitch_info_t etherswitch_info = { 2784 .es_nports = CPSW_PORTS + 1, 2785 .es_nvlangroups = CPSW_VLANS, 2786 .es_name = "TI Common Platform Ethernet Switch (CPSW)", 2787 .es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q, 2788 }; 2789 2790 static etherswitch_info_t * 2791 cpsw_getinfo(device_t dev) 2792 { 2793 return (ðerswitch_info); 2794 } 2795 2796 static int 2797 cpsw_getport(device_t dev, etherswitch_port_t *p) 2798 { 2799 int err; 2800 struct cpsw_softc *sc; 2801 struct cpswp_softc *psc; 2802 struct ifmediareq *ifmr; 2803 uint32_t reg; 2804 2805 if (p->es_port < 0 || p->es_port > CPSW_PORTS) 2806 return (ENXIO); 2807 2808 err = 0; 2809 sc = device_get_softc(dev); 2810 if (p->es_port == CPSW_CPU_PORT) { 2811 p->es_flags |= ETHERSWITCH_PORT_CPU; 2812 ifmr = &p->es_ifmr; 2813 ifmr->ifm_current = ifmr->ifm_active = 2814 IFM_ETHER | IFM_1000_T | IFM_FDX; 2815 ifmr->ifm_mask = 0; 2816 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 2817 ifmr->ifm_count = 0; 2818 } else { 2819 psc = device_get_softc(sc->port[p->es_port - 1].dev); 2820 err = ifmedia_ioctl(psc->ifp, &p->es_ifr, 2821 &psc->mii->mii_media, SIOCGIFMEDIA); 2822 } 2823 reg = cpsw_read_4(sc, CPSW_PORT_P_VLAN(p->es_port)); 2824 p->es_pvid = reg & ETHERSWITCH_VID_MASK; 2825 2826 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port)); 2827 if (reg & ALE_PORTCTL_DROP_UNTAGGED) 2828 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED; 2829 if (reg & ALE_PORTCTL_INGRESS) 2830 p->es_flags |= ETHERSWITCH_PORT_INGRESS; 2831 2832 return (err); 2833 } 2834 2835 static int 2836 cpsw_setport(device_t dev, etherswitch_port_t *p) 2837 { 2838 struct cpsw_softc *sc; 2839 struct cpswp_softc *psc; 2840 struct ifmedia *ifm; 2841 uint32_t reg; 2842 2843 if (p->es_port < 0 || p->es_port > CPSW_PORTS) 2844 return (ENXIO); 2845 2846 sc = device_get_softc(dev); 2847 if (p->es_pvid != 0) { 2848 cpsw_write_4(sc, CPSW_PORT_P_VLAN(p->es_port), 2849 p->es_pvid & ETHERSWITCH_VID_MASK); 2850 } 2851 2852 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port)); 2853 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED) 2854 reg |= ALE_PORTCTL_DROP_UNTAGGED; 2855 else 2856 reg &= ~ALE_PORTCTL_DROP_UNTAGGED; 2857 if (p->es_flags & ETHERSWITCH_PORT_INGRESS) 2858 reg |= ALE_PORTCTL_INGRESS; 2859 else 2860 reg &= ~ALE_PORTCTL_INGRESS; 2861 cpsw_write_4(sc, CPSW_ALE_PORTCTL(p->es_port), reg); 2862 2863 /* CPU port does not allow media settings. */ 2864 if (p->es_port == CPSW_CPU_PORT) 2865 return (0); 2866 2867 psc = device_get_softc(sc->port[p->es_port - 1].dev); 2868 ifm = &psc->mii->mii_media; 2869 2870 return (ifmedia_ioctl(psc->ifp, &p->es_ifr, ifm, SIOCSIFMEDIA)); 2871 } 2872 2873 static int 2874 cpsw_getconf(device_t dev, etherswitch_conf_t *conf) 2875 { 2876 2877 /* Return the VLAN mode. */ 2878 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 2879 conf->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 2880 2881 return (0); 2882 } 2883 2884 static int 2885 cpsw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 2886 { 2887 int i, vid; 2888 uint32_t ale_entry[3]; 2889 struct cpsw_softc *sc; 2890 2891 sc = device_get_softc(dev); 2892 2893 if (vg->es_vlangroup >= CPSW_VLANS) 2894 return (EINVAL); 2895 2896 vg->es_vid = 0; 2897 vid = cpsw_vgroups[vg->es_vlangroup].vid; 2898 if (vid == -1) 2899 return (0); 2900 2901 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2902 cpsw_ale_read_entry(sc, i, ale_entry); 2903 if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN) 2904 continue; 2905 if (vid != ALE_VLAN(ale_entry)) 2906 continue; 2907 2908 vg->es_fid = 0; 2909 vg->es_vid = ALE_VLAN(ale_entry) | ETHERSWITCH_VID_VALID; 2910 vg->es_member_ports = ALE_VLAN_MEMBERS(ale_entry); 2911 vg->es_untagged_ports = ALE_VLAN_UNTAG(ale_entry); 2912 } 2913 2914 return (0); 2915 } 2916 2917 static void 2918 cpsw_remove_vlan(struct cpsw_softc *sc, int vlan) 2919 { 2920 int i; 2921 uint32_t ale_entry[3]; 2922 2923 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2924 cpsw_ale_read_entry(sc, i, ale_entry); 2925 if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN) 2926 continue; 2927 if (vlan != ALE_VLAN(ale_entry)) 2928 continue; 2929 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 2930 cpsw_ale_write_entry(sc, i, ale_entry); 2931 break; 2932 } 2933 } 2934 2935 static int 2936 cpsw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 2937 { 2938 int i; 2939 struct cpsw_softc *sc; 2940 2941 sc = device_get_softc(dev); 2942 2943 for (i = 0; i < CPSW_VLANS; i++) { 2944 /* Is this Vlan ID in use by another vlangroup ? */ 2945 if (vg->es_vlangroup != i && cpsw_vgroups[i].vid == vg->es_vid) 2946 return (EINVAL); 2947 } 2948 2949 if (vg->es_vid == 0) { 2950 if (cpsw_vgroups[vg->es_vlangroup].vid == -1) 2951 return (0); 2952 cpsw_remove_vlan(sc, cpsw_vgroups[vg->es_vlangroup].vid); 2953 cpsw_vgroups[vg->es_vlangroup].vid = -1; 2954 vg->es_untagged_ports = 0; 2955 vg->es_member_ports = 0; 2956 vg->es_vid = 0; 2957 return (0); 2958 } 2959 2960 vg->es_vid &= ETHERSWITCH_VID_MASK; 2961 vg->es_member_ports &= CPSW_PORTS_MASK; 2962 vg->es_untagged_ports &= CPSW_PORTS_MASK; 2963 2964 if (cpsw_vgroups[vg->es_vlangroup].vid != -1 && 2965 cpsw_vgroups[vg->es_vlangroup].vid != vg->es_vid) 2966 return (EINVAL); 2967 2968 cpsw_vgroups[vg->es_vlangroup].vid = vg->es_vid; 2969 cpsw_ale_update_vlan_table(sc, vg->es_vid, vg->es_member_ports, 2970 vg->es_untagged_ports, vg->es_member_ports, 0); 2971 2972 return (0); 2973 } 2974 2975 static int 2976 cpsw_readreg(device_t dev, int addr) 2977 { 2978 2979 /* Not supported. */ 2980 return (0); 2981 } 2982 2983 static int 2984 cpsw_writereg(device_t dev, int addr, int value) 2985 { 2986 2987 /* Not supported. */ 2988 return (0); 2989 } 2990 2991 static int 2992 cpsw_readphy(device_t dev, int phy, int reg) 2993 { 2994 2995 /* Not supported. */ 2996 return (0); 2997 } 2998 2999 static int 3000 cpsw_writephy(device_t dev, int phy, int reg, int data) 3001 { 3002 3003 /* Not supported. */ 3004 return (0); 3005 } 3006 #endif 3007