1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 5 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * TI Common Platform Ethernet Switch (CPSW) Driver 32 * Found in TI8148 "DaVinci" and AM335x "Sitara" SoCs. 33 * 34 * This controller is documented in the AM335x Technical Reference 35 * Manual, in the TMS320DM814x DaVinci Digital Video Processors TRM 36 * and in the TMS320C6452 3 Port Switch Ethernet Subsystem TRM. 37 * 38 * It is basically a single Ethernet port (port 0) wired internally to 39 * a 3-port store-and-forward switch connected to two independent 40 * "sliver" controllers (port 1 and port 2). You can operate the 41 * controller in a variety of different ways by suitably configuring 42 * the slivers and the Address Lookup Engine (ALE) that routes packets 43 * between the ports. 44 * 45 * This code was developed and tested on a BeagleBone with 46 * an AM335x SoC. 47 */ 48 49 #include <sys/cdefs.h> 50 __FBSDID("$FreeBSD$"); 51 52 #include "opt_cpsw.h" 53 54 #include <sys/param.h> 55 #include <sys/bus.h> 56 #include <sys/kernel.h> 57 #include <sys/lock.h> 58 #include <sys/mbuf.h> 59 #include <sys/module.h> 60 #include <sys/mutex.h> 61 #include <sys/rman.h> 62 #include <sys/socket.h> 63 #include <sys/sockio.h> 64 #include <sys/sysctl.h> 65 66 #include <machine/bus.h> 67 #include <machine/resource.h> 68 #include <machine/stdarg.h> 69 70 #include <net/ethernet.h> 71 #include <net/bpf.h> 72 #include <net/if.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 #include <net/if_types.h> 76 77 #include <arm/ti/ti_scm.h> 78 #include <arm/ti/am335x/am335x_scm.h> 79 80 #include <dev/mii/mii.h> 81 #include <dev/mii/miivar.h> 82 83 #include <dev/ofw/ofw_bus.h> 84 #include <dev/ofw/ofw_bus_subr.h> 85 86 #ifdef CPSW_ETHERSWITCH 87 #include <dev/etherswitch/etherswitch.h> 88 #include "etherswitch_if.h" 89 #endif 90 91 #include "if_cpswreg.h" 92 #include "if_cpswvar.h" 93 94 #include "miibus_if.h" 95 96 /* Device probe/attach/detach. */ 97 static int cpsw_probe(device_t); 98 static int cpsw_attach(device_t); 99 static int cpsw_detach(device_t); 100 static int cpswp_probe(device_t); 101 static int cpswp_attach(device_t); 102 static int cpswp_detach(device_t); 103 104 static phandle_t cpsw_get_node(device_t, device_t); 105 106 /* Device Init/shutdown. */ 107 static int cpsw_shutdown(device_t); 108 static void cpswp_init(void *); 109 static void cpswp_init_locked(void *); 110 static void cpswp_stop_locked(struct cpswp_softc *); 111 112 /* Device Suspend/Resume. */ 113 static int cpsw_suspend(device_t); 114 static int cpsw_resume(device_t); 115 116 /* Ioctl. */ 117 static int cpswp_ioctl(struct ifnet *, u_long command, caddr_t data); 118 119 static int cpswp_miibus_readreg(device_t, int phy, int reg); 120 static int cpswp_miibus_writereg(device_t, int phy, int reg, int value); 121 static void cpswp_miibus_statchg(device_t); 122 123 /* Send/Receive packets. */ 124 static void cpsw_intr_rx(void *arg); 125 static struct mbuf *cpsw_rx_dequeue(struct cpsw_softc *); 126 static void cpsw_rx_enqueue(struct cpsw_softc *); 127 static void cpswp_start(struct ifnet *); 128 static void cpsw_intr_tx(void *); 129 static void cpswp_tx_enqueue(struct cpswp_softc *); 130 static int cpsw_tx_dequeue(struct cpsw_softc *); 131 132 /* Misc interrupts and watchdog. */ 133 static void cpsw_intr_rx_thresh(void *); 134 static void cpsw_intr_misc(void *); 135 static void cpswp_tick(void *); 136 static void cpswp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 137 static int cpswp_ifmedia_upd(struct ifnet *); 138 static void cpsw_tx_watchdog(void *); 139 140 /* ALE support */ 141 static void cpsw_ale_read_entry(struct cpsw_softc *, uint16_t, uint32_t *); 142 static void cpsw_ale_write_entry(struct cpsw_softc *, uint16_t, uint32_t *); 143 static int cpsw_ale_mc_entry_set(struct cpsw_softc *, uint8_t, int, uint8_t *); 144 static void cpsw_ale_dump_table(struct cpsw_softc *); 145 static int cpsw_ale_update_vlan_table(struct cpsw_softc *, int, int, int, int, 146 int); 147 static int cpswp_ale_update_addresses(struct cpswp_softc *, int); 148 149 /* Statistics and sysctls. */ 150 static void cpsw_add_sysctls(struct cpsw_softc *); 151 static void cpsw_stats_collect(struct cpsw_softc *); 152 static int cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS); 153 154 #ifdef CPSW_ETHERSWITCH 155 static etherswitch_info_t *cpsw_getinfo(device_t); 156 static int cpsw_getport(device_t, etherswitch_port_t *); 157 static int cpsw_setport(device_t, etherswitch_port_t *); 158 static int cpsw_getconf(device_t, etherswitch_conf_t *); 159 static int cpsw_getvgroup(device_t, etherswitch_vlangroup_t *); 160 static int cpsw_setvgroup(device_t, etherswitch_vlangroup_t *); 161 static int cpsw_readreg(device_t, int); 162 static int cpsw_writereg(device_t, int, int); 163 static int cpsw_readphy(device_t, int, int); 164 static int cpsw_writephy(device_t, int, int, int); 165 #endif 166 167 /* 168 * Arbitrary limit on number of segments in an mbuf to be transmitted. 169 * Packets with more segments than this will be defragmented before 170 * they are queued. 171 */ 172 #define CPSW_TXFRAGS 16 173 174 /* Shared resources. */ 175 static device_method_t cpsw_methods[] = { 176 /* Device interface */ 177 DEVMETHOD(device_probe, cpsw_probe), 178 DEVMETHOD(device_attach, cpsw_attach), 179 DEVMETHOD(device_detach, cpsw_detach), 180 DEVMETHOD(device_shutdown, cpsw_shutdown), 181 DEVMETHOD(device_suspend, cpsw_suspend), 182 DEVMETHOD(device_resume, cpsw_resume), 183 /* Bus interface */ 184 DEVMETHOD(bus_add_child, device_add_child_ordered), 185 /* OFW methods */ 186 DEVMETHOD(ofw_bus_get_node, cpsw_get_node), 187 #ifdef CPSW_ETHERSWITCH 188 /* etherswitch interface */ 189 DEVMETHOD(etherswitch_getinfo, cpsw_getinfo), 190 DEVMETHOD(etherswitch_readreg, cpsw_readreg), 191 DEVMETHOD(etherswitch_writereg, cpsw_writereg), 192 DEVMETHOD(etherswitch_readphyreg, cpsw_readphy), 193 DEVMETHOD(etherswitch_writephyreg, cpsw_writephy), 194 DEVMETHOD(etherswitch_getport, cpsw_getport), 195 DEVMETHOD(etherswitch_setport, cpsw_setport), 196 DEVMETHOD(etherswitch_getvgroup, cpsw_getvgroup), 197 DEVMETHOD(etherswitch_setvgroup, cpsw_setvgroup), 198 DEVMETHOD(etherswitch_getconf, cpsw_getconf), 199 #endif 200 DEVMETHOD_END 201 }; 202 203 static driver_t cpsw_driver = { 204 "cpswss", 205 cpsw_methods, 206 sizeof(struct cpsw_softc), 207 }; 208 209 static devclass_t cpsw_devclass; 210 211 DRIVER_MODULE(cpswss, simplebus, cpsw_driver, cpsw_devclass, 0, 0); 212 213 /* Port/Slave resources. */ 214 static device_method_t cpswp_methods[] = { 215 /* Device interface */ 216 DEVMETHOD(device_probe, cpswp_probe), 217 DEVMETHOD(device_attach, cpswp_attach), 218 DEVMETHOD(device_detach, cpswp_detach), 219 /* MII interface */ 220 DEVMETHOD(miibus_readreg, cpswp_miibus_readreg), 221 DEVMETHOD(miibus_writereg, cpswp_miibus_writereg), 222 DEVMETHOD(miibus_statchg, cpswp_miibus_statchg), 223 DEVMETHOD_END 224 }; 225 226 static driver_t cpswp_driver = { 227 "cpsw", 228 cpswp_methods, 229 sizeof(struct cpswp_softc), 230 }; 231 232 static devclass_t cpswp_devclass; 233 234 #ifdef CPSW_ETHERSWITCH 235 DRIVER_MODULE(etherswitch, cpswss, etherswitch_driver, etherswitch_devclass, 0, 0); 236 MODULE_DEPEND(cpswss, etherswitch, 1, 1, 1); 237 #endif 238 239 DRIVER_MODULE(cpsw, cpswss, cpswp_driver, cpswp_devclass, 0, 0); 240 DRIVER_MODULE(miibus, cpsw, miibus_driver, miibus_devclass, 0, 0); 241 MODULE_DEPEND(cpsw, ether, 1, 1, 1); 242 MODULE_DEPEND(cpsw, miibus, 1, 1, 1); 243 244 #ifdef CPSW_ETHERSWITCH 245 static struct cpsw_vlangroups cpsw_vgroups[CPSW_VLANS]; 246 #endif 247 248 static uint32_t slave_mdio_addr[] = { 0x4a100200, 0x4a100300 }; 249 250 static struct resource_spec irq_res_spec[] = { 251 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 252 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_SHAREABLE }, 253 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_SHAREABLE }, 254 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_SHAREABLE }, 255 { -1, 0 } 256 }; 257 258 static struct { 259 void (*cb)(void *); 260 } cpsw_intr_cb[] = { 261 { cpsw_intr_rx_thresh }, 262 { cpsw_intr_rx }, 263 { cpsw_intr_tx }, 264 { cpsw_intr_misc }, 265 }; 266 267 /* Number of entries here must match size of stats 268 * array in struct cpswp_softc. */ 269 static struct cpsw_stat { 270 int reg; 271 char *oid; 272 } cpsw_stat_sysctls[CPSW_SYSCTL_COUNT] = { 273 {0x00, "GoodRxFrames"}, 274 {0x04, "BroadcastRxFrames"}, 275 {0x08, "MulticastRxFrames"}, 276 {0x0C, "PauseRxFrames"}, 277 {0x10, "RxCrcErrors"}, 278 {0x14, "RxAlignErrors"}, 279 {0x18, "OversizeRxFrames"}, 280 {0x1c, "RxJabbers"}, 281 {0x20, "ShortRxFrames"}, 282 {0x24, "RxFragments"}, 283 {0x30, "RxOctets"}, 284 {0x34, "GoodTxFrames"}, 285 {0x38, "BroadcastTxFrames"}, 286 {0x3c, "MulticastTxFrames"}, 287 {0x40, "PauseTxFrames"}, 288 {0x44, "DeferredTxFrames"}, 289 {0x48, "CollisionsTxFrames"}, 290 {0x4c, "SingleCollisionTxFrames"}, 291 {0x50, "MultipleCollisionTxFrames"}, 292 {0x54, "ExcessiveCollisions"}, 293 {0x58, "LateCollisions"}, 294 {0x5c, "TxUnderrun"}, 295 {0x60, "CarrierSenseErrors"}, 296 {0x64, "TxOctets"}, 297 {0x68, "RxTx64OctetFrames"}, 298 {0x6c, "RxTx65to127OctetFrames"}, 299 {0x70, "RxTx128to255OctetFrames"}, 300 {0x74, "RxTx256to511OctetFrames"}, 301 {0x78, "RxTx512to1024OctetFrames"}, 302 {0x7c, "RxTx1024upOctetFrames"}, 303 {0x80, "NetOctets"}, 304 {0x84, "RxStartOfFrameOverruns"}, 305 {0x88, "RxMiddleOfFrameOverruns"}, 306 {0x8c, "RxDmaOverruns"} 307 }; 308 309 /* 310 * Basic debug support. 311 */ 312 313 static void 314 cpsw_debugf_head(const char *funcname) 315 { 316 int t = (int)(time_second % (24 * 60 * 60)); 317 318 printf("%02d:%02d:%02d %s ", t / (60 * 60), (t / 60) % 60, t % 60, funcname); 319 } 320 321 static void 322 cpsw_debugf(const char *fmt, ...) 323 { 324 va_list ap; 325 326 va_start(ap, fmt); 327 vprintf(fmt, ap); 328 va_end(ap); 329 printf("\n"); 330 331 } 332 333 #define CPSW_DEBUGF(_sc, a) do { \ 334 if ((_sc)->debug) { \ 335 cpsw_debugf_head(__func__); \ 336 cpsw_debugf a; \ 337 } \ 338 } while (0) 339 340 /* 341 * Locking macros 342 */ 343 #define CPSW_TX_LOCK(sc) do { \ 344 mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \ 345 mtx_lock(&(sc)->tx.lock); \ 346 } while (0) 347 348 #define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock) 349 #define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED) 350 351 #define CPSW_RX_LOCK(sc) do { \ 352 mtx_assert(&(sc)->tx.lock, MA_NOTOWNED); \ 353 mtx_lock(&(sc)->rx.lock); \ 354 } while (0) 355 356 #define CPSW_RX_UNLOCK(sc) mtx_unlock(&(sc)->rx.lock) 357 #define CPSW_RX_LOCK_ASSERT(sc) mtx_assert(&(sc)->rx.lock, MA_OWNED) 358 359 #define CPSW_PORT_LOCK(_sc) do { \ 360 mtx_assert(&(_sc)->lock, MA_NOTOWNED); \ 361 mtx_lock(&(_sc)->lock); \ 362 } while (0) 363 364 #define CPSW_PORT_UNLOCK(_sc) mtx_unlock(&(_sc)->lock) 365 #define CPSW_PORT_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->lock, MA_OWNED) 366 367 /* 368 * Read/Write macros 369 */ 370 #define cpsw_read_4(_sc, _reg) bus_read_4((_sc)->mem_res, (_reg)) 371 #define cpsw_write_4(_sc, _reg, _val) \ 372 bus_write_4((_sc)->mem_res, (_reg), (_val)) 373 374 #define cpsw_cpdma_bd_offset(i) (CPSW_CPPI_RAM_OFFSET + ((i)*16)) 375 376 #define cpsw_cpdma_bd_paddr(sc, slot) \ 377 BUS_SPACE_PHYSADDR(sc->mem_res, slot->bd_offset) 378 #define cpsw_cpdma_read_bd(sc, slot, val) \ 379 bus_read_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4) 380 #define cpsw_cpdma_write_bd(sc, slot, val) \ 381 bus_write_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4) 382 #define cpsw_cpdma_write_bd_next(sc, slot, next_slot) \ 383 cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot)) 384 #define cpsw_cpdma_write_bd_flags(sc, slot, val) \ 385 bus_write_2(sc->mem_res, slot->bd_offset + 14, val) 386 #define cpsw_cpdma_read_bd_flags(sc, slot) \ 387 bus_read_2(sc->mem_res, slot->bd_offset + 14) 388 #define cpsw_write_hdp_slot(sc, queue, slot) \ 389 cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot)) 390 #define CP_OFFSET (CPSW_CPDMA_TX_CP(0) - CPSW_CPDMA_TX_HDP(0)) 391 #define cpsw_read_cp(sc, queue) \ 392 cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET) 393 #define cpsw_write_cp(sc, queue, val) \ 394 cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val)) 395 #define cpsw_write_cp_slot(sc, queue, slot) \ 396 cpsw_write_cp(sc, queue, cpsw_cpdma_bd_paddr(sc, slot)) 397 398 #if 0 399 /* XXX temporary function versions for debugging. */ 400 static void 401 cpsw_write_hdp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot) 402 { 403 uint32_t reg = queue->hdp_offset; 404 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot); 405 CPSW_DEBUGF(("HDP <=== 0x%08x (was 0x%08x)", v, cpsw_read_4(sc, reg))); 406 cpsw_write_4(sc, reg, v); 407 } 408 409 static void 410 cpsw_write_cp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot) 411 { 412 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot); 413 CPSW_DEBUGF(("CP <=== 0x%08x (expecting 0x%08x)", v, cpsw_read_cp(sc, queue))); 414 cpsw_write_cp(sc, queue, v); 415 } 416 #endif 417 418 /* 419 * Expanded dump routines for verbose debugging. 420 */ 421 static void 422 cpsw_dump_slot(struct cpsw_softc *sc, struct cpsw_slot *slot) 423 { 424 static const char *flags[] = {"SOP", "EOP", "Owner", "EOQ", 425 "TDownCmplt", "PassCRC", "Long", "Short", "MacCtl", "Overrun", 426 "PktErr1", "PortEn/PktErr0", "RxVlanEncap", "Port2", "Port1", 427 "Port0"}; 428 struct cpsw_cpdma_bd bd; 429 const char *sep; 430 int i; 431 432 cpsw_cpdma_read_bd(sc, slot, &bd); 433 printf("BD Addr : 0x%08x Next : 0x%08x\n", 434 cpsw_cpdma_bd_paddr(sc, slot), bd.next); 435 printf(" BufPtr: 0x%08x BufLen: 0x%08x\n", bd.bufptr, bd.buflen); 436 printf(" BufOff: 0x%08x PktLen: 0x%08x\n", bd.bufoff, bd.pktlen); 437 printf(" Flags: "); 438 sep = ""; 439 for (i = 0; i < 16; ++i) { 440 if (bd.flags & (1 << (15 - i))) { 441 printf("%s%s", sep, flags[i]); 442 sep = ","; 443 } 444 } 445 printf("\n"); 446 if (slot->mbuf) { 447 printf(" Ether: %14D\n", 448 (char *)(slot->mbuf->m_data), " "); 449 printf(" Packet: %16D\n", 450 (char *)(slot->mbuf->m_data) + 14, " "); 451 } 452 } 453 454 #define CPSW_DUMP_SLOT(cs, slot) do { \ 455 IF_DEBUG(sc) { \ 456 cpsw_dump_slot(sc, slot); \ 457 } \ 458 } while (0) 459 460 static void 461 cpsw_dump_queue(struct cpsw_softc *sc, struct cpsw_slots *q) 462 { 463 struct cpsw_slot *slot; 464 int i = 0; 465 int others = 0; 466 467 STAILQ_FOREACH(slot, q, next) { 468 if (i > CPSW_TXFRAGS) 469 ++others; 470 else 471 cpsw_dump_slot(sc, slot); 472 ++i; 473 } 474 if (others) 475 printf(" ... and %d more.\n", others); 476 printf("\n"); 477 } 478 479 #define CPSW_DUMP_QUEUE(sc, q) do { \ 480 IF_DEBUG(sc) { \ 481 cpsw_dump_queue(sc, q); \ 482 } \ 483 } while (0) 484 485 static void 486 cpsw_init_slots(struct cpsw_softc *sc) 487 { 488 struct cpsw_slot *slot; 489 int i; 490 491 STAILQ_INIT(&sc->avail); 492 493 /* Put the slot descriptors onto the global avail list. */ 494 for (i = 0; i < nitems(sc->_slots); i++) { 495 slot = &sc->_slots[i]; 496 slot->bd_offset = cpsw_cpdma_bd_offset(i); 497 STAILQ_INSERT_TAIL(&sc->avail, slot, next); 498 } 499 } 500 501 static int 502 cpsw_add_slots(struct cpsw_softc *sc, struct cpsw_queue *queue, int requested) 503 { 504 const int max_slots = nitems(sc->_slots); 505 struct cpsw_slot *slot; 506 int i; 507 508 if (requested < 0) 509 requested = max_slots; 510 511 for (i = 0; i < requested; ++i) { 512 slot = STAILQ_FIRST(&sc->avail); 513 if (slot == NULL) 514 return (0); 515 if (bus_dmamap_create(sc->mbuf_dtag, 0, &slot->dmamap)) { 516 device_printf(sc->dev, "failed to create dmamap\n"); 517 return (ENOMEM); 518 } 519 STAILQ_REMOVE_HEAD(&sc->avail, next); 520 STAILQ_INSERT_TAIL(&queue->avail, slot, next); 521 ++queue->avail_queue_len; 522 ++queue->queue_slots; 523 } 524 return (0); 525 } 526 527 static void 528 cpsw_free_slot(struct cpsw_softc *sc, struct cpsw_slot *slot) 529 { 530 int error; 531 532 if (slot->dmamap) { 533 if (slot->mbuf) 534 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 535 error = bus_dmamap_destroy(sc->mbuf_dtag, slot->dmamap); 536 KASSERT(error == 0, ("Mapping still active")); 537 slot->dmamap = NULL; 538 } 539 if (slot->mbuf) { 540 m_freem(slot->mbuf); 541 slot->mbuf = NULL; 542 } 543 } 544 545 static void 546 cpsw_reset(struct cpsw_softc *sc) 547 { 548 int i; 549 550 callout_stop(&sc->watchdog.callout); 551 552 /* Reset RMII/RGMII wrapper. */ 553 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 554 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 555 ; 556 557 /* Disable TX and RX interrupts for all cores. */ 558 for (i = 0; i < 3; ++i) { 559 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(i), 0x00); 560 cpsw_write_4(sc, CPSW_WR_C_TX_EN(i), 0x00); 561 cpsw_write_4(sc, CPSW_WR_C_RX_EN(i), 0x00); 562 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(i), 0x00); 563 } 564 565 /* Reset CPSW subsystem. */ 566 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 567 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 568 ; 569 570 /* Reset Sliver port 1 and 2 */ 571 for (i = 0; i < 2; i++) { 572 /* Reset */ 573 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 574 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 575 ; 576 } 577 578 /* Reset DMA controller. */ 579 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 580 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 581 ; 582 583 /* Disable TX & RX DMA */ 584 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 0); 585 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 0); 586 587 /* Clear all queues. */ 588 for (i = 0; i < 8; i++) { 589 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0); 590 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0); 591 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0); 592 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0); 593 } 594 595 /* Clear all interrupt Masks */ 596 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF); 597 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF); 598 } 599 600 static void 601 cpsw_init(struct cpsw_softc *sc) 602 { 603 struct cpsw_slot *slot; 604 uint32_t reg; 605 606 /* Disable the interrupt pacing. */ 607 reg = cpsw_read_4(sc, CPSW_WR_INT_CONTROL); 608 reg &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK); 609 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, reg); 610 611 /* Clear ALE */ 612 cpsw_write_4(sc, CPSW_ALE_CONTROL, CPSW_ALE_CTL_CLEAR_TBL); 613 614 /* Enable ALE */ 615 reg = CPSW_ALE_CTL_ENABLE; 616 if (sc->dualemac) 617 reg |= CPSW_ALE_CTL_VLAN_AWARE; 618 cpsw_write_4(sc, CPSW_ALE_CONTROL, reg); 619 620 /* Set Host Port Mapping. */ 621 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210); 622 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0); 623 624 /* Initialize ALE: set host port to forwarding(3). */ 625 cpsw_write_4(sc, CPSW_ALE_PORTCTL(0), 626 ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD); 627 628 cpsw_write_4(sc, CPSW_SS_PTYPE, 0); 629 630 /* Enable statistics for ports 0, 1 and 2 */ 631 cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7); 632 633 /* Turn off flow control. */ 634 cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0); 635 636 /* Make IP hdr aligned with 4 */ 637 cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, 2); 638 639 /* Initialize RX Buffer Descriptors */ 640 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), 0); 641 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0); 642 643 /* Enable TX & RX DMA */ 644 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1); 645 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1); 646 647 /* Enable Interrupts for core 0 */ 648 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(0), 0xFF); 649 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0xFF); 650 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0xFF); 651 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F); 652 653 /* Enable host Error Interrupt */ 654 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 3); 655 656 /* Enable interrupts for RX and TX on Channel 0 */ 657 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 658 CPSW_CPDMA_RX_INT(0) | CPSW_CPDMA_RX_INT_THRESH(0)); 659 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1); 660 661 /* Initialze MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */ 662 /* TODO Calculate MDCLK=CLK/(CLKDIV+1) */ 663 cpsw_write_4(sc, MDIOCONTROL, MDIOCTL_ENABLE | MDIOCTL_FAULTENB | 0xff); 664 665 /* Select MII in GMII_SEL, Internal Delay mode */ 666 //ti_scm_reg_write_4(0x650, 0); 667 668 /* Initialize active queues. */ 669 slot = STAILQ_FIRST(&sc->tx.active); 670 if (slot != NULL) 671 cpsw_write_hdp_slot(sc, &sc->tx, slot); 672 slot = STAILQ_FIRST(&sc->rx.active); 673 if (slot != NULL) 674 cpsw_write_hdp_slot(sc, &sc->rx, slot); 675 cpsw_rx_enqueue(sc); 676 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), sc->rx.active_queue_len); 677 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), CPSW_TXFRAGS); 678 679 /* Activate network interface. */ 680 sc->rx.running = 1; 681 sc->tx.running = 1; 682 sc->watchdog.timer = 0; 683 callout_init(&sc->watchdog.callout, 0); 684 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc); 685 } 686 687 /* 688 * 689 * Device Probe, Attach, Detach. 690 * 691 */ 692 693 static int 694 cpsw_probe(device_t dev) 695 { 696 697 if (!ofw_bus_status_okay(dev)) 698 return (ENXIO); 699 700 if (!ofw_bus_is_compatible(dev, "ti,cpsw")) 701 return (ENXIO); 702 703 device_set_desc(dev, "3-port Switch Ethernet Subsystem"); 704 return (BUS_PROBE_DEFAULT); 705 } 706 707 static int 708 cpsw_intr_attach(struct cpsw_softc *sc) 709 { 710 int i; 711 712 for (i = 0; i < CPSW_INTR_COUNT; i++) { 713 if (bus_setup_intr(sc->dev, sc->irq_res[i], 714 INTR_TYPE_NET | INTR_MPSAFE, NULL, 715 cpsw_intr_cb[i].cb, sc, &sc->ih_cookie[i]) != 0) { 716 return (-1); 717 } 718 } 719 720 return (0); 721 } 722 723 static void 724 cpsw_intr_detach(struct cpsw_softc *sc) 725 { 726 int i; 727 728 for (i = 0; i < CPSW_INTR_COUNT; i++) { 729 if (sc->ih_cookie[i]) { 730 bus_teardown_intr(sc->dev, sc->irq_res[i], 731 sc->ih_cookie[i]); 732 } 733 } 734 } 735 736 static int 737 cpsw_get_fdt_data(struct cpsw_softc *sc, int port) 738 { 739 char *name; 740 int len, phy, vlan; 741 pcell_t phy_id[3], vlan_id; 742 phandle_t child; 743 unsigned long mdio_child_addr; 744 745 /* Find any slave with phy_id */ 746 phy = -1; 747 vlan = -1; 748 for (child = OF_child(sc->node); child != 0; child = OF_peer(child)) { 749 if (OF_getprop_alloc(child, "name", (void **)&name) < 0) 750 continue; 751 if (sscanf(name, "slave@%lx", &mdio_child_addr) != 1) { 752 OF_prop_free(name); 753 continue; 754 } 755 OF_prop_free(name); 756 if (mdio_child_addr != slave_mdio_addr[port]) 757 continue; 758 759 len = OF_getproplen(child, "phy_id"); 760 if (len / sizeof(pcell_t) == 2) { 761 /* Get phy address from fdt */ 762 if (OF_getencprop(child, "phy_id", phy_id, len) > 0) 763 phy = phy_id[1]; 764 } 765 766 len = OF_getproplen(child, "dual_emac_res_vlan"); 767 if (len / sizeof(pcell_t) == 1) { 768 /* Get phy address from fdt */ 769 if (OF_getencprop(child, "dual_emac_res_vlan", 770 &vlan_id, len) > 0) { 771 vlan = vlan_id; 772 } 773 } 774 775 break; 776 } 777 if (phy == -1) 778 return (ENXIO); 779 sc->port[port].phy = phy; 780 sc->port[port].vlan = vlan; 781 782 return (0); 783 } 784 785 static int 786 cpsw_attach(device_t dev) 787 { 788 int error, i; 789 struct cpsw_softc *sc; 790 uint32_t reg; 791 792 sc = device_get_softc(dev); 793 sc->dev = dev; 794 sc->node = ofw_bus_get_node(dev); 795 getbinuptime(&sc->attach_uptime); 796 797 if (OF_getencprop(sc->node, "active_slave", &sc->active_slave, 798 sizeof(sc->active_slave)) <= 0) { 799 sc->active_slave = 0; 800 } 801 if (sc->active_slave > 1) 802 sc->active_slave = 1; 803 804 if (OF_hasprop(sc->node, "dual_emac")) 805 sc->dualemac = 1; 806 807 for (i = 0; i < CPSW_PORTS; i++) { 808 if (!sc->dualemac && i != sc->active_slave) 809 continue; 810 if (cpsw_get_fdt_data(sc, i) != 0) { 811 device_printf(dev, 812 "failed to get PHY address from FDT\n"); 813 return (ENXIO); 814 } 815 } 816 817 /* Initialize mutexes */ 818 mtx_init(&sc->tx.lock, device_get_nameunit(dev), 819 "cpsw TX lock", MTX_DEF); 820 mtx_init(&sc->rx.lock, device_get_nameunit(dev), 821 "cpsw RX lock", MTX_DEF); 822 823 /* Allocate IRQ resources */ 824 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res); 825 if (error) { 826 device_printf(dev, "could not allocate IRQ resources\n"); 827 cpsw_detach(dev); 828 return (ENXIO); 829 } 830 831 sc->mem_rid = 0; 832 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 833 &sc->mem_rid, RF_ACTIVE); 834 if (sc->mem_res == NULL) { 835 device_printf(sc->dev, "failed to allocate memory resource\n"); 836 cpsw_detach(dev); 837 return (ENXIO); 838 } 839 840 reg = cpsw_read_4(sc, CPSW_SS_IDVER); 841 device_printf(dev, "CPSW SS Version %d.%d (%d)\n", (reg >> 8 & 0x7), 842 reg & 0xFF, (reg >> 11) & 0x1F); 843 844 cpsw_add_sysctls(sc); 845 846 /* Allocate a busdma tag and DMA safe memory for mbufs. */ 847 error = bus_dma_tag_create( 848 bus_get_dma_tag(sc->dev), /* parent */ 849 1, 0, /* alignment, boundary */ 850 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 851 BUS_SPACE_MAXADDR, /* highaddr */ 852 NULL, NULL, /* filtfunc, filtfuncarg */ 853 MCLBYTES, CPSW_TXFRAGS, /* maxsize, nsegments */ 854 MCLBYTES, 0, /* maxsegsz, flags */ 855 NULL, NULL, /* lockfunc, lockfuncarg */ 856 &sc->mbuf_dtag); /* dmatag */ 857 if (error) { 858 device_printf(dev, "bus_dma_tag_create failed\n"); 859 cpsw_detach(dev); 860 return (error); 861 } 862 863 /* Allocate a NULL buffer for padding. */ 864 sc->nullpad = malloc(ETHER_MIN_LEN, M_DEVBUF, M_WAITOK | M_ZERO); 865 866 cpsw_init_slots(sc); 867 868 /* Allocate slots to TX and RX queues. */ 869 STAILQ_INIT(&sc->rx.avail); 870 STAILQ_INIT(&sc->rx.active); 871 STAILQ_INIT(&sc->tx.avail); 872 STAILQ_INIT(&sc->tx.active); 873 // For now: 128 slots to TX, rest to RX. 874 // XXX TODO: start with 32/64 and grow dynamically based on demand. 875 if (cpsw_add_slots(sc, &sc->tx, 128) || 876 cpsw_add_slots(sc, &sc->rx, -1)) { 877 device_printf(dev, "failed to allocate dmamaps\n"); 878 cpsw_detach(dev); 879 return (ENOMEM); 880 } 881 device_printf(dev, "Initial queue size TX=%d RX=%d\n", 882 sc->tx.queue_slots, sc->rx.queue_slots); 883 884 sc->tx.hdp_offset = CPSW_CPDMA_TX_HDP(0); 885 sc->rx.hdp_offset = CPSW_CPDMA_RX_HDP(0); 886 887 if (cpsw_intr_attach(sc) == -1) { 888 device_printf(dev, "failed to setup interrupts\n"); 889 cpsw_detach(dev); 890 return (ENXIO); 891 } 892 893 #ifdef CPSW_ETHERSWITCH 894 for (i = 0; i < CPSW_VLANS; i++) 895 cpsw_vgroups[i].vid = -1; 896 #endif 897 898 /* Reset the controller. */ 899 cpsw_reset(sc); 900 cpsw_init(sc); 901 902 for (i = 0; i < CPSW_PORTS; i++) { 903 if (!sc->dualemac && i != sc->active_slave) 904 continue; 905 sc->port[i].dev = device_add_child(dev, "cpsw", i); 906 if (sc->port[i].dev == NULL) { 907 cpsw_detach(dev); 908 return (ENXIO); 909 } 910 } 911 bus_generic_probe(dev); 912 bus_generic_attach(dev); 913 914 return (0); 915 } 916 917 static int 918 cpsw_detach(device_t dev) 919 { 920 struct cpsw_softc *sc; 921 int error, i; 922 923 bus_generic_detach(dev); 924 sc = device_get_softc(dev); 925 926 for (i = 0; i < CPSW_PORTS; i++) { 927 if (sc->port[i].dev) 928 device_delete_child(dev, sc->port[i].dev); 929 } 930 931 if (device_is_attached(dev)) { 932 callout_stop(&sc->watchdog.callout); 933 callout_drain(&sc->watchdog.callout); 934 } 935 936 /* Stop and release all interrupts */ 937 cpsw_intr_detach(sc); 938 939 /* Free dmamaps and mbufs */ 940 for (i = 0; i < nitems(sc->_slots); ++i) 941 cpsw_free_slot(sc, &sc->_slots[i]); 942 943 /* Free null padding buffer. */ 944 if (sc->nullpad) 945 free(sc->nullpad, M_DEVBUF); 946 947 /* Free DMA tag */ 948 if (sc->mbuf_dtag) { 949 error = bus_dma_tag_destroy(sc->mbuf_dtag); 950 KASSERT(error == 0, ("Unable to destroy DMA tag")); 951 } 952 953 /* Free IO memory handler */ 954 if (sc->mem_res != NULL) 955 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); 956 bus_release_resources(dev, irq_res_spec, sc->irq_res); 957 958 /* Destroy mutexes */ 959 mtx_destroy(&sc->rx.lock); 960 mtx_destroy(&sc->tx.lock); 961 962 /* Detach the switch device, if present. */ 963 error = bus_generic_detach(dev); 964 if (error != 0) 965 return (error); 966 967 return (device_delete_children(dev)); 968 } 969 970 static phandle_t 971 cpsw_get_node(device_t bus, device_t dev) 972 { 973 974 /* Share controller node with port device. */ 975 return (ofw_bus_get_node(bus)); 976 } 977 978 static int 979 cpswp_probe(device_t dev) 980 { 981 982 if (device_get_unit(dev) > 1) { 983 device_printf(dev, "Only two ports are supported.\n"); 984 return (ENXIO); 985 } 986 device_set_desc(dev, "Ethernet Switch Port"); 987 988 return (BUS_PROBE_DEFAULT); 989 } 990 991 static int 992 cpswp_attach(device_t dev) 993 { 994 int error; 995 struct ifnet *ifp; 996 struct cpswp_softc *sc; 997 uint32_t reg; 998 uint8_t mac_addr[ETHER_ADDR_LEN]; 999 1000 sc = device_get_softc(dev); 1001 sc->dev = dev; 1002 sc->pdev = device_get_parent(dev); 1003 sc->swsc = device_get_softc(sc->pdev); 1004 sc->unit = device_get_unit(dev); 1005 sc->phy = sc->swsc->port[sc->unit].phy; 1006 sc->vlan = sc->swsc->port[sc->unit].vlan; 1007 if (sc->swsc->dualemac && sc->vlan == -1) 1008 sc->vlan = sc->unit + 1; 1009 1010 if (sc->unit == 0) { 1011 sc->physel = MDIOUSERPHYSEL0; 1012 sc->phyaccess = MDIOUSERACCESS0; 1013 } else { 1014 sc->physel = MDIOUSERPHYSEL1; 1015 sc->phyaccess = MDIOUSERACCESS1; 1016 } 1017 1018 mtx_init(&sc->lock, device_get_nameunit(dev), "cpsw port lock", 1019 MTX_DEF); 1020 1021 /* Allocate network interface */ 1022 ifp = sc->ifp = if_alloc(IFT_ETHER); 1023 if (ifp == NULL) { 1024 cpswp_detach(dev); 1025 return (ENXIO); 1026 } 1027 1028 if_initname(ifp, device_get_name(sc->dev), sc->unit); 1029 ifp->if_softc = sc; 1030 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 1031 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_HWCSUM; //FIXME VLAN? 1032 ifp->if_capenable = ifp->if_capabilities; 1033 1034 ifp->if_init = cpswp_init; 1035 ifp->if_start = cpswp_start; 1036 ifp->if_ioctl = cpswp_ioctl; 1037 1038 ifp->if_snd.ifq_drv_maxlen = sc->swsc->tx.queue_slots; 1039 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1040 IFQ_SET_READY(&ifp->if_snd); 1041 1042 /* Get high part of MAC address from control module (mac_id[0|1]_hi) */ 1043 ti_scm_reg_read_4(SCM_MAC_ID0_HI + sc->unit * 8, ®); 1044 mac_addr[0] = reg & 0xFF; 1045 mac_addr[1] = (reg >> 8) & 0xFF; 1046 mac_addr[2] = (reg >> 16) & 0xFF; 1047 mac_addr[3] = (reg >> 24) & 0xFF; 1048 1049 /* Get low part of MAC address from control module (mac_id[0|1]_lo) */ 1050 ti_scm_reg_read_4(SCM_MAC_ID0_LO + sc->unit * 8, ®); 1051 mac_addr[4] = reg & 0xFF; 1052 mac_addr[5] = (reg >> 8) & 0xFF; 1053 1054 error = mii_attach(dev, &sc->miibus, ifp, cpswp_ifmedia_upd, 1055 cpswp_ifmedia_sts, BMSR_DEFCAPMASK, sc->phy, MII_OFFSET_ANY, 0); 1056 if (error) { 1057 device_printf(dev, "attaching PHYs failed\n"); 1058 cpswp_detach(dev); 1059 return (error); 1060 } 1061 sc->mii = device_get_softc(sc->miibus); 1062 1063 /* Select PHY and enable interrupts */ 1064 cpsw_write_4(sc->swsc, sc->physel, 1065 MDIO_PHYSEL_LINKINTENB | (sc->phy & 0x1F)); 1066 1067 ether_ifattach(sc->ifp, mac_addr); 1068 callout_init(&sc->mii_callout, 0); 1069 1070 return (0); 1071 } 1072 1073 static int 1074 cpswp_detach(device_t dev) 1075 { 1076 struct cpswp_softc *sc; 1077 1078 sc = device_get_softc(dev); 1079 CPSW_DEBUGF(sc->swsc, ("")); 1080 if (device_is_attached(dev)) { 1081 ether_ifdetach(sc->ifp); 1082 CPSW_PORT_LOCK(sc); 1083 cpswp_stop_locked(sc); 1084 CPSW_PORT_UNLOCK(sc); 1085 callout_drain(&sc->mii_callout); 1086 } 1087 1088 bus_generic_detach(dev); 1089 1090 if_free(sc->ifp); 1091 mtx_destroy(&sc->lock); 1092 1093 return (0); 1094 } 1095 1096 /* 1097 * 1098 * Init/Shutdown. 1099 * 1100 */ 1101 1102 static int 1103 cpsw_ports_down(struct cpsw_softc *sc) 1104 { 1105 struct cpswp_softc *psc; 1106 struct ifnet *ifp1, *ifp2; 1107 1108 if (!sc->dualemac) 1109 return (1); 1110 psc = device_get_softc(sc->port[0].dev); 1111 ifp1 = psc->ifp; 1112 psc = device_get_softc(sc->port[1].dev); 1113 ifp2 = psc->ifp; 1114 if ((ifp1->if_flags & IFF_UP) == 0 && (ifp2->if_flags & IFF_UP) == 0) 1115 return (1); 1116 1117 return (0); 1118 } 1119 1120 static void 1121 cpswp_init(void *arg) 1122 { 1123 struct cpswp_softc *sc = arg; 1124 1125 CPSW_DEBUGF(sc->swsc, ("")); 1126 CPSW_PORT_LOCK(sc); 1127 cpswp_init_locked(arg); 1128 CPSW_PORT_UNLOCK(sc); 1129 } 1130 1131 static void 1132 cpswp_init_locked(void *arg) 1133 { 1134 #ifdef CPSW_ETHERSWITCH 1135 int i; 1136 #endif 1137 struct cpswp_softc *sc = arg; 1138 struct ifnet *ifp; 1139 uint32_t reg; 1140 1141 CPSW_DEBUGF(sc->swsc, ("")); 1142 CPSW_PORT_LOCK_ASSERT(sc); 1143 ifp = sc->ifp; 1144 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1145 return; 1146 1147 getbinuptime(&sc->init_uptime); 1148 1149 if (!sc->swsc->rx.running && !sc->swsc->tx.running) { 1150 /* Reset the controller. */ 1151 cpsw_reset(sc->swsc); 1152 cpsw_init(sc->swsc); 1153 } 1154 1155 /* Set Slave Mapping. */ 1156 cpsw_write_4(sc->swsc, CPSW_SL_RX_PRI_MAP(sc->unit), 0x76543210); 1157 cpsw_write_4(sc->swsc, CPSW_PORT_P_TX_PRI_MAP(sc->unit + 1), 1158 0x33221100); 1159 cpsw_write_4(sc->swsc, CPSW_SL_RX_MAXLEN(sc->unit), 0x5f2); 1160 /* Enable MAC RX/TX modules. */ 1161 /* TODO: Docs claim that IFCTL_B and IFCTL_A do the same thing? */ 1162 /* Huh? Docs call bit 0 "Loopback" some places, "FullDuplex" others. */ 1163 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit)); 1164 reg |= CPSW_SL_MACTL_GMII_ENABLE; 1165 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg); 1166 1167 /* Initialize ALE: set port to forwarding, initialize addrs */ 1168 cpsw_write_4(sc->swsc, CPSW_ALE_PORTCTL(sc->unit + 1), 1169 ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD); 1170 cpswp_ale_update_addresses(sc, 1); 1171 1172 if (sc->swsc->dualemac) { 1173 /* Set Port VID. */ 1174 cpsw_write_4(sc->swsc, CPSW_PORT_P_VLAN(sc->unit + 1), 1175 sc->vlan & 0xfff); 1176 cpsw_ale_update_vlan_table(sc->swsc, sc->vlan, 1177 (1 << (sc->unit + 1)) | (1 << 0), /* Member list */ 1178 (1 << (sc->unit + 1)) | (1 << 0), /* Untagged egress */ 1179 (1 << (sc->unit + 1)) | (1 << 0), 0); /* mcast reg flood */ 1180 #ifdef CPSW_ETHERSWITCH 1181 for (i = 0; i < CPSW_VLANS; i++) { 1182 if (cpsw_vgroups[i].vid != -1) 1183 continue; 1184 cpsw_vgroups[i].vid = sc->vlan; 1185 break; 1186 } 1187 #endif 1188 } 1189 1190 mii_mediachg(sc->mii); 1191 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc); 1192 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1193 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1194 } 1195 1196 static int 1197 cpsw_shutdown(device_t dev) 1198 { 1199 struct cpsw_softc *sc; 1200 struct cpswp_softc *psc; 1201 int i; 1202 1203 sc = device_get_softc(dev); 1204 CPSW_DEBUGF(sc, ("")); 1205 for (i = 0; i < CPSW_PORTS; i++) { 1206 if (!sc->dualemac && i != sc->active_slave) 1207 continue; 1208 psc = device_get_softc(sc->port[i].dev); 1209 CPSW_PORT_LOCK(psc); 1210 cpswp_stop_locked(psc); 1211 CPSW_PORT_UNLOCK(psc); 1212 } 1213 1214 return (0); 1215 } 1216 1217 static void 1218 cpsw_rx_teardown(struct cpsw_softc *sc) 1219 { 1220 int i = 0; 1221 1222 CPSW_RX_LOCK(sc); 1223 CPSW_DEBUGF(sc, ("starting RX teardown")); 1224 sc->rx.teardown = 1; 1225 cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0); 1226 CPSW_RX_UNLOCK(sc); 1227 while (sc->rx.running) { 1228 if (++i > 10) { 1229 device_printf(sc->dev, 1230 "Unable to cleanly shutdown receiver\n"); 1231 return; 1232 } 1233 DELAY(200); 1234 } 1235 if (!sc->rx.running) 1236 CPSW_DEBUGF(sc, ("finished RX teardown (%d retries)", i)); 1237 } 1238 1239 static void 1240 cpsw_tx_teardown(struct cpsw_softc *sc) 1241 { 1242 int i = 0; 1243 1244 CPSW_TX_LOCK(sc); 1245 CPSW_DEBUGF(sc, ("starting TX teardown")); 1246 /* Start the TX queue teardown if queue is not empty. */ 1247 if (STAILQ_FIRST(&sc->tx.active) != NULL) 1248 cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0); 1249 else 1250 sc->tx.teardown = 1; 1251 cpsw_tx_dequeue(sc); 1252 while (sc->tx.running && ++i < 10) { 1253 DELAY(200); 1254 cpsw_tx_dequeue(sc); 1255 } 1256 if (sc->tx.running) { 1257 device_printf(sc->dev, 1258 "Unable to cleanly shutdown transmitter\n"); 1259 } 1260 CPSW_DEBUGF(sc, 1261 ("finished TX teardown (%d retries, %d idle buffers)", i, 1262 sc->tx.active_queue_len)); 1263 CPSW_TX_UNLOCK(sc); 1264 } 1265 1266 static void 1267 cpswp_stop_locked(struct cpswp_softc *sc) 1268 { 1269 struct ifnet *ifp; 1270 uint32_t reg; 1271 1272 ifp = sc->ifp; 1273 CPSW_DEBUGF(sc->swsc, ("")); 1274 CPSW_PORT_LOCK_ASSERT(sc); 1275 1276 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1277 return; 1278 1279 /* Disable interface */ 1280 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1281 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1282 1283 /* Stop ticker */ 1284 callout_stop(&sc->mii_callout); 1285 1286 /* Tear down the RX/TX queues. */ 1287 if (cpsw_ports_down(sc->swsc)) { 1288 cpsw_rx_teardown(sc->swsc); 1289 cpsw_tx_teardown(sc->swsc); 1290 } 1291 1292 /* Stop MAC RX/TX modules. */ 1293 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit)); 1294 reg &= ~CPSW_SL_MACTL_GMII_ENABLE; 1295 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg); 1296 1297 if (cpsw_ports_down(sc->swsc)) { 1298 /* Capture stats before we reset controller. */ 1299 cpsw_stats_collect(sc->swsc); 1300 1301 cpsw_reset(sc->swsc); 1302 cpsw_init(sc->swsc); 1303 } 1304 } 1305 1306 /* 1307 * Suspend/Resume. 1308 */ 1309 1310 static int 1311 cpsw_suspend(device_t dev) 1312 { 1313 struct cpsw_softc *sc; 1314 struct cpswp_softc *psc; 1315 int i; 1316 1317 sc = device_get_softc(dev); 1318 CPSW_DEBUGF(sc, ("")); 1319 for (i = 0; i < CPSW_PORTS; i++) { 1320 if (!sc->dualemac && i != sc->active_slave) 1321 continue; 1322 psc = device_get_softc(sc->port[i].dev); 1323 CPSW_PORT_LOCK(psc); 1324 cpswp_stop_locked(psc); 1325 CPSW_PORT_UNLOCK(psc); 1326 } 1327 1328 return (0); 1329 } 1330 1331 static int 1332 cpsw_resume(device_t dev) 1333 { 1334 struct cpsw_softc *sc; 1335 1336 sc = device_get_softc(dev); 1337 CPSW_DEBUGF(sc, ("UNIMPLEMENTED")); 1338 1339 return (0); 1340 } 1341 1342 /* 1343 * 1344 * IOCTL 1345 * 1346 */ 1347 1348 static void 1349 cpsw_set_promisc(struct cpswp_softc *sc, int set) 1350 { 1351 uint32_t reg; 1352 1353 /* 1354 * Enabling promiscuous mode requires ALE_BYPASS to be enabled. 1355 * That disables the ALE forwarding logic and causes every 1356 * packet to be sent only to the host port. In bypass mode, 1357 * the ALE processes host port transmit packets the same as in 1358 * normal mode. 1359 */ 1360 reg = cpsw_read_4(sc->swsc, CPSW_ALE_CONTROL); 1361 reg &= ~CPSW_ALE_CTL_BYPASS; 1362 if (set) 1363 reg |= CPSW_ALE_CTL_BYPASS; 1364 cpsw_write_4(sc->swsc, CPSW_ALE_CONTROL, reg); 1365 } 1366 1367 static void 1368 cpsw_set_allmulti(struct cpswp_softc *sc, int set) 1369 { 1370 if (set) { 1371 printf("All-multicast mode unimplemented\n"); 1372 } 1373 } 1374 1375 static int 1376 cpswp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1377 { 1378 struct cpswp_softc *sc; 1379 struct ifreq *ifr; 1380 int error; 1381 uint32_t changed; 1382 1383 error = 0; 1384 sc = ifp->if_softc; 1385 ifr = (struct ifreq *)data; 1386 1387 switch (command) { 1388 case SIOCSIFCAP: 1389 changed = ifp->if_capenable ^ ifr->ifr_reqcap; 1390 if (changed & IFCAP_HWCSUM) { 1391 if ((ifr->ifr_reqcap & changed) & IFCAP_HWCSUM) 1392 ifp->if_capenable |= IFCAP_HWCSUM; 1393 else 1394 ifp->if_capenable &= ~IFCAP_HWCSUM; 1395 } 1396 error = 0; 1397 break; 1398 case SIOCSIFFLAGS: 1399 CPSW_PORT_LOCK(sc); 1400 if (ifp->if_flags & IFF_UP) { 1401 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1402 changed = ifp->if_flags ^ sc->if_flags; 1403 CPSW_DEBUGF(sc->swsc, 1404 ("SIOCSIFFLAGS: UP & RUNNING (changed=0x%x)", 1405 changed)); 1406 if (changed & IFF_PROMISC) 1407 cpsw_set_promisc(sc, 1408 ifp->if_flags & IFF_PROMISC); 1409 if (changed & IFF_ALLMULTI) 1410 cpsw_set_allmulti(sc, 1411 ifp->if_flags & IFF_ALLMULTI); 1412 } else { 1413 CPSW_DEBUGF(sc->swsc, 1414 ("SIOCSIFFLAGS: starting up")); 1415 cpswp_init_locked(sc); 1416 } 1417 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1418 CPSW_DEBUGF(sc->swsc, ("SIOCSIFFLAGS: shutting down")); 1419 cpswp_stop_locked(sc); 1420 } 1421 1422 sc->if_flags = ifp->if_flags; 1423 CPSW_PORT_UNLOCK(sc); 1424 break; 1425 case SIOCADDMULTI: 1426 cpswp_ale_update_addresses(sc, 0); 1427 break; 1428 case SIOCDELMULTI: 1429 /* Ugh. DELMULTI doesn't provide the specific address 1430 being removed, so the best we can do is remove 1431 everything and rebuild it all. */ 1432 cpswp_ale_update_addresses(sc, 1); 1433 break; 1434 case SIOCGIFMEDIA: 1435 case SIOCSIFMEDIA: 1436 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, command); 1437 break; 1438 default: 1439 error = ether_ioctl(ifp, command, data); 1440 } 1441 return (error); 1442 } 1443 1444 /* 1445 * 1446 * MIIBUS 1447 * 1448 */ 1449 static int 1450 cpswp_miibus_ready(struct cpsw_softc *sc, uint32_t reg) 1451 { 1452 uint32_t r, retries = CPSW_MIIBUS_RETRIES; 1453 1454 while (--retries) { 1455 r = cpsw_read_4(sc, reg); 1456 if ((r & MDIO_PHYACCESS_GO) == 0) 1457 return (1); 1458 DELAY(CPSW_MIIBUS_DELAY); 1459 } 1460 1461 return (0); 1462 } 1463 1464 static int 1465 cpswp_miibus_readreg(device_t dev, int phy, int reg) 1466 { 1467 struct cpswp_softc *sc; 1468 uint32_t cmd, r; 1469 1470 sc = device_get_softc(dev); 1471 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1472 device_printf(dev, "MDIO not ready to read\n"); 1473 return (0); 1474 } 1475 1476 /* Set GO, reg, phy */ 1477 cmd = MDIO_PHYACCESS_GO | (reg & 0x1F) << 21 | (phy & 0x1F) << 16; 1478 cpsw_write_4(sc->swsc, sc->phyaccess, cmd); 1479 1480 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1481 device_printf(dev, "MDIO timed out during read\n"); 1482 return (0); 1483 } 1484 1485 r = cpsw_read_4(sc->swsc, sc->phyaccess); 1486 if ((r & MDIO_PHYACCESS_ACK) == 0) { 1487 device_printf(dev, "Failed to read from PHY.\n"); 1488 r = 0; 1489 } 1490 return (r & 0xFFFF); 1491 } 1492 1493 static int 1494 cpswp_miibus_writereg(device_t dev, int phy, int reg, int value) 1495 { 1496 struct cpswp_softc *sc; 1497 uint32_t cmd; 1498 1499 sc = device_get_softc(dev); 1500 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1501 device_printf(dev, "MDIO not ready to write\n"); 1502 return (0); 1503 } 1504 1505 /* Set GO, WRITE, reg, phy, and value */ 1506 cmd = MDIO_PHYACCESS_GO | MDIO_PHYACCESS_WRITE | 1507 (reg & 0x1F) << 21 | (phy & 0x1F) << 16 | (value & 0xFFFF); 1508 cpsw_write_4(sc->swsc, sc->phyaccess, cmd); 1509 1510 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1511 device_printf(dev, "MDIO timed out during write\n"); 1512 return (0); 1513 } 1514 1515 return (0); 1516 } 1517 1518 static void 1519 cpswp_miibus_statchg(device_t dev) 1520 { 1521 struct cpswp_softc *sc; 1522 uint32_t mac_control, reg; 1523 1524 sc = device_get_softc(dev); 1525 CPSW_DEBUGF(sc->swsc, ("")); 1526 1527 reg = CPSW_SL_MACCONTROL(sc->unit); 1528 mac_control = cpsw_read_4(sc->swsc, reg); 1529 mac_control &= ~(CPSW_SL_MACTL_GIG | CPSW_SL_MACTL_IFCTL_A | 1530 CPSW_SL_MACTL_IFCTL_B | CPSW_SL_MACTL_FULLDUPLEX); 1531 1532 switch(IFM_SUBTYPE(sc->mii->mii_media_active)) { 1533 case IFM_1000_SX: 1534 case IFM_1000_LX: 1535 case IFM_1000_CX: 1536 case IFM_1000_T: 1537 mac_control |= CPSW_SL_MACTL_GIG; 1538 break; 1539 1540 case IFM_100_TX: 1541 mac_control |= CPSW_SL_MACTL_IFCTL_A; 1542 break; 1543 } 1544 if (sc->mii->mii_media_active & IFM_FDX) 1545 mac_control |= CPSW_SL_MACTL_FULLDUPLEX; 1546 1547 cpsw_write_4(sc->swsc, reg, mac_control); 1548 } 1549 1550 /* 1551 * 1552 * Transmit/Receive Packets. 1553 * 1554 */ 1555 static void 1556 cpsw_intr_rx(void *arg) 1557 { 1558 struct cpsw_softc *sc; 1559 struct ifnet *ifp; 1560 struct mbuf *received, *next; 1561 1562 sc = (struct cpsw_softc *)arg; 1563 CPSW_RX_LOCK(sc); 1564 if (sc->rx.teardown) { 1565 sc->rx.running = 0; 1566 sc->rx.teardown = 0; 1567 cpsw_write_cp(sc, &sc->rx, 0xfffffffc); 1568 } 1569 received = cpsw_rx_dequeue(sc); 1570 cpsw_rx_enqueue(sc); 1571 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 1); 1572 CPSW_RX_UNLOCK(sc); 1573 1574 while (received != NULL) { 1575 next = received->m_nextpkt; 1576 received->m_nextpkt = NULL; 1577 ifp = received->m_pkthdr.rcvif; 1578 (*ifp->if_input)(ifp, received); 1579 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1580 received = next; 1581 } 1582 } 1583 1584 static struct mbuf * 1585 cpsw_rx_dequeue(struct cpsw_softc *sc) 1586 { 1587 int nsegs, port, removed; 1588 struct cpsw_cpdma_bd bd; 1589 struct cpsw_slot *last, *slot; 1590 struct cpswp_softc *psc; 1591 struct mbuf *m, *m0, *mb_head, *mb_tail; 1592 uint16_t m0_flags; 1593 1594 nsegs = 0; 1595 m0 = NULL; 1596 last = NULL; 1597 mb_head = NULL; 1598 mb_tail = NULL; 1599 removed = 0; 1600 1601 /* Pull completed packets off hardware RX queue. */ 1602 while ((slot = STAILQ_FIRST(&sc->rx.active)) != NULL) { 1603 cpsw_cpdma_read_bd(sc, slot, &bd); 1604 1605 /* 1606 * Stop on packets still in use by hardware, but do not stop 1607 * on packets with the teardown complete flag, they will be 1608 * discarded later. 1609 */ 1610 if ((bd.flags & (CPDMA_BD_OWNER | CPDMA_BD_TDOWNCMPLT)) == 1611 CPDMA_BD_OWNER) 1612 break; 1613 1614 last = slot; 1615 ++removed; 1616 STAILQ_REMOVE_HEAD(&sc->rx.active, next); 1617 STAILQ_INSERT_TAIL(&sc->rx.avail, slot, next); 1618 1619 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTREAD); 1620 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1621 1622 m = slot->mbuf; 1623 slot->mbuf = NULL; 1624 1625 if (bd.flags & CPDMA_BD_TDOWNCMPLT) { 1626 CPSW_DEBUGF(sc, ("RX teardown is complete")); 1627 m_freem(m); 1628 sc->rx.running = 0; 1629 sc->rx.teardown = 0; 1630 break; 1631 } 1632 1633 port = (bd.flags & CPDMA_BD_PORT_MASK) - 1; 1634 KASSERT(port >= 0 && port <= 1, 1635 ("patcket received with invalid port: %d", port)); 1636 psc = device_get_softc(sc->port[port].dev); 1637 1638 /* Set up mbuf */ 1639 m->m_data += bd.bufoff; 1640 m->m_len = bd.buflen; 1641 if (bd.flags & CPDMA_BD_SOP) { 1642 m->m_pkthdr.len = bd.pktlen; 1643 m->m_pkthdr.rcvif = psc->ifp; 1644 m->m_flags |= M_PKTHDR; 1645 m0_flags = bd.flags; 1646 m0 = m; 1647 } 1648 nsegs++; 1649 m->m_next = NULL; 1650 m->m_nextpkt = NULL; 1651 if (bd.flags & CPDMA_BD_EOP && m0 != NULL) { 1652 if (m0_flags & CPDMA_BD_PASS_CRC) 1653 m_adj(m0, -ETHER_CRC_LEN); 1654 m0_flags = 0; 1655 m0 = NULL; 1656 if (nsegs > sc->rx.longest_chain) 1657 sc->rx.longest_chain = nsegs; 1658 nsegs = 0; 1659 } 1660 1661 if ((psc->ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1662 /* check for valid CRC by looking into pkt_err[5:4] */ 1663 if ((bd.flags & 1664 (CPDMA_BD_SOP | CPDMA_BD_PKT_ERR_MASK)) == 1665 CPDMA_BD_SOP) { 1666 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1667 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1668 m->m_pkthdr.csum_data = 0xffff; 1669 } 1670 } 1671 1672 if (STAILQ_FIRST(&sc->rx.active) != NULL && 1673 (bd.flags & (CPDMA_BD_EOP | CPDMA_BD_EOQ)) == 1674 (CPDMA_BD_EOP | CPDMA_BD_EOQ)) { 1675 cpsw_write_hdp_slot(sc, &sc->rx, 1676 STAILQ_FIRST(&sc->rx.active)); 1677 sc->rx.queue_restart++; 1678 } 1679 1680 /* Add mbuf to packet list to be returned. */ 1681 if (mb_tail != NULL && (bd.flags & CPDMA_BD_SOP)) { 1682 mb_tail->m_nextpkt = m; 1683 } else if (mb_tail != NULL) { 1684 mb_tail->m_next = m; 1685 } else if (mb_tail == NULL && (bd.flags & CPDMA_BD_SOP) == 0) { 1686 if (bootverbose) 1687 printf( 1688 "%s: %s: discanding fragment packet w/o header\n", 1689 __func__, psc->ifp->if_xname); 1690 m_freem(m); 1691 continue; 1692 } else { 1693 mb_head = m; 1694 } 1695 mb_tail = m; 1696 } 1697 1698 if (removed != 0) { 1699 cpsw_write_cp_slot(sc, &sc->rx, last); 1700 sc->rx.queue_removes += removed; 1701 sc->rx.avail_queue_len += removed; 1702 sc->rx.active_queue_len -= removed; 1703 if (sc->rx.avail_queue_len > sc->rx.max_avail_queue_len) 1704 sc->rx.max_avail_queue_len = sc->rx.avail_queue_len; 1705 CPSW_DEBUGF(sc, ("Removed %d received packet(s) from RX queue", removed)); 1706 } 1707 1708 return (mb_head); 1709 } 1710 1711 static void 1712 cpsw_rx_enqueue(struct cpsw_softc *sc) 1713 { 1714 bus_dma_segment_t seg[1]; 1715 struct cpsw_cpdma_bd bd; 1716 struct cpsw_slot *first_new_slot, *last_old_slot, *next, *slot; 1717 int error, nsegs, added = 0; 1718 1719 /* Register new mbufs with hardware. */ 1720 first_new_slot = NULL; 1721 last_old_slot = STAILQ_LAST(&sc->rx.active, cpsw_slot, next); 1722 while ((slot = STAILQ_FIRST(&sc->rx.avail)) != NULL) { 1723 if (first_new_slot == NULL) 1724 first_new_slot = slot; 1725 if (slot->mbuf == NULL) { 1726 slot->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1727 if (slot->mbuf == NULL) { 1728 device_printf(sc->dev, 1729 "Unable to fill RX queue\n"); 1730 break; 1731 } 1732 slot->mbuf->m_len = 1733 slot->mbuf->m_pkthdr.len = 1734 slot->mbuf->m_ext.ext_size; 1735 } 1736 1737 error = bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, slot->dmamap, 1738 slot->mbuf, seg, &nsegs, BUS_DMA_NOWAIT); 1739 1740 KASSERT(nsegs == 1, ("More than one segment (nsegs=%d)", nsegs)); 1741 KASSERT(error == 0, ("DMA error (error=%d)", error)); 1742 if (error != 0 || nsegs != 1) { 1743 device_printf(sc->dev, 1744 "%s: Can't prep RX buf for DMA (nsegs=%d, error=%d)\n", 1745 __func__, nsegs, error); 1746 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1747 m_freem(slot->mbuf); 1748 slot->mbuf = NULL; 1749 break; 1750 } 1751 1752 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_PREREAD); 1753 1754 /* Create and submit new rx descriptor. */ 1755 if ((next = STAILQ_NEXT(slot, next)) != NULL) 1756 bd.next = cpsw_cpdma_bd_paddr(sc, next); 1757 else 1758 bd.next = 0; 1759 bd.bufptr = seg->ds_addr; 1760 bd.bufoff = 0; 1761 bd.buflen = MCLBYTES - 1; 1762 bd.pktlen = bd.buflen; 1763 bd.flags = CPDMA_BD_OWNER; 1764 cpsw_cpdma_write_bd(sc, slot, &bd); 1765 ++added; 1766 1767 STAILQ_REMOVE_HEAD(&sc->rx.avail, next); 1768 STAILQ_INSERT_TAIL(&sc->rx.active, slot, next); 1769 } 1770 1771 if (added == 0 || first_new_slot == NULL) 1772 return; 1773 1774 CPSW_DEBUGF(sc, ("Adding %d buffers to RX queue", added)); 1775 1776 /* Link new entries to hardware RX queue. */ 1777 if (last_old_slot == NULL) { 1778 /* Start a fresh queue. */ 1779 cpsw_write_hdp_slot(sc, &sc->rx, first_new_slot); 1780 } else { 1781 /* Add buffers to end of current queue. */ 1782 cpsw_cpdma_write_bd_next(sc, last_old_slot, first_new_slot); 1783 } 1784 sc->rx.queue_adds += added; 1785 sc->rx.avail_queue_len -= added; 1786 sc->rx.active_queue_len += added; 1787 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), added); 1788 if (sc->rx.active_queue_len > sc->rx.max_active_queue_len) 1789 sc->rx.max_active_queue_len = sc->rx.active_queue_len; 1790 } 1791 1792 static void 1793 cpswp_start(struct ifnet *ifp) 1794 { 1795 struct cpswp_softc *sc; 1796 1797 sc = ifp->if_softc; 1798 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1799 sc->swsc->tx.running == 0) { 1800 return; 1801 } 1802 CPSW_TX_LOCK(sc->swsc); 1803 cpswp_tx_enqueue(sc); 1804 cpsw_tx_dequeue(sc->swsc); 1805 CPSW_TX_UNLOCK(sc->swsc); 1806 } 1807 1808 static void 1809 cpsw_intr_tx(void *arg) 1810 { 1811 struct cpsw_softc *sc; 1812 1813 sc = (struct cpsw_softc *)arg; 1814 CPSW_TX_LOCK(sc); 1815 if (cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)) == 0xfffffffc) 1816 cpsw_write_cp(sc, &sc->tx, 0xfffffffc); 1817 cpsw_tx_dequeue(sc); 1818 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 2); 1819 CPSW_TX_UNLOCK(sc); 1820 } 1821 1822 static void 1823 cpswp_tx_enqueue(struct cpswp_softc *sc) 1824 { 1825 bus_dma_segment_t segs[CPSW_TXFRAGS]; 1826 struct cpsw_cpdma_bd bd; 1827 struct cpsw_slot *first_new_slot, *last, *last_old_slot, *next, *slot; 1828 struct mbuf *m0; 1829 int error, nsegs, seg, added = 0, padlen; 1830 1831 /* Pull pending packets from IF queue and prep them for DMA. */ 1832 last = NULL; 1833 first_new_slot = NULL; 1834 last_old_slot = STAILQ_LAST(&sc->swsc->tx.active, cpsw_slot, next); 1835 while ((slot = STAILQ_FIRST(&sc->swsc->tx.avail)) != NULL) { 1836 IF_DEQUEUE(&sc->ifp->if_snd, m0); 1837 if (m0 == NULL) 1838 break; 1839 1840 slot->mbuf = m0; 1841 padlen = ETHER_MIN_LEN - ETHER_CRC_LEN - m0->m_pkthdr.len; 1842 if (padlen < 0) 1843 padlen = 0; 1844 else if (padlen > 0) 1845 m_append(slot->mbuf, padlen, sc->swsc->nullpad); 1846 1847 /* Create mapping in DMA memory */ 1848 error = bus_dmamap_load_mbuf_sg(sc->swsc->mbuf_dtag, 1849 slot->dmamap, slot->mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 1850 /* If the packet is too fragmented, try to simplify. */ 1851 if (error == EFBIG || 1852 (error == 0 && nsegs > sc->swsc->tx.avail_queue_len)) { 1853 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap); 1854 m0 = m_defrag(slot->mbuf, M_NOWAIT); 1855 if (m0 == NULL) { 1856 device_printf(sc->dev, 1857 "Can't defragment packet; dropping\n"); 1858 m_freem(slot->mbuf); 1859 } else { 1860 CPSW_DEBUGF(sc->swsc, 1861 ("Requeueing defragmented packet")); 1862 IF_PREPEND(&sc->ifp->if_snd, m0); 1863 } 1864 slot->mbuf = NULL; 1865 continue; 1866 } 1867 if (error != 0) { 1868 device_printf(sc->dev, 1869 "%s: Can't setup DMA (error=%d), dropping packet\n", 1870 __func__, error); 1871 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap); 1872 m_freem(slot->mbuf); 1873 slot->mbuf = NULL; 1874 break; 1875 } 1876 1877 bus_dmamap_sync(sc->swsc->mbuf_dtag, slot->dmamap, 1878 BUS_DMASYNC_PREWRITE); 1879 1880 CPSW_DEBUGF(sc->swsc, 1881 ("Queueing TX packet: %d segments + %d pad bytes", 1882 nsegs, padlen)); 1883 1884 if (first_new_slot == NULL) 1885 first_new_slot = slot; 1886 1887 /* Link from the previous descriptor. */ 1888 if (last != NULL) 1889 cpsw_cpdma_write_bd_next(sc->swsc, last, slot); 1890 1891 slot->ifp = sc->ifp; 1892 1893 /* If there is only one segment, the for() loop 1894 * gets skipped and the single buffer gets set up 1895 * as both SOP and EOP. */ 1896 if (nsegs > 1) { 1897 next = STAILQ_NEXT(slot, next); 1898 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next); 1899 } else 1900 bd.next = 0; 1901 /* Start by setting up the first buffer. */ 1902 bd.bufptr = segs[0].ds_addr; 1903 bd.bufoff = 0; 1904 bd.buflen = segs[0].ds_len; 1905 bd.pktlen = m_length(slot->mbuf, NULL); 1906 bd.flags = CPDMA_BD_SOP | CPDMA_BD_OWNER; 1907 if (sc->swsc->dualemac) { 1908 bd.flags |= CPDMA_BD_TO_PORT; 1909 bd.flags |= ((sc->unit + 1) & CPDMA_BD_PORT_MASK); 1910 } 1911 for (seg = 1; seg < nsegs; ++seg) { 1912 /* Save the previous buffer (which isn't EOP) */ 1913 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1914 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1915 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next); 1916 slot = STAILQ_FIRST(&sc->swsc->tx.avail); 1917 1918 /* Setup next buffer (which isn't SOP) */ 1919 if (nsegs > seg + 1) { 1920 next = STAILQ_NEXT(slot, next); 1921 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next); 1922 } else 1923 bd.next = 0; 1924 bd.bufptr = segs[seg].ds_addr; 1925 bd.bufoff = 0; 1926 bd.buflen = segs[seg].ds_len; 1927 bd.pktlen = 0; 1928 bd.flags = CPDMA_BD_OWNER; 1929 } 1930 1931 /* Save the final buffer. */ 1932 bd.flags |= CPDMA_BD_EOP; 1933 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1934 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1935 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next); 1936 1937 last = slot; 1938 added += nsegs; 1939 if (nsegs > sc->swsc->tx.longest_chain) 1940 sc->swsc->tx.longest_chain = nsegs; 1941 1942 BPF_MTAP(sc->ifp, m0); 1943 } 1944 1945 if (first_new_slot == NULL) 1946 return; 1947 1948 /* Attach the list of new buffers to the hardware TX queue. */ 1949 if (last_old_slot != NULL && 1950 (cpsw_cpdma_read_bd_flags(sc->swsc, last_old_slot) & 1951 CPDMA_BD_EOQ) == 0) { 1952 /* Add buffers to end of current queue. */ 1953 cpsw_cpdma_write_bd_next(sc->swsc, last_old_slot, 1954 first_new_slot); 1955 } else { 1956 /* Start a fresh queue. */ 1957 cpsw_write_hdp_slot(sc->swsc, &sc->swsc->tx, first_new_slot); 1958 } 1959 sc->swsc->tx.queue_adds += added; 1960 sc->swsc->tx.avail_queue_len -= added; 1961 sc->swsc->tx.active_queue_len += added; 1962 if (sc->swsc->tx.active_queue_len > sc->swsc->tx.max_active_queue_len) { 1963 sc->swsc->tx.max_active_queue_len = sc->swsc->tx.active_queue_len; 1964 } 1965 CPSW_DEBUGF(sc->swsc, ("Queued %d TX packet(s)", added)); 1966 } 1967 1968 static int 1969 cpsw_tx_dequeue(struct cpsw_softc *sc) 1970 { 1971 struct cpsw_slot *slot, *last_removed_slot = NULL; 1972 struct cpsw_cpdma_bd bd; 1973 uint32_t flags, removed = 0; 1974 1975 /* Pull completed buffers off the hardware TX queue. */ 1976 slot = STAILQ_FIRST(&sc->tx.active); 1977 while (slot != NULL) { 1978 flags = cpsw_cpdma_read_bd_flags(sc, slot); 1979 1980 /* TearDown complete is only marked on the SOP for the packet. */ 1981 if ((flags & (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) == 1982 (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) { 1983 sc->tx.teardown = 1; 1984 } 1985 1986 if ((flags & (CPDMA_BD_SOP | CPDMA_BD_OWNER)) == 1987 (CPDMA_BD_SOP | CPDMA_BD_OWNER) && sc->tx.teardown == 0) 1988 break; /* Hardware is still using this packet. */ 1989 1990 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 1991 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1992 m_freem(slot->mbuf); 1993 slot->mbuf = NULL; 1994 1995 if (slot->ifp) { 1996 if (sc->tx.teardown == 0) 1997 if_inc_counter(slot->ifp, IFCOUNTER_OPACKETS, 1); 1998 else 1999 if_inc_counter(slot->ifp, IFCOUNTER_OQDROPS, 1); 2000 } 2001 2002 /* Dequeue any additional buffers used by this packet. */ 2003 while (slot != NULL && slot->mbuf == NULL) { 2004 STAILQ_REMOVE_HEAD(&sc->tx.active, next); 2005 STAILQ_INSERT_TAIL(&sc->tx.avail, slot, next); 2006 ++removed; 2007 last_removed_slot = slot; 2008 slot = STAILQ_FIRST(&sc->tx.active); 2009 } 2010 2011 cpsw_write_cp_slot(sc, &sc->tx, last_removed_slot); 2012 2013 /* Restart the TX queue if necessary. */ 2014 cpsw_cpdma_read_bd(sc, last_removed_slot, &bd); 2015 if (slot != NULL && bd.next != 0 && (bd.flags & 2016 (CPDMA_BD_EOP | CPDMA_BD_OWNER | CPDMA_BD_EOQ)) == 2017 (CPDMA_BD_EOP | CPDMA_BD_EOQ)) { 2018 cpsw_write_hdp_slot(sc, &sc->tx, slot); 2019 sc->tx.queue_restart++; 2020 break; 2021 } 2022 } 2023 2024 if (removed != 0) { 2025 sc->tx.queue_removes += removed; 2026 sc->tx.active_queue_len -= removed; 2027 sc->tx.avail_queue_len += removed; 2028 if (sc->tx.avail_queue_len > sc->tx.max_avail_queue_len) 2029 sc->tx.max_avail_queue_len = sc->tx.avail_queue_len; 2030 CPSW_DEBUGF(sc, ("TX removed %d completed packet(s)", removed)); 2031 } 2032 2033 if (sc->tx.teardown && STAILQ_EMPTY(&sc->tx.active)) { 2034 CPSW_DEBUGF(sc, ("TX teardown is complete")); 2035 sc->tx.teardown = 0; 2036 sc->tx.running = 0; 2037 } 2038 2039 return (removed); 2040 } 2041 2042 /* 2043 * 2044 * Miscellaneous interrupts. 2045 * 2046 */ 2047 2048 static void 2049 cpsw_intr_rx_thresh(void *arg) 2050 { 2051 struct cpsw_softc *sc; 2052 struct ifnet *ifp; 2053 struct mbuf *received, *next; 2054 2055 sc = (struct cpsw_softc *)arg; 2056 CPSW_RX_LOCK(sc); 2057 received = cpsw_rx_dequeue(sc); 2058 cpsw_rx_enqueue(sc); 2059 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 0); 2060 CPSW_RX_UNLOCK(sc); 2061 2062 while (received != NULL) { 2063 next = received->m_nextpkt; 2064 received->m_nextpkt = NULL; 2065 ifp = received->m_pkthdr.rcvif; 2066 (*ifp->if_input)(ifp, received); 2067 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2068 received = next; 2069 } 2070 } 2071 2072 static void 2073 cpsw_intr_misc_host_error(struct cpsw_softc *sc) 2074 { 2075 uint32_t intstat; 2076 uint32_t dmastat; 2077 int txerr, rxerr, txchan, rxchan; 2078 2079 printf("\n\n"); 2080 device_printf(sc->dev, 2081 "HOST ERROR: PROGRAMMING ERROR DETECTED BY HARDWARE\n"); 2082 printf("\n\n"); 2083 intstat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 2084 device_printf(sc->dev, "CPSW_CPDMA_DMA_INTSTAT_MASKED=0x%x\n", intstat); 2085 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS); 2086 device_printf(sc->dev, "CPSW_CPDMA_DMASTATUS=0x%x\n", dmastat); 2087 2088 txerr = (dmastat >> 20) & 15; 2089 txchan = (dmastat >> 16) & 7; 2090 rxerr = (dmastat >> 12) & 15; 2091 rxchan = (dmastat >> 8) & 7; 2092 2093 switch (txerr) { 2094 case 0: break; 2095 case 1: printf("SOP error on TX channel %d\n", txchan); 2096 break; 2097 case 2: printf("Ownership bit not set on SOP buffer on TX channel %d\n", txchan); 2098 break; 2099 case 3: printf("Zero Next Buffer but not EOP on TX channel %d\n", txchan); 2100 break; 2101 case 4: printf("Zero Buffer Pointer on TX channel %d\n", txchan); 2102 break; 2103 case 5: printf("Zero Buffer Length on TX channel %d\n", txchan); 2104 break; 2105 case 6: printf("Packet length error on TX channel %d\n", txchan); 2106 break; 2107 default: printf("Unknown error on TX channel %d\n", txchan); 2108 break; 2109 } 2110 2111 if (txerr != 0) { 2112 printf("CPSW_CPDMA_TX%d_HDP=0x%x\n", 2113 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(txchan))); 2114 printf("CPSW_CPDMA_TX%d_CP=0x%x\n", 2115 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_CP(txchan))); 2116 cpsw_dump_queue(sc, &sc->tx.active); 2117 } 2118 2119 switch (rxerr) { 2120 case 0: break; 2121 case 2: printf("Ownership bit not set on RX channel %d\n", rxchan); 2122 break; 2123 case 4: printf("Zero Buffer Pointer on RX channel %d\n", rxchan); 2124 break; 2125 case 5: printf("Zero Buffer Length on RX channel %d\n", rxchan); 2126 break; 2127 case 6: printf("Buffer offset too big on RX channel %d\n", rxchan); 2128 break; 2129 default: printf("Unknown RX error on RX channel %d\n", rxchan); 2130 break; 2131 } 2132 2133 if (rxerr != 0) { 2134 printf("CPSW_CPDMA_RX%d_HDP=0x%x\n", 2135 rxchan, cpsw_read_4(sc,CPSW_CPDMA_RX_HDP(rxchan))); 2136 printf("CPSW_CPDMA_RX%d_CP=0x%x\n", 2137 rxchan, cpsw_read_4(sc, CPSW_CPDMA_RX_CP(rxchan))); 2138 cpsw_dump_queue(sc, &sc->rx.active); 2139 } 2140 2141 printf("\nALE Table\n"); 2142 cpsw_ale_dump_table(sc); 2143 2144 // XXX do something useful here?? 2145 panic("CPSW HOST ERROR INTERRUPT"); 2146 2147 // Suppress this interrupt in the future. 2148 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, intstat); 2149 printf("XXX HOST ERROR INTERRUPT SUPPRESSED\n"); 2150 // The watchdog will probably reset the controller 2151 // in a little while. It will probably fail again. 2152 } 2153 2154 static void 2155 cpsw_intr_misc(void *arg) 2156 { 2157 struct cpsw_softc *sc = arg; 2158 uint32_t stat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0)); 2159 2160 if (stat & CPSW_WR_C_MISC_EVNT_PEND) 2161 CPSW_DEBUGF(sc, ("Time sync event interrupt unimplemented")); 2162 if (stat & CPSW_WR_C_MISC_STAT_PEND) 2163 cpsw_stats_collect(sc); 2164 if (stat & CPSW_WR_C_MISC_HOST_PEND) 2165 cpsw_intr_misc_host_error(sc); 2166 if (stat & CPSW_WR_C_MISC_MDIOLINK) { 2167 cpsw_write_4(sc, MDIOLINKINTMASKED, 2168 cpsw_read_4(sc, MDIOLINKINTMASKED)); 2169 } 2170 if (stat & CPSW_WR_C_MISC_MDIOUSER) { 2171 CPSW_DEBUGF(sc, 2172 ("MDIO operation completed interrupt unimplemented")); 2173 } 2174 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 3); 2175 } 2176 2177 /* 2178 * 2179 * Periodic Checks and Watchdog. 2180 * 2181 */ 2182 2183 static void 2184 cpswp_tick(void *msc) 2185 { 2186 struct cpswp_softc *sc = msc; 2187 2188 /* Check for media type change */ 2189 mii_tick(sc->mii); 2190 if (sc->media_status != sc->mii->mii_media.ifm_media) { 2191 printf("%s: media type changed (ifm_media=%x)\n", __func__, 2192 sc->mii->mii_media.ifm_media); 2193 cpswp_ifmedia_upd(sc->ifp); 2194 } 2195 2196 /* Schedule another timeout one second from now */ 2197 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc); 2198 } 2199 2200 static void 2201 cpswp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2202 { 2203 struct cpswp_softc *sc; 2204 struct mii_data *mii; 2205 2206 sc = ifp->if_softc; 2207 CPSW_DEBUGF(sc->swsc, ("")); 2208 CPSW_PORT_LOCK(sc); 2209 2210 mii = sc->mii; 2211 mii_pollstat(mii); 2212 2213 ifmr->ifm_active = mii->mii_media_active; 2214 ifmr->ifm_status = mii->mii_media_status; 2215 CPSW_PORT_UNLOCK(sc); 2216 } 2217 2218 static int 2219 cpswp_ifmedia_upd(struct ifnet *ifp) 2220 { 2221 struct cpswp_softc *sc; 2222 2223 sc = ifp->if_softc; 2224 CPSW_DEBUGF(sc->swsc, ("")); 2225 CPSW_PORT_LOCK(sc); 2226 mii_mediachg(sc->mii); 2227 sc->media_status = sc->mii->mii_media.ifm_media; 2228 CPSW_PORT_UNLOCK(sc); 2229 2230 return (0); 2231 } 2232 2233 static void 2234 cpsw_tx_watchdog_full_reset(struct cpsw_softc *sc) 2235 { 2236 struct cpswp_softc *psc; 2237 int i; 2238 2239 cpsw_debugf_head("CPSW watchdog"); 2240 device_printf(sc->dev, "watchdog timeout\n"); 2241 printf("CPSW_CPDMA_TX%d_HDP=0x%x\n", 0, 2242 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0))); 2243 printf("CPSW_CPDMA_TX%d_CP=0x%x\n", 0, 2244 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0))); 2245 cpsw_dump_queue(sc, &sc->tx.active); 2246 for (i = 0; i < CPSW_PORTS; i++) { 2247 if (!sc->dualemac && i != sc->active_slave) 2248 continue; 2249 psc = device_get_softc(sc->port[i].dev); 2250 CPSW_PORT_LOCK(psc); 2251 cpswp_stop_locked(psc); 2252 CPSW_PORT_UNLOCK(psc); 2253 } 2254 } 2255 2256 static void 2257 cpsw_tx_watchdog(void *msc) 2258 { 2259 struct cpsw_softc *sc; 2260 2261 sc = msc; 2262 CPSW_TX_LOCK(sc); 2263 if (sc->tx.active_queue_len == 0 || !sc->tx.running) { 2264 sc->watchdog.timer = 0; /* Nothing to do. */ 2265 } else if (sc->tx.queue_removes > sc->tx.queue_removes_at_last_tick) { 2266 sc->watchdog.timer = 0; /* Stuff done while we weren't looking. */ 2267 } else if (cpsw_tx_dequeue(sc) > 0) { 2268 sc->watchdog.timer = 0; /* We just did something. */ 2269 } else { 2270 /* There was something to do but it didn't get done. */ 2271 ++sc->watchdog.timer; 2272 if (sc->watchdog.timer > 5) { 2273 sc->watchdog.timer = 0; 2274 ++sc->watchdog.resets; 2275 cpsw_tx_watchdog_full_reset(sc); 2276 } 2277 } 2278 sc->tx.queue_removes_at_last_tick = sc->tx.queue_removes; 2279 CPSW_TX_UNLOCK(sc); 2280 2281 /* Schedule another timeout one second from now */ 2282 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc); 2283 } 2284 2285 /* 2286 * 2287 * ALE support routines. 2288 * 2289 */ 2290 2291 static void 2292 cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 2293 { 2294 cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023); 2295 ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0); 2296 ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1); 2297 ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2); 2298 } 2299 2300 static void 2301 cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 2302 { 2303 cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]); 2304 cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]); 2305 cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]); 2306 cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023)); 2307 } 2308 2309 static void 2310 cpsw_ale_remove_all_mc_entries(struct cpsw_softc *sc) 2311 { 2312 int i; 2313 uint32_t ale_entry[3]; 2314 2315 /* First four entries are link address and broadcast. */ 2316 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) { 2317 cpsw_ale_read_entry(sc, i, ale_entry); 2318 if ((ALE_TYPE(ale_entry) == ALE_TYPE_ADDR || 2319 ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) && 2320 ALE_MCAST(ale_entry) == 1) { /* MCast link addr */ 2321 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 2322 cpsw_ale_write_entry(sc, i, ale_entry); 2323 } 2324 } 2325 } 2326 2327 static int 2328 cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmap, int vlan, 2329 uint8_t *mac) 2330 { 2331 int free_index = -1, matching_index = -1, i; 2332 uint32_t ale_entry[3], ale_type; 2333 2334 /* Find a matching entry or a free entry. */ 2335 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) { 2336 cpsw_ale_read_entry(sc, i, ale_entry); 2337 2338 /* Entry Type[61:60] is 0 for free entry */ 2339 if (free_index < 0 && ALE_TYPE(ale_entry) == 0) 2340 free_index = i; 2341 2342 if ((((ale_entry[1] >> 8) & 0xFF) == mac[0]) && 2343 (((ale_entry[1] >> 0) & 0xFF) == mac[1]) && 2344 (((ale_entry[0] >>24) & 0xFF) == mac[2]) && 2345 (((ale_entry[0] >>16) & 0xFF) == mac[3]) && 2346 (((ale_entry[0] >> 8) & 0xFF) == mac[4]) && 2347 (((ale_entry[0] >> 0) & 0xFF) == mac[5])) { 2348 matching_index = i; 2349 break; 2350 } 2351 } 2352 2353 if (matching_index < 0) { 2354 if (free_index < 0) 2355 return (ENOMEM); 2356 i = free_index; 2357 } 2358 2359 if (vlan != -1) 2360 ale_type = ALE_TYPE_VLAN_ADDR << 28 | vlan << 16; 2361 else 2362 ale_type = ALE_TYPE_ADDR << 28; 2363 2364 /* Set MAC address */ 2365 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 2366 ale_entry[1] = mac[0] << 8 | mac[1]; 2367 2368 /* Entry type[61:60] and Mcast fwd state[63:62] is fw(3). */ 2369 ale_entry[1] |= ALE_MCAST_FWD | ale_type; 2370 2371 /* Set portmask [68:66] */ 2372 ale_entry[2] = (portmap & 7) << 2; 2373 2374 cpsw_ale_write_entry(sc, i, ale_entry); 2375 2376 return 0; 2377 } 2378 2379 static void 2380 cpsw_ale_dump_table(struct cpsw_softc *sc) { 2381 int i; 2382 uint32_t ale_entry[3]; 2383 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2384 cpsw_ale_read_entry(sc, i, ale_entry); 2385 switch (ALE_TYPE(ale_entry)) { 2386 case ALE_TYPE_VLAN: 2387 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2], 2388 ale_entry[1], ale_entry[0]); 2389 printf("type: %u ", ALE_TYPE(ale_entry)); 2390 printf("vlan: %u ", ALE_VLAN(ale_entry)); 2391 printf("untag: %u ", ALE_VLAN_UNTAG(ale_entry)); 2392 printf("reg flood: %u ", ALE_VLAN_REGFLOOD(ale_entry)); 2393 printf("unreg flood: %u ", ALE_VLAN_UNREGFLOOD(ale_entry)); 2394 printf("members: %u ", ALE_VLAN_MEMBERS(ale_entry)); 2395 printf("\n"); 2396 break; 2397 case ALE_TYPE_ADDR: 2398 case ALE_TYPE_VLAN_ADDR: 2399 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2], 2400 ale_entry[1], ale_entry[0]); 2401 printf("type: %u ", ALE_TYPE(ale_entry)); 2402 printf("mac: %02x:%02x:%02x:%02x:%02x:%02x ", 2403 (ale_entry[1] >> 8) & 0xFF, 2404 (ale_entry[1] >> 0) & 0xFF, 2405 (ale_entry[0] >>24) & 0xFF, 2406 (ale_entry[0] >>16) & 0xFF, 2407 (ale_entry[0] >> 8) & 0xFF, 2408 (ale_entry[0] >> 0) & 0xFF); 2409 printf(ALE_MCAST(ale_entry) ? "mcast " : "ucast "); 2410 if (ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) 2411 printf("vlan: %u ", ALE_VLAN(ale_entry)); 2412 printf("port: %u ", ALE_PORTS(ale_entry)); 2413 printf("\n"); 2414 break; 2415 } 2416 } 2417 printf("\n"); 2418 } 2419 2420 static int 2421 cpswp_ale_update_addresses(struct cpswp_softc *sc, int purge) 2422 { 2423 uint8_t *mac; 2424 uint32_t ale_entry[3], ale_type, portmask; 2425 struct ifmultiaddr *ifma; 2426 2427 if (sc->swsc->dualemac) { 2428 ale_type = ALE_TYPE_VLAN_ADDR << 28 | sc->vlan << 16; 2429 portmask = 1 << (sc->unit + 1) | 1 << 0; 2430 } else { 2431 ale_type = ALE_TYPE_ADDR << 28; 2432 portmask = 7; 2433 } 2434 2435 /* 2436 * Route incoming packets for our MAC address to Port 0 (host). 2437 * For simplicity, keep this entry at table index 0 for port 1 and 2438 * at index 2 for port 2 in the ALE. 2439 */ 2440 if_addr_rlock(sc->ifp); 2441 mac = LLADDR((struct sockaddr_dl *)sc->ifp->if_addr->ifa_addr); 2442 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 2443 ale_entry[1] = ale_type | mac[0] << 8 | mac[1]; /* addr entry + mac */ 2444 ale_entry[2] = 0; /* port = 0 */ 2445 cpsw_ale_write_entry(sc->swsc, 0 + 2 * sc->unit, ale_entry); 2446 2447 /* Set outgoing MAC Address for slave port. */ 2448 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_HI(sc->unit + 1), 2449 mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]); 2450 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_LO(sc->unit + 1), 2451 mac[5] << 8 | mac[4]); 2452 if_addr_runlock(sc->ifp); 2453 2454 /* Keep the broadcast address at table entry 1 (or 3). */ 2455 ale_entry[0] = 0xffffffff; /* Lower 32 bits of MAC */ 2456 /* ALE_MCAST_FWD, Addr type, upper 16 bits of Mac */ 2457 ale_entry[1] = ALE_MCAST_FWD | ale_type | 0xffff; 2458 ale_entry[2] = portmask << 2; 2459 cpsw_ale_write_entry(sc->swsc, 1 + 2 * sc->unit, ale_entry); 2460 2461 /* SIOCDELMULTI doesn't specify the particular address 2462 being removed, so we have to remove all and rebuild. */ 2463 if (purge) 2464 cpsw_ale_remove_all_mc_entries(sc->swsc); 2465 2466 /* Set other multicast addrs desired. */ 2467 if_maddr_rlock(sc->ifp); 2468 CK_STAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 2469 if (ifma->ifma_addr->sa_family != AF_LINK) 2470 continue; 2471 cpsw_ale_mc_entry_set(sc->swsc, portmask, sc->vlan, 2472 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 2473 } 2474 if_maddr_runlock(sc->ifp); 2475 2476 return (0); 2477 } 2478 2479 static int 2480 cpsw_ale_update_vlan_table(struct cpsw_softc *sc, int vlan, int ports, 2481 int untag, int mcregflood, int mcunregflood) 2482 { 2483 int free_index, i, matching_index; 2484 uint32_t ale_entry[3]; 2485 2486 free_index = matching_index = -1; 2487 /* Find a matching entry or a free entry. */ 2488 for (i = 5; i < CPSW_MAX_ALE_ENTRIES; i++) { 2489 cpsw_ale_read_entry(sc, i, ale_entry); 2490 2491 /* Entry Type[61:60] is 0 for free entry */ 2492 if (free_index < 0 && ALE_TYPE(ale_entry) == 0) 2493 free_index = i; 2494 2495 if (ALE_VLAN(ale_entry) == vlan) { 2496 matching_index = i; 2497 break; 2498 } 2499 } 2500 2501 if (matching_index < 0) { 2502 if (free_index < 0) 2503 return (-1); 2504 i = free_index; 2505 } 2506 2507 ale_entry[0] = (untag & 7) << 24 | (mcregflood & 7) << 16 | 2508 (mcunregflood & 7) << 8 | (ports & 7); 2509 ale_entry[1] = ALE_TYPE_VLAN << 28 | vlan << 16; 2510 ale_entry[2] = 0; 2511 cpsw_ale_write_entry(sc, i, ale_entry); 2512 2513 return (0); 2514 } 2515 2516 /* 2517 * 2518 * Statistics and Sysctls. 2519 * 2520 */ 2521 2522 #if 0 2523 static void 2524 cpsw_stats_dump(struct cpsw_softc *sc) 2525 { 2526 int i; 2527 uint32_t r; 2528 2529 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2530 r = cpsw_read_4(sc, CPSW_STATS_OFFSET + 2531 cpsw_stat_sysctls[i].reg); 2532 CPSW_DEBUGF(sc, ("%s: %ju + %u = %ju", cpsw_stat_sysctls[i].oid, 2533 (intmax_t)sc->shadow_stats[i], r, 2534 (intmax_t)sc->shadow_stats[i] + r)); 2535 } 2536 } 2537 #endif 2538 2539 static void 2540 cpsw_stats_collect(struct cpsw_softc *sc) 2541 { 2542 int i; 2543 uint32_t r; 2544 2545 CPSW_DEBUGF(sc, ("Controller shadow statistics updated.")); 2546 2547 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2548 r = cpsw_read_4(sc, CPSW_STATS_OFFSET + 2549 cpsw_stat_sysctls[i].reg); 2550 sc->shadow_stats[i] += r; 2551 cpsw_write_4(sc, CPSW_STATS_OFFSET + cpsw_stat_sysctls[i].reg, 2552 r); 2553 } 2554 } 2555 2556 static int 2557 cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS) 2558 { 2559 struct cpsw_softc *sc; 2560 struct cpsw_stat *stat; 2561 uint64_t result; 2562 2563 sc = (struct cpsw_softc *)arg1; 2564 stat = &cpsw_stat_sysctls[oidp->oid_number]; 2565 result = sc->shadow_stats[oidp->oid_number]; 2566 result += cpsw_read_4(sc, CPSW_STATS_OFFSET + stat->reg); 2567 return (sysctl_handle_64(oidp, &result, 0, req)); 2568 } 2569 2570 static int 2571 cpsw_stat_attached(SYSCTL_HANDLER_ARGS) 2572 { 2573 struct cpsw_softc *sc; 2574 struct bintime t; 2575 unsigned result; 2576 2577 sc = (struct cpsw_softc *)arg1; 2578 getbinuptime(&t); 2579 bintime_sub(&t, &sc->attach_uptime); 2580 result = t.sec; 2581 return (sysctl_handle_int(oidp, &result, 0, req)); 2582 } 2583 2584 static int 2585 cpsw_intr_coalesce(SYSCTL_HANDLER_ARGS) 2586 { 2587 int error; 2588 struct cpsw_softc *sc; 2589 uint32_t ctrl, intr_per_ms; 2590 2591 sc = (struct cpsw_softc *)arg1; 2592 error = sysctl_handle_int(oidp, &sc->coal_us, 0, req); 2593 if (error != 0 || req->newptr == NULL) 2594 return (error); 2595 2596 ctrl = cpsw_read_4(sc, CPSW_WR_INT_CONTROL); 2597 ctrl &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK); 2598 if (sc->coal_us == 0) { 2599 /* Disable the interrupt pace hardware. */ 2600 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl); 2601 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), 0); 2602 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), 0); 2603 return (0); 2604 } 2605 2606 if (sc->coal_us > CPSW_WR_C_IMAX_US_MAX) 2607 sc->coal_us = CPSW_WR_C_IMAX_US_MAX; 2608 if (sc->coal_us < CPSW_WR_C_IMAX_US_MIN) 2609 sc->coal_us = CPSW_WR_C_IMAX_US_MIN; 2610 intr_per_ms = 1000 / sc->coal_us; 2611 /* Just to make sure... */ 2612 if (intr_per_ms > CPSW_WR_C_IMAX_MAX) 2613 intr_per_ms = CPSW_WR_C_IMAX_MAX; 2614 if (intr_per_ms < CPSW_WR_C_IMAX_MIN) 2615 intr_per_ms = CPSW_WR_C_IMAX_MIN; 2616 2617 /* Set the prescale to produce 4us pulses from the 125 Mhz clock. */ 2618 ctrl |= (125 * 4) & CPSW_WR_INT_PRESCALE_MASK; 2619 2620 /* Enable the interrupt pace hardware. */ 2621 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), intr_per_ms); 2622 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), intr_per_ms); 2623 ctrl |= CPSW_WR_INT_C0_RX_PULSE | CPSW_WR_INT_C0_TX_PULSE; 2624 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl); 2625 2626 return (0); 2627 } 2628 2629 static int 2630 cpsw_stat_uptime(SYSCTL_HANDLER_ARGS) 2631 { 2632 struct cpsw_softc *swsc; 2633 struct cpswp_softc *sc; 2634 struct bintime t; 2635 unsigned result; 2636 2637 swsc = arg1; 2638 sc = device_get_softc(swsc->port[arg2].dev); 2639 if (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) { 2640 getbinuptime(&t); 2641 bintime_sub(&t, &sc->init_uptime); 2642 result = t.sec; 2643 } else 2644 result = 0; 2645 return (sysctl_handle_int(oidp, &result, 0, req)); 2646 } 2647 2648 static void 2649 cpsw_add_queue_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node, 2650 struct cpsw_queue *queue) 2651 { 2652 struct sysctl_oid_list *parent; 2653 2654 parent = SYSCTL_CHILDREN(node); 2655 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "totalBuffers", 2656 CTLFLAG_RD, &queue->queue_slots, 0, 2657 "Total buffers currently assigned to this queue"); 2658 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "activeBuffers", 2659 CTLFLAG_RD, &queue->active_queue_len, 0, 2660 "Buffers currently registered with hardware controller"); 2661 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxActiveBuffers", 2662 CTLFLAG_RD, &queue->max_active_queue_len, 0, 2663 "Max value of activeBuffers since last driver reset"); 2664 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "availBuffers", 2665 CTLFLAG_RD, &queue->avail_queue_len, 0, 2666 "Buffers allocated to this queue but not currently " 2667 "registered with hardware controller"); 2668 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxAvailBuffers", 2669 CTLFLAG_RD, &queue->max_avail_queue_len, 0, 2670 "Max value of availBuffers since last driver reset"); 2671 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalEnqueued", 2672 CTLFLAG_RD, &queue->queue_adds, 0, 2673 "Total buffers added to queue"); 2674 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalDequeued", 2675 CTLFLAG_RD, &queue->queue_removes, 0, 2676 "Total buffers removed from queue"); 2677 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "queueRestart", 2678 CTLFLAG_RD, &queue->queue_restart, 0, 2679 "Total times the queue has been restarted"); 2680 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "longestChain", 2681 CTLFLAG_RD, &queue->longest_chain, 0, 2682 "Max buffers used for a single packet"); 2683 } 2684 2685 static void 2686 cpsw_add_watchdog_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node, 2687 struct cpsw_softc *sc) 2688 { 2689 struct sysctl_oid_list *parent; 2690 2691 parent = SYSCTL_CHILDREN(node); 2692 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "resets", 2693 CTLFLAG_RD, &sc->watchdog.resets, 0, 2694 "Total number of watchdog resets"); 2695 } 2696 2697 static void 2698 cpsw_add_sysctls(struct cpsw_softc *sc) 2699 { 2700 struct sysctl_ctx_list *ctx; 2701 struct sysctl_oid *stats_node, *queue_node, *node; 2702 struct sysctl_oid_list *parent, *stats_parent, *queue_parent; 2703 struct sysctl_oid_list *ports_parent, *port_parent; 2704 char port[16]; 2705 int i; 2706 2707 ctx = device_get_sysctl_ctx(sc->dev); 2708 parent = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2709 2710 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "debug", 2711 CTLFLAG_RW, &sc->debug, 0, "Enable switch debug messages"); 2712 2713 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "attachedSecs", 2714 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, cpsw_stat_attached, "IU", 2715 "Time since driver attach"); 2716 2717 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "intr_coalesce_us", 2718 CTLTYPE_UINT | CTLFLAG_RW, sc, 0, cpsw_intr_coalesce, "IU", 2719 "minimum time between interrupts"); 2720 2721 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "ports", 2722 CTLFLAG_RD, NULL, "CPSW Ports Statistics"); 2723 ports_parent = SYSCTL_CHILDREN(node); 2724 for (i = 0; i < CPSW_PORTS; i++) { 2725 if (!sc->dualemac && i != sc->active_slave) 2726 continue; 2727 port[0] = '0' + i; 2728 port[1] = '\0'; 2729 node = SYSCTL_ADD_NODE(ctx, ports_parent, OID_AUTO, 2730 port, CTLFLAG_RD, NULL, "CPSW Port Statistics"); 2731 port_parent = SYSCTL_CHILDREN(node); 2732 SYSCTL_ADD_PROC(ctx, port_parent, OID_AUTO, "uptime", 2733 CTLTYPE_UINT | CTLFLAG_RD, sc, i, 2734 cpsw_stat_uptime, "IU", "Seconds since driver init"); 2735 } 2736 2737 stats_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", 2738 CTLFLAG_RD, NULL, "CPSW Statistics"); 2739 stats_parent = SYSCTL_CHILDREN(stats_node); 2740 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2741 SYSCTL_ADD_PROC(ctx, stats_parent, i, 2742 cpsw_stat_sysctls[i].oid, 2743 CTLTYPE_U64 | CTLFLAG_RD, sc, 0, 2744 cpsw_stats_sysctl, "IU", 2745 cpsw_stat_sysctls[i].oid); 2746 } 2747 2748 queue_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "queue", 2749 CTLFLAG_RD, NULL, "CPSW Queue Statistics"); 2750 queue_parent = SYSCTL_CHILDREN(queue_node); 2751 2752 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "tx", 2753 CTLFLAG_RD, NULL, "TX Queue Statistics"); 2754 cpsw_add_queue_sysctls(ctx, node, &sc->tx); 2755 2756 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "rx", 2757 CTLFLAG_RD, NULL, "RX Queue Statistics"); 2758 cpsw_add_queue_sysctls(ctx, node, &sc->rx); 2759 2760 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "watchdog", 2761 CTLFLAG_RD, NULL, "Watchdog Statistics"); 2762 cpsw_add_watchdog_sysctls(ctx, node, sc); 2763 } 2764 2765 #ifdef CPSW_ETHERSWITCH 2766 static etherswitch_info_t etherswitch_info = { 2767 .es_nports = CPSW_PORTS + 1, 2768 .es_nvlangroups = CPSW_VLANS, 2769 .es_name = "TI Common Platform Ethernet Switch (CPSW)", 2770 .es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q, 2771 }; 2772 2773 static etherswitch_info_t * 2774 cpsw_getinfo(device_t dev) 2775 { 2776 return (ðerswitch_info); 2777 } 2778 2779 static int 2780 cpsw_getport(device_t dev, etherswitch_port_t *p) 2781 { 2782 int err; 2783 struct cpsw_softc *sc; 2784 struct cpswp_softc *psc; 2785 struct ifmediareq *ifmr; 2786 uint32_t reg; 2787 2788 if (p->es_port < 0 || p->es_port > CPSW_PORTS) 2789 return (ENXIO); 2790 2791 err = 0; 2792 sc = device_get_softc(dev); 2793 if (p->es_port == CPSW_CPU_PORT) { 2794 p->es_flags |= ETHERSWITCH_PORT_CPU; 2795 ifmr = &p->es_ifmr; 2796 ifmr->ifm_current = ifmr->ifm_active = 2797 IFM_ETHER | IFM_1000_T | IFM_FDX; 2798 ifmr->ifm_mask = 0; 2799 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 2800 ifmr->ifm_count = 0; 2801 } else { 2802 psc = device_get_softc(sc->port[p->es_port - 1].dev); 2803 err = ifmedia_ioctl(psc->ifp, &p->es_ifr, 2804 &psc->mii->mii_media, SIOCGIFMEDIA); 2805 } 2806 reg = cpsw_read_4(sc, CPSW_PORT_P_VLAN(p->es_port)); 2807 p->es_pvid = reg & ETHERSWITCH_VID_MASK; 2808 2809 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port)); 2810 if (reg & ALE_PORTCTL_DROP_UNTAGGED) 2811 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED; 2812 if (reg & ALE_PORTCTL_INGRESS) 2813 p->es_flags |= ETHERSWITCH_PORT_INGRESS; 2814 2815 return (err); 2816 } 2817 2818 static int 2819 cpsw_setport(device_t dev, etherswitch_port_t *p) 2820 { 2821 struct cpsw_softc *sc; 2822 struct cpswp_softc *psc; 2823 struct ifmedia *ifm; 2824 uint32_t reg; 2825 2826 if (p->es_port < 0 || p->es_port > CPSW_PORTS) 2827 return (ENXIO); 2828 2829 sc = device_get_softc(dev); 2830 if (p->es_pvid != 0) { 2831 cpsw_write_4(sc, CPSW_PORT_P_VLAN(p->es_port), 2832 p->es_pvid & ETHERSWITCH_VID_MASK); 2833 } 2834 2835 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port)); 2836 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED) 2837 reg |= ALE_PORTCTL_DROP_UNTAGGED; 2838 else 2839 reg &= ~ALE_PORTCTL_DROP_UNTAGGED; 2840 if (p->es_flags & ETHERSWITCH_PORT_INGRESS) 2841 reg |= ALE_PORTCTL_INGRESS; 2842 else 2843 reg &= ~ALE_PORTCTL_INGRESS; 2844 cpsw_write_4(sc, CPSW_ALE_PORTCTL(p->es_port), reg); 2845 2846 /* CPU port does not allow media settings. */ 2847 if (p->es_port == CPSW_CPU_PORT) 2848 return (0); 2849 2850 psc = device_get_softc(sc->port[p->es_port - 1].dev); 2851 ifm = &psc->mii->mii_media; 2852 2853 return (ifmedia_ioctl(psc->ifp, &p->es_ifr, ifm, SIOCSIFMEDIA)); 2854 } 2855 2856 static int 2857 cpsw_getconf(device_t dev, etherswitch_conf_t *conf) 2858 { 2859 2860 /* Return the VLAN mode. */ 2861 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 2862 conf->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 2863 2864 return (0); 2865 } 2866 2867 static int 2868 cpsw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 2869 { 2870 int i, vid; 2871 uint32_t ale_entry[3]; 2872 struct cpsw_softc *sc; 2873 2874 sc = device_get_softc(dev); 2875 2876 if (vg->es_vlangroup >= CPSW_VLANS) 2877 return (EINVAL); 2878 2879 vg->es_vid = 0; 2880 vid = cpsw_vgroups[vg->es_vlangroup].vid; 2881 if (vid == -1) 2882 return (0); 2883 2884 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2885 cpsw_ale_read_entry(sc, i, ale_entry); 2886 if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN) 2887 continue; 2888 if (vid != ALE_VLAN(ale_entry)) 2889 continue; 2890 2891 vg->es_fid = 0; 2892 vg->es_vid = ALE_VLAN(ale_entry) | ETHERSWITCH_VID_VALID; 2893 vg->es_member_ports = ALE_VLAN_MEMBERS(ale_entry); 2894 vg->es_untagged_ports = ALE_VLAN_UNTAG(ale_entry); 2895 } 2896 2897 return (0); 2898 } 2899 2900 static void 2901 cpsw_remove_vlan(struct cpsw_softc *sc, int vlan) 2902 { 2903 int i; 2904 uint32_t ale_entry[3]; 2905 2906 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2907 cpsw_ale_read_entry(sc, i, ale_entry); 2908 if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN) 2909 continue; 2910 if (vlan != ALE_VLAN(ale_entry)) 2911 continue; 2912 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 2913 cpsw_ale_write_entry(sc, i, ale_entry); 2914 break; 2915 } 2916 } 2917 2918 static int 2919 cpsw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 2920 { 2921 int i; 2922 struct cpsw_softc *sc; 2923 2924 sc = device_get_softc(dev); 2925 2926 for (i = 0; i < CPSW_VLANS; i++) { 2927 /* Is this Vlan ID in use by another vlangroup ? */ 2928 if (vg->es_vlangroup != i && cpsw_vgroups[i].vid == vg->es_vid) 2929 return (EINVAL); 2930 } 2931 2932 if (vg->es_vid == 0) { 2933 if (cpsw_vgroups[vg->es_vlangroup].vid == -1) 2934 return (0); 2935 cpsw_remove_vlan(sc, cpsw_vgroups[vg->es_vlangroup].vid); 2936 cpsw_vgroups[vg->es_vlangroup].vid = -1; 2937 vg->es_untagged_ports = 0; 2938 vg->es_member_ports = 0; 2939 vg->es_vid = 0; 2940 return (0); 2941 } 2942 2943 vg->es_vid &= ETHERSWITCH_VID_MASK; 2944 vg->es_member_ports &= CPSW_PORTS_MASK; 2945 vg->es_untagged_ports &= CPSW_PORTS_MASK; 2946 2947 if (cpsw_vgroups[vg->es_vlangroup].vid != -1 && 2948 cpsw_vgroups[vg->es_vlangroup].vid != vg->es_vid) 2949 return (EINVAL); 2950 2951 cpsw_vgroups[vg->es_vlangroup].vid = vg->es_vid; 2952 cpsw_ale_update_vlan_table(sc, vg->es_vid, vg->es_member_ports, 2953 vg->es_untagged_ports, vg->es_member_ports, 0); 2954 2955 return (0); 2956 } 2957 2958 static int 2959 cpsw_readreg(device_t dev, int addr) 2960 { 2961 2962 /* Not supported. */ 2963 return (0); 2964 } 2965 2966 static int 2967 cpsw_writereg(device_t dev, int addr, int value) 2968 { 2969 2970 /* Not supported. */ 2971 return (0); 2972 } 2973 2974 static int 2975 cpsw_readphy(device_t dev, int phy, int reg) 2976 { 2977 2978 /* Not supported. */ 2979 return (0); 2980 } 2981 2982 static int 2983 cpsw_writephy(device_t dev, int phy, int reg, int data) 2984 { 2985 2986 /* Not supported. */ 2987 return (0); 2988 } 2989 #endif 2990