1 /*- 2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /** 29 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code 30 * here uses 0-5. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 #include <sys/lock.h> 44 #include <sys/mutex.h> 45 #include <sys/gpio.h> 46 #include <sys/interrupt.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 51 #include <arm/ti/ti_cpuid.h> 52 #include <arm/ti/ti_gpio.h> 53 #include <arm/ti/ti_scm.h> 54 #include <arm/ti/ti_prcm.h> 55 56 #include <dev/fdt/fdt_common.h> 57 #include <dev/gpio/gpiobusvar.h> 58 #include <dev/ofw/openfirm.h> 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 62 #include "gpio_if.h" 63 #include "ti_gpio_if.h" 64 65 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X) 66 #error "Unknown SoC" 67 #endif 68 69 /* Register definitions */ 70 #define TI_GPIO_REVISION 0x0000 71 #define TI_GPIO_SYSCONFIG 0x0010 72 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024 73 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028 74 #define TI_GPIO_IRQSTATUS_0 0x002C 75 #define TI_GPIO_IRQSTATUS_1 0x0030 76 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 77 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 78 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C 79 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 80 #define TI_GPIO_IRQWAKEN_0 0x0044 81 #define TI_GPIO_IRQWAKEN_1 0x0048 82 #define TI_GPIO_SYSSTATUS 0x0114 83 #define TI_GPIO_IRQSTATUS1 0x0118 84 #define TI_GPIO_IRQENABLE1 0x011C 85 #define TI_GPIO_WAKEUPENABLE 0x0120 86 #define TI_GPIO_IRQSTATUS2 0x0128 87 #define TI_GPIO_IRQENABLE2 0x012C 88 #define TI_GPIO_CTRL 0x0130 89 #define TI_GPIO_OE 0x0134 90 #define TI_GPIO_DATAIN 0x0138 91 #define TI_GPIO_DATAOUT 0x013C 92 #define TI_GPIO_LEVELDETECT0 0x0140 93 #define TI_GPIO_LEVELDETECT1 0x0144 94 #define TI_GPIO_RISINGDETECT 0x0148 95 #define TI_GPIO_FALLINGDETECT 0x014C 96 #define TI_GPIO_DEBOUNCENABLE 0x0150 97 #define TI_GPIO_DEBOUNCINGTIME 0x0154 98 #define TI_GPIO_CLEARWKUPENA 0x0180 99 #define TI_GPIO_SETWKUENA 0x0184 100 #define TI_GPIO_CLEARDATAOUT 0x0190 101 #define TI_GPIO_SETDATAOUT 0x0194 102 103 /* Other SoC Specific definitions */ 104 #define OMAP4_MAX_GPIO_BANKS 6 105 #define OMAP4_FIRST_GPIO_BANK 1 106 #define OMAP4_INTR_PER_BANK 1 107 #define OMAP4_GPIO_REV 0x50600801 108 #define AM335X_MAX_GPIO_BANKS 4 109 #define AM335X_FIRST_GPIO_BANK 0 110 #define AM335X_INTR_PER_BANK 2 111 #define AM335X_GPIO_REV 0x50600801 112 #define PINS_PER_BANK 32 113 #define TI_GPIO_BANK(p) ((p) / PINS_PER_BANK) 114 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK)) 115 116 static struct ti_gpio_softc *ti_gpio_sc = NULL; 117 static int ti_gpio_detach(device_t); 118 119 static u_int 120 ti_max_gpio_banks(void) 121 { 122 switch(ti_chip()) { 123 #ifdef SOC_OMAP4 124 case CHIP_OMAP_4: 125 return (OMAP4_MAX_GPIO_BANKS); 126 #endif 127 #ifdef SOC_TI_AM335X 128 case CHIP_AM335X: 129 return (AM335X_MAX_GPIO_BANKS); 130 #endif 131 } 132 return (0); 133 } 134 135 static u_int 136 ti_max_gpio_intrs(void) 137 { 138 switch(ti_chip()) { 139 #ifdef SOC_OMAP4 140 case CHIP_OMAP_4: 141 return (OMAP4_MAX_GPIO_BANKS * OMAP4_INTR_PER_BANK); 142 #endif 143 #ifdef SOC_TI_AM335X 144 case CHIP_AM335X: 145 return (AM335X_MAX_GPIO_BANKS * AM335X_INTR_PER_BANK); 146 #endif 147 } 148 return (0); 149 } 150 151 static u_int 152 ti_first_gpio_bank(void) 153 { 154 switch(ti_chip()) { 155 #ifdef SOC_OMAP4 156 case CHIP_OMAP_4: 157 return (OMAP4_FIRST_GPIO_BANK); 158 #endif 159 #ifdef SOC_TI_AM335X 160 case CHIP_AM335X: 161 return (AM335X_FIRST_GPIO_BANK); 162 #endif 163 } 164 return (0); 165 } 166 167 static uint32_t 168 ti_gpio_rev(void) 169 { 170 switch(ti_chip()) { 171 #ifdef SOC_OMAP4 172 case CHIP_OMAP_4: 173 return (OMAP4_GPIO_REV); 174 #endif 175 #ifdef SOC_TI_AM335X 176 case CHIP_AM335X: 177 return (AM335X_GPIO_REV); 178 #endif 179 } 180 return (0); 181 } 182 183 /** 184 * ti_gpio_mem_spec - Resource specification used when allocating resources 185 * ti_gpio_irq_spec - Resource specification used when allocating resources 186 * 187 * This driver module can have up to six independent memory regions, each 188 * region typically controls 32 GPIO pins. 189 * 190 * On OMAP3 and OMAP4 there is only one physical interrupt line per bank, 191 * but there are two set of registers which control the interrupt delivery 192 * to internal subsystems. The first set of registers control the 193 * interrupts delivery to the MPU and the second set control the 194 * interrupts delivery to the DSP. 195 * 196 * On AM335x there are two physical interrupt lines for each GPIO module. 197 * Each interrupt line is controlled by a set of registers. 198 */ 199 static struct resource_spec ti_gpio_mem_spec[] = { 200 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 201 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL }, 202 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL }, 203 { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL }, 204 #if !defined(SOC_TI_AM335X) 205 { SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL }, 206 { SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL }, 207 #endif 208 { -1, 0, 0 } 209 }; 210 static struct resource_spec ti_gpio_irq_spec[] = { 211 { SYS_RES_IRQ, 0, RF_ACTIVE }, 212 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, 213 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, 214 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, 215 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL }, 216 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL }, 217 #if defined(SOC_TI_AM335X) 218 { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL }, 219 { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL }, 220 #endif 221 { -1, 0, 0 } 222 }; 223 224 /** 225 * Macros for driver mutex locking 226 */ 227 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 228 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 229 #define TI_GPIO_LOCK_INIT(_sc) \ 230 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 231 "ti_gpio", MTX_SPIN) 232 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 233 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 234 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 235 236 /** 237 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers 238 * @sc: GPIO device context 239 * @bank: The bank to read from 240 * @off: The offset of a register from the GPIO register address range 241 * 242 * 243 * RETURNS: 244 * 32-bit value read from the register. 245 */ 246 static inline uint32_t 247 ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off) 248 { 249 return (bus_read_4(sc->sc_mem_res[bank], off)); 250 } 251 252 /** 253 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers 254 * @sc: GPIO device context 255 * @bank: The bank to write to 256 * @off: The offset of a register from the GPIO register address range 257 * @val: The value to write into the register 258 * 259 * RETURNS: 260 * nothing 261 */ 262 static inline void 263 ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off, 264 uint32_t val) 265 { 266 bus_write_4(sc->sc_mem_res[bank], off, val); 267 } 268 269 static inline void 270 ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask) 271 { 272 273 /* We clear both set of registers. */ 274 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask); 275 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask); 276 } 277 278 static inline void 279 ti_gpio_intr_set(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask) 280 { 281 282 /* 283 * On OMAP4 we unmask only the MPU interrupt and on AM335x we 284 * also activate only the first interrupt. 285 */ 286 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_SET_0, mask); 287 } 288 289 static inline void 290 ti_gpio_intr_ack(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask) 291 { 292 293 /* 294 * Acknowledge the interrupt on both registers even if we use only 295 * the first one. 296 */ 297 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_0, mask); 298 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_1, mask); 299 } 300 301 static inline uint32_t 302 ti_gpio_intr_status(struct ti_gpio_softc *sc, unsigned int bank) 303 { 304 uint32_t reg; 305 306 /* Get the status from both registers. */ 307 reg = ti_gpio_read_4(sc, bank, TI_GPIO_IRQSTATUS_0); 308 reg |= ti_gpio_read_4(sc, bank, TI_GPIO_IRQSTATUS_1); 309 310 return (reg); 311 } 312 313 static device_t 314 ti_gpio_get_bus(device_t dev) 315 { 316 struct ti_gpio_softc *sc; 317 318 sc = device_get_softc(dev); 319 320 return (sc->sc_busdev); 321 } 322 323 /** 324 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 325 * @dev: gpio device handle 326 * @maxpin: pointer to a value that upon return will contain the maximum number 327 * of pins in the device. 328 * 329 * 330 * LOCKING: 331 * No locking required, returns static data. 332 * 333 * RETURNS: 334 * Returns 0 on success otherwise an error code 335 */ 336 static int 337 ti_gpio_pin_max(device_t dev, int *maxpin) 338 { 339 340 *maxpin = ti_max_gpio_banks() * PINS_PER_BANK - 1; 341 342 return (0); 343 } 344 345 static int 346 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin) 347 { 348 349 if (pin >= sc->sc_maxpin || 350 TI_GPIO_BANK(pin) >= ti_max_gpio_banks() || 351 sc->sc_mem_res[TI_GPIO_BANK(pin)] == NULL) { 352 return (EINVAL); 353 } 354 355 return (0); 356 } 357 358 /** 359 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin 360 * @dev: gpio device handle 361 * @pin: the number of the pin 362 * @caps: pointer to a value that upon return will contain the capabilities 363 * 364 * Currently all pins have the same capability, notably: 365 * - GPIO_PIN_INPUT 366 * - GPIO_PIN_OUTPUT 367 * - GPIO_PIN_PULLUP 368 * - GPIO_PIN_PULLDOWN 369 * 370 * LOCKING: 371 * No locking required, returns static data. 372 * 373 * RETURNS: 374 * Returns 0 on success otherwise an error code 375 */ 376 static int 377 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 378 { 379 struct ti_gpio_softc *sc; 380 381 sc = device_get_softc(dev); 382 if (ti_gpio_valid_pin(sc, pin) != 0) 383 return (EINVAL); 384 385 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP | 386 GPIO_PIN_PULLDOWN); 387 388 return (0); 389 } 390 391 /** 392 * ti_gpio_pin_getflags - Gets the current flags of a given pin 393 * @dev: gpio device handle 394 * @pin: the number of the pin 395 * @flags: upon return will contain the current flags of the pin 396 * 397 * Reads the current flags of a given pin, here we actually read the H/W 398 * registers to determine the flags, rather than storing the value in the 399 * setflags call. 400 * 401 * LOCKING: 402 * Internally locks the context 403 * 404 * RETURNS: 405 * Returns 0 on success otherwise an error code 406 */ 407 static int 408 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 409 { 410 struct ti_gpio_softc *sc; 411 412 sc = device_get_softc(dev); 413 if (ti_gpio_valid_pin(sc, pin) != 0) 414 return (EINVAL); 415 416 /* Get the current pin state */ 417 TI_GPIO_LOCK(sc); 418 TI_GPIO_GET_FLAGS(dev, pin, flags); 419 TI_GPIO_UNLOCK(sc); 420 421 return (0); 422 } 423 424 /** 425 * ti_gpio_pin_getname - Gets the name of a given pin 426 * @dev: gpio device handle 427 * @pin: the number of the pin 428 * @name: buffer to put the name in 429 * 430 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 431 * of the pin. 432 * 433 * LOCKING: 434 * No locking required, returns static data. 435 * 436 * RETURNS: 437 * Returns 0 on success otherwise an error code 438 */ 439 static int 440 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 441 { 442 struct ti_gpio_softc *sc; 443 444 sc = device_get_softc(dev); 445 if (ti_gpio_valid_pin(sc, pin) != 0) 446 return (EINVAL); 447 448 /* Set a very simple name */ 449 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 450 name[GPIOMAXNAME - 1] = '\0'; 451 452 return (0); 453 } 454 455 /** 456 * ti_gpio_pin_setflags - Sets the flags for a given pin 457 * @dev: gpio device handle 458 * @pin: the number of the pin 459 * @flags: the flags to set 460 * 461 * The flags of the pin correspond to things like input/output mode, pull-ups, 462 * pull-downs, etc. This driver doesn't support all flags, only the following: 463 * - GPIO_PIN_INPUT 464 * - GPIO_PIN_OUTPUT 465 * - GPIO_PIN_PULLUP 466 * - GPIO_PIN_PULLDOWN 467 * 468 * LOCKING: 469 * Internally locks the context 470 * 471 * RETURNS: 472 * Returns 0 on success otherwise an error code 473 */ 474 static int 475 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 476 { 477 struct ti_gpio_softc *sc; 478 uint32_t oe; 479 480 sc = device_get_softc(dev); 481 if (ti_gpio_valid_pin(sc, pin) != 0) 482 return (EINVAL); 483 484 /* Set the GPIO mode and state */ 485 TI_GPIO_LOCK(sc); 486 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { 487 TI_GPIO_UNLOCK(sc); 488 return (EINVAL); 489 } 490 491 /* If configuring as an output set the "output enable" bit */ 492 oe = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), TI_GPIO_OE); 493 if (flags & GPIO_PIN_INPUT) 494 oe |= TI_GPIO_MASK(pin); 495 else 496 oe &= ~TI_GPIO_MASK(pin); 497 ti_gpio_write_4(sc, TI_GPIO_BANK(pin), TI_GPIO_OE, oe); 498 TI_GPIO_UNLOCK(sc); 499 500 return (0); 501 } 502 503 /** 504 * ti_gpio_pin_set - Sets the current level on a GPIO pin 505 * @dev: gpio device handle 506 * @pin: the number of the pin 507 * @value: non-zero value will drive the pin high, otherwise the pin is 508 * driven low. 509 * 510 * 511 * LOCKING: 512 * Internally locks the context 513 * 514 * RETURNS: 515 * Returns 0 on success otherwise a error code 516 */ 517 static int 518 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 519 { 520 struct ti_gpio_softc *sc; 521 uint32_t reg; 522 523 sc = device_get_softc(dev); 524 if (ti_gpio_valid_pin(sc, pin) != 0) 525 return (EINVAL); 526 527 TI_GPIO_LOCK(sc); 528 if (value == GPIO_PIN_LOW) 529 reg = TI_GPIO_CLEARDATAOUT; 530 else 531 reg = TI_GPIO_SETDATAOUT; 532 ti_gpio_write_4(sc, TI_GPIO_BANK(pin), reg, TI_GPIO_MASK(pin)); 533 TI_GPIO_UNLOCK(sc); 534 535 return (0); 536 } 537 538 /** 539 * ti_gpio_pin_get - Gets the current level on a GPIO pin 540 * @dev: gpio device handle 541 * @pin: the number of the pin 542 * @value: pointer to a value that upond return will contain the pin value 543 * 544 * The pin must be configured as an input pin beforehand, otherwise this 545 * function will fail. 546 * 547 * LOCKING: 548 * Internally locks the context 549 * 550 * RETURNS: 551 * Returns 0 on success otherwise a error code 552 */ 553 static int 554 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 555 { 556 struct ti_gpio_softc *sc; 557 uint32_t oe, reg, val; 558 559 sc = device_get_softc(dev); 560 if (ti_gpio_valid_pin(sc, pin) != 0) 561 return (EINVAL); 562 563 /* 564 * Return data from output latch when set as output and from the 565 * input register otherwise. 566 */ 567 TI_GPIO_LOCK(sc); 568 oe = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), TI_GPIO_OE); 569 if (oe & TI_GPIO_MASK(pin)) 570 reg = TI_GPIO_DATAIN; 571 else 572 reg = TI_GPIO_DATAOUT; 573 val = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), reg); 574 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0; 575 TI_GPIO_UNLOCK(sc); 576 577 return (0); 578 } 579 580 /** 581 * ti_gpio_pin_toggle - Toggles a given GPIO pin 582 * @dev: gpio device handle 583 * @pin: the number of the pin 584 * 585 * 586 * LOCKING: 587 * Internally locks the context 588 * 589 * RETURNS: 590 * Returns 0 on success otherwise a error code 591 */ 592 static int 593 ti_gpio_pin_toggle(device_t dev, uint32_t pin) 594 { 595 struct ti_gpio_softc *sc; 596 uint32_t reg, val; 597 598 sc = device_get_softc(dev); 599 if (ti_gpio_valid_pin(sc, pin) != 0) 600 return (EINVAL); 601 602 /* Toggle the pin */ 603 TI_GPIO_LOCK(sc); 604 val = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), TI_GPIO_DATAOUT); 605 if (val & TI_GPIO_MASK(pin)) 606 reg = TI_GPIO_CLEARDATAOUT; 607 else 608 reg = TI_GPIO_SETDATAOUT; 609 ti_gpio_write_4(sc, TI_GPIO_BANK(pin), reg, TI_GPIO_MASK(pin)); 610 TI_GPIO_UNLOCK(sc); 611 612 return (0); 613 } 614 615 /** 616 * ti_gpio_intr - ISR for all GPIO modules 617 * @arg: the soft context pointer 618 * 619 * LOCKING: 620 * Internally locks the context 621 * 622 */ 623 static int 624 ti_gpio_intr(void *arg) 625 { 626 int bank_last, irq; 627 struct intr_event *event; 628 struct ti_gpio_softc *sc; 629 uint32_t reg; 630 631 sc = (struct ti_gpio_softc *)arg; 632 bank_last = -1; 633 reg = 0; /* squelch bogus gcc warning */ 634 for (irq = 0; irq < sc->sc_maxpin; irq++) { 635 636 /* Read interrupt status only once for each bank. */ 637 if (TI_GPIO_BANK(irq) != bank_last) { 638 reg = ti_gpio_intr_status(sc, TI_GPIO_BANK(irq)); 639 bank_last = TI_GPIO_BANK(irq); 640 } 641 if ((reg & TI_GPIO_MASK(irq)) == 0) 642 continue; 643 event = sc->sc_events[irq]; 644 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers)) 645 intr_event_handle(event, NULL); 646 else 647 device_printf(sc->sc_dev, "Stray IRQ %d\n", irq); 648 /* Ack the IRQ Status bit. */ 649 ti_gpio_intr_ack(sc, TI_GPIO_BANK(irq), TI_GPIO_MASK(irq)); 650 } 651 652 return (FILTER_HANDLED); 653 } 654 655 static int 656 ti_gpio_attach_intr(device_t dev) 657 { 658 int i; 659 struct ti_gpio_softc *sc; 660 661 sc = device_get_softc(dev); 662 for (i = 0; i < ti_max_gpio_intrs(); i++) { 663 if (sc->sc_irq_res[i] == NULL) 664 break; 665 666 /* 667 * Register our interrupt filter for each of the IRQ resources. 668 */ 669 if (bus_setup_intr(dev, sc->sc_irq_res[i], 670 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc, 671 &sc->sc_irq_hdl[i]) != 0) { 672 device_printf(dev, 673 "WARNING: unable to register interrupt filter\n"); 674 return (-1); 675 } 676 } 677 678 return (0); 679 } 680 681 static int 682 ti_gpio_detach_intr(device_t dev) 683 { 684 int i; 685 struct ti_gpio_softc *sc; 686 687 /* Teardown our interrupt filters. */ 688 sc = device_get_softc(dev); 689 for (i = 0; i < ti_max_gpio_intrs(); i++) { 690 if (sc->sc_irq_res[i] == NULL) 691 break; 692 693 if (sc->sc_irq_hdl[i]) { 694 bus_teardown_intr(dev, sc->sc_irq_res[i], 695 sc->sc_irq_hdl[i]); 696 } 697 } 698 699 return (0); 700 } 701 702 static int 703 ti_gpio_bank_init(device_t dev, int bank) 704 { 705 int pin; 706 struct ti_gpio_softc *sc; 707 uint32_t flags, reg_oe, rev; 708 709 sc = device_get_softc(dev); 710 711 /* Enable the interface and functional clocks for the module. */ 712 ti_prcm_clk_enable(GPIO0_CLK + ti_first_gpio_bank() + bank); 713 714 /* 715 * Read the revision number of the module. TI don't publish the 716 * actual revision numbers, so instead the values have been 717 * determined by experimentation. 718 */ 719 rev = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION); 720 721 /* Check the revision. */ 722 if (rev != ti_gpio_rev()) { 723 device_printf(dev, "Warning: could not determine the revision " 724 "of GPIO module %d (revision:0x%08x)\n", bank, rev); 725 return (EINVAL); 726 } 727 728 /* Disable interrupts for all pins. */ 729 ti_gpio_intr_clr(sc, bank, 0xffffffff); 730 731 /* Init OE register based on pads configuration. */ 732 reg_oe = 0xffffffff; 733 for (pin = 0; pin < PINS_PER_BANK; pin++) { 734 TI_GPIO_GET_FLAGS(dev, PINS_PER_BANK * bank + pin, &flags); 735 if (flags & GPIO_PIN_OUTPUT) 736 reg_oe &= ~(1UL << pin); 737 } 738 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe); 739 740 return (0); 741 } 742 743 /** 744 * ti_gpio_attach - attach function for the driver 745 * @dev: gpio device handle 746 * 747 * Allocates and sets up the driver context for all GPIO banks. This function 748 * expects the memory ranges and IRQs to already be allocated to the driver. 749 * 750 * LOCKING: 751 * None 752 * 753 * RETURNS: 754 * Always returns 0 755 */ 756 static int 757 ti_gpio_attach(device_t dev) 758 { 759 struct ti_gpio_softc *sc; 760 unsigned int i; 761 int err; 762 763 if (ti_gpio_sc != NULL) 764 return (ENXIO); 765 766 ti_gpio_sc = sc = device_get_softc(dev); 767 sc->sc_dev = dev; 768 TI_GPIO_LOCK_INIT(sc); 769 ti_gpio_pin_max(dev, &sc->sc_maxpin); 770 sc->sc_maxpin++; 771 772 /* There are up to 6 different GPIO register sets located in different 773 * memory areas on the chip. The memory range should have been set for 774 * the driver when it was added as a child. 775 */ 776 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) { 777 device_printf(dev, "Error: could not allocate mem resources\n"); 778 ti_gpio_detach(dev); 779 return (ENXIO); 780 } 781 782 /* Request the IRQ resources */ 783 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) { 784 device_printf(dev, "Error: could not allocate irq resources\n"); 785 ti_gpio_detach(dev); 786 return (ENXIO); 787 } 788 789 /* Setup the IRQ resources */ 790 if (ti_gpio_attach_intr(dev) != 0) { 791 device_printf(dev, "Error: could not setup irq handlers\n"); 792 ti_gpio_detach(dev); 793 return (ENXIO); 794 } 795 796 /* 797 * Initialize the interrupt settings. The default is active-low 798 * interrupts. 799 */ 800 sc->sc_irq_trigger = malloc( 801 sizeof(*sc->sc_irq_trigger) * sc->sc_maxpin, 802 M_DEVBUF, M_WAITOK | M_ZERO); 803 sc->sc_irq_polarity = malloc( 804 sizeof(*sc->sc_irq_polarity) * sc->sc_maxpin, 805 M_DEVBUF, M_WAITOK | M_ZERO); 806 for (i = 0; i < sc->sc_maxpin; i++) { 807 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL; 808 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW; 809 } 810 811 sc->sc_events = malloc(sizeof(struct intr_event *) * sc->sc_maxpin, 812 M_DEVBUF, M_WAITOK | M_ZERO); 813 814 /* We need to go through each block and ensure the clocks are running and 815 * the module is enabled. It might be better to do this only when the 816 * pins are configured which would result in less power used if the GPIO 817 * pins weren't used ... 818 */ 819 for (i = 0; i < ti_max_gpio_banks(); i++) { 820 if (sc->sc_mem_res[i] != NULL) { 821 /* Initialize the GPIO module. */ 822 err = ti_gpio_bank_init(dev, i); 823 if (err != 0) { 824 ti_gpio_detach(dev); 825 return (err); 826 } 827 } 828 } 829 sc->sc_busdev = gpiobus_attach_bus(dev); 830 if (sc->sc_busdev == NULL) { 831 ti_gpio_detach(dev); 832 return (ENXIO); 833 } 834 835 return (0); 836 } 837 838 /** 839 * ti_gpio_detach - detach function for the driver 840 * @dev: scm device handle 841 * 842 * Allocates and sets up the driver context, this simply entails creating a 843 * bus mappings for the SCM register set. 844 * 845 * LOCKING: 846 * None 847 * 848 * RETURNS: 849 * Always returns 0 850 */ 851 static int 852 ti_gpio_detach(device_t dev) 853 { 854 struct ti_gpio_softc *sc = device_get_softc(dev); 855 unsigned int i; 856 857 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 858 859 /* Disable all interrupts */ 860 for (i = 0; i < ti_max_gpio_banks(); i++) { 861 if (sc->sc_mem_res[i] != NULL) 862 ti_gpio_intr_clr(sc, i, 0xffffffff); 863 } 864 gpiobus_detach_bus(dev); 865 if (sc->sc_events) 866 free(sc->sc_events, M_DEVBUF); 867 if (sc->sc_irq_polarity) 868 free(sc->sc_irq_polarity, M_DEVBUF); 869 if (sc->sc_irq_trigger) 870 free(sc->sc_irq_trigger, M_DEVBUF); 871 /* Release the memory and IRQ resources. */ 872 ti_gpio_detach_intr(dev); 873 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); 874 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 875 TI_GPIO_LOCK_DESTROY(sc); 876 877 return (0); 878 } 879 880 static uint32_t 881 ti_gpio_intr_reg(struct ti_gpio_softc *sc, int irq) 882 { 883 884 if (ti_gpio_valid_pin(sc, irq) != 0) 885 return (0); 886 887 if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) { 888 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 889 return (TI_GPIO_LEVELDETECT0); 890 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 891 return (TI_GPIO_LEVELDETECT1); 892 } else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) { 893 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 894 return (TI_GPIO_FALLINGDETECT); 895 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 896 return (TI_GPIO_RISINGDETECT); 897 } 898 899 return (0); 900 } 901 902 static void 903 ti_gpio_mask_irq(void *source) 904 { 905 int irq; 906 uint32_t reg, val; 907 908 irq = (int)source; 909 if (ti_gpio_valid_pin(ti_gpio_sc, irq) != 0) 910 return; 911 912 TI_GPIO_LOCK(ti_gpio_sc); 913 ti_gpio_intr_clr(ti_gpio_sc, TI_GPIO_BANK(irq), TI_GPIO_MASK(irq)); 914 reg = ti_gpio_intr_reg(ti_gpio_sc, irq); 915 if (reg != 0) { 916 val = ti_gpio_read_4(ti_gpio_sc, TI_GPIO_BANK(irq), reg); 917 val &= ~TI_GPIO_MASK(irq); 918 ti_gpio_write_4(ti_gpio_sc, TI_GPIO_BANK(irq), reg, val); 919 } 920 TI_GPIO_UNLOCK(ti_gpio_sc); 921 } 922 923 static void 924 ti_gpio_unmask_irq(void *source) 925 { 926 int irq; 927 uint32_t reg, val; 928 929 irq = (int)source; 930 if (ti_gpio_valid_pin(ti_gpio_sc, irq) != 0) 931 return; 932 933 TI_GPIO_LOCK(ti_gpio_sc); 934 reg = ti_gpio_intr_reg(ti_gpio_sc, irq); 935 if (reg != 0) { 936 val = ti_gpio_read_4(ti_gpio_sc, TI_GPIO_BANK(irq), reg); 937 val |= TI_GPIO_MASK(irq); 938 ti_gpio_write_4(ti_gpio_sc, TI_GPIO_BANK(irq), reg, val); 939 ti_gpio_intr_set(ti_gpio_sc, TI_GPIO_BANK(irq), 940 TI_GPIO_MASK(irq)); 941 } 942 TI_GPIO_UNLOCK(ti_gpio_sc); 943 } 944 945 static int 946 ti_gpio_activate_resource(device_t dev, device_t child, int type, int rid, 947 struct resource *res) 948 { 949 int pin; 950 951 if (type != SYS_RES_IRQ) 952 return (ENXIO); 953 954 /* Unmask the interrupt. */ 955 pin = rman_get_start(res); 956 ti_gpio_unmask_irq((void *)(uintptr_t)pin); 957 958 return (0); 959 } 960 961 static int 962 ti_gpio_deactivate_resource(device_t dev, device_t child, int type, int rid, 963 struct resource *res) 964 { 965 int pin; 966 967 if (type != SYS_RES_IRQ) 968 return (ENXIO); 969 970 /* Mask the interrupt. */ 971 pin = rman_get_start(res); 972 ti_gpio_mask_irq((void *)(uintptr_t)pin); 973 974 return (0); 975 } 976 977 static int 978 ti_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig, 979 enum intr_polarity pol) 980 { 981 struct ti_gpio_softc *sc; 982 uint32_t oldreg, reg, val; 983 984 sc = device_get_softc(dev); 985 if (ti_gpio_valid_pin(sc, irq) != 0) 986 return (EINVAL); 987 988 /* There is no standard trigger or polarity. */ 989 if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM) 990 return (EINVAL); 991 992 TI_GPIO_LOCK(sc); 993 /* 994 * TRM recommends add the new event before remove the old one to 995 * avoid losing interrupts. 996 */ 997 oldreg = ti_gpio_intr_reg(sc, irq); 998 sc->sc_irq_trigger[irq] = trig; 999 sc->sc_irq_polarity[irq] = pol; 1000 reg = ti_gpio_intr_reg(sc, irq); 1001 if (reg != 0) { 1002 /* Apply the new settings. */ 1003 val = ti_gpio_read_4(sc, TI_GPIO_BANK(irq), reg); 1004 val |= TI_GPIO_MASK(irq); 1005 ti_gpio_write_4(sc, TI_GPIO_BANK(irq), reg, val); 1006 } 1007 if (reg != oldreg && oldreg != 0) { 1008 /* Remove the old settings. */ 1009 val = ti_gpio_read_4(sc, TI_GPIO_BANK(irq), oldreg); 1010 val &= ~TI_GPIO_MASK(irq); 1011 ti_gpio_write_4(sc, TI_GPIO_BANK(irq), oldreg, val); 1012 } 1013 TI_GPIO_UNLOCK(sc); 1014 1015 return (0); 1016 } 1017 1018 static int 1019 ti_gpio_setup_intr(device_t dev, device_t child, struct resource *ires, 1020 int flags, driver_filter_t *filt, driver_intr_t *handler, 1021 void *arg, void **cookiep) 1022 { 1023 struct ti_gpio_softc *sc; 1024 struct intr_event *event; 1025 int pin, error; 1026 1027 sc = device_get_softc(dev); 1028 pin = rman_get_start(ires); 1029 if (ti_gpio_valid_pin(sc, pin) != 0) 1030 panic("%s: bad pin %d", __func__, pin); 1031 1032 event = sc->sc_events[pin]; 1033 if (event == NULL) { 1034 error = intr_event_create(&event, (void *)(uintptr_t)pin, 0, 1035 pin, ti_gpio_mask_irq, ti_gpio_unmask_irq, NULL, NULL, 1036 "gpio%d pin%d:", device_get_unit(dev), pin); 1037 if (error != 0) 1038 return (error); 1039 sc->sc_events[pin] = event; 1040 } 1041 intr_event_add_handler(event, device_get_nameunit(child), filt, 1042 handler, arg, intr_priority(flags), flags, cookiep); 1043 1044 return (0); 1045 } 1046 1047 static int 1048 ti_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires, 1049 void *cookie) 1050 { 1051 struct ti_gpio_softc *sc; 1052 int pin, err; 1053 1054 sc = device_get_softc(dev); 1055 pin = rman_get_start(ires); 1056 if (ti_gpio_valid_pin(sc, pin) != 0) 1057 panic("%s: bad pin %d", __func__, pin); 1058 if (sc->sc_events[pin] == NULL) 1059 panic("Trying to teardown unoccupied IRQ"); 1060 err = intr_event_remove_handler(cookie); 1061 if (!err) 1062 sc->sc_events[pin] = NULL; 1063 1064 return (err); 1065 } 1066 1067 static phandle_t 1068 ti_gpio_get_node(device_t bus, device_t dev) 1069 { 1070 1071 /* We only have one child, the GPIO bus, which needs our own node. */ 1072 return (ofw_bus_get_node(bus)); 1073 } 1074 1075 static device_method_t ti_gpio_methods[] = { 1076 DEVMETHOD(device_attach, ti_gpio_attach), 1077 DEVMETHOD(device_detach, ti_gpio_detach), 1078 1079 /* GPIO protocol */ 1080 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus), 1081 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 1082 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 1083 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 1084 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 1085 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 1086 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 1087 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 1088 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 1089 1090 /* Bus interface */ 1091 DEVMETHOD(bus_activate_resource, ti_gpio_activate_resource), 1092 DEVMETHOD(bus_deactivate_resource, ti_gpio_deactivate_resource), 1093 DEVMETHOD(bus_config_intr, ti_gpio_config_intr), 1094 DEVMETHOD(bus_setup_intr, ti_gpio_setup_intr), 1095 DEVMETHOD(bus_teardown_intr, ti_gpio_teardown_intr), 1096 1097 /* ofw_bus interface */ 1098 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 1099 1100 {0, 0}, 1101 }; 1102 1103 driver_t ti_gpio_driver = { 1104 "gpio", 1105 ti_gpio_methods, 1106 sizeof(struct ti_gpio_softc), 1107 }; 1108