1b9305a86SEmmanuel Vadot /*- 2b9305a86SEmmanuel Vadot * Copyright (c) 2019 Emmanuel Vadot <manu@FreeBSD.org> 3b9305a86SEmmanuel Vadot * 40050ea24SMichal Meloun * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se> 50050ea24SMichal Meloun * 6b9305a86SEmmanuel Vadot * Redistribution and use in source and binary forms, with or without 7b9305a86SEmmanuel Vadot * modification, are permitted provided that the following conditions 8b9305a86SEmmanuel Vadot * are met: 9b9305a86SEmmanuel Vadot * 1. Redistributions of source code must retain the above copyright 10b9305a86SEmmanuel Vadot * notice, this list of conditions and the following disclaimer. 11b9305a86SEmmanuel Vadot * 2. Redistributions in binary form must reproduce the above copyright 12b9305a86SEmmanuel Vadot * notice, this list of conditions and the following disclaimer in the 13b9305a86SEmmanuel Vadot * documentation and/or other materials provided with the distribution. 14b9305a86SEmmanuel Vadot * 15b9305a86SEmmanuel Vadot * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16b9305a86SEmmanuel Vadot * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17b9305a86SEmmanuel Vadot * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18b9305a86SEmmanuel Vadot * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19b9305a86SEmmanuel Vadot * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20b9305a86SEmmanuel Vadot * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21b9305a86SEmmanuel Vadot * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22b9305a86SEmmanuel Vadot * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23b9305a86SEmmanuel Vadot * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24b9305a86SEmmanuel Vadot * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25b9305a86SEmmanuel Vadot * SUCH DAMAGE. 26b9305a86SEmmanuel Vadot * 27b9305a86SEmmanuel Vadot * $FreeBSD$ 28b9305a86SEmmanuel Vadot */ 29b9305a86SEmmanuel Vadot 30b9305a86SEmmanuel Vadot #include <sys/cdefs.h> 31b9305a86SEmmanuel Vadot __FBSDID("$FreeBSD$"); 32b9305a86SEmmanuel Vadot 33b9305a86SEmmanuel Vadot #include <sys/param.h> 34b9305a86SEmmanuel Vadot #include <sys/systm.h> 35b9305a86SEmmanuel Vadot #include <sys/bus.h> 36b9305a86SEmmanuel Vadot #include <sys/fbio.h> 37b9305a86SEmmanuel Vadot #include <sys/kernel.h> 38b9305a86SEmmanuel Vadot #include <sys/module.h> 390050ea24SMichal Meloun #include <sys/queue.h> 40b9305a86SEmmanuel Vadot #include <sys/rman.h> 41b9305a86SEmmanuel Vadot #include <sys/resource.h> 42b9305a86SEmmanuel Vadot #include <machine/bus.h> 43b9305a86SEmmanuel Vadot #include <vm/vm.h> 44b9305a86SEmmanuel Vadot #include <vm/vm_extern.h> 45b9305a86SEmmanuel Vadot #include <vm/vm_kern.h> 46b9305a86SEmmanuel Vadot #include <vm/pmap.h> 47b9305a86SEmmanuel Vadot 48b9305a86SEmmanuel Vadot #include <dev/fdt/simplebus.h> 49b9305a86SEmmanuel Vadot 50b9305a86SEmmanuel Vadot #include <dev/ofw/ofw_bus.h> 51b9305a86SEmmanuel Vadot #include <dev/ofw/ofw_bus_subr.h> 52b9305a86SEmmanuel Vadot 530050ea24SMichal Meloun #include <dev/extres/clk/clk.h> 54b9305a86SEmmanuel Vadot 550050ea24SMichal Meloun #include <arm/ti/ti_sysc.h> 560050ea24SMichal Meloun #include <arm/ti/clk/clock_common.h> 570050ea24SMichal Meloun 580050ea24SMichal Meloun #define DEBUG_SYSC 0 590050ea24SMichal Meloun 600050ea24SMichal Meloun #if DEBUG_SYSC 610050ea24SMichal Meloun #define DPRINTF(dev, msg...) device_printf(dev, msg) 620050ea24SMichal Meloun #else 630050ea24SMichal Meloun #define DPRINTF(dev, msg...) 640050ea24SMichal Meloun #endif 650050ea24SMichal Meloun 660050ea24SMichal Meloun /* Documentation/devicetree/bindings/bus/ti-sysc.txt 670050ea24SMichal Meloun * 680050ea24SMichal Meloun * Documentation/devicetree/clock/clock-bindings.txt 690050ea24SMichal Meloun * Defines phandle + optional pair 700050ea24SMichal Meloun * Documentation/devicetree/clock/ti-clkctl.txt 710050ea24SMichal Meloun */ 72b9305a86SEmmanuel Vadot 73b9305a86SEmmanuel Vadot static int ti_sysc_probe(device_t dev); 74b9305a86SEmmanuel Vadot static int ti_sysc_attach(device_t dev); 75b9305a86SEmmanuel Vadot static int ti_sysc_detach(device_t dev); 76b9305a86SEmmanuel Vadot 770050ea24SMichal Meloun #define TI_SYSC_DRA7_MCAN 15 780050ea24SMichal Meloun #define TI_SYSC_USB_HOST_FS 14 790050ea24SMichal Meloun #define TI_SYSC_DRA7_MCASP 13 800050ea24SMichal Meloun #define TI_SYSC_MCASP 12 810050ea24SMichal Meloun #define TI_SYSC_OMAP_AES 11 820050ea24SMichal Meloun #define TI_SYSC_OMAP3_SHAM 10 830050ea24SMichal Meloun #define TI_SYSC_OMAP4_SR 9 840050ea24SMichal Meloun #define TI_SYSC_OMAP3630_SR 8 850050ea24SMichal Meloun #define TI_SYSC_OMAP3430_SR 7 860050ea24SMichal Meloun #define TI_SYSC_OMAP4_TIMER 6 870050ea24SMichal Meloun #define TI_SYSC_OMAP2_TIMER 5 880050ea24SMichal Meloun /* Above needs special workarounds */ 890050ea24SMichal Meloun #define TI_SYSC_OMAP4_SIMPLE 4 900050ea24SMichal Meloun #define TI_SYSC_OMAP4 3 910050ea24SMichal Meloun #define TI_SYSC_OMAP2 2 920050ea24SMichal Meloun #define TI_SYSC 1 930050ea24SMichal Meloun #define TI_SYSC_END 0 940050ea24SMichal Meloun 950050ea24SMichal Meloun static struct ofw_compat_data compat_data[] = { 960050ea24SMichal Meloun { "ti,sysc-dra7-mcan", TI_SYSC_DRA7_MCAN }, 970050ea24SMichal Meloun { "ti,sysc-usb-host-fs", TI_SYSC_USB_HOST_FS }, 980050ea24SMichal Meloun { "ti,sysc-dra7-mcasp", TI_SYSC_DRA7_MCASP }, 990050ea24SMichal Meloun { "ti,sysc-mcasp", TI_SYSC_MCASP }, 1000050ea24SMichal Meloun { "ti,sysc-omap-aes", TI_SYSC_OMAP_AES }, 1010050ea24SMichal Meloun { "ti,sysc-omap3-sham", TI_SYSC_OMAP3_SHAM }, 1020050ea24SMichal Meloun { "ti,sysc-omap4-sr", TI_SYSC_OMAP4_SR }, 1030050ea24SMichal Meloun { "ti,sysc-omap3630-sr", TI_SYSC_OMAP3630_SR }, 1040050ea24SMichal Meloun { "ti,sysc-omap3430-sr", TI_SYSC_OMAP3430_SR }, 1050050ea24SMichal Meloun { "ti,sysc-omap4-timer", TI_SYSC_OMAP4_TIMER }, 1060050ea24SMichal Meloun { "ti,sysc-omap2-timer", TI_SYSC_OMAP2_TIMER }, 1070050ea24SMichal Meloun /* Above needs special workarounds */ 1080050ea24SMichal Meloun { "ti,sysc-omap4-simple", TI_SYSC_OMAP4_SIMPLE }, 1090050ea24SMichal Meloun { "ti,sysc-omap4", TI_SYSC_OMAP4 }, 1100050ea24SMichal Meloun { "ti,sysc-omap2", TI_SYSC_OMAP2 }, 1110050ea24SMichal Meloun { "ti,sysc", TI_SYSC }, 1120050ea24SMichal Meloun { NULL, TI_SYSC_END } 1130050ea24SMichal Meloun }; 1140050ea24SMichal Meloun 1150050ea24SMichal Meloun /* reg-names can be "rev", "sysc" and "syss" */ 1160050ea24SMichal Meloun static const char * reg_names[] = { "rev", "sysc", "syss" }; 1170050ea24SMichal Meloun #define REG_REV 0 1180050ea24SMichal Meloun #define REG_SYSC 1 1190050ea24SMichal Meloun #define REG_SYSS 2 1200050ea24SMichal Meloun #define REG_MAX 3 1210050ea24SMichal Meloun 1220050ea24SMichal Meloun /* master idle / slave idle mode defined in 8.1.3.2.1 / 8.1.3.2.2 */ 1238a7a4683SEmmanuel Vadot #include <dt-bindings/bus/ti-sysc.h> 1240050ea24SMichal Meloun #define SYSC_IDLE_MAX 4 1250050ea24SMichal Meloun 1260050ea24SMichal Meloun struct sysc_reg { 1270050ea24SMichal Meloun uint64_t address; 1280050ea24SMichal Meloun uint64_t size; 1290050ea24SMichal Meloun }; 1300050ea24SMichal Meloun 1310050ea24SMichal Meloun struct clk_list { 1320050ea24SMichal Meloun TAILQ_ENTRY(clk_list) next; 1330050ea24SMichal Meloun clk_t clk; 1340050ea24SMichal Meloun }; 1350050ea24SMichal Meloun 1360050ea24SMichal Meloun struct ti_sysc_softc { 1370050ea24SMichal Meloun struct simplebus_softc sc; 1380050ea24SMichal Meloun bool attach_done; 1390050ea24SMichal Meloun 1400050ea24SMichal Meloun device_t dev; 1410050ea24SMichal Meloun int device_type; 1420050ea24SMichal Meloun 1430050ea24SMichal Meloun struct sysc_reg reg[REG_MAX]; 1440050ea24SMichal Meloun /* Offset from host base address */ 1450050ea24SMichal Meloun uint64_t offset_reg[REG_MAX]; 1460050ea24SMichal Meloun 1470050ea24SMichal Meloun uint32_t ti_sysc_mask; 1480050ea24SMichal Meloun int32_t ti_sysc_midle[SYSC_IDLE_MAX]; 1490050ea24SMichal Meloun int32_t ti_sysc_sidle[SYSC_IDLE_MAX]; 1500050ea24SMichal Meloun uint32_t ti_sysc_delay_us; 1510050ea24SMichal Meloun uint32_t ti_syss_mask; 1520050ea24SMichal Meloun 1530050ea24SMichal Meloun int num_clocks; 1540050ea24SMichal Meloun TAILQ_HEAD(, clk_list) clk_list; 1550050ea24SMichal Meloun 1560050ea24SMichal Meloun /* deprecated ti_hwmods */ 1570050ea24SMichal Meloun bool ti_no_reset_on_init; 1580050ea24SMichal Meloun bool ti_no_idle_on_init; 1590050ea24SMichal Meloun bool ti_no_idle; 1600050ea24SMichal Meloun }; 1610050ea24SMichal Meloun 1620050ea24SMichal Meloun /* 1630050ea24SMichal Meloun * All sysc seems to have a reg["rev"] register. 1640050ea24SMichal Meloun * Lets use that for identification of which module the driver are connected to. 1650050ea24SMichal Meloun */ 1660050ea24SMichal Meloun uint64_t 1670050ea24SMichal Meloun ti_sysc_get_rev_address(device_t dev) { 1680050ea24SMichal Meloun struct ti_sysc_softc *sc = device_get_softc(dev); 1690050ea24SMichal Meloun 1700050ea24SMichal Meloun return (sc->reg[REG_REV].address); 1710050ea24SMichal Meloun } 1720050ea24SMichal Meloun 1730050ea24SMichal Meloun uint64_t 1740050ea24SMichal Meloun ti_sysc_get_rev_address_offset_host(device_t dev) { 1750050ea24SMichal Meloun struct ti_sysc_softc *sc = device_get_softc(dev); 1760050ea24SMichal Meloun 1770050ea24SMichal Meloun return (sc->offset_reg[REG_REV]); 1780050ea24SMichal Meloun } 1790050ea24SMichal Meloun 1800050ea24SMichal Meloun uint64_t 1810050ea24SMichal Meloun ti_sysc_get_sysc_address(device_t dev) { 1820050ea24SMichal Meloun struct ti_sysc_softc *sc = device_get_softc(dev); 1830050ea24SMichal Meloun 1840050ea24SMichal Meloun return (sc->reg[REG_SYSC].address); 1850050ea24SMichal Meloun } 1860050ea24SMichal Meloun 1870050ea24SMichal Meloun uint64_t 1880050ea24SMichal Meloun ti_sysc_get_sysc_address_offset_host(device_t dev) { 1890050ea24SMichal Meloun struct ti_sysc_softc *sc = device_get_softc(dev); 1900050ea24SMichal Meloun 1910050ea24SMichal Meloun return (sc->offset_reg[REG_SYSC]); 1920050ea24SMichal Meloun } 1930050ea24SMichal Meloun 1940050ea24SMichal Meloun uint64_t 1950050ea24SMichal Meloun ti_sysc_get_syss_address(device_t dev) { 1960050ea24SMichal Meloun struct ti_sysc_softc *sc = device_get_softc(dev); 1970050ea24SMichal Meloun 1980050ea24SMichal Meloun return (sc->reg[REG_SYSS].address); 1990050ea24SMichal Meloun } 2000050ea24SMichal Meloun 2010050ea24SMichal Meloun uint64_t 2020050ea24SMichal Meloun ti_sysc_get_syss_address_offset_host(device_t dev) { 2030050ea24SMichal Meloun struct ti_sysc_softc *sc = device_get_softc(dev); 2040050ea24SMichal Meloun 2050050ea24SMichal Meloun return (sc->offset_reg[REG_SYSS]); 2060050ea24SMichal Meloun } 2070050ea24SMichal Meloun 2080050ea24SMichal Meloun /* 2090050ea24SMichal Meloun * Due no memory region is assigned the sysc driver the children needs to 2100050ea24SMichal Meloun * handle the practical read/writes to the registers. 2110050ea24SMichal Meloun * Check if sysc has reset bit. 2120050ea24SMichal Meloun */ 2130050ea24SMichal Meloun uint32_t 2140050ea24SMichal Meloun ti_sysc_get_soft_reset_bit(device_t dev) { 2150050ea24SMichal Meloun struct ti_sysc_softc *sc = device_get_softc(dev); 2160050ea24SMichal Meloun switch (sc->device_type) { 2170050ea24SMichal Meloun case TI_SYSC_OMAP4_TIMER: 2180050ea24SMichal Meloun case TI_SYSC_OMAP4_SIMPLE: 2190050ea24SMichal Meloun case TI_SYSC_OMAP4: 2200050ea24SMichal Meloun if (sc->ti_sysc_mask & SYSC_OMAP4_SOFTRESET) { 2210050ea24SMichal Meloun return (SYSC_OMAP4_SOFTRESET); 2220050ea24SMichal Meloun } 2230050ea24SMichal Meloun break; 2240050ea24SMichal Meloun 2250050ea24SMichal Meloun case TI_SYSC_OMAP2_TIMER: 2260050ea24SMichal Meloun case TI_SYSC_OMAP2: 2270050ea24SMichal Meloun case TI_SYSC: 2280050ea24SMichal Meloun if (sc->ti_sysc_mask & SYSC_OMAP2_SOFTRESET) { 2290050ea24SMichal Meloun return (SYSC_OMAP2_SOFTRESET); 2300050ea24SMichal Meloun } 2310050ea24SMichal Meloun break; 2320050ea24SMichal Meloun default: 2330050ea24SMichal Meloun break; 2340050ea24SMichal Meloun } 2350050ea24SMichal Meloun 2360050ea24SMichal Meloun return (0); 2370050ea24SMichal Meloun } 2380050ea24SMichal Meloun 2390050ea24SMichal Meloun int 2400050ea24SMichal Meloun ti_sysc_clock_enable(device_t dev) { 2410050ea24SMichal Meloun struct clk_list *clkp, *clkp_tmp; 2420050ea24SMichal Meloun struct ti_sysc_softc *sc = device_get_softc(dev); 2430050ea24SMichal Meloun int err; 2440050ea24SMichal Meloun 2450050ea24SMichal Meloun TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) { 2460050ea24SMichal Meloun err = clk_enable(clkp->clk); 2470050ea24SMichal Meloun 2480050ea24SMichal Meloun if (err) { 2490050ea24SMichal Meloun DPRINTF(sc->dev, "clk_enable %s failed %d\n", 2500050ea24SMichal Meloun clk_get_name(clkp->clk), err); 2510050ea24SMichal Meloun break; 2520050ea24SMichal Meloun } 2530050ea24SMichal Meloun } 2540050ea24SMichal Meloun return (err); 2550050ea24SMichal Meloun } 2560050ea24SMichal Meloun 2570050ea24SMichal Meloun int 2580050ea24SMichal Meloun ti_sysc_clock_disable(device_t dev) { 2590050ea24SMichal Meloun struct clk_list *clkp, *clkp_tmp; 2600050ea24SMichal Meloun struct ti_sysc_softc *sc = device_get_softc(dev); 2610050ea24SMichal Meloun int err = 0; 2620050ea24SMichal Meloun 2630050ea24SMichal Meloun TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) { 2640050ea24SMichal Meloun err = clk_disable(clkp->clk); 2650050ea24SMichal Meloun 2660050ea24SMichal Meloun if (err) { 2670050ea24SMichal Meloun DPRINTF(sc->dev, "clk_enable %s failed %d\n", 2680050ea24SMichal Meloun clk_get_name(clkp->clk), err); 2690050ea24SMichal Meloun break; 2700050ea24SMichal Meloun } 2710050ea24SMichal Meloun } 2720050ea24SMichal Meloun return (err); 2730050ea24SMichal Meloun } 2740050ea24SMichal Meloun 2750050ea24SMichal Meloun static int 2760050ea24SMichal Meloun parse_regfields(struct ti_sysc_softc *sc) { 2770050ea24SMichal Meloun phandle_t node; 2780050ea24SMichal Meloun uint32_t parent_address_cells; 2790050ea24SMichal Meloun uint32_t parent_size_cells; 2800050ea24SMichal Meloun cell_t *reg; 2810050ea24SMichal Meloun ssize_t nreg; 2820050ea24SMichal Meloun int err, k, reg_i, prop_idx; 2830050ea24SMichal Meloun uint32_t idx; 2840050ea24SMichal Meloun 2850050ea24SMichal Meloun node = ofw_bus_get_node(sc->dev); 2860050ea24SMichal Meloun 2870050ea24SMichal Meloun /* Get parents address and size properties */ 2880050ea24SMichal Meloun err = OF_searchencprop(OF_parent(node), "#address-cells", 2890050ea24SMichal Meloun &parent_address_cells, sizeof(parent_address_cells)); 2900050ea24SMichal Meloun if (err == -1) 2910050ea24SMichal Meloun return (ENXIO); 2920050ea24SMichal Meloun if (!(parent_address_cells == 1 || parent_address_cells == 2)) { 2930050ea24SMichal Meloun DPRINTF(sc->dev, "Expect parent #address-cells=[1||2]\n"); 2940050ea24SMichal Meloun return (ENXIO); 2950050ea24SMichal Meloun } 2960050ea24SMichal Meloun 2970050ea24SMichal Meloun err = OF_searchencprop(OF_parent(node), "#size-cells", 2980050ea24SMichal Meloun &parent_size_cells, sizeof(parent_size_cells)); 2990050ea24SMichal Meloun if (err == -1) 3000050ea24SMichal Meloun return (ENXIO); 3010050ea24SMichal Meloun 3020050ea24SMichal Meloun if (!(parent_size_cells == 1 || parent_size_cells == 2)) { 3030050ea24SMichal Meloun DPRINTF(sc->dev, "Expect parent #size-cells = [1||2]\n"); 3040050ea24SMichal Meloun return (ENXIO); 3050050ea24SMichal Meloun } 3060050ea24SMichal Meloun 3070050ea24SMichal Meloun /* Grab the content of reg properties */ 3080050ea24SMichal Meloun nreg = OF_getproplen(node, "reg"); 3090050ea24SMichal Meloun reg = malloc(nreg, M_DEVBUF, M_WAITOK); 3100050ea24SMichal Meloun OF_getencprop(node, "reg", reg, nreg); 3110050ea24SMichal Meloun 3120050ea24SMichal Meloun /* Make sure address & size are 0 */ 3130050ea24SMichal Meloun for (idx = 0; idx < REG_MAX; idx++) { 3140050ea24SMichal Meloun sc->reg[idx].address = 0; 3150050ea24SMichal Meloun sc->reg[idx].size = 0; 3160050ea24SMichal Meloun } 3170050ea24SMichal Meloun 3180050ea24SMichal Meloun /* Loop through reg-names and figure out which reg-name corresponds to 3190050ea24SMichal Meloun * index populate the values into the reg array. 3200050ea24SMichal Meloun */ 3210050ea24SMichal Meloun for (idx = 0, reg_i = 0; idx < REG_MAX && reg_i < nreg; idx++) { 3220050ea24SMichal Meloun err = ofw_bus_find_string_index(node, "reg-names", 3230050ea24SMichal Meloun reg_names[idx], &prop_idx); 3240050ea24SMichal Meloun if (err != 0) 3250050ea24SMichal Meloun continue; 3260050ea24SMichal Meloun 3270050ea24SMichal Meloun for (k = 0; k < parent_address_cells; k++) { 3280050ea24SMichal Meloun sc->reg[prop_idx].address <<= 32; 3290050ea24SMichal Meloun sc->reg[prop_idx].address |= reg[reg_i++]; 3300050ea24SMichal Meloun } 3310050ea24SMichal Meloun 3320050ea24SMichal Meloun for (k = 0; k < parent_size_cells; k++) { 3330050ea24SMichal Meloun sc->reg[prop_idx].size <<= 32; 3340050ea24SMichal Meloun sc->reg[prop_idx].size |= reg[reg_i++]; 3350050ea24SMichal Meloun } 3360050ea24SMichal Meloun 3370050ea24SMichal Meloun if (sc->sc.nranges == 0) 3380050ea24SMichal Meloun sc->offset_reg[prop_idx] = sc->reg[prop_idx].address; 3390050ea24SMichal Meloun else 3400050ea24SMichal Meloun sc->offset_reg[prop_idx] = sc->reg[prop_idx].address - 3410050ea24SMichal Meloun sc->sc.ranges[REG_REV].host; 3420050ea24SMichal Meloun 3430050ea24SMichal Meloun DPRINTF(sc->dev, "reg[%s] adress %#jx size %#jx\n", 3440050ea24SMichal Meloun reg_names[idx], 3450050ea24SMichal Meloun sc->reg[prop_idx].address, 3460050ea24SMichal Meloun sc->reg[prop_idx].size); 3470050ea24SMichal Meloun } 3480050ea24SMichal Meloun free(reg, M_DEVBUF); 3490050ea24SMichal Meloun return (0); 3500050ea24SMichal Meloun } 3510050ea24SMichal Meloun 3520050ea24SMichal Meloun static void 3530050ea24SMichal Meloun parse_idle(struct ti_sysc_softc *sc, const char *name, uint32_t *idle) { 3540050ea24SMichal Meloun phandle_t node; 3550050ea24SMichal Meloun cell_t value[SYSC_IDLE_MAX]; 3560050ea24SMichal Meloun int len, no, i; 3570050ea24SMichal Meloun 3580050ea24SMichal Meloun node = ofw_bus_get_node(sc->dev); 3590050ea24SMichal Meloun 3600050ea24SMichal Meloun if (!OF_hasprop(node, name)) { 3610050ea24SMichal Meloun return; 3620050ea24SMichal Meloun } 3630050ea24SMichal Meloun 3640050ea24SMichal Meloun len = OF_getproplen(node, name); 3650050ea24SMichal Meloun no = len / sizeof(cell_t); 3660050ea24SMichal Meloun if (no >= SYSC_IDLE_MAX) { 3670050ea24SMichal Meloun DPRINTF(sc->dev, "Limit %s\n", name); 3680050ea24SMichal Meloun no = SYSC_IDLE_MAX-1; 3690050ea24SMichal Meloun len = no * sizeof(cell_t); 3700050ea24SMichal Meloun } 3710050ea24SMichal Meloun 3720050ea24SMichal Meloun OF_getencprop(node, name, value, len); 3730050ea24SMichal Meloun for (i = 0; i < no; i++) { 3740050ea24SMichal Meloun idle[i] = value[i]; 3750050ea24SMichal Meloun #if DEBUG_SYSC 3760050ea24SMichal Meloun DPRINTF(sc->dev, "%s[%d] = %d ", 3770050ea24SMichal Meloun name, i, value[i]); 3780050ea24SMichal Meloun switch(value[i]) { 3790050ea24SMichal Meloun case SYSC_IDLE_FORCE: 3800050ea24SMichal Meloun DPRINTF(sc->dev, "SYSC_IDLE_FORCE\n"); 3810050ea24SMichal Meloun break; 3820050ea24SMichal Meloun case SYSC_IDLE_NO: 3830050ea24SMichal Meloun DPRINTF(sc->dev, "SYSC_IDLE_NO\n"); 3840050ea24SMichal Meloun break; 3850050ea24SMichal Meloun case SYSC_IDLE_SMART: 3860050ea24SMichal Meloun DPRINTF(sc->dev, "SYSC_IDLE_SMART\n"); 3870050ea24SMichal Meloun break; 3880050ea24SMichal Meloun case SYSC_IDLE_SMART_WKUP: 3890050ea24SMichal Meloun DPRINTF(sc->dev, "SYSC_IDLE_SMART_WKUP\n"); 3900050ea24SMichal Meloun break; 3910050ea24SMichal Meloun } 3920050ea24SMichal Meloun #endif 3930050ea24SMichal Meloun } 3940050ea24SMichal Meloun for ( ; i < SYSC_IDLE_MAX; i++) 3950050ea24SMichal Meloun idle[i] = -1; 3960050ea24SMichal Meloun } 3970050ea24SMichal Meloun 3980050ea24SMichal Meloun static int 3990050ea24SMichal Meloun ti_sysc_attach_clocks(struct ti_sysc_softc *sc) { 4000050ea24SMichal Meloun clk_t *clk; 4010050ea24SMichal Meloun struct clk_list *clkp; 4020050ea24SMichal Meloun int index, err; 4030050ea24SMichal Meloun 4040050ea24SMichal Meloun clk = malloc(sc->num_clocks*sizeof(clk_t), M_DEVBUF, M_WAITOK | M_ZERO); 4050050ea24SMichal Meloun 4060050ea24SMichal Meloun /* Check if all clocks can be found */ 4070050ea24SMichal Meloun for (index = 0; index < sc->num_clocks; index++) { 4080050ea24SMichal Meloun err = clk_get_by_ofw_index(sc->dev, 0, index, &clk[index]); 4090050ea24SMichal Meloun 4100050ea24SMichal Meloun if (err != 0) { 4110050ea24SMichal Meloun free(clk, M_DEVBUF); 4120050ea24SMichal Meloun return (1); 4130050ea24SMichal Meloun } 4140050ea24SMichal Meloun } 4150050ea24SMichal Meloun 4160050ea24SMichal Meloun /* All clocks are found, add to list */ 4170050ea24SMichal Meloun for (index = 0; index < sc->num_clocks; index++) { 4180050ea24SMichal Meloun clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO); 4190050ea24SMichal Meloun clkp->clk = clk[index]; 4200050ea24SMichal Meloun TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next); 4210050ea24SMichal Meloun } 4220050ea24SMichal Meloun 4230050ea24SMichal Meloun /* Release the clk array */ 4240050ea24SMichal Meloun free(clk, M_DEVBUF); 4250050ea24SMichal Meloun return (0); 4260050ea24SMichal Meloun } 4270050ea24SMichal Meloun 4280050ea24SMichal Meloun static int 4290050ea24SMichal Meloun ti_sysc_simplebus_attach_child(device_t dev) { 4300050ea24SMichal Meloun device_t cdev; 4310050ea24SMichal Meloun phandle_t node, child; 4320050ea24SMichal Meloun struct ti_sysc_softc *sc = device_get_softc(dev); 4330050ea24SMichal Meloun 4340050ea24SMichal Meloun node = ofw_bus_get_node(sc->dev); 4350050ea24SMichal Meloun 4360050ea24SMichal Meloun for (child = OF_child(node); child > 0; child = OF_peer(child)) { 4370050ea24SMichal Meloun cdev = simplebus_add_device(sc->dev, child, 0, NULL, -1, NULL); 4380050ea24SMichal Meloun if (cdev != NULL) 4390050ea24SMichal Meloun device_probe_and_attach(cdev); 4400050ea24SMichal Meloun } 4410050ea24SMichal Meloun return (0); 4420050ea24SMichal Meloun } 4430050ea24SMichal Meloun 4440050ea24SMichal Meloun /* Device interface */ 445b9305a86SEmmanuel Vadot static int 446b9305a86SEmmanuel Vadot ti_sysc_probe(device_t dev) 447b9305a86SEmmanuel Vadot { 448b9305a86SEmmanuel Vadot if (!ofw_bus_status_okay(dev)) 449b9305a86SEmmanuel Vadot return (ENXIO); 450b9305a86SEmmanuel Vadot 451b9305a86SEmmanuel Vadot if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 452b9305a86SEmmanuel Vadot return (ENXIO); 453b9305a86SEmmanuel Vadot 454b9305a86SEmmanuel Vadot device_set_desc(dev, "TI SYSC Interconnect"); 4553dffab60SIan Lepore 456b9305a86SEmmanuel Vadot return (BUS_PROBE_DEFAULT); 457b9305a86SEmmanuel Vadot } 458b9305a86SEmmanuel Vadot 459b9305a86SEmmanuel Vadot static int 460b9305a86SEmmanuel Vadot ti_sysc_attach(device_t dev) 461b9305a86SEmmanuel Vadot { 462b9305a86SEmmanuel Vadot struct ti_sysc_softc *sc; 4630050ea24SMichal Meloun phandle_t node; 4640050ea24SMichal Meloun int err; 4650050ea24SMichal Meloun cell_t value; 466b9305a86SEmmanuel Vadot 467b9305a86SEmmanuel Vadot sc = device_get_softc(dev); 468b9305a86SEmmanuel Vadot sc->dev = dev; 4690050ea24SMichal Meloun sc->device_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 470b9305a86SEmmanuel Vadot 4710050ea24SMichal Meloun node = ofw_bus_get_node(sc->dev); 4720050ea24SMichal Meloun /* ranges - use simplebus */ 4730050ea24SMichal Meloun simplebus_init(sc->dev, node); 474b9305a86SEmmanuel Vadot if (simplebus_fill_ranges(node, &sc->sc) < 0) { 4750050ea24SMichal Meloun DPRINTF(sc->dev, "could not get ranges\n"); 476b9305a86SEmmanuel Vadot return (ENXIO); 477b9305a86SEmmanuel Vadot } 478b9305a86SEmmanuel Vadot 4790050ea24SMichal Meloun if (sc->sc.nranges == 0) { 4800050ea24SMichal Meloun DPRINTF(sc->dev, "nranges == 0\n"); 4810050ea24SMichal Meloun return (ENXIO); 482b9305a86SEmmanuel Vadot } 483b9305a86SEmmanuel Vadot 4840050ea24SMichal Meloun /* Required field reg & reg-names - assume at least "rev" exists */ 4850050ea24SMichal Meloun err = parse_regfields(sc); 4860050ea24SMichal Meloun if (err) { 4870050ea24SMichal Meloun DPRINTF(sc->dev, "parse_regfields failed %d\n", err); 4880050ea24SMichal Meloun return (ENXIO); 4890050ea24SMichal Meloun } 4900050ea24SMichal Meloun 4910050ea24SMichal Meloun /* Optional */ 4920050ea24SMichal Meloun if (OF_hasprop(node, "ti,sysc-mask")) { 4930050ea24SMichal Meloun OF_getencprop(node, "ti,sysc-mask", &value, sizeof(cell_t)); 4940050ea24SMichal Meloun sc->ti_sysc_mask = value; 4950050ea24SMichal Meloun } 4960050ea24SMichal Meloun if (OF_hasprop(node, "ti,syss-mask")) { 4970050ea24SMichal Meloun OF_getencprop(node, "ti,syss-mask", &value, sizeof(cell_t)); 4980050ea24SMichal Meloun sc->ti_syss_mask = value; 4990050ea24SMichal Meloun } 5000050ea24SMichal Meloun if (OF_hasprop(node, "ti,sysc-delay-us")) { 5010050ea24SMichal Meloun OF_getencprop(node, "ti,sysc-delay-us", &value, sizeof(cell_t)); 5020050ea24SMichal Meloun sc->ti_sysc_delay_us = value; 5030050ea24SMichal Meloun } 5040050ea24SMichal Meloun 5050050ea24SMichal Meloun DPRINTF(sc->dev, "sysc_mask %x syss_mask %x delay_us %x\n", 5060050ea24SMichal Meloun sc->ti_sysc_mask, sc->ti_syss_mask, sc->ti_sysc_delay_us); 5070050ea24SMichal Meloun 5080050ea24SMichal Meloun parse_idle(sc, "ti,sysc-midle", sc->ti_sysc_midle); 5090050ea24SMichal Meloun parse_idle(sc, "ti,sysc-sidle", sc->ti_sysc_sidle); 5100050ea24SMichal Meloun 5110050ea24SMichal Meloun if (OF_hasprop(node, "ti,no-reset-on-init")) 5120050ea24SMichal Meloun sc->ti_no_reset_on_init = true; 5130050ea24SMichal Meloun else 5140050ea24SMichal Meloun sc->ti_no_reset_on_init = false; 5150050ea24SMichal Meloun 5160050ea24SMichal Meloun if (OF_hasprop(node, "ti,no-idle-on-init")) 5170050ea24SMichal Meloun sc->ti_no_idle_on_init = true; 5180050ea24SMichal Meloun else 5190050ea24SMichal Meloun sc->ti_no_idle_on_init = false; 5200050ea24SMichal Meloun 5210050ea24SMichal Meloun if (OF_hasprop(node, "ti,no-idle")) 5220050ea24SMichal Meloun sc->ti_no_idle = true; 5230050ea24SMichal Meloun else 5240050ea24SMichal Meloun sc->ti_no_idle = false; 5250050ea24SMichal Meloun 5260050ea24SMichal Meloun DPRINTF(sc->dev, 5270050ea24SMichal Meloun "no-reset-on-init %d, no-idle-on-init %d, no-idle %d\n", 5280050ea24SMichal Meloun sc->ti_no_reset_on_init, 5290050ea24SMichal Meloun sc->ti_no_idle_on_init, 5300050ea24SMichal Meloun sc->ti_no_idle); 5310050ea24SMichal Meloun 5320050ea24SMichal Meloun if (OF_hasprop(node, "clocks")) { 5330050ea24SMichal Meloun struct clock_cell_info cell_info; 5340050ea24SMichal Meloun read_clock_cells(sc->dev, &cell_info); 5350050ea24SMichal Meloun free(cell_info.clock_cells, M_DEVBUF); 5360050ea24SMichal Meloun free(cell_info.clock_cells_ncells, M_DEVBUF); 5370050ea24SMichal Meloun 5380050ea24SMichal Meloun sc->num_clocks = cell_info.num_real_clocks; 5390050ea24SMichal Meloun TAILQ_INIT(&sc->clk_list); 5400050ea24SMichal Meloun 5410050ea24SMichal Meloun err = ti_sysc_attach_clocks(sc); 5420050ea24SMichal Meloun if (err) { 5430050ea24SMichal Meloun DPRINTF(sc->dev, "Failed to attach clocks\n"); 5440050ea24SMichal Meloun return (bus_generic_attach(sc->dev)); 5450050ea24SMichal Meloun } 5460050ea24SMichal Meloun } 5470050ea24SMichal Meloun 5480050ea24SMichal Meloun err = ti_sysc_simplebus_attach_child(sc->dev); 5490050ea24SMichal Meloun if (err) { 5500050ea24SMichal Meloun DPRINTF(sc->dev, "ti_sysc_simplebus_attach_child %d\n", 5510050ea24SMichal Meloun err); 5520050ea24SMichal Meloun return (err); 5530050ea24SMichal Meloun } 5540050ea24SMichal Meloun 5550050ea24SMichal Meloun sc->attach_done = true; 5560050ea24SMichal Meloun 5570050ea24SMichal Meloun return (bus_generic_attach(sc->dev)); 558b9305a86SEmmanuel Vadot } 559b9305a86SEmmanuel Vadot 560b9305a86SEmmanuel Vadot static int 561b9305a86SEmmanuel Vadot ti_sysc_detach(device_t dev) 562b9305a86SEmmanuel Vadot { 563b9305a86SEmmanuel Vadot return (EBUSY); 564b9305a86SEmmanuel Vadot } 565b9305a86SEmmanuel Vadot 5660050ea24SMichal Meloun /* Bus interface */ 5670050ea24SMichal Meloun static void 5680050ea24SMichal Meloun ti_sysc_new_pass(device_t dev) 5690050ea24SMichal Meloun { 5700050ea24SMichal Meloun struct ti_sysc_softc *sc; 5710050ea24SMichal Meloun int err; 5720050ea24SMichal Meloun phandle_t node; 5730050ea24SMichal Meloun 5740050ea24SMichal Meloun sc = device_get_softc(dev); 5750050ea24SMichal Meloun 5760050ea24SMichal Meloun if (sc->attach_done) { 5770050ea24SMichal Meloun bus_generic_new_pass(sc->dev); 5780050ea24SMichal Meloun return; 5790050ea24SMichal Meloun } 5800050ea24SMichal Meloun 5810050ea24SMichal Meloun node = ofw_bus_get_node(sc->dev); 5820050ea24SMichal Meloun if (OF_hasprop(node, "clocks")) { 5830050ea24SMichal Meloun err = ti_sysc_attach_clocks(sc); 5840050ea24SMichal Meloun if (err) { 5850050ea24SMichal Meloun DPRINTF(sc->dev, "Failed to attach clocks\n"); 5860050ea24SMichal Meloun return; 5870050ea24SMichal Meloun } 5880050ea24SMichal Meloun } 5890050ea24SMichal Meloun 5900050ea24SMichal Meloun err = ti_sysc_simplebus_attach_child(sc->dev); 5910050ea24SMichal Meloun if (err) { 5920050ea24SMichal Meloun DPRINTF(sc->dev, 5930050ea24SMichal Meloun "ti_sysc_simplebus_attach_child failed %d\n", err); 5940050ea24SMichal Meloun return; 5950050ea24SMichal Meloun } 5960050ea24SMichal Meloun sc->attach_done = true; 5970050ea24SMichal Meloun 5980050ea24SMichal Meloun bus_generic_attach(sc->dev); 5990050ea24SMichal Meloun } 6000050ea24SMichal Meloun 601b9305a86SEmmanuel Vadot static device_method_t ti_sysc_methods[] = { 602b9305a86SEmmanuel Vadot /* Device interface */ 603b9305a86SEmmanuel Vadot DEVMETHOD(device_probe, ti_sysc_probe), 604b9305a86SEmmanuel Vadot DEVMETHOD(device_attach, ti_sysc_attach), 605b9305a86SEmmanuel Vadot DEVMETHOD(device_detach, ti_sysc_detach), 606b9305a86SEmmanuel Vadot 6070050ea24SMichal Meloun /* Bus interface */ 6080050ea24SMichal Meloun DEVMETHOD(bus_new_pass, ti_sysc_new_pass), 6090050ea24SMichal Meloun 610b9305a86SEmmanuel Vadot DEVMETHOD_END 611b9305a86SEmmanuel Vadot }; 612b9305a86SEmmanuel Vadot 613b9305a86SEmmanuel Vadot DEFINE_CLASS_1(ti_sysc, ti_sysc_driver, ti_sysc_methods, 614b9305a86SEmmanuel Vadot sizeof(struct ti_sysc_softc), simplebus_driver); 615b9305a86SEmmanuel Vadot 6168537e671SJohn Baldwin EARLY_DRIVER_MODULE(ti_sysc, simplebus, ti_sysc_driver, 0, 0, 6178537e671SJohn Baldwin BUS_PASS_BUS + BUS_PASS_ORDER_FIRST); 618