1/*- 2 * Copyright (c) 2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28#include <machine/asm.h> 29#include <machine/armreg.h> 30__FBSDID("$FreeBSD$"); 31 32#include "assym.inc" 33 34 .text 35 36.macro save_registers el 37.if \el == 1 38 mov x18, sp 39 sub sp, sp, #128 40.endif 41 sub sp, sp, #(TF_SIZE + 16) 42 stp x29, x30, [sp, #(TF_SIZE)] 43 stp x28, x29, [sp, #(TF_X + 28 * 8)] 44 stp x26, x27, [sp, #(TF_X + 26 * 8)] 45 stp x24, x25, [sp, #(TF_X + 24 * 8)] 46 stp x22, x23, [sp, #(TF_X + 22 * 8)] 47 stp x20, x21, [sp, #(TF_X + 20 * 8)] 48 stp x18, x19, [sp, #(TF_X + 18 * 8)] 49 stp x16, x17, [sp, #(TF_X + 16 * 8)] 50 stp x14, x15, [sp, #(TF_X + 14 * 8)] 51 stp x12, x13, [sp, #(TF_X + 12 * 8)] 52 stp x10, x11, [sp, #(TF_X + 10 * 8)] 53 stp x8, x9, [sp, #(TF_X + 8 * 8)] 54 stp x6, x7, [sp, #(TF_X + 6 * 8)] 55 stp x4, x5, [sp, #(TF_X + 4 * 8)] 56 stp x2, x3, [sp, #(TF_X + 2 * 8)] 57 stp x0, x1, [sp, #(TF_X + 0 * 8)] 58 mrs x10, elr_el1 59 mrs x11, spsr_el1 60 mrs x12, esr_el1 61.if \el == 0 62 mrs x18, sp_el0 63.endif 64 str x10, [sp, #(TF_ELR)] 65 stp w11, w12, [sp, #(TF_SPSR)] 66 stp x18, lr, [sp, #(TF_SP)] 67 mrs x18, tpidr_el1 68 add x29, sp, #(TF_SIZE) 69.if \el == 0 70 /* Apply the SSBD (CVE-2018-3639) workaround if needed */ 71 ldr x1, [x18, #PC_SSBD] 72 cbz x1, 1f 73 mov w0, #1 74 blr x1 751: 76.endif 77.endm 78 79.macro restore_registers el 80.if \el == 1 81 msr daifset, #2 82 /* 83 * Disable interrupts, x18 may change in the interrupt exception 84 * handler. For EL0 exceptions, do_ast already did this. 85 */ 86.endif 87.if \el == 0 88 /* Remove the SSBD (CVE-2018-3639) workaround if needed */ 89 ldr x1, [x18, #PC_SSBD] 90 cbz x1, 1f 91 mov w0, #0 92 blr x1 931: 94.endif 95 ldp x18, lr, [sp, #(TF_SP)] 96 ldp x10, x11, [sp, #(TF_ELR)] 97.if \el == 0 98 msr sp_el0, x18 99.endif 100 msr spsr_el1, x11 101 msr elr_el1, x10 102 ldp x0, x1, [sp, #(TF_X + 0 * 8)] 103 ldp x2, x3, [sp, #(TF_X + 2 * 8)] 104 ldp x4, x5, [sp, #(TF_X + 4 * 8)] 105 ldp x6, x7, [sp, #(TF_X + 6 * 8)] 106 ldp x8, x9, [sp, #(TF_X + 8 * 8)] 107 ldp x10, x11, [sp, #(TF_X + 10 * 8)] 108 ldp x12, x13, [sp, #(TF_X + 12 * 8)] 109 ldp x14, x15, [sp, #(TF_X + 14 * 8)] 110 ldp x16, x17, [sp, #(TF_X + 16 * 8)] 111.if \el == 0 112 /* 113 * We only restore the callee saved registers when returning to 114 * userland as they may have been updated by a system call or signal. 115 */ 116 ldp x18, x19, [sp, #(TF_X + 18 * 8)] 117 ldp x20, x21, [sp, #(TF_X + 20 * 8)] 118 ldp x22, x23, [sp, #(TF_X + 22 * 8)] 119 ldp x24, x25, [sp, #(TF_X + 24 * 8)] 120 ldp x26, x27, [sp, #(TF_X + 26 * 8)] 121 ldp x28, x29, [sp, #(TF_X + 28 * 8)] 122.else 123 ldr x29, [sp, #(TF_X + 29 * 8)] 124.endif 125.if \el == 0 126 add sp, sp, #(TF_SIZE + 16) 127.else 128 mov sp, x18 129 mrs x18, tpidr_el1 130.endif 131.endm 132 133.macro do_ast 134 mrs x19, daif 135 /* Make sure the IRQs are enabled before calling ast() */ 136 bic x19, x19, #PSR_I 1371: 138 /* Disable interrupts */ 139 msr daifset, #2 140 141 /* Read the current thread flags */ 142 ldr x1, [x18, #PC_CURTHREAD] /* Load curthread */ 143 ldr x2, [x1, #TD_FLAGS] 144 145 /* Check if we have either bits set */ 146 mov x3, #((TDF_ASTPENDING|TDF_NEEDRESCHED) >> 8) 147 lsl x3, x3, #8 148 and x2, x2, x3 149 cbz x2, 2f 150 151 /* Restore interrupts */ 152 msr daif, x19 153 154 /* handle the ast */ 155 mov x0, sp 156 bl _C_LABEL(ast) 157 158 /* Re-check for new ast scheduled */ 159 b 1b 1602: 161.endm 162 163ENTRY(handle_el1h_sync) 164 save_registers 1 165 ldr x0, [x18, #PC_CURTHREAD] 166 mov x1, sp 167 bl do_el1h_sync 168 restore_registers 1 169 eret 170END(handle_el1h_sync) 171 172ENTRY(handle_el1h_irq) 173 save_registers 1 174 mov x0, sp 175 bl intr_irq_handler 176 restore_registers 1 177 eret 178END(handle_el1h_irq) 179 180ENTRY(handle_el0_sync) 181 save_registers 0 182 ldr x0, [x18, #PC_CURTHREAD] 183 mov x1, sp 184 str x1, [x0, #TD_FRAME] 185 bl do_el0_sync 186 do_ast 187 restore_registers 0 188 eret 189END(handle_el0_sync) 190 191ENTRY(handle_el0_irq) 192 save_registers 0 193 mov x0, sp 194 bl intr_irq_handler 195 do_ast 196 restore_registers 0 197 eret 198END(handle_el0_irq) 199 200ENTRY(handle_serror) 201 save_registers 0 202 mov x0, sp 2031: bl do_serror 204 b 1b 205END(handle_serror) 206 207ENTRY(handle_empty_exception) 208 save_registers 0 209 mov x0, sp 2101: bl unhandled_exception 211 b 1b 212END(handle_unhandled_exception) 213 214.macro vempty 215 .align 7 216 b handle_empty_exception 217.endm 218 219.macro vector name 220 .align 7 221 b handle_\name 222.endm 223 224 .align 11 225 .globl exception_vectors 226exception_vectors: 227 vempty /* Synchronous EL1t */ 228 vempty /* IRQ EL1t */ 229 vempty /* FIQ EL1t */ 230 vempty /* Error EL1t */ 231 232 vector el1h_sync /* Synchronous EL1h */ 233 vector el1h_irq /* IRQ EL1h */ 234 vempty /* FIQ EL1h */ 235 vector serror /* Error EL1h */ 236 237 vector el0_sync /* Synchronous 64-bit EL0 */ 238 vector el0_irq /* IRQ 64-bit EL0 */ 239 vempty /* FIQ 64-bit EL0 */ 240 vector serror /* Error 64-bit EL0 */ 241 242 vector el0_sync /* Synchronous 32-bit EL0 */ 243 vector el0_irq /* IRQ 32-bit EL0 */ 244 vempty /* FIQ 32-bit EL0 */ 245 vector serror /* Error 32-bit EL0 */ 246 247