1 /*- 2 * Copyright (c) 2015-2016 The FreeBSD Foundation 3 * 4 * This software was developed by Andrew Turner under 5 * the sponsorship of the FreeBSD Foundation. 6 * 7 * This software was developed by Semihalf under 8 * the sponsorship of the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include "opt_acpi.h" 33 #include "opt_platform.h" 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bitstring.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/ktr.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/rman.h> 47 #include <sys/pcpu.h> 48 #include <sys/proc.h> 49 #include <sys/cpuset.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/smp.h> 53 #include <sys/interrupt.h> 54 55 #include <vm/vm.h> 56 #include <vm/pmap.h> 57 58 #include <machine/bus.h> 59 #include <machine/cpu.h> 60 #include <machine/intr.h> 61 62 #ifdef FDT 63 #include <dev/fdt/fdt_intr.h> 64 #include <dev/ofw/ofw_bus_subr.h> 65 #endif 66 67 #ifdef DEV_ACPI 68 #include <contrib/dev/acpica/include/acpi.h> 69 #include <dev/acpica/acpivar.h> 70 #endif 71 72 #include "gic_if.h" 73 #include "pic_if.h" 74 #include "msi_if.h" 75 76 #include <arm/arm/gic_common.h> 77 #include "gic_v3_reg.h" 78 #include "gic_v3_var.h" 79 80 static bus_print_child_t gic_v3_print_child; 81 static bus_get_domain_t gic_v3_get_domain; 82 static bus_read_ivar_t gic_v3_read_ivar; 83 static bus_write_ivar_t gic_v3_write_ivar; 84 static bus_alloc_resource_t gic_v3_alloc_resource; 85 86 static pic_disable_intr_t gic_v3_disable_intr; 87 static pic_enable_intr_t gic_v3_enable_intr; 88 static pic_map_intr_t gic_v3_map_intr; 89 static pic_setup_intr_t gic_v3_setup_intr; 90 static pic_teardown_intr_t gic_v3_teardown_intr; 91 static pic_post_filter_t gic_v3_post_filter; 92 static pic_post_ithread_t gic_v3_post_ithread; 93 static pic_pre_ithread_t gic_v3_pre_ithread; 94 static pic_bind_intr_t gic_v3_bind_intr; 95 #ifdef SMP 96 static pic_init_secondary_t gic_v3_init_secondary; 97 static pic_ipi_send_t gic_v3_ipi_send; 98 static pic_ipi_setup_t gic_v3_ipi_setup; 99 #endif 100 101 static gic_reserve_msi_range_t gic_v3_reserve_msi_range; 102 static gic_alloc_msi_t gic_v3_gic_alloc_msi; 103 static gic_release_msi_t gic_v3_gic_release_msi; 104 static gic_alloc_msix_t gic_v3_gic_alloc_msix; 105 static gic_release_msix_t gic_v3_gic_release_msix; 106 107 static msi_alloc_msi_t gic_v3_alloc_msi; 108 static msi_release_msi_t gic_v3_release_msi; 109 static msi_alloc_msix_t gic_v3_alloc_msix; 110 static msi_release_msix_t gic_v3_release_msix; 111 static msi_map_msi_t gic_v3_map_msi; 112 113 static u_int gic_irq_cpu; 114 #ifdef SMP 115 static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1]; 116 static u_int sgi_first_unused = GIC_FIRST_SGI; 117 #endif 118 119 static device_method_t gic_v3_methods[] = { 120 /* Device interface */ 121 DEVMETHOD(device_detach, gic_v3_detach), 122 123 /* Bus interface */ 124 DEVMETHOD(bus_print_child, gic_v3_print_child), 125 DEVMETHOD(bus_get_domain, gic_v3_get_domain), 126 DEVMETHOD(bus_read_ivar, gic_v3_read_ivar), 127 DEVMETHOD(bus_write_ivar, gic_v3_write_ivar), 128 DEVMETHOD(bus_alloc_resource, gic_v3_alloc_resource), 129 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 130 131 /* Interrupt controller interface */ 132 DEVMETHOD(pic_disable_intr, gic_v3_disable_intr), 133 DEVMETHOD(pic_enable_intr, gic_v3_enable_intr), 134 DEVMETHOD(pic_map_intr, gic_v3_map_intr), 135 DEVMETHOD(pic_setup_intr, gic_v3_setup_intr), 136 DEVMETHOD(pic_teardown_intr, gic_v3_teardown_intr), 137 DEVMETHOD(pic_post_filter, gic_v3_post_filter), 138 DEVMETHOD(pic_post_ithread, gic_v3_post_ithread), 139 DEVMETHOD(pic_pre_ithread, gic_v3_pre_ithread), 140 #ifdef SMP 141 DEVMETHOD(pic_bind_intr, gic_v3_bind_intr), 142 DEVMETHOD(pic_init_secondary, gic_v3_init_secondary), 143 DEVMETHOD(pic_ipi_send, gic_v3_ipi_send), 144 DEVMETHOD(pic_ipi_setup, gic_v3_ipi_setup), 145 #endif 146 147 /* MSI/MSI-X */ 148 DEVMETHOD(msi_alloc_msi, gic_v3_alloc_msi), 149 DEVMETHOD(msi_release_msi, gic_v3_release_msi), 150 DEVMETHOD(msi_alloc_msix, gic_v3_alloc_msix), 151 DEVMETHOD(msi_release_msix, gic_v3_release_msix), 152 DEVMETHOD(msi_map_msi, gic_v3_map_msi), 153 154 /* GIC */ 155 DEVMETHOD(gic_reserve_msi_range, gic_v3_reserve_msi_range), 156 DEVMETHOD(gic_alloc_msi, gic_v3_gic_alloc_msi), 157 DEVMETHOD(gic_release_msi, gic_v3_gic_release_msi), 158 DEVMETHOD(gic_alloc_msix, gic_v3_gic_alloc_msix), 159 DEVMETHOD(gic_release_msix, gic_v3_gic_release_msix), 160 161 /* End */ 162 DEVMETHOD_END 163 }; 164 165 DEFINE_CLASS_0(gic, gic_v3_driver, gic_v3_methods, 166 sizeof(struct gic_v3_softc)); 167 168 /* 169 * Driver-specific definitions. 170 */ 171 MALLOC_DEFINE(M_GIC_V3, "GICv3", GIC_V3_DEVSTR); 172 173 /* 174 * Helper functions and definitions. 175 */ 176 /* Destination registers, either Distributor or Re-Distributor */ 177 enum gic_v3_xdist { 178 DIST = 0, 179 REDIST, 180 }; 181 182 struct gic_v3_irqsrc { 183 struct intr_irqsrc gi_isrc; 184 uint32_t gi_irq; 185 enum intr_polarity gi_pol; 186 enum intr_trigger gi_trig; 187 #define GI_FLAG_MSI (1 << 1) /* This interrupt source should only */ 188 /* be used for MSI/MSI-X interrupts */ 189 #define GI_FLAG_MSI_USED (1 << 2) /* This irq is already allocated */ 190 /* for a MSI/MSI-X interrupt */ 191 u_int gi_flags; 192 }; 193 194 /* Helper routines starting with gic_v3_ */ 195 static int gic_v3_dist_init(struct gic_v3_softc *); 196 static int gic_v3_redist_alloc(struct gic_v3_softc *); 197 static int gic_v3_redist_find(struct gic_v3_softc *); 198 static int gic_v3_redist_init(struct gic_v3_softc *); 199 static int gic_v3_cpu_init(struct gic_v3_softc *); 200 static void gic_v3_wait_for_rwp(struct gic_v3_softc *, enum gic_v3_xdist); 201 202 /* A sequence of init functions for primary (boot) CPU */ 203 typedef int (*gic_v3_initseq_t) (struct gic_v3_softc *); 204 /* Primary CPU initialization sequence */ 205 static gic_v3_initseq_t gic_v3_primary_init[] = { 206 gic_v3_dist_init, 207 gic_v3_redist_alloc, 208 gic_v3_redist_init, 209 gic_v3_cpu_init, 210 NULL 211 }; 212 213 #ifdef SMP 214 /* Secondary CPU initialization sequence */ 215 static gic_v3_initseq_t gic_v3_secondary_init[] = { 216 gic_v3_redist_init, 217 gic_v3_cpu_init, 218 NULL 219 }; 220 #endif 221 222 uint32_t 223 gic_r_read_4(device_t dev, bus_size_t offset) 224 { 225 struct gic_v3_softc *sc; 226 struct resource *rdist; 227 228 sc = device_get_softc(dev); 229 rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res; 230 return (bus_read_4(rdist, offset)); 231 } 232 233 uint64_t 234 gic_r_read_8(device_t dev, bus_size_t offset) 235 { 236 struct gic_v3_softc *sc; 237 struct resource *rdist; 238 239 sc = device_get_softc(dev); 240 rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res; 241 return (bus_read_8(rdist, offset)); 242 } 243 244 void 245 gic_r_write_4(device_t dev, bus_size_t offset, uint32_t val) 246 { 247 struct gic_v3_softc *sc; 248 struct resource *rdist; 249 250 sc = device_get_softc(dev); 251 rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res; 252 bus_write_4(rdist, offset, val); 253 } 254 255 void 256 gic_r_write_8(device_t dev, bus_size_t offset, uint64_t val) 257 { 258 struct gic_v3_softc *sc; 259 struct resource *rdist; 260 261 sc = device_get_softc(dev); 262 rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res; 263 bus_write_8(rdist, offset, val); 264 } 265 266 static void 267 gic_v3_reserve_msi_range(device_t dev, u_int start, u_int count) 268 { 269 struct gic_v3_softc *sc; 270 int i; 271 272 sc = device_get_softc(dev); 273 274 KASSERT((start + count) < sc->gic_nirqs, 275 ("%s: Trying to allocate too many MSI IRQs: %d + %d > %d", __func__, 276 start, count, sc->gic_nirqs)); 277 for (i = 0; i < count; i++) { 278 KASSERT(sc->gic_irqs[start + i].gi_isrc.isrc_handlers == 0, 279 ("%s: MSI interrupt %d already has a handler", __func__, 280 count + i)); 281 KASSERT(sc->gic_irqs[start + i].gi_pol == INTR_POLARITY_CONFORM, 282 ("%s: MSI interrupt %d already has a polarity", __func__, 283 count + i)); 284 KASSERT(sc->gic_irqs[start + i].gi_trig == INTR_TRIGGER_CONFORM, 285 ("%s: MSI interrupt %d already has a trigger", __func__, 286 count + i)); 287 sc->gic_irqs[start + i].gi_pol = INTR_POLARITY_HIGH; 288 sc->gic_irqs[start + i].gi_trig = INTR_TRIGGER_EDGE; 289 sc->gic_irqs[start + i].gi_flags |= GI_FLAG_MSI; 290 } 291 } 292 293 /* 294 * Device interface. 295 */ 296 int 297 gic_v3_attach(device_t dev) 298 { 299 struct gic_v3_softc *sc; 300 gic_v3_initseq_t *init_func; 301 uint32_t typer; 302 int rid; 303 int err; 304 size_t i; 305 u_int irq; 306 const char *name; 307 308 sc = device_get_softc(dev); 309 sc->gic_registered = FALSE; 310 sc->dev = dev; 311 err = 0; 312 313 /* Initialize mutex */ 314 mtx_init(&sc->gic_mtx, "GICv3 lock", NULL, MTX_SPIN); 315 316 /* 317 * Allocate array of struct resource. 318 * One entry for Distributor and all remaining for Re-Distributor. 319 */ 320 sc->gic_res = malloc( 321 sizeof(*sc->gic_res) * (sc->gic_redists.nregions + 1), 322 M_GIC_V3, M_WAITOK); 323 324 /* Now allocate corresponding resources */ 325 for (i = 0, rid = 0; i < (sc->gic_redists.nregions + 1); i++, rid++) { 326 sc->gic_res[rid] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 327 &rid, RF_ACTIVE); 328 if (sc->gic_res[rid] == NULL) 329 return (ENXIO); 330 } 331 332 /* 333 * Distributor interface 334 */ 335 sc->gic_dist = sc->gic_res[0]; 336 337 /* 338 * Re-Dristributor interface 339 */ 340 /* Allocate space under region descriptions */ 341 sc->gic_redists.regions = malloc( 342 sizeof(*sc->gic_redists.regions) * sc->gic_redists.nregions, 343 M_GIC_V3, M_WAITOK); 344 345 /* Fill-up bus_space information for each region. */ 346 for (i = 0, rid = 1; i < sc->gic_redists.nregions; i++, rid++) 347 sc->gic_redists.regions[i] = sc->gic_res[rid]; 348 349 /* Get the number of supported SPI interrupts */ 350 typer = gic_d_read(sc, 4, GICD_TYPER); 351 sc->gic_nirqs = GICD_TYPER_I_NUM(typer); 352 if (sc->gic_nirqs > GIC_I_NUM_MAX) 353 sc->gic_nirqs = GIC_I_NUM_MAX; 354 355 sc->gic_irqs = malloc(sizeof(*sc->gic_irqs) * sc->gic_nirqs, 356 M_GIC_V3, M_WAITOK | M_ZERO); 357 name = device_get_nameunit(dev); 358 for (irq = 0; irq < sc->gic_nirqs; irq++) { 359 struct intr_irqsrc *isrc; 360 361 sc->gic_irqs[irq].gi_irq = irq; 362 sc->gic_irqs[irq].gi_pol = INTR_POLARITY_CONFORM; 363 sc->gic_irqs[irq].gi_trig = INTR_TRIGGER_CONFORM; 364 365 isrc = &sc->gic_irqs[irq].gi_isrc; 366 if (irq <= GIC_LAST_SGI) { 367 err = intr_isrc_register(isrc, sc->dev, 368 INTR_ISRCF_IPI, "%s,i%u", name, irq - GIC_FIRST_SGI); 369 } else if (irq <= GIC_LAST_PPI) { 370 err = intr_isrc_register(isrc, sc->dev, 371 INTR_ISRCF_PPI, "%s,p%u", name, irq - GIC_FIRST_PPI); 372 } else { 373 err = intr_isrc_register(isrc, sc->dev, 0, 374 "%s,s%u", name, irq - GIC_FIRST_SPI); 375 } 376 if (err != 0) { 377 /* XXX call intr_isrc_deregister() */ 378 free(sc->gic_irqs, M_DEVBUF); 379 return (err); 380 } 381 } 382 383 mtx_init(&sc->gic_mbi_mtx, "GICv3 mbi lock", NULL, MTX_DEF); 384 if (sc->gic_mbi_start > 0) { 385 if (!sc->gic_mbi_end) { 386 /* 387 * This is to address SPI based msi ranges, where 388 * SPI range is not specified in ACPI 389 */ 390 sc->gic_mbi_end = sc->gic_nirqs - 1; 391 } 392 gic_v3_reserve_msi_range(dev, sc->gic_mbi_start, 393 sc->gic_mbi_end - sc->gic_mbi_start); 394 395 if (bootverbose) { 396 device_printf(dev, "using spi %u to %u\n", sc->gic_mbi_start, 397 sc->gic_mbi_end); 398 } 399 } 400 401 /* 402 * Read the Peripheral ID2 register. This is an implementation 403 * defined register, but seems to be implemented in all GICv3 404 * parts and Linux expects it to be there. 405 */ 406 sc->gic_pidr2 = gic_d_read(sc, 4, GICD_PIDR2); 407 408 /* Get the number of supported interrupt identifier bits */ 409 sc->gic_idbits = GICD_TYPER_IDBITS(typer); 410 411 if (bootverbose) { 412 device_printf(dev, "SPIs: %u, IDs: %u\n", 413 sc->gic_nirqs, (1 << sc->gic_idbits) - 1); 414 } 415 416 /* Train init sequence for boot CPU */ 417 for (init_func = gic_v3_primary_init; *init_func != NULL; init_func++) { 418 err = (*init_func)(sc); 419 if (err != 0) 420 return (err); 421 } 422 423 return (0); 424 } 425 426 int 427 gic_v3_detach(device_t dev) 428 { 429 struct gic_v3_softc *sc; 430 size_t i; 431 int rid; 432 433 sc = device_get_softc(dev); 434 435 if (device_is_attached(dev)) { 436 /* 437 * XXX: We should probably deregister PIC 438 */ 439 if (sc->gic_registered) 440 panic("Trying to detach registered PIC"); 441 } 442 for (rid = 0; rid < (sc->gic_redists.nregions + 1); rid++) 443 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->gic_res[rid]); 444 445 for (i = 0; i <= mp_maxid; i++) 446 free(sc->gic_redists.pcpu[i], M_GIC_V3); 447 448 free(sc->ranges, M_GIC_V3); 449 free(sc->gic_res, M_GIC_V3); 450 free(sc->gic_redists.regions, M_GIC_V3); 451 452 return (0); 453 } 454 455 static int 456 gic_v3_print_child(device_t bus, device_t child) 457 { 458 struct resource_list *rl; 459 int retval = 0; 460 461 rl = BUS_GET_RESOURCE_LIST(bus, child); 462 KASSERT(rl != NULL, ("%s: No resource list", __func__)); 463 retval += bus_print_child_header(bus, child); 464 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 465 retval += bus_print_child_footer(bus, child); 466 467 return (retval); 468 } 469 470 static int 471 gic_v3_get_domain(device_t dev, device_t child, int *domain) 472 { 473 struct gic_v3_devinfo *di; 474 475 di = device_get_ivars(child); 476 if (di->gic_domain < 0) 477 return (ENOENT); 478 479 *domain = di->gic_domain; 480 return (0); 481 } 482 483 static int 484 gic_v3_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 485 { 486 struct gic_v3_softc *sc; 487 struct gic_v3_devinfo *di; 488 489 sc = device_get_softc(dev); 490 491 switch (which) { 492 case GICV3_IVAR_NIRQS: 493 *result = (intr_nirq - sc->gic_nirqs) / sc->gic_nchildren; 494 return (0); 495 case GICV3_IVAR_REDIST: 496 *result = (uintptr_t)sc->gic_redists.pcpu[PCPU_GET(cpuid)]; 497 return (0); 498 case GIC_IVAR_HW_REV: 499 KASSERT( 500 GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv3 || 501 GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv4, 502 ("gic_v3_read_ivar: Invalid GIC architecture: %d (%.08X)", 503 GICR_PIDR2_ARCH(sc->gic_pidr2), sc->gic_pidr2)); 504 *result = GICR_PIDR2_ARCH(sc->gic_pidr2); 505 return (0); 506 case GIC_IVAR_BUS: 507 KASSERT(sc->gic_bus != GIC_BUS_UNKNOWN, 508 ("gic_v3_read_ivar: Unknown bus type")); 509 KASSERT(sc->gic_bus <= GIC_BUS_MAX, 510 ("gic_v3_read_ivar: Invalid bus type %u", sc->gic_bus)); 511 *result = sc->gic_bus; 512 return (0); 513 case GIC_IVAR_VGIC: 514 di = device_get_ivars(child); 515 if (di == NULL) 516 return (EINVAL); 517 *result = di->is_vgic; 518 return (0); 519 } 520 521 return (ENOENT); 522 } 523 524 static int 525 gic_v3_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 526 { 527 switch(which) { 528 case GICV3_IVAR_NIRQS: 529 case GICV3_IVAR_REDIST: 530 case GIC_IVAR_HW_REV: 531 case GIC_IVAR_BUS: 532 return (EINVAL); 533 } 534 535 return (ENOENT); 536 } 537 538 static struct resource * 539 gic_v3_alloc_resource(device_t bus, device_t child, int type, int *rid, 540 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 541 { 542 struct gic_v3_softc *sc; 543 struct resource_list_entry *rle; 544 struct resource_list *rl; 545 int j; 546 547 /* We only allocate memory */ 548 if (type != SYS_RES_MEMORY) 549 return (NULL); 550 551 sc = device_get_softc(bus); 552 553 if (RMAN_IS_DEFAULT_RANGE(start, end)) { 554 rl = BUS_GET_RESOURCE_LIST(bus, child); 555 if (rl == NULL) 556 return (NULL); 557 558 /* Find defaults for this rid */ 559 rle = resource_list_find(rl, type, *rid); 560 if (rle == NULL) 561 return (NULL); 562 563 start = rle->start; 564 end = rle->end; 565 count = rle->count; 566 } 567 568 /* Remap through ranges property */ 569 for (j = 0; j < sc->nranges; j++) { 570 if (start >= sc->ranges[j].bus && end < 571 sc->ranges[j].bus + sc->ranges[j].size) { 572 start -= sc->ranges[j].bus; 573 start += sc->ranges[j].host; 574 end -= sc->ranges[j].bus; 575 end += sc->ranges[j].host; 576 break; 577 } 578 } 579 if (j == sc->nranges && sc->nranges != 0) { 580 if (bootverbose) 581 device_printf(bus, "Could not map resource " 582 "%#jx-%#jx\n", (uintmax_t)start, (uintmax_t)end); 583 584 return (NULL); 585 } 586 587 return (bus_generic_alloc_resource(bus, child, type, rid, start, end, 588 count, flags)); 589 } 590 591 int 592 arm_gic_v3_intr(void *arg) 593 { 594 struct gic_v3_softc *sc = arg; 595 struct gic_v3_irqsrc *gi; 596 struct intr_pic *pic; 597 uint64_t active_irq; 598 struct trapframe *tf; 599 600 pic = sc->gic_pic; 601 602 while (1) { 603 if (CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1) { 604 /* 605 * Hardware: Cavium ThunderX 606 * Chip revision: Pass 1.0 (early version) 607 * Pass 1.1 (production) 608 * ERRATUM: 22978, 23154 609 */ 610 __asm __volatile( 611 "nop;nop;nop;nop;nop;nop;nop;nop; \n" 612 "mrs %0, ICC_IAR1_EL1 \n" 613 "nop;nop;nop;nop; \n" 614 "dsb sy \n" 615 : "=&r" (active_irq)); 616 } else { 617 active_irq = gic_icc_read(IAR1); 618 } 619 620 if (active_irq >= GIC_FIRST_LPI) { 621 intr_child_irq_handler(pic, active_irq); 622 continue; 623 } 624 625 if (__predict_false(active_irq >= sc->gic_nirqs)) 626 return (FILTER_HANDLED); 627 628 tf = curthread->td_intr_frame; 629 gi = &sc->gic_irqs[active_irq]; 630 if (active_irq <= GIC_LAST_SGI) { 631 /* Call EOI for all IPI before dispatch. */ 632 gic_icc_write(EOIR1, (uint64_t)active_irq); 633 #ifdef SMP 634 intr_ipi_dispatch(sgi_to_ipi[gi->gi_irq], tf); 635 #else 636 device_printf(sc->dev, "SGI %ju on UP system detected\n", 637 (uintmax_t)(active_irq - GIC_FIRST_SGI)); 638 #endif 639 } else if (active_irq >= GIC_FIRST_PPI && 640 active_irq <= GIC_LAST_SPI) { 641 if (gi->gi_trig == INTR_TRIGGER_EDGE) 642 gic_icc_write(EOIR1, gi->gi_irq); 643 644 if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) { 645 if (gi->gi_trig != INTR_TRIGGER_EDGE) 646 gic_icc_write(EOIR1, gi->gi_irq); 647 gic_v3_disable_intr(sc->dev, &gi->gi_isrc); 648 device_printf(sc->dev, 649 "Stray irq %lu disabled\n", active_irq); 650 } 651 } 652 } 653 } 654 655 #ifdef FDT 656 static int 657 gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp, 658 enum intr_polarity *polp, enum intr_trigger *trigp) 659 { 660 u_int irq; 661 662 if (ncells < 3) 663 return (EINVAL); 664 665 /* 666 * The 1st cell is the interrupt type: 667 * 0 = SPI 668 * 1 = PPI 669 * The 2nd cell contains the interrupt number: 670 * [0 - 987] for SPI 671 * [0 - 15] for PPI 672 * The 3rd cell is the flags, encoded as follows: 673 * bits[3:0] trigger type and level flags 674 * 1 = edge triggered 675 * 2 = edge triggered (PPI only) 676 * 4 = level-sensitive 677 * 8 = level-sensitive (PPI only) 678 */ 679 switch (cells[0]) { 680 case 0: 681 irq = GIC_FIRST_SPI + cells[1]; 682 /* SPI irq is checked later. */ 683 break; 684 case 1: 685 irq = GIC_FIRST_PPI + cells[1]; 686 if (irq > GIC_LAST_PPI) { 687 device_printf(dev, "unsupported PPI interrupt " 688 "number %u\n", cells[1]); 689 return (EINVAL); 690 } 691 break; 692 default: 693 device_printf(dev, "unsupported interrupt type " 694 "configuration %u\n", cells[0]); 695 return (EINVAL); 696 } 697 698 switch (cells[2] & FDT_INTR_MASK) { 699 case FDT_INTR_EDGE_RISING: 700 *trigp = INTR_TRIGGER_EDGE; 701 *polp = INTR_POLARITY_HIGH; 702 break; 703 case FDT_INTR_EDGE_FALLING: 704 *trigp = INTR_TRIGGER_EDGE; 705 *polp = INTR_POLARITY_LOW; 706 break; 707 case FDT_INTR_LEVEL_HIGH: 708 *trigp = INTR_TRIGGER_LEVEL; 709 *polp = INTR_POLARITY_HIGH; 710 break; 711 case FDT_INTR_LEVEL_LOW: 712 *trigp = INTR_TRIGGER_LEVEL; 713 *polp = INTR_POLARITY_LOW; 714 break; 715 default: 716 device_printf(dev, "unsupported trigger/polarity " 717 "configuration 0x%02x\n", cells[2]); 718 return (EINVAL); 719 } 720 721 /* Check the interrupt is valid */ 722 if (irq >= GIC_FIRST_SPI && *polp != INTR_POLARITY_HIGH) 723 return (EINVAL); 724 725 *irqp = irq; 726 return (0); 727 } 728 #endif 729 730 static int 731 gic_map_msi(device_t dev, struct intr_map_data_msi *msi_data, u_int *irqp, 732 enum intr_polarity *polp, enum intr_trigger *trigp) 733 { 734 struct gic_v3_irqsrc *gi; 735 736 /* SPI-mapped MSI */ 737 gi = (struct gic_v3_irqsrc *)msi_data->isrc; 738 if (gi == NULL) 739 return (ENXIO); 740 741 *irqp = gi->gi_irq; 742 743 /* MSI/MSI-X interrupts are always edge triggered with high polarity */ 744 *polp = INTR_POLARITY_HIGH; 745 *trigp = INTR_TRIGGER_EDGE; 746 747 return (0); 748 } 749 750 static int 751 do_gic_v3_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp, 752 enum intr_polarity *polp, enum intr_trigger *trigp) 753 { 754 struct gic_v3_softc *sc; 755 enum intr_polarity pol; 756 enum intr_trigger trig; 757 struct intr_map_data_msi *dam; 758 #ifdef FDT 759 struct intr_map_data_fdt *daf; 760 #endif 761 #ifdef DEV_ACPI 762 struct intr_map_data_acpi *daa; 763 #endif 764 u_int irq; 765 766 sc = device_get_softc(dev); 767 768 switch (data->type) { 769 #ifdef FDT 770 case INTR_MAP_DATA_FDT: 771 daf = (struct intr_map_data_fdt *)data; 772 if (gic_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol, 773 &trig) != 0) 774 return (EINVAL); 775 break; 776 #endif 777 #ifdef DEV_ACPI 778 case INTR_MAP_DATA_ACPI: 779 daa = (struct intr_map_data_acpi *)data; 780 irq = daa->irq; 781 pol = daa->pol; 782 trig = daa->trig; 783 break; 784 #endif 785 case INTR_MAP_DATA_MSI: 786 /* SPI-mapped MSI */ 787 dam = (struct intr_map_data_msi *)data; 788 if (gic_map_msi(dev, dam, &irq, &pol, &trig) != 0) 789 return (EINVAL); 790 break; 791 default: 792 return (EINVAL); 793 } 794 795 if (irq >= sc->gic_nirqs) 796 return (EINVAL); 797 switch (pol) { 798 case INTR_POLARITY_CONFORM: 799 case INTR_POLARITY_LOW: 800 case INTR_POLARITY_HIGH: 801 break; 802 default: 803 return (EINVAL); 804 } 805 switch (trig) { 806 case INTR_TRIGGER_CONFORM: 807 case INTR_TRIGGER_EDGE: 808 case INTR_TRIGGER_LEVEL: 809 break; 810 default: 811 return (EINVAL); 812 } 813 814 *irqp = irq; 815 if (polp != NULL) 816 *polp = pol; 817 if (trigp != NULL) 818 *trigp = trig; 819 return (0); 820 } 821 822 static int 823 gic_v3_map_intr(device_t dev, struct intr_map_data *data, 824 struct intr_irqsrc **isrcp) 825 { 826 struct gic_v3_softc *sc; 827 int error; 828 u_int irq; 829 830 error = do_gic_v3_map_intr(dev, data, &irq, NULL, NULL); 831 if (error == 0) { 832 sc = device_get_softc(dev); 833 *isrcp = GIC_INTR_ISRC(sc, irq); 834 } 835 return (error); 836 } 837 838 static int 839 gic_v3_setup_intr(device_t dev, struct intr_irqsrc *isrc, 840 struct resource *res, struct intr_map_data *data) 841 { 842 struct gic_v3_softc *sc = device_get_softc(dev); 843 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc; 844 enum intr_trigger trig; 845 enum intr_polarity pol; 846 uint32_t reg; 847 u_int irq; 848 int error; 849 850 if (data == NULL) 851 return (ENOTSUP); 852 853 error = do_gic_v3_map_intr(dev, data, &irq, &pol, &trig); 854 if (error != 0) 855 return (error); 856 857 if (gi->gi_irq != irq || pol == INTR_POLARITY_CONFORM || 858 trig == INTR_TRIGGER_CONFORM) 859 return (EINVAL); 860 861 /* Compare config if this is not first setup. */ 862 if (isrc->isrc_handlers != 0) { 863 if (pol != gi->gi_pol || trig != gi->gi_trig) 864 return (EINVAL); 865 else 866 return (0); 867 } 868 869 /* For MSI/MSI-X we should have already configured these */ 870 if ((gi->gi_flags & GI_FLAG_MSI) == 0) { 871 gi->gi_pol = pol; 872 gi->gi_trig = trig; 873 } 874 875 /* 876 * XXX - In case that per CPU interrupt is going to be enabled in time 877 * when SMP is already started, we need some IPI call which 878 * enables it on others CPUs. Further, it's more complicated as 879 * pic_enable_source() and pic_disable_source() should act on 880 * per CPU basis only. Thus, it should be solved here somehow. 881 */ 882 if (isrc->isrc_flags & INTR_ISRCF_PPI) 883 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu); 884 885 if (irq >= GIC_FIRST_PPI && irq <= GIC_LAST_SPI) { 886 mtx_lock_spin(&sc->gic_mtx); 887 888 /* Set the trigger and polarity */ 889 if (irq <= GIC_LAST_PPI) 890 reg = gic_r_read(sc, 4, 891 GICR_SGI_BASE_SIZE + GICD_ICFGR(irq)); 892 else 893 reg = gic_d_read(sc, 4, GICD_ICFGR(irq)); 894 if (trig == INTR_TRIGGER_LEVEL) 895 reg &= ~(2 << ((irq % 16) * 2)); 896 else 897 reg |= 2 << ((irq % 16) * 2); 898 899 if (irq <= GIC_LAST_PPI) { 900 gic_r_write(sc, 4, 901 GICR_SGI_BASE_SIZE + GICD_ICFGR(irq), reg); 902 gic_v3_wait_for_rwp(sc, REDIST); 903 } else { 904 gic_d_write(sc, 4, GICD_ICFGR(irq), reg); 905 gic_v3_wait_for_rwp(sc, DIST); 906 } 907 908 mtx_unlock_spin(&sc->gic_mtx); 909 910 gic_v3_bind_intr(dev, isrc); 911 } 912 913 return (0); 914 } 915 916 static int 917 gic_v3_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 918 struct resource *res, struct intr_map_data *data) 919 { 920 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc; 921 922 if (isrc->isrc_handlers == 0 && (gi->gi_flags & GI_FLAG_MSI) == 0) { 923 gi->gi_pol = INTR_POLARITY_CONFORM; 924 gi->gi_trig = INTR_TRIGGER_CONFORM; 925 } 926 927 return (0); 928 } 929 930 static void 931 gic_v3_disable_intr(device_t dev, struct intr_irqsrc *isrc) 932 { 933 struct gic_v3_softc *sc; 934 struct gic_v3_irqsrc *gi; 935 u_int irq; 936 937 sc = device_get_softc(dev); 938 gi = (struct gic_v3_irqsrc *)isrc; 939 irq = gi->gi_irq; 940 941 if (irq <= GIC_LAST_PPI) { 942 /* SGIs and PPIs in corresponding Re-Distributor */ 943 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ICENABLER(irq), 944 GICD_I_MASK(irq)); 945 gic_v3_wait_for_rwp(sc, REDIST); 946 } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) { 947 /* SPIs in distributor */ 948 gic_d_write(sc, 4, GICD_ICENABLER(irq), GICD_I_MASK(irq)); 949 gic_v3_wait_for_rwp(sc, DIST); 950 } else 951 panic("%s: Unsupported IRQ %u", __func__, irq); 952 } 953 954 static void 955 gic_v3_enable_intr(device_t dev, struct intr_irqsrc *isrc) 956 { 957 struct gic_v3_softc *sc; 958 struct gic_v3_irqsrc *gi; 959 u_int irq; 960 961 sc = device_get_softc(dev); 962 gi = (struct gic_v3_irqsrc *)isrc; 963 irq = gi->gi_irq; 964 965 if (irq <= GIC_LAST_PPI) { 966 /* SGIs and PPIs in corresponding Re-Distributor */ 967 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ISENABLER(irq), 968 GICD_I_MASK(irq)); 969 gic_v3_wait_for_rwp(sc, REDIST); 970 } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) { 971 /* SPIs in distributor */ 972 gic_d_write(sc, 4, GICD_ISENABLER(irq), GICD_I_MASK(irq)); 973 gic_v3_wait_for_rwp(sc, DIST); 974 } else 975 panic("%s: Unsupported IRQ %u", __func__, irq); 976 } 977 978 static void 979 gic_v3_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 980 { 981 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc; 982 983 gic_v3_disable_intr(dev, isrc); 984 gic_icc_write(EOIR1, gi->gi_irq); 985 } 986 987 static void 988 gic_v3_post_ithread(device_t dev, struct intr_irqsrc *isrc) 989 { 990 991 gic_v3_enable_intr(dev, isrc); 992 } 993 994 static void 995 gic_v3_post_filter(device_t dev, struct intr_irqsrc *isrc) 996 { 997 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc; 998 999 if (gi->gi_trig == INTR_TRIGGER_EDGE) 1000 return; 1001 1002 gic_icc_write(EOIR1, gi->gi_irq); 1003 } 1004 1005 static int 1006 gic_v3_bind_intr(device_t dev, struct intr_irqsrc *isrc) 1007 { 1008 struct gic_v3_softc *sc; 1009 struct gic_v3_irqsrc *gi; 1010 int cpu; 1011 1012 gi = (struct gic_v3_irqsrc *)isrc; 1013 if (gi->gi_irq <= GIC_LAST_PPI) 1014 return (EINVAL); 1015 1016 KASSERT(gi->gi_irq >= GIC_FIRST_SPI && gi->gi_irq <= GIC_LAST_SPI, 1017 ("%s: Attempting to bind an invalid IRQ", __func__)); 1018 1019 sc = device_get_softc(dev); 1020 1021 if (CPU_EMPTY(&isrc->isrc_cpu)) { 1022 gic_irq_cpu = intr_irq_next_cpu(gic_irq_cpu, &all_cpus); 1023 CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu); 1024 gic_d_write(sc, 8, GICD_IROUTER(gi->gi_irq), 1025 CPU_AFFINITY(gic_irq_cpu)); 1026 } else { 1027 /* 1028 * We can only bind to a single CPU so select 1029 * the first CPU found. 1030 */ 1031 cpu = CPU_FFS(&isrc->isrc_cpu) - 1; 1032 gic_d_write(sc, 8, GICD_IROUTER(gi->gi_irq), CPU_AFFINITY(cpu)); 1033 } 1034 1035 return (0); 1036 } 1037 1038 #ifdef SMP 1039 static void 1040 gic_v3_init_secondary(device_t dev) 1041 { 1042 device_t child; 1043 struct gic_v3_softc *sc; 1044 gic_v3_initseq_t *init_func; 1045 struct intr_irqsrc *isrc; 1046 u_int cpu, irq; 1047 int err, i; 1048 1049 sc = device_get_softc(dev); 1050 cpu = PCPU_GET(cpuid); 1051 1052 /* Train init sequence for boot CPU */ 1053 for (init_func = gic_v3_secondary_init; *init_func != NULL; 1054 init_func++) { 1055 err = (*init_func)(sc); 1056 if (err != 0) { 1057 device_printf(dev, 1058 "Could not initialize GIC for CPU%u\n", cpu); 1059 return; 1060 } 1061 } 1062 1063 /* Unmask attached SGI interrupts. */ 1064 for (irq = GIC_FIRST_SGI; irq <= GIC_LAST_SGI; irq++) { 1065 isrc = GIC_INTR_ISRC(sc, irq); 1066 if (intr_isrc_init_on_cpu(isrc, cpu)) 1067 gic_v3_enable_intr(dev, isrc); 1068 } 1069 1070 /* Unmask attached PPI interrupts. */ 1071 for (irq = GIC_FIRST_PPI; irq <= GIC_LAST_PPI; irq++) { 1072 isrc = GIC_INTR_ISRC(sc, irq); 1073 if (intr_isrc_init_on_cpu(isrc, cpu)) 1074 gic_v3_enable_intr(dev, isrc); 1075 } 1076 1077 for (i = 0; i < sc->gic_nchildren; i++) { 1078 child = sc->gic_children[i]; 1079 PIC_INIT_SECONDARY(child); 1080 } 1081 } 1082 1083 static void 1084 gic_v3_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus, 1085 u_int ipi) 1086 { 1087 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc; 1088 uint64_t aff, val, irq; 1089 int i; 1090 1091 #define GIC_AFF_MASK (CPU_AFF3_MASK | CPU_AFF2_MASK | CPU_AFF1_MASK) 1092 #define GIC_AFFINITY(i) (CPU_AFFINITY(i) & GIC_AFF_MASK) 1093 aff = GIC_AFFINITY(0); 1094 irq = gi->gi_irq; 1095 val = 0; 1096 1097 /* Iterate through all CPUs in set */ 1098 for (i = 0; i <= mp_maxid; i++) { 1099 /* Move to the next affinity group */ 1100 if (aff != GIC_AFFINITY(i)) { 1101 /* Send the IPI */ 1102 if (val != 0) { 1103 gic_icc_write(SGI1R, val); 1104 val = 0; 1105 } 1106 aff = GIC_AFFINITY(i); 1107 } 1108 1109 /* Send the IPI to this cpu */ 1110 if (CPU_ISSET(i, &cpus)) { 1111 #define ICC_SGI1R_AFFINITY(aff) \ 1112 (((uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT) | \ 1113 ((uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT) | \ 1114 ((uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT)) 1115 /* Set the affinity when the first at this level */ 1116 if (val == 0) 1117 val = ICC_SGI1R_AFFINITY(aff) | 1118 irq << ICC_SGI1R_EL1_SGIID_SHIFT; 1119 /* Set the bit to send the IPI to te CPU */ 1120 val |= 1 << CPU_AFF0(CPU_AFFINITY(i)); 1121 } 1122 } 1123 1124 /* Send the IPI to the last cpu affinity group */ 1125 if (val != 0) 1126 gic_icc_write(SGI1R, val); 1127 #undef GIC_AFF_MASK 1128 #undef GIC_AFFINITY 1129 } 1130 1131 static int 1132 gic_v3_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp) 1133 { 1134 struct intr_irqsrc *isrc; 1135 struct gic_v3_softc *sc = device_get_softc(dev); 1136 1137 if (sgi_first_unused > GIC_LAST_SGI) 1138 return (ENOSPC); 1139 1140 isrc = GIC_INTR_ISRC(sc, sgi_first_unused); 1141 sgi_to_ipi[sgi_first_unused++] = ipi; 1142 1143 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu); 1144 1145 *isrcp = isrc; 1146 return (0); 1147 } 1148 #endif /* SMP */ 1149 1150 /* 1151 * Helper routines 1152 */ 1153 static void 1154 gic_v3_wait_for_rwp(struct gic_v3_softc *sc, enum gic_v3_xdist xdist) 1155 { 1156 struct resource *res; 1157 u_int cpuid; 1158 size_t us_left = 1000000; 1159 1160 cpuid = PCPU_GET(cpuid); 1161 1162 switch (xdist) { 1163 case DIST: 1164 res = sc->gic_dist; 1165 break; 1166 case REDIST: 1167 res = &sc->gic_redists.pcpu[cpuid]->res; 1168 break; 1169 default: 1170 KASSERT(0, ("%s: Attempt to wait for unknown RWP", __func__)); 1171 return; 1172 } 1173 1174 while ((bus_read_4(res, GICD_CTLR) & GICD_CTLR_RWP) != 0) { 1175 DELAY(1); 1176 if (us_left-- == 0) 1177 panic("GICD Register write pending for too long"); 1178 } 1179 } 1180 1181 /* CPU interface. */ 1182 static __inline void 1183 gic_v3_cpu_priority(uint64_t mask) 1184 { 1185 1186 /* Set prority mask */ 1187 gic_icc_write(PMR, mask & ICC_PMR_EL1_PRIO_MASK); 1188 } 1189 1190 static int 1191 gic_v3_cpu_enable_sre(struct gic_v3_softc *sc) 1192 { 1193 uint64_t sre; 1194 u_int cpuid; 1195 1196 cpuid = PCPU_GET(cpuid); 1197 /* 1198 * Set the SRE bit to enable access to GIC CPU interface 1199 * via system registers. 1200 */ 1201 sre = READ_SPECIALREG(icc_sre_el1); 1202 sre |= ICC_SRE_EL1_SRE; 1203 WRITE_SPECIALREG(icc_sre_el1, sre); 1204 isb(); 1205 /* 1206 * Now ensure that the bit is set. 1207 */ 1208 sre = READ_SPECIALREG(icc_sre_el1); 1209 if ((sre & ICC_SRE_EL1_SRE) == 0) { 1210 /* We are done. This was disabled in EL2 */ 1211 device_printf(sc->dev, "ERROR: CPU%u cannot enable CPU interface " 1212 "via system registers\n", cpuid); 1213 return (ENXIO); 1214 } else if (bootverbose) { 1215 device_printf(sc->dev, 1216 "CPU%u enabled CPU interface via system registers\n", 1217 cpuid); 1218 } 1219 1220 return (0); 1221 } 1222 1223 static int 1224 gic_v3_cpu_init(struct gic_v3_softc *sc) 1225 { 1226 int err; 1227 1228 /* Enable access to CPU interface via system registers */ 1229 err = gic_v3_cpu_enable_sre(sc); 1230 if (err != 0) 1231 return (err); 1232 /* Priority mask to minimum - accept all interrupts */ 1233 gic_v3_cpu_priority(GIC_PRIORITY_MIN); 1234 /* Disable EOI mode */ 1235 gic_icc_clear(CTLR, ICC_CTLR_EL1_EOIMODE); 1236 /* Enable group 1 (insecure) interrups */ 1237 gic_icc_set(IGRPEN1, ICC_IGRPEN0_EL1_EN); 1238 1239 return (0); 1240 } 1241 1242 /* Distributor */ 1243 static int 1244 gic_v3_dist_init(struct gic_v3_softc *sc) 1245 { 1246 uint64_t aff; 1247 u_int i; 1248 1249 /* 1250 * 1. Disable the Distributor 1251 */ 1252 gic_d_write(sc, 4, GICD_CTLR, 0); 1253 gic_v3_wait_for_rwp(sc, DIST); 1254 1255 /* 1256 * 2. Configure the Distributor 1257 */ 1258 /* Set all SPIs to be Group 1 Non-secure */ 1259 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_IGROUPRn) 1260 gic_d_write(sc, 4, GICD_IGROUPR(i), 0xFFFFFFFF); 1261 1262 /* Set all global interrupts to be level triggered, active low. */ 1263 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ICFGRn) 1264 gic_d_write(sc, 4, GICD_ICFGR(i), 0x00000000); 1265 1266 /* Set priority to all shared interrupts */ 1267 for (i = GIC_FIRST_SPI; 1268 i < sc->gic_nirqs; i += GICD_I_PER_IPRIORITYn) { 1269 /* Set highest priority */ 1270 gic_d_write(sc, 4, GICD_IPRIORITYR(i), GIC_PRIORITY_MAX); 1271 } 1272 1273 /* 1274 * Disable all interrupts. Leave PPI and SGIs as they are enabled in 1275 * Re-Distributor registers. 1276 */ 1277 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ISENABLERn) 1278 gic_d_write(sc, 4, GICD_ICENABLER(i), 0xFFFFFFFF); 1279 1280 gic_v3_wait_for_rwp(sc, DIST); 1281 1282 /* 1283 * 3. Enable Distributor 1284 */ 1285 /* Enable Distributor with ARE, Group 1 */ 1286 gic_d_write(sc, 4, GICD_CTLR, GICD_CTLR_ARE_NS | GICD_CTLR_G1A | 1287 GICD_CTLR_G1); 1288 1289 /* 1290 * 4. Route all interrupts to boot CPU. 1291 */ 1292 aff = CPU_AFFINITY(0); 1293 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i++) 1294 gic_d_write(sc, 8, GICD_IROUTER(i), aff); 1295 1296 return (0); 1297 } 1298 1299 /* Re-Distributor */ 1300 static int 1301 gic_v3_redist_alloc(struct gic_v3_softc *sc) 1302 { 1303 u_int cpuid; 1304 1305 /* Allocate struct resource for all CPU's Re-Distributor registers */ 1306 for (cpuid = 0; cpuid <= mp_maxid; cpuid++) 1307 if (CPU_ISSET(cpuid, &all_cpus) != 0) 1308 sc->gic_redists.pcpu[cpuid] = 1309 malloc(sizeof(*sc->gic_redists.pcpu[0]), 1310 M_GIC_V3, M_WAITOK); 1311 else 1312 sc->gic_redists.pcpu[cpuid] = NULL; 1313 return (0); 1314 } 1315 1316 static int 1317 gic_v3_redist_find(struct gic_v3_softc *sc) 1318 { 1319 struct resource r_res; 1320 bus_space_handle_t r_bsh; 1321 uint64_t aff; 1322 uint64_t typer; 1323 uint32_t pidr2; 1324 u_int cpuid; 1325 size_t i; 1326 1327 cpuid = PCPU_GET(cpuid); 1328 1329 aff = CPU_AFFINITY(cpuid); 1330 /* Affinity in format for comparison with typer */ 1331 aff = (CPU_AFF3(aff) << 24) | (CPU_AFF2(aff) << 16) | 1332 (CPU_AFF1(aff) << 8) | CPU_AFF0(aff); 1333 1334 if (bootverbose) { 1335 device_printf(sc->dev, 1336 "Start searching for Re-Distributor\n"); 1337 } 1338 /* Iterate through Re-Distributor regions */ 1339 for (i = 0; i < sc->gic_redists.nregions; i++) { 1340 /* Take a copy of the region's resource */ 1341 r_res = *sc->gic_redists.regions[i]; 1342 r_bsh = rman_get_bushandle(&r_res); 1343 1344 pidr2 = bus_read_4(&r_res, GICR_PIDR2); 1345 switch (GICR_PIDR2_ARCH(pidr2)) { 1346 case GICR_PIDR2_ARCH_GICv3: /* fall through */ 1347 case GICR_PIDR2_ARCH_GICv4: 1348 break; 1349 default: 1350 device_printf(sc->dev, 1351 "No Re-Distributor found for CPU%u\n", cpuid); 1352 return (ENODEV); 1353 } 1354 1355 do { 1356 typer = bus_read_8(&r_res, GICR_TYPER); 1357 if ((typer >> GICR_TYPER_AFF_SHIFT) == aff) { 1358 KASSERT(sc->gic_redists.pcpu[cpuid] != NULL, 1359 ("Invalid pointer to per-CPU redistributor")); 1360 /* Copy res contents to its final destination */ 1361 sc->gic_redists.pcpu[cpuid]->res = r_res; 1362 sc->gic_redists.pcpu[cpuid]->lpi_enabled = false; 1363 if (bootverbose) { 1364 device_printf(sc->dev, 1365 "CPU%u Re-Distributor has been found\n", 1366 cpuid); 1367 } 1368 return (0); 1369 } 1370 1371 r_bsh += (GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE); 1372 if ((typer & GICR_TYPER_VLPIS) != 0) { 1373 r_bsh += 1374 (GICR_VLPI_BASE_SIZE + GICR_RESERVED_SIZE); 1375 } 1376 1377 rman_set_bushandle(&r_res, r_bsh); 1378 } while ((typer & GICR_TYPER_LAST) == 0); 1379 } 1380 1381 device_printf(sc->dev, "No Re-Distributor found for CPU%u\n", cpuid); 1382 return (ENXIO); 1383 } 1384 1385 static int 1386 gic_v3_redist_wake(struct gic_v3_softc *sc) 1387 { 1388 uint32_t waker; 1389 size_t us_left = 1000000; 1390 1391 waker = gic_r_read(sc, 4, GICR_WAKER); 1392 /* Wake up Re-Distributor for this CPU */ 1393 waker &= ~GICR_WAKER_PS; 1394 gic_r_write(sc, 4, GICR_WAKER, waker); 1395 /* 1396 * When clearing ProcessorSleep bit it is required to wait for 1397 * ChildrenAsleep to become zero following the processor power-on. 1398 */ 1399 while ((gic_r_read(sc, 4, GICR_WAKER) & GICR_WAKER_CA) != 0) { 1400 DELAY(1); 1401 if (us_left-- == 0) { 1402 panic("Could not wake Re-Distributor for CPU%u", 1403 PCPU_GET(cpuid)); 1404 } 1405 } 1406 1407 if (bootverbose) { 1408 device_printf(sc->dev, "CPU%u Re-Distributor woke up\n", 1409 PCPU_GET(cpuid)); 1410 } 1411 1412 return (0); 1413 } 1414 1415 static int 1416 gic_v3_redist_init(struct gic_v3_softc *sc) 1417 { 1418 int err; 1419 size_t i; 1420 1421 err = gic_v3_redist_find(sc); 1422 if (err != 0) 1423 return (err); 1424 1425 err = gic_v3_redist_wake(sc); 1426 if (err != 0) 1427 return (err); 1428 1429 /* Configure SGIs and PPIs to be Group1 Non-secure */ 1430 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_IGROUPR0, 1431 0xFFFFFFFF); 1432 1433 /* Disable SPIs */ 1434 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ICENABLER0, 1435 GICR_I_ENABLER_PPI_MASK); 1436 /* Enable SGIs */ 1437 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ISENABLER0, 1438 GICR_I_ENABLER_SGI_MASK); 1439 1440 /* Set priority for SGIs and PPIs */ 1441 for (i = 0; i <= GIC_LAST_PPI; i += GICR_I_PER_IPRIORITYn) { 1442 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_IPRIORITYR(i), 1443 GIC_PRIORITY_MAX); 1444 } 1445 1446 gic_v3_wait_for_rwp(sc, REDIST); 1447 1448 return (0); 1449 } 1450 1451 /* 1452 * SPI-mapped Message Based Interrupts -- a GICv3 MSI/MSI-X controller. 1453 */ 1454 1455 static int 1456 gic_v3_gic_alloc_msi(device_t dev, u_int mbi_start, u_int mbi_count, 1457 int count, int maxcount, struct intr_irqsrc **isrc) 1458 { 1459 struct gic_v3_softc *sc; 1460 int i, irq, end_irq; 1461 bool found; 1462 1463 KASSERT(powerof2(count), ("%s: bad count", __func__)); 1464 KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__)); 1465 1466 sc = device_get_softc(dev); 1467 1468 mtx_lock(&sc->gic_mbi_mtx); 1469 1470 found = false; 1471 for (irq = mbi_start; irq < mbi_start + mbi_count; irq++) { 1472 /* Start on an aligned interrupt */ 1473 if ((irq & (maxcount - 1)) != 0) 1474 continue; 1475 1476 /* Assume we found a valid range until shown otherwise */ 1477 found = true; 1478 1479 /* Check this range is valid */ 1480 for (end_irq = irq; end_irq != irq + count; end_irq++) { 1481 /* No free interrupts */ 1482 if (end_irq == mbi_start + mbi_count) { 1483 found = false; 1484 break; 1485 } 1486 1487 KASSERT((sc->gic_irqs[end_irq].gi_flags & GI_FLAG_MSI)!= 0, 1488 ("%s: Non-MSI interrupt found", __func__)); 1489 1490 /* This is already used */ 1491 if ((sc->gic_irqs[end_irq].gi_flags & GI_FLAG_MSI_USED) == 1492 GI_FLAG_MSI_USED) { 1493 found = false; 1494 break; 1495 } 1496 } 1497 if (found) 1498 break; 1499 } 1500 1501 /* Not enough interrupts were found */ 1502 if (!found || irq == mbi_start + mbi_count) { 1503 mtx_unlock(&sc->gic_mbi_mtx); 1504 return (ENXIO); 1505 } 1506 1507 for (i = 0; i < count; i++) { 1508 /* Mark the interrupt as used */ 1509 sc->gic_irqs[irq + i].gi_flags |= GI_FLAG_MSI_USED; 1510 } 1511 mtx_unlock(&sc->gic_mbi_mtx); 1512 1513 for (i = 0; i < count; i++) 1514 isrc[i] = (struct intr_irqsrc *)&sc->gic_irqs[irq + i]; 1515 1516 return (0); 1517 } 1518 1519 static int 1520 gic_v3_gic_release_msi(device_t dev, int count, struct intr_irqsrc **isrc) 1521 { 1522 struct gic_v3_softc *sc; 1523 struct gic_v3_irqsrc *gi; 1524 int i; 1525 1526 sc = device_get_softc(dev); 1527 1528 mtx_lock(&sc->gic_mbi_mtx); 1529 for (i = 0; i < count; i++) { 1530 gi = (struct gic_v3_irqsrc *)isrc[i]; 1531 1532 KASSERT((gi->gi_flags & GI_FLAG_MSI_USED) == GI_FLAG_MSI_USED, 1533 ("%s: Trying to release an unused MSI-X interrupt", 1534 __func__)); 1535 1536 gi->gi_flags &= ~GI_FLAG_MSI_USED; 1537 } 1538 mtx_unlock(&sc->gic_mbi_mtx); 1539 1540 return (0); 1541 } 1542 1543 static int 1544 gic_v3_gic_alloc_msix(device_t dev, u_int mbi_start, u_int mbi_count, 1545 struct intr_irqsrc **isrcp) 1546 { 1547 struct gic_v3_softc *sc; 1548 int irq; 1549 1550 sc = device_get_softc(dev); 1551 1552 mtx_lock(&sc->gic_mbi_mtx); 1553 /* Find an unused interrupt */ 1554 for (irq = mbi_start; irq < mbi_start + mbi_count; irq++) { 1555 KASSERT((sc->gic_irqs[irq].gi_flags & GI_FLAG_MSI) != 0, 1556 ("%s: Non-MSI interrupt found", __func__)); 1557 if ((sc->gic_irqs[irq].gi_flags & GI_FLAG_MSI_USED) == 0) 1558 break; 1559 } 1560 /* No free interrupt was found */ 1561 if (irq == mbi_start + mbi_count) { 1562 mtx_unlock(&sc->gic_mbi_mtx); 1563 return (ENXIO); 1564 } 1565 1566 /* Mark the interrupt as used */ 1567 sc->gic_irqs[irq].gi_flags |= GI_FLAG_MSI_USED; 1568 mtx_unlock(&sc->gic_mbi_mtx); 1569 1570 *isrcp = (struct intr_irqsrc *)&sc->gic_irqs[irq]; 1571 1572 return (0); 1573 } 1574 1575 static int 1576 gic_v3_gic_release_msix(device_t dev, struct intr_irqsrc *isrc) 1577 { 1578 struct gic_v3_softc *sc; 1579 struct gic_v3_irqsrc *gi; 1580 1581 sc = device_get_softc(dev); 1582 gi = (struct gic_v3_irqsrc *)isrc; 1583 1584 KASSERT((gi->gi_flags & GI_FLAG_MSI_USED) == GI_FLAG_MSI_USED, 1585 ("%s: Trying to release an unused MSI-X interrupt", __func__)); 1586 1587 mtx_lock(&sc->gic_mbi_mtx); 1588 gi->gi_flags &= ~GI_FLAG_MSI_USED; 1589 mtx_unlock(&sc->gic_mbi_mtx); 1590 1591 return (0); 1592 } 1593 1594 static int 1595 gic_v3_alloc_msi(device_t dev, device_t child, int count, int maxcount, 1596 device_t *pic, struct intr_irqsrc **isrc) 1597 { 1598 struct gic_v3_softc *sc; 1599 int error; 1600 1601 sc = device_get_softc(dev); 1602 error = gic_v3_gic_alloc_msi(dev, sc->gic_mbi_start, 1603 sc->gic_mbi_end - sc->gic_mbi_start, count, maxcount, isrc); 1604 if (error != 0) 1605 return (error); 1606 1607 *pic = dev; 1608 return (0); 1609 } 1610 1611 static int 1612 gic_v3_release_msi(device_t dev, device_t child, int count, 1613 struct intr_irqsrc **isrc) 1614 { 1615 return (gic_v3_gic_release_msi(dev, count, isrc)); 1616 } 1617 1618 static int 1619 gic_v3_alloc_msix(device_t dev, device_t child, device_t *pic, 1620 struct intr_irqsrc **isrc) 1621 { 1622 struct gic_v3_softc *sc; 1623 int error; 1624 1625 sc = device_get_softc(dev); 1626 error = gic_v3_gic_alloc_msix(dev, sc->gic_mbi_start, 1627 sc->gic_mbi_end - sc->gic_mbi_start, isrc); 1628 if (error != 0) 1629 return (error); 1630 1631 *pic = dev; 1632 1633 return (0); 1634 } 1635 1636 static int 1637 gic_v3_release_msix(device_t dev, device_t child, struct intr_irqsrc *isrc) 1638 { 1639 return (gic_v3_gic_release_msix(dev, isrc)); 1640 } 1641 1642 static int 1643 gic_v3_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc, 1644 uint64_t *addr, uint32_t *data) 1645 { 1646 struct gic_v3_softc *sc = device_get_softc(dev); 1647 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc; 1648 1649 *addr = vtophys(rman_get_virtual(sc->gic_dist)) + GICD_SETSPI_NSR; 1650 *data = gi->gi_irq; 1651 1652 return (0); 1653 } 1654