1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * 4 * This software was developed by Semihalf under 5 * the sponsorship of the FreeBSD Foundation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _GIC_V3_REG_H_ 30 #define _GIC_V3_REG_H_ 31 32 /* 33 * Maximum number of interrupts 34 * supported by GIC (including SGIs, PPIs and SPIs) 35 */ 36 #define GIC_I_NUM_MAX (1020) 37 /* 38 * Priority MAX/MIN values 39 */ 40 #define GIC_PRIORITY_MAX (0x00UL) 41 /* Upper value is determined by LPI max priority */ 42 #define GIC_PRIORITY_MIN (0xFCUL) 43 44 /* Numbers for shared peripheral interrupts */ 45 #define GIC_LAST_SPI (1019) 46 /* Numbers for local peripheral interrupts */ 47 #define GIC_FIRST_LPI (8192) 48 49 /* 50 * Registers (v2/v3) 51 */ 52 /* GICD_CTLR */ 53 #define GICD_CTLR_G1 (1 << 0) 54 #define GICD_CTLR_G1A (1 << 1) 55 #define GICD_CTLR_ARE_NS (1 << 4) 56 #define GICD_CTLR_RWP (1 << 31) 57 58 /* GICD_TYPER */ 59 #define GICD_TYPER_SECURITYEXTN (1 << 10) 60 #define GICD_TYPER_MBIS (1 << 16) 61 #define GICD_TYPER_LPIS (1 << 17) 62 #define GICD_TYPER_DVIS (1 << 18) 63 #define GICD_TYPER_IDBITS_SHIFT 19 64 #define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1) 65 66 /* 67 * Registers (v3) 68 */ 69 #define GICD_STATUSR 0x0010 70 71 #define GICD_SETSPI_NSR 0x0040 72 #define GICD_CLRSPI_NSR 0x0048 73 #define GICD_SETSPI_SR 0x0050 74 #define GICD_CLRSPI_SR 0x0058 75 #define GICD_SPI_INTID_MASK 0x3ff 76 77 #define GICD_IROUTER(n) (0x6000 + ((n) * 8)) 78 #define GICD_AFF3 (0xfful << 32) 79 #define GICD_IROUTER_IRM (1ul << 31) 80 #define GICD_AFF2 (0xfful << 16) 81 #define GICD_AFF1 (0xfful << 8) 82 #define GICD_AFF0 (0xfful << 0) 83 #define GICD_AFF (GICD_AFF0 | GICD_AFF1 | GICD_AFF1 | GICD_AFF3) 84 85 #define GICD_PIDR4 0xFFD0 86 #define GICD_PIDR5 0xFFD4 87 #define GICD_PIDR6 0xFFD8 88 #define GICD_PIDR7 0xFFDC 89 #define GICD_PIDR0 0xFFE0 90 #define GICD_PIDR1 0xFFE4 91 #define GICD_PIDR2 0xFFE8 92 93 #define GICD_SIZE 0x10000 94 95 #define GICR_PIDR2_ARCH_SHIFT 4 96 #define GICR_PIDR2_ARCH_MASK 0xF0 97 #define GICR_PIDR2_ARCH(x) \ 98 (((x) & GICR_PIDR2_ARCH_MASK) >> GICR_PIDR2_ARCH_SHIFT) 99 #define GICR_PIDR2_ARCH_GICv3 0x3 100 #define GICR_PIDR2_ARCH_GICv4 0x4 101 102 #define GICD_PIDR3 0xFFEC 103 104 /* 105 * Redistributor registers 106 */ 107 108 /* RD_base registers */ 109 #define GICR_CTLR 0x0000 110 #define GICR_CTLR_LPI_ENABLE (1 << 0) 111 #define GICR_CTLR_RWP (1 << 3) 112 #define GICR_CTLR_DPG0 (1 << 24) 113 #define GICR_CTLR_DPG1NS (1 << 25) 114 #define GICR_CTLR_DPG1S (1 << 26) 115 #define GICR_CTLR_UWP (1 << 31) 116 117 #define GICR_IIDR 0x0004 118 119 #define GICR_TYPER 0x0008 120 #define GICR_TYPER_PLPIS (1 << 0) 121 #define GICR_TYPER_VLPIS (1 << 1) 122 #define GICR_TYPER_LAST (1 << 4) 123 #define GICR_TYPER_CPUNUM_SHIFT (8) 124 #define GICR_TYPER_CPUNUM_MASK (0xFFFUL << GICR_TYPER_CPUNUM_SHIFT) 125 #define GICR_TYPER_CPUNUM(x) \ 126 (((x) & GICR_TYPER_CPUNUM_MASK) >> GICR_TYPER_CPUNUM_SHIFT) 127 #define GICR_TYPER_AFF_SHIFT 32 128 #define GICR_TYPER_AFF_MASK (0xfffffffful << GICR_TYPER_AFF_SHIFT) 129 #define GICR_TYPER_AFF(x) \ 130 (((x) & GICR_TYPER_AFF_MASK) >> GICR_TYPER_AFF_SHIFT) 131 132 #define GICR_STATUSR 0x0010 133 134 #define GICR_WAKER 0x0014 135 #define GICR_WAKER_PS (1 << 1) /* Processor sleep */ 136 #define GICR_WAKER_CA (1 << 2) /* Children asleep */ 137 138 #define GICR_SETLPIR 0x0040 139 #define GICR_CLRLPIR 0x0048 140 141 #define GICR_PROPBASER 0x0070 142 #define GICR_PROPBASER_IDBITS_MASK 0x1FUL 143 /* 144 * Cacheability 145 * 0x0 - Device-nGnRnE 146 * 0x1 - Normal Inner Non-cacheable 147 * 0x2 - Normal Inner Read-allocate, Write-through 148 * 0x3 - Normal Inner Read-allocate, Write-back 149 * 0x4 - Normal Inner Write-allocate, Write-through 150 * 0x5 - Normal Inner Write-allocate, Write-back 151 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through 152 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back 153 */ 154 #define GICR_PROPBASER_CACHE_SHIFT 7 155 #define GICR_PROPBASER_CACHE_DnGnRnE 0x0UL 156 #define GICR_PROPBASER_CACHE_NIN 0x1UL 157 #define GICR_PROPBASER_CACHE_NIRAWT 0x2UL 158 #define GICR_PROPBASER_CACHE_NIRAWB 0x3UL 159 #define GICR_PROPBASER_CACHE_NIWAWT 0x4UL 160 #define GICR_PROPBASER_CACHE_NIWAWB 0x5UL 161 #define GICR_PROPBASER_CACHE_NIRAWAWT 0x6UL 162 #define GICR_PROPBASER_CACHE_NIRAWAWB 0x7UL 163 #define GICR_PROPBASER_CACHE_MASK \ 164 (0x7UL << GICR_PROPBASER_CACHE_SHIFT) 165 166 /* 167 * Shareability 168 * 0x0 - Non-shareable 169 * 0x1 - Inner-shareable 170 * 0x2 - Outer-shareable 171 * 0x3 - Reserved. Threated as 0x0 172 */ 173 #define GICR_PROPBASER_SHARE_SHIFT 10 174 #define GICR_PROPBASER_SHARE_NS 0x0UL 175 #define GICR_PROPBASER_SHARE_IS 0x1UL 176 #define GICR_PROPBASER_SHARE_OS 0x2UL 177 #define GICR_PROPBASER_SHARE_RES 0x3UL 178 #define GICR_PROPBASER_SHARE_MASK \ 179 (0x3UL << GICR_PROPBASER_SHARE_SHIFT) 180 181 #define GICR_PROPBASER_OUTER_CACHE_SHIFT 56 182 #define GICR_PROPBASER_OUTER_CACHE_MASK \ 183 (0x7UL << GICR_PROPBASER_OUTER_CACHE_SHIFT) 184 185 #define GICR_PENDBASER 0x0078 186 /* 187 * Cacheability 188 * 0x0 - Device-nGnRnE 189 * 0x1 - Normal Inner Non-cacheable 190 * 0x2 - Normal Inner Read-allocate, Write-through 191 * 0x3 - Normal Inner Read-allocate, Write-back 192 * 0x4 - Normal Inner Write-allocate, Write-through 193 * 0x5 - Normal Inner Write-allocate, Write-back 194 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through 195 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back 196 */ 197 #define GICR_PENDBASER_CACHE_SHIFT 7 198 #define GICR_PENDBASER_CACHE_DnGnRnE 0x0UL 199 #define GICR_PENDBASER_CACHE_NIN 0x1UL 200 #define GICR_PENDBASER_CACHE_NIRAWT 0x2UL 201 #define GICR_PENDBASER_CACHE_NIRAWB 0x3UL 202 #define GICR_PENDBASER_CACHE_NIWAWT 0x4UL 203 #define GICR_PENDBASER_CACHE_NIWAWB 0x5UL 204 #define GICR_PENDBASER_CACHE_NIRAWAWT 0x6UL 205 #define GICR_PENDBASER_CACHE_NIRAWAWB 0x7UL 206 #define GICR_PENDBASER_CACHE_MASK \ 207 (0x7UL << GICR_PENDBASER_CACHE_SHIFT) 208 209 /* 210 * Shareability 211 * 0x0 - Non-shareable 212 * 0x1 - Inner-shareable 213 * 0x2 - Outer-shareable 214 * 0x3 - Reserved. Threated as 0x0 215 */ 216 #define GICR_PENDBASER_SHARE_SHIFT 10 217 #define GICR_PENDBASER_SHARE_NS 0x0UL 218 #define GICR_PENDBASER_SHARE_IS 0x1UL 219 #define GICR_PENDBASER_SHARE_OS 0x2UL 220 #define GICR_PENDBASER_SHARE_RES 0x3UL 221 #define GICR_PENDBASER_SHARE_MASK \ 222 (0x3UL << GICR_PENDBASER_SHARE_SHIFT) 223 224 #define GICR_PENDBASER_OUTER_CACHE_SHIFT 56 225 #define GICR_PENDBASER_OUTER_CACHE_MASK \ 226 (0x7UL << GICR_PENDBASER_OUTER_CACHE_SHIFT) 227 228 #define GICR_INVLPIR 0x00a0 229 #define GICR_INVALLR 0x00b0 230 #define GICR_SYNCR 0x00c0 231 232 #define GICR_PIDR2 GICD_PIDR2 233 234 /* SGI_base registers */ 235 #define GICR_IGROUPR0 (0x0080) 236 #define GICR_ISENABLER0 (0x0100) 237 #define GICR_ICENABLER0 (0x0180) 238 #define GICR_I_ENABLER_SGI_MASK (0x0000FFFF) 239 #define GICR_I_ENABLER_PPI_MASK (0xFFFF0000) 240 241 #define GICR_I_PER_IPRIORITYn (GICD_I_PER_IPRIORITYn) 242 243 #define GICR_ISPENDR0 0x0200 244 #define GICR_ICPENDR0 0x0280 245 #define GICR_ISACTIVER0 0x0300 246 #define GICR_ICACTIVER0 0x0380 247 #define GICR_IPRIORITYR(n) (0x0400 + (((n) >> 2) * 4)) 248 #define GICR_ICFGR0 0x0c00 249 #define GICR_ICFGR1 0x0c04 250 #define GICR_IGRPMODR0 0x0d00 251 #define GICR_NSACR 0x0e00 252 253 /* Re-distributor registers for SGIs and PPIs */ 254 #define GICR_RD_BASE 0 255 #define GICR_RD_BASE_SIZE PAGE_SIZE_64K 256 #define GICR_SGI_BASE (1 * PAGE_SIZE_64K) 257 #define GICR_SGI_BASE_SIZE PAGE_SIZE_64K 258 #define GICR_VLPI_BASE (2 * PAGE_SIZE_64K) 259 #define GICR_VLPI_BASE_SIZE PAGE_SIZE_64K 260 #define GICR_RESERVED_SIZE PAGE_SIZE_64K 261 262 /* 263 * ITS registers 264 */ 265 #define GITS_PIDR2 GICR_PIDR2 266 #define GITS_PIDR2_ARCH_MASK GICR_PIDR2_ARCH_MASK 267 #define GITS_PIDR2_ARCH_GICv3 GICR_PIDR2_ARCH_GICv3 268 #define GITS_PIDR2_ARCH_GICv4 GICR_PIDR2_ARCH_GICv4 269 270 #define GITS_CTLR (0x0000) 271 #define GITS_CTLR_EN (1 << 0) 272 273 #define GITS_IIDR (0x0004) 274 #define GITS_IIDR_PRODUCT_SHIFT 24 275 #define GITS_IIDR_PRODUCT_MASK (0xff << GITS_IIDR_PRODUCT_SHIFT) 276 #define GITS_IIDR_VARIANT_SHIFT 16 277 #define GITS_IIDR_VARIANT_MASK (0xf << GITS_IIDR_VARIANT_SHIFT) 278 #define GITS_IIDR_REVISION_SHIFT 12 279 #define GITS_IIDR_REVISION_MASK (0xf << GITS_IIDR_REVISION_SHIFT) 280 #define GITS_IIDR_IMPLEMENTOR_SHIFT 0 281 #define GITS_IIDR_IMPLEMENTOR_MASK (0xfff << GITS_IIDR_IMPLEMENTOR_SHIFT) 282 283 #define GITS_IIDR_RAW(impl, prod, var, rev) \ 284 ((prod) << GITS_IIDR_PRODUCT_SHIFT | \ 285 (var) << GITS_IIDR_VARIANT_SHIFT | \ 286 (rev) << GITS_IIDR_REVISION_SHIFT | \ 287 (impl) << GITS_IIDR_IMPLEMENTOR_SHIFT) 288 289 #define GITS_IIDR_IMPL_ARM (0x43B) 290 #define GITS_IIDR_PROD_GIC500 (0x0) 291 #define GITS_IIDR_IMPL_CAVIUM (0x34c) 292 #define GITS_IIDR_PROD_THUNDER (0xa1) 293 #define GITS_IIDR_VAR_THUNDER_1 (0x0) 294 295 #define GITS_CBASER (0x0080) 296 #define GITS_CBASER_VALID (1UL << 63) 297 /* 298 * Cacheability 299 * 0x0 - Device-nGnRnE 300 * 0x1 - Normal Inner Non-cacheable 301 * 0x2 - Normal Inner Read-allocate, Write-through 302 * 0x3 - Normal Inner Read-allocate, Write-back 303 * 0x4 - Normal Inner Write-allocate, Write-through 304 * 0x5 - Normal Inner Write-allocate, Write-back 305 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through 306 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back 307 */ 308 #define GITS_CBASER_CACHE_SHIFT 59 309 #define GITS_CBASER_CACHE_DnGnRnE 0x0UL 310 #define GITS_CBASER_CACHE_NIN 0x1UL 311 #define GITS_CBASER_CACHE_NIRAWT 0x2UL 312 #define GITS_CBASER_CACHE_NIRAWB 0x3UL 313 #define GITS_CBASER_CACHE_NIWAWT 0x4UL 314 #define GITS_CBASER_CACHE_NIWAWB 0x5UL 315 #define GITS_CBASER_CACHE_NIRAWAWT 0x6UL 316 #define GITS_CBASER_CACHE_NIRAWAWB 0x7UL 317 #define GITS_CBASER_CACHE_MASK (0x7UL << GITS_CBASER_CACHE_SHIFT) 318 /* 319 * Shareability 320 * 0x0 - Non-shareable 321 * 0x1 - Inner-shareable 322 * 0x2 - Outer-shareable 323 * 0x3 - Reserved. Threated as 0x0 324 */ 325 #define GITS_CBASER_SHARE_SHIFT 10 326 #define GITS_CBASER_SHARE_NS 0x0UL 327 #define GITS_CBASER_SHARE_IS 0x1UL 328 #define GITS_CBASER_SHARE_OS 0x2UL 329 #define GITS_CBASER_SHARE_RES 0x3UL 330 #define GITS_CBASER_SHARE_MASK \ 331 (0x3UL << GITS_CBASER_SHARE_SHIFT) 332 333 #define GITS_CBASER_PA_SHIFT 12 334 #define GITS_CBASER_PA_MASK (0xFFFFFFFFFUL << GITS_CBASER_PA_SHIFT) 335 #define GITS_CBASER_SIZE_SHIFT 0 336 #define GITS_CBASER_SIZE_MASK (0xFF << GITS_CBASER_SIZE_SHIFT) 337 #define GITS_CBASER_SIZE(x) \ 338 (4096 * (((x) & GITS_CBASER_SIZE_MASK) + 1)) 339 340 #define GITS_CWRITER (0x0088) 341 #define GITS_CREADR (0x0090) 342 #define GITS_CREADR_STALL 1ul 343 344 #define GITS_CMD_OFFSET(reg) ((reg) & 0xfffe0ul) 345 #define GITS_CMD_SIZE 0x20 346 347 #define GITS_BASER_BASE (0x0100) 348 #define GITS_BASER(x) (GITS_BASER_BASE + (x) * 8) 349 350 #define GITS_BASER_VALID (1UL << 63) 351 352 #define GITS_BASER_INDIRECT_SHIFT 62 353 #define GITS_BASER_INDIRECT (1UL << GITS_BASER_INDIRECT_SHIFT) 354 355 #define GITS_BASER_TYPE_SHIFT 56 356 #define GITS_BASER_TYPE(x) \ 357 (((x) & GITS_BASER_TYPE_MASK) >> GITS_BASER_TYPE_SHIFT) 358 #define GITS_BASER_TYPE_UNIMPL 0x0UL /* Unimplemented */ 359 #define GITS_BASER_TYPE_DEV 0x1UL /* Devices */ 360 #define GITS_BASER_TYPE_VP 0x2UL /* Virtual Processors */ 361 #define GITS_BASER_TYPE_PP 0x3UL /* Physical Processors */ 362 #define GITS_BASER_TYPE_IC 0x4UL /* Interrupt Collections */ 363 #define GITS_BASER_TYPE_RES5 0x5UL /* Reserved */ 364 #define GITS_BASER_TYPE_RES6 0x6UL /* Reserved */ 365 #define GITS_BASER_TYPE_RES7 0x7UL /* Reserved */ 366 #define GITS_BASER_TYPE_MASK (0x7UL << GITS_BASER_TYPE_SHIFT) 367 /* 368 * Cacheability 369 * 0x0 - Non-cacheable, non-bufferable 370 * 0x1 - Non-cacheable 371 * 0x2 - Read-allocate, Write-through 372 * 0x3 - Read-allocate, Write-back 373 * 0x4 - Write-allocate, Write-through 374 * 0x5 - Write-allocate, Write-back 375 * 0x6 - Read-allocate, Write-allocate, Write-through 376 * 0x7 - Read-allocate, Write-allocate, Write-back 377 */ 378 #define GITS_BASER_CACHE_SHIFT 59 379 #define GITS_BASER_CACHE_NCNB 0x0UL 380 #define GITS_BASER_CACHE_NC 0x1UL 381 #define GITS_BASER_CACHE_RAWT 0x2UL 382 #define GITS_BASER_CACHE_RAWB 0x3UL 383 #define GITS_BASER_CACHE_WAWT 0x4UL 384 #define GITS_BASER_CACHE_WAWB 0x5UL 385 #define GITS_BASER_CACHE_RAWAWT 0x6UL 386 #define GITS_BASER_CACHE_RAWAWB 0x7UL 387 #define GITS_BASER_CACHE_MASK (0x7UL << GITS_BASER_CACHE_SHIFT) 388 389 #define GITS_BASER_ESIZE_SHIFT 48 390 #define GITS_BASER_ESIZE_MASK (0x1FUL << GITS_BASER_ESIZE_SHIFT) 391 #define GITS_BASER_ESIZE(x) \ 392 ((((x) & GITS_BASER_ESIZE_MASK) >> GITS_BASER_ESIZE_SHIFT) + 1) 393 394 #define GITS_BASER_PA_SHIFT 12 395 #define GITS_BASER_PA_MASK (0xFFFFFFFFFUL << GITS_BASER_PA_SHIFT) 396 397 /* 398 * Shareability 399 * 0x0 - Non-shareable 400 * 0x1 - Inner-shareable 401 * 0x2 - Outer-shareable 402 * 0x3 - Reserved. Threated as 0x0 403 */ 404 #define GITS_BASER_SHARE_SHIFT 10 405 #define GITS_BASER_SHARE_NS 0x0UL 406 #define GITS_BASER_SHARE_IS 0x1UL 407 #define GITS_BASER_SHARE_OS 0x2UL 408 #define GITS_BASER_SHARE_RES 0x3UL 409 #define GITS_BASER_SHARE_MASK (0x3UL << GITS_BASER_SHARE_SHIFT) 410 411 #define GITS_BASER_PSZ_SHIFT 8 412 #define GITS_BASER_PSZ_4K 0x0UL 413 #define GITS_BASER_PSZ_16K 0x1UL 414 #define GITS_BASER_PSZ_64K 0x2UL 415 #define GITS_BASER_PSZ_MASK (0x3UL << GITS_BASER_PSZ_SHIFT) 416 417 #define GITS_BASER_SIZE_MASK 0xFFUL 418 419 #define GITS_BASER_NUM 8 420 /* Size of entries in a level 1 indirect table */ 421 #define GITS_INDIRECT_L1_ESIZE 8 422 423 #define GITS_TYPER (0x0008) 424 #define GITS_TYPER_HCC_SHIFT 24 425 #define GITS_TYPER_PTA (1UL << 19) 426 #define GITS_TYPER_DEVB_SHIFT 13 427 #define GITS_TYPER_DEVB_MASK (0x1FUL << GITS_TYPER_DEVB_SHIFT) 428 /* Number of device identifiers implemented */ 429 #define GITS_TYPER_DEVB(x) \ 430 ((((x) & GITS_TYPER_DEVB_MASK) >> GITS_TYPER_DEVB_SHIFT) + 1) 431 #define GITS_TYPER_ITTES_SHIFT 4 432 #define GITS_TYPER_ITTES_MASK (0xFUL << GITS_TYPER_ITTES_SHIFT) 433 /* Number of bytes per ITT Entry */ 434 #define GITS_TYPER_ITTES(x) \ 435 ((((x) & GITS_TYPER_ITTES_MASK) >> GITS_TYPER_ITTES_SHIFT) + 1) 436 437 #define GITS_TRANSLATER (0x10040) 438 439 /* 440 * LPI related 441 */ 442 #define LPI_CONF_PRIO_MASK (0xFC) 443 #define LPI_CONF_GROUP1 (1 << 1) 444 #define LPI_CONF_ENABLE (1 << 0) 445 446 /* 447 * GIC 500 ITS tracking facility 448 */ 449 #define GITS_TRKCTLR 0xC000 450 #define GITS_TRKR 0xC004 451 #define GITS_TRKDIDR 0xC008 452 #define GITS_TRKPIDR 0xC00C 453 #define GITS_TRKVIDR 0xC010 454 #define GITS_TRKTGTR 0xC014 455 #define GITS_TRKICR 0xC018 456 #define GITS_TRKLCR 0xC018 457 458 /* 459 * CPU interface 460 */ 461 462 /* 463 * Registers list (ICC_xyz_EL1): 464 * 465 * PMR - Priority Mask Register 466 * * interrupts of priority higher than specified 467 * in this mask will be signalled to the CPU. 468 * (0xff - lowest possible prio., 0x00 - highest prio.) 469 * 470 * CTLR - Control Register 471 * * controls behavior of the CPU interface and displays 472 * implemented features. 473 * 474 * IGRPEN1 - Interrupt Group 1 Enable Register 475 * 476 * IAR1 - Interrupt Acknowledge Register Group 1 477 * * contains number of the highest priority pending 478 * interrupt from the Group 1. 479 * 480 * EOIR1 - End of Interrupt Register Group 1 481 * * Writes inform CPU interface about completed Group 1 482 * interrupts processing. 483 */ 484 485 #define gic_icc_write(reg, val) \ 486 do { \ 487 WRITE_SPECIALREG(icc_ ##reg ##_el1, val); \ 488 isb(); \ 489 } while (0) 490 491 #define gic_icc_read(reg) \ 492 ({ \ 493 uint64_t val; \ 494 \ 495 val = READ_SPECIALREG(icc_ ##reg ##_el1); \ 496 (val); \ 497 }) 498 499 #define gic_icc_set(reg, mask) \ 500 do { \ 501 uint64_t val; \ 502 val = gic_icc_read(reg); \ 503 val |= (mask); \ 504 gic_icc_write(reg, val); \ 505 } while (0) 506 507 #define gic_icc_clear(reg, mask) \ 508 do { \ 509 uint64_t val; \ 510 val = gic_icc_read(reg); \ 511 val &= ~(mask); \ 512 gic_icc_write(reg, val); \ 513 } while (0) 514 515 #endif /* _GIC_V3_REG_H_ */ 516