1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Semihalf under 6 * the sponsorship of the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _GIC_V3_REG_H_ 33 #define _GIC_V3_REG_H_ 34 35 /* 36 * Maximum number of interrupts 37 * supported by GIC (including SGIs, PPIs and SPIs) 38 */ 39 #define GIC_I_NUM_MAX (1020) 40 /* 41 * Priority MAX/MIN values 42 */ 43 #define GIC_PRIORITY_MAX (0x00UL) 44 /* Upper value is determined by LPI max priority */ 45 #define GIC_PRIORITY_MIN (0xFCUL) 46 47 /* Numbers for shared peripheral interrupts */ 48 #define GIC_LAST_SPI (1019) 49 /* Numbers for local peripheral interrupts */ 50 #define GIC_FIRST_LPI (8192) 51 52 /* 53 * Registers (v2/v3) 54 */ 55 /* GICD_CTLR */ 56 #define GICD_CTLR_G1 (1 << 0) 57 #define GICD_CTLR_G1A (1 << 1) 58 #define GICD_CTLR_ARE_NS (1 << 4) 59 #define GICD_CTLR_RWP (1 << 31) 60 /* GICD_TYPER */ 61 #define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1) 62 63 /* 64 * Registers (v3) 65 */ 66 #define GICD_IROUTER(n) (0x6000 + ((n) * 8)) 67 68 #define GICD_PIDR4 0xFFD0 69 #define GICD_PIDR5 0xFFD4 70 #define GICD_PIDR6 0xFFD8 71 #define GICD_PIDR7 0xFFDC 72 #define GICD_PIDR0 0xFFE0 73 #define GICD_PIDR1 0xFFE4 74 #define GICD_PIDR2 0xFFE8 75 76 #define GICR_PIDR2_ARCH_SHIFT 4 77 #define GICR_PIDR2_ARCH_MASK 0xF0 78 #define GICR_PIDR2_ARCH(x) \ 79 (((x) & GICR_PIDR2_ARCH_MASK) >> GICR_PIDR2_ARCH_SHIFT) 80 #define GICR_PIDR2_ARCH_GICv3 0x3 81 #define GICR_PIDR2_ARCH_GICv4 0x4 82 83 #define GICD_PIDR3 0xFFEC 84 85 /* Redistributor registers */ 86 #define GICR_CTLR GICD_CTLR 87 #define GICR_CTLR_LPI_ENABLE (1 << 0) 88 89 #define GICR_PIDR2 GICD_PIDR2 90 91 #define GICR_TYPER (0x0008) 92 #define GICR_TYPER_PLPIS (1 << 0) 93 #define GICR_TYPER_VLPIS (1 << 1) 94 #define GICR_TYPER_LAST (1 << 4) 95 #define GICR_TYPER_CPUNUM_SHIFT (8) 96 #define GICR_TYPER_CPUNUM_MASK (0xFFFUL << GICR_TYPER_CPUNUM_SHIFT) 97 #define GICR_TYPER_CPUNUM(x) \ 98 (((x) & GICR_TYPER_CPUNUM_MASK) >> GICR_TYPER_CPUNUM_SHIFT) 99 #define GICR_TYPER_AFF_SHIFT (32) 100 101 #define GICR_WAKER (0x0014) 102 #define GICR_WAKER_PS (1 << 1) /* Processor sleep */ 103 #define GICR_WAKER_CA (1 << 2) /* Children asleep */ 104 105 #define GICR_PROPBASER (0x0070) 106 #define GICR_PROPBASER_IDBITS_MASK 0x1FUL 107 /* 108 * Cacheability 109 * 0x0 - Device-nGnRnE 110 * 0x1 - Normal Inner Non-cacheable 111 * 0x2 - Normal Inner Read-allocate, Write-through 112 * 0x3 - Normal Inner Read-allocate, Write-back 113 * 0x4 - Normal Inner Write-allocate, Write-through 114 * 0x5 - Normal Inner Write-allocate, Write-back 115 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through 116 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back 117 */ 118 #define GICR_PROPBASER_CACHE_SHIFT 7 119 #define GICR_PROPBASER_CACHE_DnGnRnE 0x0UL 120 #define GICR_PROPBASER_CACHE_NIN 0x1UL 121 #define GICR_PROPBASER_CACHE_NIRAWT 0x2UL 122 #define GICR_PROPBASER_CACHE_NIRAWB 0x3UL 123 #define GICR_PROPBASER_CACHE_NIWAWT 0x4UL 124 #define GICR_PROPBASER_CACHE_NIWAWB 0x5UL 125 #define GICR_PROPBASER_CACHE_NIRAWAWT 0x6UL 126 #define GICR_PROPBASER_CACHE_NIRAWAWB 0x7UL 127 #define GICR_PROPBASER_CACHE_MASK \ 128 (0x7UL << GICR_PROPBASER_CACHE_SHIFT) 129 130 /* 131 * Shareability 132 * 0x0 - Non-shareable 133 * 0x1 - Inner-shareable 134 * 0x2 - Outer-shareable 135 * 0x3 - Reserved. Threated as 0x0 136 */ 137 #define GICR_PROPBASER_SHARE_SHIFT 10 138 #define GICR_PROPBASER_SHARE_NS 0x0UL 139 #define GICR_PROPBASER_SHARE_IS 0x1UL 140 #define GICR_PROPBASER_SHARE_OS 0x2UL 141 #define GICR_PROPBASER_SHARE_RES 0x3UL 142 #define GICR_PROPBASER_SHARE_MASK \ 143 (0x3UL << GICR_PROPBASER_SHARE_SHIFT) 144 145 #define GICR_PENDBASER (0x0078) 146 /* 147 * Cacheability 148 * 0x0 - Device-nGnRnE 149 * 0x1 - Normal Inner Non-cacheable 150 * 0x2 - Normal Inner Read-allocate, Write-through 151 * 0x3 - Normal Inner Read-allocate, Write-back 152 * 0x4 - Normal Inner Write-allocate, Write-through 153 * 0x5 - Normal Inner Write-allocate, Write-back 154 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through 155 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back 156 */ 157 #define GICR_PENDBASER_CACHE_SHIFT 7 158 #define GICR_PENDBASER_CACHE_DnGnRnE 0x0UL 159 #define GICR_PENDBASER_CACHE_NIN 0x1UL 160 #define GICR_PENDBASER_CACHE_NIRAWT 0x2UL 161 #define GICR_PENDBASER_CACHE_NIRAWB 0x3UL 162 #define GICR_PENDBASER_CACHE_NIWAWT 0x4UL 163 #define GICR_PENDBASER_CACHE_NIWAWB 0x5UL 164 #define GICR_PENDBASER_CACHE_NIRAWAWT 0x6UL 165 #define GICR_PENDBASER_CACHE_NIRAWAWB 0x7UL 166 #define GICR_PENDBASER_CACHE_MASK \ 167 (0x7UL << GICR_PENDBASER_CACHE_SHIFT) 168 169 /* 170 * Shareability 171 * 0x0 - Non-shareable 172 * 0x1 - Inner-shareable 173 * 0x2 - Outer-shareable 174 * 0x3 - Reserved. Threated as 0x0 175 */ 176 #define GICR_PENDBASER_SHARE_SHIFT 10 177 #define GICR_PENDBASER_SHARE_NS 0x0UL 178 #define GICR_PENDBASER_SHARE_IS 0x1UL 179 #define GICR_PENDBASER_SHARE_OS 0x2UL 180 #define GICR_PENDBASER_SHARE_RES 0x3UL 181 #define GICR_PENDBASER_SHARE_MASK \ 182 (0x3UL << GICR_PENDBASER_SHARE_SHIFT) 183 184 /* Re-distributor registers for SGIs and PPIs */ 185 #define GICR_RD_BASE_SIZE PAGE_SIZE_64K 186 #define GICR_SGI_BASE_SIZE PAGE_SIZE_64K 187 #define GICR_VLPI_BASE_SIZE PAGE_SIZE_64K 188 #define GICR_RESERVED_SIZE PAGE_SIZE_64K 189 190 #define GICR_IGROUPR0 (0x0080) 191 #define GICR_ISENABLER0 (0x0100) 192 #define GICR_ICENABLER0 (0x0180) 193 #define GICR_I_ENABLER_SGI_MASK (0x0000FFFF) 194 #define GICR_I_ENABLER_PPI_MASK (0xFFFF0000) 195 196 #define GICR_I_PER_IPRIORITYn (GICD_I_PER_IPRIORITYn) 197 198 /* ITS registers */ 199 #define GITS_PIDR2 GICR_PIDR2 200 #define GITS_PIDR2_ARCH_MASK GICR_PIDR2_ARCH_MASK 201 #define GITS_PIDR2_ARCH_GICv3 GICR_PIDR2_ARCH_GICv3 202 #define GITS_PIDR2_ARCH_GICv4 GICR_PIDR2_ARCH_GICv4 203 204 #define GITS_CTLR (0x0000) 205 #define GITS_CTLR_EN (1 << 0) 206 207 #define GITS_IIDR (0x0004) 208 #define GITS_IIDR_PRODUCT_SHIFT 24 209 #define GITS_IIDR_PRODUCT_MASK (0xff << GITS_IIDR_PRODUCT_SHIFT) 210 #define GITS_IIDR_VARIANT_SHIFT 16 211 #define GITS_IIDR_VARIANT_MASK (0xf << GITS_IIDR_VARIANT_SHIFT) 212 #define GITS_IIDR_REVISION_SHIFT 12 213 #define GITS_IIDR_REVISION_MASK (0xf << GITS_IIDR_REVISION_SHIFT) 214 #define GITS_IIDR_IMPLEMENTOR_SHIFT 0 215 #define GITS_IIDR_IMPLEMENTOR_MASK (0xfff << GITS_IIDR_IMPLEMENTOR_SHIFT) 216 217 #define GITS_IIDR_RAW(impl, prod, var, rev) \ 218 ((prod) << GITS_IIDR_PRODUCT_SHIFT | \ 219 (var) << GITS_IIDR_VARIANT_SHIFT | \ 220 (rev) << GITS_IIDR_REVISION_SHIFT | \ 221 (impl) << GITS_IIDR_IMPLEMENTOR_SHIFT) 222 223 #define GITS_IIDR_IMPL_ARM (0x43B) 224 #define GITS_IIDR_PROD_GIC500 (0x0) 225 #define GITS_IIDR_IMPL_CAVIUM (0x34c) 226 #define GITS_IIDR_PROD_THUNDER (0xa1) 227 #define GITS_IIDR_VAR_THUNDER_1 (0x0) 228 229 #define GITS_CBASER (0x0080) 230 #define GITS_CBASER_VALID (1UL << 63) 231 /* 232 * Cacheability 233 * 0x0 - Device-nGnRnE 234 * 0x1 - Normal Inner Non-cacheable 235 * 0x2 - Normal Inner Read-allocate, Write-through 236 * 0x3 - Normal Inner Read-allocate, Write-back 237 * 0x4 - Normal Inner Write-allocate, Write-through 238 * 0x5 - Normal Inner Write-allocate, Write-back 239 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through 240 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back 241 */ 242 #define GITS_CBASER_CACHE_SHIFT 59 243 #define GITS_CBASER_CACHE_DnGnRnE 0x0UL 244 #define GITS_CBASER_CACHE_NIN 0x1UL 245 #define GITS_CBASER_CACHE_NIRAWT 0x2UL 246 #define GITS_CBASER_CACHE_NIRAWB 0x3UL 247 #define GITS_CBASER_CACHE_NIWAWT 0x4UL 248 #define GITS_CBASER_CACHE_NIWAWB 0x5UL 249 #define GITS_CBASER_CACHE_NIRAWAWT 0x6UL 250 #define GITS_CBASER_CACHE_NIRAWAWB 0x7UL 251 #define GITS_CBASER_CACHE_MASK (0x7UL << GITS_CBASER_CACHE_SHIFT) 252 /* 253 * Shareability 254 * 0x0 - Non-shareable 255 * 0x1 - Inner-shareable 256 * 0x2 - Outer-shareable 257 * 0x3 - Reserved. Threated as 0x0 258 */ 259 #define GITS_CBASER_SHARE_SHIFT 10 260 #define GITS_CBASER_SHARE_NS 0x0UL 261 #define GITS_CBASER_SHARE_IS 0x1UL 262 #define GITS_CBASER_SHARE_OS 0x2UL 263 #define GITS_CBASER_SHARE_RES 0x3UL 264 #define GITS_CBASER_SHARE_MASK \ 265 (0x3UL << GITS_CBASER_SHARE_SHIFT) 266 267 #define GITS_CBASER_PA_SHIFT 12 268 #define GITS_CBASER_PA_MASK (0xFFFFFFFFFUL << GITS_CBASER_PA_SHIFT) 269 270 #define GITS_CWRITER (0x0088) 271 #define GITS_CREADR (0x0090) 272 273 #define GITS_BASER_BASE (0x0100) 274 #define GITS_BASER(x) (GITS_BASER_BASE + (x) * 8) 275 276 #define GITS_BASER_VALID (1UL << 63) 277 278 #define GITS_BASER_TYPE_SHIFT 56 279 #define GITS_BASER_TYPE(x) \ 280 (((x) & GITS_BASER_TYPE_MASK) >> GITS_BASER_TYPE_SHIFT) 281 #define GITS_BASER_TYPE_UNIMPL 0x0UL /* Unimplemented */ 282 #define GITS_BASER_TYPE_DEV 0x1UL /* Devices */ 283 #define GITS_BASER_TYPE_VP 0x2UL /* Virtual Processors */ 284 #define GITS_BASER_TYPE_PP 0x3UL /* Physical Processors */ 285 #define GITS_BASER_TYPE_IC 0x4UL /* Interrupt Collections */ 286 #define GITS_BASER_TYPE_RES5 0x5UL /* Reserved */ 287 #define GITS_BASER_TYPE_RES6 0x6UL /* Reserved */ 288 #define GITS_BASER_TYPE_RES7 0x7UL /* Reserved */ 289 #define GITS_BASER_TYPE_MASK (0x7UL << GITS_BASER_TYPE_SHIFT) 290 /* 291 * Cacheability 292 * 0x0 - Non-cacheable, non-bufferable 293 * 0x1 - Non-cacheable 294 * 0x2 - Read-allocate, Write-through 295 * 0x3 - Read-allocate, Write-back 296 * 0x4 - Write-allocate, Write-through 297 * 0x5 - Write-allocate, Write-back 298 * 0x6 - Read-allocate, Write-allocate, Write-through 299 * 0x7 - Read-allocate, Write-allocate, Write-back 300 */ 301 #define GITS_BASER_CACHE_SHIFT 59 302 #define GITS_BASER_CACHE_NCNB 0x0UL 303 #define GITS_BASER_CACHE_NC 0x1UL 304 #define GITS_BASER_CACHE_RAWT 0x2UL 305 #define GITS_BASER_CACHE_RAWB 0x3UL 306 #define GITS_BASER_CACHE_WAWT 0x4UL 307 #define GITS_BASER_CACHE_WAWB 0x5UL 308 #define GITS_BASER_CACHE_RAWAWT 0x6UL 309 #define GITS_BASER_CACHE_RAWAWB 0x7UL 310 #define GITS_BASER_CACHE_MASK (0x7UL << GITS_BASER_CACHE_SHIFT) 311 312 #define GITS_BASER_ESIZE_SHIFT 48 313 #define GITS_BASER_ESIZE_MASK (0x1FUL << GITS_BASER_ESIZE_SHIFT) 314 #define GITS_BASER_ESIZE(x) \ 315 ((((x) & GITS_BASER_ESIZE_MASK) >> GITS_BASER_ESIZE_SHIFT) + 1) 316 317 #define GITS_BASER_PA_SHIFT 12 318 #define GITS_BASER_PA_MASK (0xFFFFFFFFFUL << GITS_BASER_PA_SHIFT) 319 320 /* 321 * Shareability 322 * 0x0 - Non-shareable 323 * 0x1 - Inner-shareable 324 * 0x2 - Outer-shareable 325 * 0x3 - Reserved. Threated as 0x0 326 */ 327 #define GITS_BASER_SHARE_SHIFT 10 328 #define GITS_BASER_SHARE_NS 0x0UL 329 #define GITS_BASER_SHARE_IS 0x1UL 330 #define GITS_BASER_SHARE_OS 0x2UL 331 #define GITS_BASER_SHARE_RES 0x3UL 332 #define GITS_BASER_SHARE_MASK (0x3UL << GITS_BASER_SHARE_SHIFT) 333 334 #define GITS_BASER_PSZ_SHIFT 8 335 #define GITS_BASER_PSZ_4K 0x0UL 336 #define GITS_BASER_PSZ_16K 0x1UL 337 #define GITS_BASER_PSZ_64K 0x2UL 338 #define GITS_BASER_PSZ_MASK (0x3UL << GITS_BASER_PSZ_SHIFT) 339 340 #define GITS_BASER_SIZE_MASK 0xFFUL 341 342 #define GITS_BASER_NUM 8 343 344 #define GITS_TYPER (0x0008) 345 #define GITS_TYPER_PTA (1UL << 19) 346 #define GITS_TYPER_DEVB_SHIFT 13 347 #define GITS_TYPER_DEVB_MASK (0x1FUL << GITS_TYPER_DEVB_SHIFT) 348 /* Number of device identifiers implemented */ 349 #define GITS_TYPER_DEVB(x) \ 350 ((((x) & GITS_TYPER_DEVB_MASK) >> GITS_TYPER_DEVB_SHIFT) + 1) 351 #define GITS_TYPER_ITTES_SHIFT 4 352 #define GITS_TYPER_ITTES_MASK (0xFUL << GITS_TYPER_ITTES_SHIFT) 353 /* Number of bytes per ITT Entry */ 354 #define GITS_TYPER_ITTES(x) \ 355 ((((x) & GITS_TYPER_ITTES_MASK) >> GITS_TYPER_ITTES_SHIFT) + 1) 356 357 #define GITS_TRANSLATER (0x10040) 358 /* 359 * LPI related 360 */ 361 #define LPI_CONF_PRIO_MASK (0xFC) 362 #define LPI_CONF_GROUP1 (1 << 1) 363 #define LPI_CONF_ENABLE (1 << 0) 364 365 /* 366 * GIC 500 ITS tracking facility 367 */ 368 #define GITS_TRKCTLR 0xC000 369 #define GITS_TRKR 0xC004 370 #define GITS_TRKDIDR 0xC008 371 #define GITS_TRKPIDR 0xC00C 372 #define GITS_TRKVIDR 0xC010 373 #define GITS_TRKTGTR 0xC014 374 #define GITS_TRKICR 0xC018 375 #define GITS_TRKLCR 0xC018 376 377 /* 378 * CPU interface 379 */ 380 381 /* 382 * Registers list (ICC_xyz_EL1): 383 * 384 * PMR - Priority Mask Register 385 * * interrupts of priority higher than specified 386 * in this mask will be signalled to the CPU. 387 * (0xff - lowest possible prio., 0x00 - highest prio.) 388 * 389 * CTLR - Control Register 390 * * controls behavior of the CPU interface and displays 391 * implemented features. 392 * 393 * IGRPEN1 - Interrupt Group 1 Enable Register 394 * 395 * IAR1 - Interrupt Acknowledge Register Group 1 396 * * contains number of the highest priority pending 397 * interrupt from the Group 1. 398 * 399 * EOIR1 - End of Interrupt Register Group 1 400 * * Writes inform CPU interface about completed Group 1 401 * interrupts processing. 402 */ 403 404 #define gic_icc_write(reg, val) \ 405 do { \ 406 WRITE_SPECIALREG(icc_ ##reg ##_el1, val); \ 407 isb(); \ 408 } while (0) 409 410 #define gic_icc_read(reg) \ 411 ({ \ 412 uint64_t val; \ 413 \ 414 val = READ_SPECIALREG(icc_ ##reg ##_el1); \ 415 (val); \ 416 }) 417 418 #define gic_icc_set(reg, mask) \ 419 do { \ 420 uint64_t val; \ 421 val = gic_icc_read(reg); \ 422 val |= (mask); \ 423 gic_icc_write(reg, val); \ 424 } while (0) 425 426 #define gic_icc_clear(reg, mask) \ 427 do { \ 428 uint64_t val; \ 429 val = gic_icc_read(reg); \ 430 val &= ~(mask); \ 431 gic_icc_write(reg, val); \ 432 } while (0) 433 434 #endif /* _GIC_V3_REG_H_ */ 435