1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * 4 * This software was developed by Semihalf under 5 * the sponsorship of the FreeBSD Foundation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _GIC_V3_VAR_H_ 32 #define _GIC_V3_VAR_H_ 33 34 #include <arm/arm/gic_common.h> 35 36 #define GIC_V3_DEVSTR "ARM Generic Interrupt Controller v3.0" 37 38 DECLARE_CLASS(gic_v3_driver); 39 40 struct gic_v3_irqsrc; 41 42 struct redist_pcpu { 43 struct resource res; /* mem resource for redist */ 44 vm_offset_t pend_base; 45 bool lpi_enabled; /* redist LPI configured? */ 46 }; 47 48 struct gic_redists { 49 /* 50 * Re-Distributor region description. 51 * We will have few of those depending 52 * on the #redistributor-regions property in FDT. 53 */ 54 struct resource ** regions; 55 /* Number of Re-Distributor regions */ 56 u_int nregions; 57 /* Per-CPU Re-Distributor data */ 58 struct redist_pcpu *pcpu[MAXCPU]; 59 }; 60 61 struct gic_v3_softc { 62 device_t dev; 63 struct resource ** gic_res; 64 struct mtx gic_mtx; 65 /* Distributor */ 66 struct resource * gic_dist; 67 /* Re-Distributors */ 68 struct gic_redists gic_redists; 69 70 /* Message Based Interrupts */ 71 u_int gic_mbi_start; 72 u_int gic_mbi_end; 73 struct mtx gic_mbi_mtx; 74 75 uint32_t gic_pidr2; 76 u_int gic_bus; 77 78 u_int gic_nirqs; 79 u_int gic_idbits; 80 81 boolean_t gic_registered; 82 83 int gic_nchildren; 84 device_t *gic_children; 85 struct intr_pic *gic_pic; 86 struct gic_v3_irqsrc *gic_irqs; 87 88 int nranges; 89 struct arm_gic_range * ranges; 90 }; 91 92 struct gic_v3_devinfo { 93 int gic_domain; 94 int msi_xref; 95 int is_vgic; 96 }; 97 98 #define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc) 99 100 MALLOC_DECLARE(M_GIC_V3); 101 102 /* ivars */ 103 #define GICV3_IVAR_NIRQS 1000 104 /* 1001 was GICV3_IVAR_REDIST_VADDR */ 105 #define GICV3_IVAR_REDIST 1002 106 107 __BUS_ACCESSOR(gicv3, nirqs, GICV3, NIRQS, u_int); 108 __BUS_ACCESSOR(gicv3, redist, GICV3, REDIST, void *); 109 110 /* Device methods */ 111 int gic_v3_attach(device_t dev); 112 int gic_v3_detach(device_t dev); 113 int arm_gic_v3_intr(void *); 114 115 uint32_t gic_r_read_4(device_t, bus_size_t); 116 uint64_t gic_r_read_8(device_t, bus_size_t); 117 void gic_r_write_4(device_t, bus_size_t, uint32_t var); 118 void gic_r_write_8(device_t, bus_size_t, uint64_t var); 119 120 /* 121 * GIC Distributor accessors. 122 * Notice that only GIC sofc can be passed. 123 */ 124 #define gic_d_read(sc, len, reg) \ 125 ({ \ 126 bus_read_##len(sc->gic_dist, reg); \ 127 }) 128 129 #define gic_d_write(sc, len, reg, val) \ 130 ({ \ 131 bus_write_##len(sc->gic_dist, reg, val);\ 132 }) 133 134 /* GIC Re-Distributor accessors (per-CPU) */ 135 #define gic_r_read(sc, len, reg) \ 136 ({ \ 137 u_int cpu = PCPU_GET(cpuid); \ 138 \ 139 bus_read_##len( \ 140 &sc->gic_redists.pcpu[cpu]->res, \ 141 reg); \ 142 }) 143 144 #define gic_r_write(sc, len, reg, val) \ 145 ({ \ 146 u_int cpu = PCPU_GET(cpuid); \ 147 \ 148 bus_write_##len( \ 149 &sc->gic_redists.pcpu[cpu]->res, \ 150 reg, val); \ 151 }) 152 153 #endif /* _GIC_V3_VAR_H_ */ 154