1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Semihalf under 6 * the sponsorship of the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _GIC_V3_VAR_H_ 33 #define _GIC_V3_VAR_H_ 34 35 #define GIC_V3_DEVSTR "ARM Generic Interrupt Controller v3.0" 36 37 DECLARE_CLASS(gic_v3_driver); 38 39 struct gic_v3_irqsrc; 40 41 struct redist_lpis { 42 vm_offset_t conf_base; 43 vm_offset_t pend_base[MAXCPU]; 44 uint64_t flags; 45 }; 46 47 struct gic_redists { 48 /* 49 * Re-Distributor region description. 50 * We will have few of those depending 51 * on the #redistributor-regions property in FDT. 52 */ 53 struct resource ** regions; 54 /* Number of Re-Distributor regions */ 55 u_int nregions; 56 /* Per-CPU Re-Distributor handler */ 57 struct resource * pcpu[MAXCPU]; 58 /* LPIs data */ 59 struct redist_lpis lpis; 60 }; 61 62 struct gic_v3_softc { 63 device_t dev; 64 struct resource ** gic_res; 65 struct mtx gic_mtx; 66 /* Distributor */ 67 struct resource * gic_dist; 68 /* Re-Distributors */ 69 struct gic_redists gic_redists; 70 71 uint32_t gic_pidr2; 72 u_int gic_bus; 73 74 u_int gic_nirqs; 75 u_int gic_idbits; 76 77 boolean_t gic_registered; 78 79 int gic_nchildren; 80 device_t *gic_children; 81 struct intr_pic *gic_pic; 82 struct gic_v3_irqsrc *gic_irqs; 83 }; 84 85 #define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc) 86 87 MALLOC_DECLARE(M_GIC_V3); 88 89 /* ivars */ 90 enum { 91 GICV3_IVAR_NIRQS, 92 GICV3_IVAR_REDIST_VADDR, 93 }; 94 95 __BUS_ACCESSOR(gicv3, nirqs, GICV3, NIRQS, u_int); 96 __BUS_ACCESSOR(gicv3, redist_vaddr, GICV3, REDIST_VADDR, void *); 97 98 /* Device methods */ 99 int gic_v3_attach(device_t dev); 100 int gic_v3_detach(device_t dev); 101 int arm_gic_v3_intr(void *); 102 103 uint32_t gic_r_read_4(device_t, bus_size_t); 104 uint64_t gic_r_read_8(device_t, bus_size_t); 105 void gic_r_write_4(device_t, bus_size_t, uint32_t var); 106 void gic_r_write_8(device_t, bus_size_t, uint64_t var); 107 108 /* 109 * GIC Distributor accessors. 110 * Notice that only GIC sofc can be passed. 111 */ 112 #define gic_d_read(sc, len, reg) \ 113 ({ \ 114 bus_read_##len(sc->gic_dist, reg); \ 115 }) 116 117 #define gic_d_write(sc, len, reg, val) \ 118 ({ \ 119 bus_write_##len(sc->gic_dist, reg, val);\ 120 }) 121 122 /* GIC Re-Distributor accessors (per-CPU) */ 123 #define gic_r_read(sc, len, reg) \ 124 ({ \ 125 u_int cpu = PCPU_GET(cpuid); \ 126 \ 127 bus_read_##len( \ 128 sc->gic_redists.pcpu[cpu], \ 129 reg); \ 130 }) 131 132 #define gic_r_write(sc, len, reg, val) \ 133 ({ \ 134 u_int cpu = PCPU_GET(cpuid); \ 135 \ 136 bus_write_##len( \ 137 sc->gic_redists.pcpu[cpu], \ 138 reg, val); \ 139 }) 140 141 #endif /* _GIC_V3_VAR_H_ */ 142