1 /*- 2 * Copyright (c) 2015-2016 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Andrew Turner under 6 * the sponsorship of the FreeBSD Foundation. 7 * 8 * This software was developed by Semihalf under 9 * the sponsorship of the FreeBSD Foundation. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include "opt_acpi.h" 34 #include "opt_platform.h" 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/cpuset.h> 43 #include <sys/endian.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/proc.h> 48 #include <sys/queue.h> 49 #include <sys/rman.h> 50 #include <sys/smp.h> 51 #include <sys/vmem.h> 52 53 #include <vm/vm.h> 54 #include <vm/pmap.h> 55 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 59 #include <arm/arm/gic_common.h> 60 #include <arm64/arm64/gic_v3_reg.h> 61 #include <arm64/arm64/gic_v3_var.h> 62 63 #ifdef FDT 64 #include <dev/ofw/openfirm.h> 65 #include <dev/ofw/ofw_bus.h> 66 #include <dev/ofw/ofw_bus_subr.h> 67 #endif 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 71 #include "pcib_if.h" 72 #include "pic_if.h" 73 #include "msi_if.h" 74 75 MALLOC_DEFINE(M_GICV3_ITS, "GICv3 ITS", 76 "ARM GICv3 Interrupt Translation Service"); 77 78 #define LPI_NIRQS (64 * 1024) 79 80 /* The size and alignment of the command circular buffer */ 81 #define ITS_CMDQ_SIZE (64 * 1024) /* Must be a multiple of 4K */ 82 #define ITS_CMDQ_ALIGN (64 * 1024) 83 84 #define LPI_CONFTAB_SIZE LPI_NIRQS 85 #define LPI_CONFTAB_ALIGN (64 * 1024) 86 #define LPI_CONFTAB_MAX_ADDR ((1ul << 48) - 1) /* We need a 47 bit PA */ 87 88 /* 1 bit per SPI, PPI, and SGI (8k), and 1 bit per LPI (LPI_CONFTAB_SIZE) */ 89 #define LPI_PENDTAB_SIZE ((LPI_NIRQS + GIC_FIRST_LPI) / 8) 90 #define LPI_PENDTAB_ALIGN (64 * 1024) 91 #define LPI_PENDTAB_MAX_ADDR ((1ul << 48) - 1) /* We need a 47 bit PA */ 92 93 #define LPI_INT_TRANS_TAB_ALIGN 256 94 #define LPI_INT_TRANS_TAB_MAX_ADDR ((1ul << 48) - 1) 95 96 /* ITS commands encoding */ 97 #define ITS_CMD_MOVI (0x01) 98 #define ITS_CMD_SYNC (0x05) 99 #define ITS_CMD_MAPD (0x08) 100 #define ITS_CMD_MAPC (0x09) 101 #define ITS_CMD_MAPTI (0x0a) 102 #define ITS_CMD_MAPI (0x0b) 103 #define ITS_CMD_INV (0x0c) 104 #define ITS_CMD_INVALL (0x0d) 105 /* Command */ 106 #define CMD_COMMAND_MASK (0xFFUL) 107 /* PCI device ID */ 108 #define CMD_DEVID_SHIFT (32) 109 #define CMD_DEVID_MASK (0xFFFFFFFFUL << CMD_DEVID_SHIFT) 110 /* Size of IRQ ID bitfield */ 111 #define CMD_SIZE_MASK (0xFFUL) 112 /* Virtual LPI ID */ 113 #define CMD_ID_MASK (0xFFFFFFFFUL) 114 /* Physical LPI ID */ 115 #define CMD_PID_SHIFT (32) 116 #define CMD_PID_MASK (0xFFFFFFFFUL << CMD_PID_SHIFT) 117 /* Collection */ 118 #define CMD_COL_MASK (0xFFFFUL) 119 /* Target (CPU or Re-Distributor) */ 120 #define CMD_TARGET_SHIFT (16) 121 #define CMD_TARGET_MASK (0xFFFFFFFFUL << CMD_TARGET_SHIFT) 122 /* Interrupt Translation Table address */ 123 #define CMD_ITT_MASK (0xFFFFFFFFFF00UL) 124 /* Valid command bit */ 125 #define CMD_VALID_SHIFT (63) 126 #define CMD_VALID_MASK (1UL << CMD_VALID_SHIFT) 127 128 #define ITS_TARGET_NONE 0xFBADBEEF 129 130 /* LPI chunk owned by ITS device */ 131 struct lpi_chunk { 132 u_int lpi_base; 133 u_int lpi_free; /* First free LPI in set */ 134 u_int lpi_num; /* Total number of LPIs in chunk */ 135 u_int lpi_busy; /* Number of busy LPIs in chink */ 136 }; 137 138 /* ITS device */ 139 struct its_dev { 140 TAILQ_ENTRY(its_dev) entry; 141 /* PCI device */ 142 device_t pci_dev; 143 /* Device ID (i.e. PCI device ID) */ 144 uint32_t devid; 145 /* List of assigned LPIs */ 146 struct lpi_chunk lpis; 147 /* Virtual address of ITT */ 148 vm_offset_t itt; 149 size_t itt_size; 150 }; 151 152 /* 153 * ITS command descriptor. 154 * Idea for command description passing taken from Linux. 155 */ 156 struct its_cmd_desc { 157 uint8_t cmd_type; 158 159 union { 160 struct { 161 struct its_dev *its_dev; 162 struct its_col *col; 163 uint32_t id; 164 } cmd_desc_movi; 165 166 struct { 167 struct its_col *col; 168 } cmd_desc_sync; 169 170 struct { 171 struct its_col *col; 172 uint8_t valid; 173 } cmd_desc_mapc; 174 175 struct { 176 struct its_dev *its_dev; 177 struct its_col *col; 178 uint32_t pid; 179 uint32_t id; 180 } cmd_desc_mapvi; 181 182 struct { 183 struct its_dev *its_dev; 184 struct its_col *col; 185 uint32_t pid; 186 } cmd_desc_mapi; 187 188 struct { 189 struct its_dev *its_dev; 190 uint8_t valid; 191 } cmd_desc_mapd; 192 193 struct { 194 struct its_dev *its_dev; 195 struct its_col *col; 196 uint32_t pid; 197 } cmd_desc_inv; 198 199 struct { 200 struct its_col *col; 201 } cmd_desc_invall; 202 }; 203 }; 204 205 /* ITS command. Each command is 32 bytes long */ 206 struct its_cmd { 207 uint64_t cmd_dword[4]; /* ITS command double word */ 208 }; 209 210 /* An ITS private table */ 211 struct its_ptable { 212 vm_offset_t ptab_vaddr; 213 unsigned long ptab_size; 214 }; 215 216 /* ITS collection description. */ 217 struct its_col { 218 uint64_t col_target; /* Target Re-Distributor */ 219 uint64_t col_id; /* Collection ID */ 220 }; 221 222 struct gicv3_its_irqsrc { 223 struct intr_irqsrc gi_isrc; 224 u_int gi_irq; 225 struct its_dev *gi_its_dev; 226 }; 227 228 struct gicv3_its_softc { 229 struct intr_pic *sc_pic; 230 struct resource *sc_its_res; 231 232 cpuset_t sc_cpus; 233 u_int gic_irq_cpu; 234 235 struct its_ptable sc_its_ptab[GITS_BASER_NUM]; 236 struct its_col *sc_its_cols[MAXCPU]; /* Per-CPU collections */ 237 238 /* 239 * TODO: We should get these from the parent as we only want a 240 * single copy of each across the interrupt controller. 241 */ 242 vm_offset_t sc_conf_base; 243 vm_offset_t sc_pend_base[MAXCPU]; 244 245 /* Command handling */ 246 struct mtx sc_its_cmd_lock; 247 struct its_cmd *sc_its_cmd_base; /* Command circular buffer address */ 248 size_t sc_its_cmd_next_idx; 249 250 vmem_t *sc_irq_alloc; 251 struct gicv3_its_irqsrc *sc_irqs; 252 u_int sc_irq_base; 253 u_int sc_irq_length; 254 255 struct mtx sc_its_dev_lock; 256 TAILQ_HEAD(its_dev_list, its_dev) sc_its_dev_list; 257 258 #define ITS_FLAGS_CMDQ_FLUSH 0x00000001 259 #define ITS_FLAGS_LPI_CONF_FLUSH 0x00000002 260 #define ITS_FLAGS_ERRATA_CAVIUM_22375 0x00000004 261 u_int sc_its_flags; 262 }; 263 264 typedef void (its_quirk_func_t)(device_t); 265 static its_quirk_func_t its_quirk_cavium_22375; 266 267 static const struct { 268 const char *desc; 269 uint32_t iidr; 270 uint32_t iidr_mask; 271 its_quirk_func_t *func; 272 } its_quirks[] = { 273 { 274 /* Cavium ThunderX Pass 1.x */ 275 .desc = "Cavoum ThunderX errata: 22375, 24313", 276 .iidr = GITS_IIDR_RAW(GITS_IIDR_IMPL_CAVIUM, 277 GITS_IIDR_PROD_THUNDER, GITS_IIDR_VAR_THUNDER_1, 0), 278 .iidr_mask = ~GITS_IIDR_REVISION_MASK, 279 .func = its_quirk_cavium_22375, 280 }, 281 }; 282 283 #define gic_its_read_4(sc, reg) \ 284 bus_read_4((sc)->sc_its_res, (reg)) 285 #define gic_its_read_8(sc, reg) \ 286 bus_read_8((sc)->sc_its_res, (reg)) 287 288 #define gic_its_write_4(sc, reg, val) \ 289 bus_write_4((sc)->sc_its_res, (reg), (val)) 290 #define gic_its_write_8(sc, reg, val) \ 291 bus_write_8((sc)->sc_its_res, (reg), (val)) 292 293 static device_attach_t gicv3_its_attach; 294 static device_detach_t gicv3_its_detach; 295 296 static pic_disable_intr_t gicv3_its_disable_intr; 297 static pic_enable_intr_t gicv3_its_enable_intr; 298 static pic_map_intr_t gicv3_its_map_intr; 299 static pic_setup_intr_t gicv3_its_setup_intr; 300 static pic_post_filter_t gicv3_its_post_filter; 301 static pic_post_ithread_t gicv3_its_post_ithread; 302 static pic_pre_ithread_t gicv3_its_pre_ithread; 303 static pic_bind_intr_t gicv3_its_bind_intr; 304 #ifdef SMP 305 static pic_init_secondary_t gicv3_its_init_secondary; 306 #endif 307 static msi_alloc_msi_t gicv3_its_alloc_msi; 308 static msi_release_msi_t gicv3_its_release_msi; 309 static msi_alloc_msix_t gicv3_its_alloc_msix; 310 static msi_release_msix_t gicv3_its_release_msix; 311 static msi_map_msi_t gicv3_its_map_msi; 312 313 static void its_cmd_movi(device_t, struct gicv3_its_irqsrc *); 314 static void its_cmd_mapc(device_t, struct its_col *, uint8_t); 315 static void its_cmd_mapti(device_t, struct gicv3_its_irqsrc *); 316 static void its_cmd_mapd(device_t, struct its_dev *, uint8_t); 317 static void its_cmd_inv(device_t, struct its_dev *, struct gicv3_its_irqsrc *); 318 static void its_cmd_invall(device_t, struct its_col *); 319 320 static device_method_t gicv3_its_methods[] = { 321 /* Device interface */ 322 DEVMETHOD(device_detach, gicv3_its_detach), 323 324 /* Interrupt controller interface */ 325 DEVMETHOD(pic_disable_intr, gicv3_its_disable_intr), 326 DEVMETHOD(pic_enable_intr, gicv3_its_enable_intr), 327 DEVMETHOD(pic_map_intr, gicv3_its_map_intr), 328 DEVMETHOD(pic_setup_intr, gicv3_its_setup_intr), 329 DEVMETHOD(pic_post_filter, gicv3_its_post_filter), 330 DEVMETHOD(pic_post_ithread, gicv3_its_post_ithread), 331 DEVMETHOD(pic_pre_ithread, gicv3_its_pre_ithread), 332 #ifdef SMP 333 DEVMETHOD(pic_bind_intr, gicv3_its_bind_intr), 334 DEVMETHOD(pic_init_secondary, gicv3_its_init_secondary), 335 #endif 336 337 /* MSI/MSI-X */ 338 DEVMETHOD(msi_alloc_msi, gicv3_its_alloc_msi), 339 DEVMETHOD(msi_release_msi, gicv3_its_release_msi), 340 DEVMETHOD(msi_alloc_msix, gicv3_its_alloc_msix), 341 DEVMETHOD(msi_release_msix, gicv3_its_release_msix), 342 DEVMETHOD(msi_map_msi, gicv3_its_map_msi), 343 344 /* End */ 345 DEVMETHOD_END 346 }; 347 348 static DEFINE_CLASS_0(gic, gicv3_its_driver, gicv3_its_methods, 349 sizeof(struct gicv3_its_softc)); 350 351 static void 352 gicv3_its_cmdq_init(struct gicv3_its_softc *sc) 353 { 354 vm_paddr_t cmd_paddr; 355 uint64_t reg, tmp; 356 357 /* Set up the command circular buffer */ 358 sc->sc_its_cmd_base = contigmalloc(ITS_CMDQ_SIZE, M_GICV3_ITS, 359 M_WAITOK | M_ZERO, 0, (1ul << 48) - 1, ITS_CMDQ_ALIGN, 0); 360 sc->sc_its_cmd_next_idx = 0; 361 362 cmd_paddr = vtophys(sc->sc_its_cmd_base); 363 364 /* Set the base of the command buffer */ 365 reg = GITS_CBASER_VALID | 366 (GITS_CBASER_CACHE_NIWAWB << GITS_CBASER_CACHE_SHIFT) | 367 cmd_paddr | (GITS_CBASER_SHARE_IS << GITS_CBASER_SHARE_SHIFT) | 368 (ITS_CMDQ_SIZE / 4096 - 1); 369 gic_its_write_8(sc, GITS_CBASER, reg); 370 371 /* Read back to check for fixed value fields */ 372 tmp = gic_its_read_8(sc, GITS_CBASER); 373 374 if ((tmp & GITS_CBASER_SHARE_MASK) != 375 (GITS_CBASER_SHARE_IS << GITS_CBASER_SHARE_SHIFT)) { 376 /* Check if the hardware reported non-shareable */ 377 if ((tmp & GITS_CBASER_SHARE_MASK) == 378 (GITS_CBASER_SHARE_NS << GITS_CBASER_SHARE_SHIFT)) { 379 /* If so remove the cache attribute */ 380 reg &= ~GITS_CBASER_CACHE_MASK; 381 reg &= ~GITS_CBASER_SHARE_MASK; 382 /* Set to Non-cacheable, Non-shareable */ 383 reg |= GITS_CBASER_CACHE_NIN << GITS_CBASER_CACHE_SHIFT; 384 reg |= GITS_CBASER_SHARE_NS << GITS_CBASER_SHARE_SHIFT; 385 386 gic_its_write_8(sc, GITS_CBASER, reg); 387 } 388 389 /* The command queue has to be flushed after each command */ 390 sc->sc_its_flags |= ITS_FLAGS_CMDQ_FLUSH; 391 } 392 393 /* Get the next command from the start of the buffer */ 394 gic_its_write_8(sc, GITS_CWRITER, 0x0); 395 } 396 397 static int 398 gicv3_its_table_init(device_t dev, struct gicv3_its_softc *sc) 399 { 400 vm_offset_t table; 401 vm_paddr_t paddr; 402 uint64_t cache, reg, share, tmp, type; 403 size_t esize, its_tbl_size, nidents, nitspages, npages; 404 int i, page_size; 405 int devbits; 406 407 if ((sc->sc_its_flags & ITS_FLAGS_ERRATA_CAVIUM_22375) != 0) { 408 /* 409 * GITS_TYPER[17:13] of ThunderX reports that device IDs 410 * are to be 21 bits in length. The entry size of the ITS 411 * table can be read from GITS_BASERn[52:48] and on ThunderX 412 * is supposed to be 8 bytes in length (for device table). 413 * Finally the page size that is to be used by ITS to access 414 * this table will be set to 64KB. 415 * 416 * This gives 0x200000 entries of size 0x8 bytes covered by 417 * 256 pages each of which 64KB in size. The number of pages 418 * (minus 1) should then be written to GITS_BASERn[7:0]. In 419 * that case this value would be 0xFF but on ThunderX the 420 * maximum value that HW accepts is 0xFD. 421 * 422 * Set an arbitrary number of device ID bits to 20 in order 423 * to limit the number of entries in ITS device table to 424 * 0x100000 and the table size to 8MB. 425 */ 426 devbits = 20; 427 cache = 0; 428 } else { 429 devbits = GITS_TYPER_DEVB(gic_its_read_8(sc, GITS_TYPER)); 430 cache = GITS_BASER_CACHE_WAWB; 431 } 432 share = GITS_BASER_SHARE_IS; 433 page_size = PAGE_SIZE_64K; 434 435 for (i = 0; i < GITS_BASER_NUM; i++) { 436 reg = gic_its_read_8(sc, GITS_BASER(i)); 437 /* The type of table */ 438 type = GITS_BASER_TYPE(reg); 439 /* The table entry size */ 440 esize = GITS_BASER_ESIZE(reg); 441 442 switch(type) { 443 case GITS_BASER_TYPE_DEV: 444 nidents = (1 << devbits); 445 its_tbl_size = esize * nidents; 446 its_tbl_size = roundup2(its_tbl_size, PAGE_SIZE_64K); 447 break; 448 case GITS_BASER_TYPE_VP: 449 case GITS_BASER_TYPE_PP: /* Undocumented? */ 450 case GITS_BASER_TYPE_IC: 451 its_tbl_size = page_size; 452 break; 453 default: 454 continue; 455 } 456 npages = howmany(its_tbl_size, PAGE_SIZE); 457 458 /* Allocate the table */ 459 table = (vm_offset_t)contigmalloc(npages * PAGE_SIZE, 460 M_GICV3_ITS, M_WAITOK | M_ZERO, 0, (1ul << 48) - 1, 461 PAGE_SIZE_64K, 0); 462 463 sc->sc_its_ptab[i].ptab_vaddr = table; 464 sc->sc_its_ptab[i].ptab_size = npages * PAGE_SIZE; 465 466 paddr = vtophys(table); 467 468 while (1) { 469 nitspages = howmany(its_tbl_size, page_size); 470 471 /* Clear the fields we will be setting */ 472 reg &= ~(GITS_BASER_VALID | 473 GITS_BASER_CACHE_MASK | GITS_BASER_TYPE_MASK | 474 GITS_BASER_ESIZE_MASK | GITS_BASER_PA_MASK | 475 GITS_BASER_SHARE_MASK | GITS_BASER_PSZ_MASK | 476 GITS_BASER_SIZE_MASK); 477 /* Set the new values */ 478 reg |= GITS_BASER_VALID | 479 (cache << GITS_BASER_CACHE_SHIFT) | 480 (type << GITS_BASER_TYPE_SHIFT) | 481 ((esize - 1) << GITS_BASER_ESIZE_SHIFT) | 482 paddr | (share << GITS_BASER_SHARE_SHIFT) | 483 (nitspages - 1); 484 485 switch (page_size) { 486 case PAGE_SIZE: /* 4KB */ 487 reg |= 488 GITS_BASER_PSZ_4K << GITS_BASER_PSZ_SHIFT; 489 break; 490 case PAGE_SIZE_16K: /* 16KB */ 491 reg |= 492 GITS_BASER_PSZ_16K << GITS_BASER_PSZ_SHIFT; 493 break; 494 case PAGE_SIZE_64K: /* 64KB */ 495 reg |= 496 GITS_BASER_PSZ_64K << GITS_BASER_PSZ_SHIFT; 497 break; 498 } 499 500 gic_its_write_8(sc, GITS_BASER(i), reg); 501 502 /* Read back to check */ 503 tmp = gic_its_read_8(sc, GITS_BASER(i)); 504 505 /* Do the shareability masks line up? */ 506 if ((tmp & GITS_BASER_SHARE_MASK) != 507 (reg & GITS_BASER_SHARE_MASK)) { 508 share = (tmp & GITS_BASER_SHARE_MASK) >> 509 GITS_BASER_SHARE_SHIFT; 510 continue; 511 } 512 513 if ((tmp & GITS_BASER_PSZ_MASK) != 514 (reg & GITS_BASER_PSZ_MASK)) { 515 switch (page_size) { 516 case PAGE_SIZE_16K: 517 page_size = PAGE_SIZE; 518 continue; 519 case PAGE_SIZE_64K: 520 page_size = PAGE_SIZE_16K; 521 continue; 522 } 523 } 524 525 if (tmp != reg) { 526 device_printf(dev, "GITS_BASER%d: " 527 "unable to be updated: %lx != %lx\n", 528 i, reg, tmp); 529 return (ENXIO); 530 } 531 532 /* We should have made all needed changes */ 533 break; 534 } 535 } 536 537 return (0); 538 } 539 540 static void 541 gicv3_its_conftable_init(struct gicv3_its_softc *sc) 542 { 543 544 sc->sc_conf_base = (vm_offset_t)contigmalloc(LPI_CONFTAB_SIZE, 545 M_GICV3_ITS, M_WAITOK, 0, LPI_CONFTAB_MAX_ADDR, LPI_CONFTAB_ALIGN, 546 0); 547 548 /* Set the default configuration */ 549 memset((void *)sc->sc_conf_base, GIC_PRIORITY_MAX | LPI_CONF_GROUP1, 550 LPI_CONFTAB_SIZE); 551 552 /* Flush the table to memory */ 553 cpu_dcache_wb_range(sc->sc_conf_base, LPI_CONFTAB_SIZE); 554 } 555 556 static void 557 gicv3_its_pendtables_init(struct gicv3_its_softc *sc) 558 { 559 int i; 560 561 for (i = 0; i <= mp_maxid; i++) { 562 if (CPU_ISSET(i, &sc->sc_cpus) == 0) 563 continue; 564 565 sc->sc_pend_base[i] = (vm_offset_t)contigmalloc( 566 LPI_PENDTAB_SIZE, M_GICV3_ITS, M_WAITOK | M_ZERO, 567 0, LPI_PENDTAB_MAX_ADDR, LPI_PENDTAB_ALIGN, 0); 568 569 /* Flush so the ITS can see the memory */ 570 cpu_dcache_wb_range((vm_offset_t)sc->sc_pend_base[i], 571 LPI_PENDTAB_SIZE); 572 } 573 } 574 575 static int 576 its_init_cpu(device_t dev, struct gicv3_its_softc *sc) 577 { 578 device_t gicv3; 579 vm_paddr_t target; 580 uint64_t xbaser, tmp; 581 uint32_t ctlr; 582 u_int cpuid; 583 584 gicv3 = device_get_parent(dev); 585 cpuid = PCPU_GET(cpuid); 586 if (!CPU_ISSET(cpuid, &sc->sc_cpus)) 587 return (0); 588 589 /* Check if the ITS is enabled on this CPU */ 590 if ((gic_r_read_4(gicv3, GICR_TYPER) & GICR_TYPER_PLPIS) == 0) { 591 return (ENXIO); 592 } 593 594 /* Disable LPIs */ 595 ctlr = gic_r_read_4(gicv3, GICR_CTLR); 596 ctlr &= ~GICR_CTLR_LPI_ENABLE; 597 gic_r_write_4(gicv3, GICR_CTLR, ctlr); 598 599 /* Make sure changes are observable my the GIC */ 600 dsb(sy); 601 602 /* 603 * Set the redistributor base 604 */ 605 xbaser = vtophys(sc->sc_conf_base) | 606 (GICR_PROPBASER_SHARE_IS << GICR_PROPBASER_SHARE_SHIFT) | 607 (GICR_PROPBASER_CACHE_NIWAWB << GICR_PROPBASER_CACHE_SHIFT) | 608 (flsl(LPI_CONFTAB_SIZE | GIC_FIRST_LPI) - 1); 609 gic_r_write_8(gicv3, GICR_PROPBASER, xbaser); 610 611 /* Check the cache attributes we set */ 612 tmp = gic_r_read_8(gicv3, GICR_PROPBASER); 613 614 if ((tmp & GICR_PROPBASER_SHARE_MASK) != 615 (xbaser & GICR_PROPBASER_SHARE_MASK)) { 616 if ((tmp & GICR_PROPBASER_SHARE_MASK) == 617 (GICR_PROPBASER_SHARE_NS << GICR_PROPBASER_SHARE_SHIFT)) { 618 /* We need to mark as non-cacheable */ 619 xbaser &= ~(GICR_PROPBASER_SHARE_MASK | 620 GICR_PROPBASER_CACHE_MASK); 621 /* Non-cacheable */ 622 xbaser |= GICR_PROPBASER_CACHE_NIN << 623 GICR_PROPBASER_CACHE_SHIFT; 624 /* Non-sareable */ 625 xbaser |= GICR_PROPBASER_SHARE_NS << 626 GICR_PROPBASER_SHARE_SHIFT; 627 gic_r_write_8(gicv3, GICR_PROPBASER, xbaser); 628 } 629 sc->sc_its_flags |= ITS_FLAGS_LPI_CONF_FLUSH; 630 } 631 632 /* 633 * Set the LPI pending table base 634 */ 635 xbaser = vtophys(sc->sc_pend_base[cpuid]) | 636 (GICR_PENDBASER_CACHE_NIWAWB << GICR_PENDBASER_CACHE_SHIFT) | 637 (GICR_PENDBASER_SHARE_IS << GICR_PENDBASER_SHARE_SHIFT); 638 639 gic_r_write_8(gicv3, GICR_PENDBASER, xbaser); 640 641 tmp = gic_r_read_8(gicv3, GICR_PENDBASER); 642 643 if ((tmp & GICR_PENDBASER_SHARE_MASK) == 644 (GICR_PENDBASER_SHARE_NS << GICR_PENDBASER_SHARE_SHIFT)) { 645 /* Clear the cahce and shareability bits */ 646 xbaser &= ~(GICR_PENDBASER_CACHE_MASK | 647 GICR_PENDBASER_SHARE_MASK); 648 /* Mark as non-shareable */ 649 xbaser |= GICR_PENDBASER_SHARE_NS << GICR_PENDBASER_SHARE_SHIFT; 650 /* And non-cacheable */ 651 xbaser |= GICR_PENDBASER_CACHE_NIN << 652 GICR_PENDBASER_CACHE_SHIFT; 653 } 654 655 /* Enable LPIs */ 656 ctlr = gic_r_read_4(gicv3, GICR_CTLR); 657 ctlr |= GICR_CTLR_LPI_ENABLE; 658 gic_r_write_4(gicv3, GICR_CTLR, ctlr); 659 660 /* Make sure the GIC has seen everything */ 661 dsb(sy); 662 663 if ((gic_its_read_8(sc, GITS_TYPER) & GITS_TYPER_PTA) != 0) { 664 /* This ITS wants the redistributor physical address */ 665 target = vtophys(gicv3_get_redist_vaddr(dev)); 666 } else { 667 /* This ITS wants the unique processor number */ 668 target = GICR_TYPER_CPUNUM(gic_r_read_8(gicv3, GICR_TYPER)); 669 } 670 671 sc->sc_its_cols[cpuid]->col_target = target; 672 sc->sc_its_cols[cpuid]->col_id = cpuid; 673 674 its_cmd_mapc(dev, sc->sc_its_cols[cpuid], 1); 675 its_cmd_invall(dev, sc->sc_its_cols[cpuid]); 676 677 return (0); 678 } 679 680 static int 681 gicv3_its_attach(device_t dev) 682 { 683 struct gicv3_its_softc *sc; 684 const char *name; 685 uint32_t iidr; 686 int domain, err, i, rid; 687 688 sc = device_get_softc(dev); 689 690 sc->sc_irq_length = gicv3_get_nirqs(dev); 691 sc->sc_irq_base = GIC_FIRST_LPI; 692 sc->sc_irq_base += device_get_unit(dev) * sc->sc_irq_length; 693 694 rid = 0; 695 sc->sc_its_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 696 RF_ACTIVE); 697 if (sc->sc_its_res == NULL) { 698 device_printf(dev, "Could not allocate memory\n"); 699 return (ENXIO); 700 } 701 702 iidr = gic_its_read_4(sc, GITS_IIDR); 703 for (i = 0; i < nitems(its_quirks); i++) { 704 if ((iidr & its_quirks[i].iidr_mask) == its_quirks[i].iidr) { 705 if (bootverbose) { 706 device_printf(dev, "Applying %s\n", 707 its_quirks[i].desc); 708 } 709 its_quirks[i].func(dev); 710 break; 711 } 712 } 713 714 /* Allocate the private tables */ 715 err = gicv3_its_table_init(dev, sc); 716 if (err != 0) 717 return (err); 718 719 /* Protects access to the device list */ 720 mtx_init(&sc->sc_its_dev_lock, "ITS device lock", NULL, MTX_SPIN); 721 722 /* Protects access to the ITS command circular buffer. */ 723 mtx_init(&sc->sc_its_cmd_lock, "ITS cmd lock", NULL, MTX_SPIN); 724 725 CPU_ZERO(&sc->sc_cpus); 726 if (bus_get_domain(dev, &domain) == 0) { 727 if (domain < MAXMEMDOM) 728 CPU_COPY(&cpuset_domain[domain], &sc->sc_cpus); 729 } else { 730 /* XXX : cannot handle more than one ITS per cpu */ 731 if (device_get_unit(dev) == 0) 732 CPU_COPY(&all_cpus, &sc->sc_cpus); 733 } 734 735 /* Allocate the command circular buffer */ 736 gicv3_its_cmdq_init(sc); 737 738 /* Allocate the per-CPU collections */ 739 for (int cpu = 0; cpu <= mp_maxid; cpu++) 740 if (CPU_ISSET(cpu, &sc->sc_cpus) != 0) 741 sc->sc_its_cols[cpu] = malloc( 742 sizeof(*sc->sc_its_cols[0]), M_GICV3_ITS, 743 M_WAITOK | M_ZERO); 744 else 745 sc->sc_its_cols[cpu] = NULL; 746 747 /* Enable the ITS */ 748 gic_its_write_4(sc, GITS_CTLR, 749 gic_its_read_4(sc, GITS_CTLR) | GITS_CTLR_EN); 750 751 /* Create the LPI configuration table */ 752 gicv3_its_conftable_init(sc); 753 754 /* And the pending tebles */ 755 gicv3_its_pendtables_init(sc); 756 757 /* Enable LPIs on this CPU */ 758 its_init_cpu(dev, sc); 759 760 TAILQ_INIT(&sc->sc_its_dev_list); 761 762 /* 763 * Create the vmem object to allocate INTRNG IRQs from. We try to 764 * use all IRQs not already used by the GICv3. 765 * XXX: This assumes there are no other interrupt controllers in the 766 * system. 767 */ 768 sc->sc_irq_alloc = vmem_create("GICv3 ITS IRQs", 0, 769 gicv3_get_nirqs(dev), 1, 1, M_FIRSTFIT | M_WAITOK); 770 771 sc->sc_irqs = malloc(sizeof(*sc->sc_irqs) * sc->sc_irq_length, 772 M_GICV3_ITS, M_WAITOK | M_ZERO); 773 name = device_get_nameunit(dev); 774 for (i = 0; i < sc->sc_irq_length; i++) { 775 sc->sc_irqs[i].gi_irq = i; 776 err = intr_isrc_register(&sc->sc_irqs[i].gi_isrc, dev, 0, 777 "%s,%u", name, i); 778 } 779 780 return (0); 781 } 782 783 static int 784 gicv3_its_detach(device_t dev) 785 { 786 787 return (ENXIO); 788 } 789 790 static void 791 its_quirk_cavium_22375(device_t dev) 792 { 793 struct gicv3_its_softc *sc; 794 795 sc = device_get_softc(dev); 796 sc->sc_its_flags |= ITS_FLAGS_ERRATA_CAVIUM_22375; 797 } 798 799 static void 800 gicv3_its_disable_intr(device_t dev, struct intr_irqsrc *isrc) 801 { 802 struct gicv3_its_softc *sc; 803 struct gicv3_its_irqsrc *girq; 804 uint8_t *conf; 805 806 sc = device_get_softc(dev); 807 girq = (struct gicv3_its_irqsrc *)isrc; 808 conf = (uint8_t *)sc->sc_conf_base; 809 810 conf[girq->gi_irq] &= ~LPI_CONF_ENABLE; 811 812 if ((sc->sc_its_flags & ITS_FLAGS_LPI_CONF_FLUSH) != 0) { 813 /* Clean D-cache under command. */ 814 cpu_dcache_wb_range((vm_offset_t)&conf[girq->gi_irq], 1); 815 } else { 816 /* DSB inner shareable, store */ 817 dsb(ishst); 818 } 819 820 its_cmd_inv(dev, girq->gi_its_dev, girq); 821 } 822 823 static void 824 gicv3_its_enable_intr(device_t dev, struct intr_irqsrc *isrc) 825 { 826 struct gicv3_its_softc *sc; 827 struct gicv3_its_irqsrc *girq; 828 uint8_t *conf; 829 830 sc = device_get_softc(dev); 831 girq = (struct gicv3_its_irqsrc *)isrc; 832 conf = (uint8_t *)sc->sc_conf_base; 833 834 conf[girq->gi_irq] |= LPI_CONF_ENABLE; 835 836 if ((sc->sc_its_flags & ITS_FLAGS_LPI_CONF_FLUSH) != 0) { 837 /* Clean D-cache under command. */ 838 cpu_dcache_wb_range((vm_offset_t)&conf[girq->gi_irq], 1); 839 } else { 840 /* DSB inner shareable, store */ 841 dsb(ishst); 842 } 843 844 its_cmd_inv(dev, girq->gi_its_dev, girq); 845 } 846 847 static int 848 gicv3_its_intr(void *arg, uintptr_t irq) 849 { 850 struct gicv3_its_softc *sc = arg; 851 struct gicv3_its_irqsrc *girq; 852 struct trapframe *tf; 853 854 irq -= sc->sc_irq_base; 855 girq = &sc->sc_irqs[irq]; 856 if (girq == NULL) 857 panic("gicv3_its_intr: Invalid interrupt %ld", 858 irq + sc->sc_irq_base); 859 860 tf = curthread->td_intr_frame; 861 intr_isrc_dispatch(&girq->gi_isrc, tf); 862 return (FILTER_HANDLED); 863 } 864 865 static void 866 gicv3_its_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 867 { 868 struct gicv3_its_irqsrc *girq; 869 struct gicv3_its_softc *sc; 870 871 sc = device_get_softc(dev); 872 girq = (struct gicv3_its_irqsrc *)isrc; 873 gicv3_its_disable_intr(dev, isrc); 874 gic_icc_write(EOIR1, girq->gi_irq + sc->sc_irq_base); 875 } 876 877 static void 878 gicv3_its_post_ithread(device_t dev, struct intr_irqsrc *isrc) 879 { 880 881 gicv3_its_enable_intr(dev, isrc); 882 } 883 884 static void 885 gicv3_its_post_filter(device_t dev, struct intr_irqsrc *isrc) 886 { 887 struct gicv3_its_irqsrc *girq; 888 struct gicv3_its_softc *sc; 889 890 sc = device_get_softc(dev); 891 girq = (struct gicv3_its_irqsrc *)isrc; 892 gic_icc_write(EOIR1, girq->gi_irq + sc->sc_irq_base); 893 } 894 895 static int 896 gicv3_its_bind_intr(device_t dev, struct intr_irqsrc *isrc) 897 { 898 struct gicv3_its_irqsrc *girq; 899 struct gicv3_its_softc *sc; 900 901 sc = device_get_softc(dev); 902 girq = (struct gicv3_its_irqsrc *)isrc; 903 if (CPU_EMPTY(&isrc->isrc_cpu)) { 904 sc->gic_irq_cpu = intr_irq_next_cpu(sc->gic_irq_cpu, 905 &sc->sc_cpus); 906 CPU_SETOF(sc->gic_irq_cpu, &isrc->isrc_cpu); 907 } 908 909 its_cmd_movi(dev, girq); 910 911 return (0); 912 } 913 914 static int 915 gicv3_its_map_intr(device_t dev, struct intr_map_data *data, 916 struct intr_irqsrc **isrcp) 917 { 918 919 /* 920 * This should never happen, we only call this function to map 921 * interrupts found before the controller driver is ready. 922 */ 923 panic("gicv3_its_map_intr: Unable to map a MSI interrupt"); 924 } 925 926 static int 927 gicv3_its_setup_intr(device_t dev, struct intr_irqsrc *isrc, 928 struct resource *res, struct intr_map_data *data) 929 { 930 931 /* Bind the interrupt to a CPU */ 932 gicv3_its_bind_intr(dev, isrc); 933 934 return (0); 935 } 936 937 #ifdef SMP 938 static void 939 gicv3_its_init_secondary(device_t dev) 940 { 941 struct gicv3_its_softc *sc; 942 943 sc = device_get_softc(dev); 944 945 /* 946 * This is fatal as otherwise we may bind interrupts to this CPU. 947 * We need a way to tell the interrupt framework to only bind to a 948 * subset of given CPUs when it performs the shuffle. 949 */ 950 if (its_init_cpu(dev, sc) != 0) 951 panic("gicv3_its_init_secondary: No usable ITS on CPU%d", 952 PCPU_GET(cpuid)); 953 } 954 #endif 955 956 static uint32_t 957 its_get_devid(device_t pci_dev) 958 { 959 uintptr_t id; 960 961 if (pci_get_id(pci_dev, PCI_ID_MSI, &id) != 0) 962 panic("its_get_devid: Unable to get the MSI DeviceID"); 963 964 return (id); 965 } 966 967 static struct its_dev * 968 its_device_find(device_t dev, device_t child) 969 { 970 struct gicv3_its_softc *sc; 971 struct its_dev *its_dev = NULL; 972 973 sc = device_get_softc(dev); 974 975 mtx_lock_spin(&sc->sc_its_dev_lock); 976 TAILQ_FOREACH(its_dev, &sc->sc_its_dev_list, entry) { 977 if (its_dev->pci_dev == child) 978 break; 979 } 980 mtx_unlock_spin(&sc->sc_its_dev_lock); 981 982 return (its_dev); 983 } 984 985 static struct its_dev * 986 its_device_get(device_t dev, device_t child, u_int nvecs) 987 { 988 struct gicv3_its_softc *sc; 989 struct its_dev *its_dev; 990 vmem_addr_t irq_base; 991 size_t esize; 992 993 sc = device_get_softc(dev); 994 995 its_dev = its_device_find(dev, child); 996 if (its_dev != NULL) 997 return (its_dev); 998 999 its_dev = malloc(sizeof(*its_dev), M_GICV3_ITS, M_NOWAIT | M_ZERO); 1000 if (its_dev == NULL) 1001 return (NULL); 1002 1003 its_dev->pci_dev = child; 1004 its_dev->devid = its_get_devid(child); 1005 1006 its_dev->lpis.lpi_busy = 0; 1007 its_dev->lpis.lpi_num = nvecs; 1008 its_dev->lpis.lpi_free = nvecs; 1009 1010 if (vmem_alloc(sc->sc_irq_alloc, nvecs, M_FIRSTFIT | M_NOWAIT, 1011 &irq_base) != 0) { 1012 free(its_dev, M_GICV3_ITS); 1013 return (NULL); 1014 } 1015 its_dev->lpis.lpi_base = irq_base; 1016 1017 /* Get ITT entry size */ 1018 esize = GITS_TYPER_ITTES(gic_its_read_8(sc, GITS_TYPER)); 1019 1020 /* 1021 * Allocate ITT for this device. 1022 * PA has to be 256 B aligned. At least two entries for device. 1023 */ 1024 its_dev->itt_size = roundup2(MAX(nvecs, 2) * esize, 256); 1025 its_dev->itt = (vm_offset_t)contigmalloc(its_dev->itt_size, 1026 M_GICV3_ITS, M_NOWAIT | M_ZERO, 0, LPI_INT_TRANS_TAB_MAX_ADDR, 1027 LPI_INT_TRANS_TAB_ALIGN, 0); 1028 if (its_dev->itt == 0) { 1029 vmem_free(sc->sc_irq_alloc, its_dev->lpis.lpi_base, nvecs); 1030 free(its_dev, M_GICV3_ITS); 1031 return (NULL); 1032 } 1033 1034 mtx_lock_spin(&sc->sc_its_dev_lock); 1035 TAILQ_INSERT_TAIL(&sc->sc_its_dev_list, its_dev, entry); 1036 mtx_unlock_spin(&sc->sc_its_dev_lock); 1037 1038 /* Map device to its ITT */ 1039 its_cmd_mapd(dev, its_dev, 1); 1040 1041 return (its_dev); 1042 } 1043 1044 static void 1045 its_device_release(device_t dev, struct its_dev *its_dev) 1046 { 1047 struct gicv3_its_softc *sc; 1048 1049 KASSERT(its_dev->lpis.lpi_busy == 0, 1050 ("its_device_release: Trying to release an inuse ITS device")); 1051 1052 /* Unmap device in ITS */ 1053 its_cmd_mapd(dev, its_dev, 0); 1054 1055 sc = device_get_softc(dev); 1056 1057 /* Remove the device from the list of devices */ 1058 mtx_lock_spin(&sc->sc_its_dev_lock); 1059 TAILQ_REMOVE(&sc->sc_its_dev_list, its_dev, entry); 1060 mtx_unlock_spin(&sc->sc_its_dev_lock); 1061 1062 /* Free ITT */ 1063 KASSERT(its_dev->itt != 0, ("Invalid ITT in valid ITS device")); 1064 contigfree((void *)its_dev->itt, its_dev->itt_size, M_GICV3_ITS); 1065 1066 /* Free the IRQ allocation */ 1067 vmem_free(sc->sc_irq_alloc, its_dev->lpis.lpi_base, 1068 its_dev->lpis.lpi_num); 1069 1070 free(its_dev, M_GICV3_ITS); 1071 } 1072 1073 static int 1074 gicv3_its_alloc_msi(device_t dev, device_t child, int count, int maxcount, 1075 device_t *pic, struct intr_irqsrc **srcs) 1076 { 1077 struct gicv3_its_softc *sc; 1078 struct gicv3_its_irqsrc *girq; 1079 struct its_dev *its_dev; 1080 u_int irq; 1081 int i; 1082 1083 its_dev = its_device_get(dev, child, count); 1084 if (its_dev == NULL) 1085 return (ENXIO); 1086 1087 KASSERT(its_dev->lpis.lpi_free >= count, 1088 ("gicv3_its_alloc_msi: No free LPIs")); 1089 sc = device_get_softc(dev); 1090 irq = its_dev->lpis.lpi_base + its_dev->lpis.lpi_num - 1091 its_dev->lpis.lpi_free; 1092 for (i = 0; i < count; i++, irq++) { 1093 its_dev->lpis.lpi_free--; 1094 girq = &sc->sc_irqs[irq]; 1095 girq->gi_its_dev = its_dev; 1096 srcs[i] = (struct intr_irqsrc *)girq; 1097 } 1098 its_dev->lpis.lpi_busy += count; 1099 *pic = dev; 1100 1101 return (0); 1102 } 1103 1104 static int 1105 gicv3_its_release_msi(device_t dev, device_t child, int count, 1106 struct intr_irqsrc **isrc) 1107 { 1108 struct gicv3_its_irqsrc *girq; 1109 struct its_dev *its_dev; 1110 int i; 1111 1112 its_dev = its_device_find(dev, child); 1113 1114 KASSERT(its_dev != NULL, 1115 ("gicv3_its_release_msi: Releasing a MSI interrupt with " 1116 "no ITS device")); 1117 KASSERT(its_dev->lpis.lpi_busy >= count, 1118 ("gicv3_its_release_msi: Releasing more interrupts than " 1119 "were allocated: releasing %d, allocated %d", count, 1120 its_dev->lpis.lpi_busy)); 1121 for (i = 0; i < count; i++) { 1122 girq = (struct gicv3_its_irqsrc *)isrc[i]; 1123 girq->gi_its_dev = NULL; 1124 } 1125 its_dev->lpis.lpi_busy -= count; 1126 1127 if (its_dev->lpis.lpi_busy == 0) 1128 its_device_release(dev, its_dev); 1129 1130 return (0); 1131 } 1132 1133 static int 1134 gicv3_its_alloc_msix(device_t dev, device_t child, device_t *pic, 1135 struct intr_irqsrc **isrcp) 1136 { 1137 struct gicv3_its_softc *sc; 1138 struct gicv3_its_irqsrc *girq; 1139 struct its_dev *its_dev; 1140 u_int nvecs, irq; 1141 1142 nvecs = pci_msix_count(child); 1143 its_dev = its_device_get(dev, child, nvecs); 1144 if (its_dev == NULL) 1145 return (ENXIO); 1146 1147 KASSERT(its_dev->lpis.lpi_free > 0, 1148 ("gicv3_its_alloc_msix: No free LPIs")); 1149 sc = device_get_softc(dev); 1150 irq = its_dev->lpis.lpi_base + its_dev->lpis.lpi_num - 1151 its_dev->lpis.lpi_free; 1152 its_dev->lpis.lpi_free--; 1153 its_dev->lpis.lpi_busy++; 1154 girq = &sc->sc_irqs[irq]; 1155 girq->gi_its_dev = its_dev; 1156 1157 *pic = dev; 1158 *isrcp = (struct intr_irqsrc *)girq; 1159 1160 return (0); 1161 } 1162 1163 static int 1164 gicv3_its_release_msix(device_t dev, device_t child, struct intr_irqsrc *isrc) 1165 { 1166 struct gicv3_its_irqsrc *girq; 1167 struct its_dev *its_dev; 1168 1169 its_dev = its_device_find(dev, child); 1170 1171 KASSERT(its_dev != NULL, 1172 ("gicv3_its_release_msix: Releasing a MSI-X interrupt with " 1173 "no ITS device")); 1174 KASSERT(its_dev->lpis.lpi_busy > 0, 1175 ("gicv3_its_release_msix: Releasing more interrupts than " 1176 "were allocated: allocated %d", its_dev->lpis.lpi_busy)); 1177 girq = (struct gicv3_its_irqsrc *)isrc; 1178 girq->gi_its_dev = NULL; 1179 its_dev->lpis.lpi_busy--; 1180 1181 if (its_dev->lpis.lpi_busy == 0) 1182 its_device_release(dev, its_dev); 1183 1184 return (0); 1185 } 1186 1187 static int 1188 gicv3_its_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc, 1189 uint64_t *addr, uint32_t *data) 1190 { 1191 struct gicv3_its_softc *sc; 1192 struct gicv3_its_irqsrc *girq; 1193 1194 sc = device_get_softc(dev); 1195 girq = (struct gicv3_its_irqsrc *)isrc; 1196 1197 /* Map the message to the given IRQ */ 1198 its_cmd_mapti(dev, girq); 1199 1200 *addr = vtophys(rman_get_virtual(sc->sc_its_res)) + GITS_TRANSLATER; 1201 *data = girq->gi_irq - girq->gi_its_dev->lpis.lpi_base; 1202 1203 return (0); 1204 } 1205 1206 /* 1207 * Commands handling. 1208 */ 1209 1210 static __inline void 1211 cmd_format_command(struct its_cmd *cmd, uint8_t cmd_type) 1212 { 1213 /* Command field: DW0 [7:0] */ 1214 cmd->cmd_dword[0] &= htole64(~CMD_COMMAND_MASK); 1215 cmd->cmd_dword[0] |= htole64(cmd_type); 1216 } 1217 1218 static __inline void 1219 cmd_format_devid(struct its_cmd *cmd, uint32_t devid) 1220 { 1221 /* Device ID field: DW0 [63:32] */ 1222 cmd->cmd_dword[0] &= htole64(~CMD_DEVID_MASK); 1223 cmd->cmd_dword[0] |= htole64((uint64_t)devid << CMD_DEVID_SHIFT); 1224 } 1225 1226 static __inline void 1227 cmd_format_size(struct its_cmd *cmd, uint16_t size) 1228 { 1229 /* Size field: DW1 [4:0] */ 1230 cmd->cmd_dword[1] &= htole64(~CMD_SIZE_MASK); 1231 cmd->cmd_dword[1] |= htole64((size & CMD_SIZE_MASK)); 1232 } 1233 1234 static __inline void 1235 cmd_format_id(struct its_cmd *cmd, uint32_t id) 1236 { 1237 /* ID field: DW1 [31:0] */ 1238 cmd->cmd_dword[1] &= htole64(~CMD_ID_MASK); 1239 cmd->cmd_dword[1] |= htole64(id); 1240 } 1241 1242 static __inline void 1243 cmd_format_pid(struct its_cmd *cmd, uint32_t pid) 1244 { 1245 /* Physical ID field: DW1 [63:32] */ 1246 cmd->cmd_dword[1] &= htole64(~CMD_PID_MASK); 1247 cmd->cmd_dword[1] |= htole64((uint64_t)pid << CMD_PID_SHIFT); 1248 } 1249 1250 static __inline void 1251 cmd_format_col(struct its_cmd *cmd, uint16_t col_id) 1252 { 1253 /* Collection field: DW2 [16:0] */ 1254 cmd->cmd_dword[2] &= htole64(~CMD_COL_MASK); 1255 cmd->cmd_dword[2] |= htole64(col_id); 1256 } 1257 1258 static __inline void 1259 cmd_format_target(struct its_cmd *cmd, uint64_t target) 1260 { 1261 /* Target Address field: DW2 [47:16] */ 1262 cmd->cmd_dword[2] &= htole64(~CMD_TARGET_MASK); 1263 cmd->cmd_dword[2] |= htole64(target & CMD_TARGET_MASK); 1264 } 1265 1266 static __inline void 1267 cmd_format_itt(struct its_cmd *cmd, uint64_t itt) 1268 { 1269 /* ITT Address field: DW2 [47:8] */ 1270 cmd->cmd_dword[2] &= htole64(~CMD_ITT_MASK); 1271 cmd->cmd_dword[2] |= htole64(itt & CMD_ITT_MASK); 1272 } 1273 1274 static __inline void 1275 cmd_format_valid(struct its_cmd *cmd, uint8_t valid) 1276 { 1277 /* Valid field: DW2 [63] */ 1278 cmd->cmd_dword[2] &= htole64(~CMD_VALID_MASK); 1279 cmd->cmd_dword[2] |= htole64((uint64_t)valid << CMD_VALID_SHIFT); 1280 } 1281 1282 static inline bool 1283 its_cmd_queue_full(struct gicv3_its_softc *sc) 1284 { 1285 size_t read_idx, next_write_idx; 1286 1287 /* Get the index of the next command */ 1288 next_write_idx = (sc->sc_its_cmd_next_idx + 1) % 1289 (ITS_CMDQ_SIZE / sizeof(struct its_cmd)); 1290 /* And the index of the current command being read */ 1291 read_idx = gic_its_read_4(sc, GITS_CREADR) / sizeof(struct its_cmd); 1292 1293 /* 1294 * The queue is full when the write offset points 1295 * at the command before the current read offset. 1296 */ 1297 return (next_write_idx == read_idx); 1298 } 1299 1300 static inline void 1301 its_cmd_sync(struct gicv3_its_softc *sc, struct its_cmd *cmd) 1302 { 1303 1304 if ((sc->sc_its_flags & ITS_FLAGS_CMDQ_FLUSH) != 0) { 1305 /* Clean D-cache under command. */ 1306 cpu_dcache_wb_range((vm_offset_t)cmd, sizeof(*cmd)); 1307 } else { 1308 /* DSB inner shareable, store */ 1309 dsb(ishst); 1310 } 1311 1312 } 1313 1314 static inline uint64_t 1315 its_cmd_cwriter_offset(struct gicv3_its_softc *sc, struct its_cmd *cmd) 1316 { 1317 uint64_t off; 1318 1319 off = (cmd - sc->sc_its_cmd_base) * sizeof(*cmd); 1320 1321 return (off); 1322 } 1323 1324 static void 1325 its_cmd_wait_completion(device_t dev, struct its_cmd *cmd_first, 1326 struct its_cmd *cmd_last) 1327 { 1328 struct gicv3_its_softc *sc; 1329 uint64_t first, last, read; 1330 size_t us_left; 1331 1332 sc = device_get_softc(dev); 1333 1334 /* 1335 * XXX ARM64TODO: This is obviously a significant delay. 1336 * The reason for that is that currently the time frames for 1337 * the command to complete are not known. 1338 */ 1339 us_left = 1000000; 1340 1341 first = its_cmd_cwriter_offset(sc, cmd_first); 1342 last = its_cmd_cwriter_offset(sc, cmd_last); 1343 1344 for (;;) { 1345 read = gic_its_read_8(sc, GITS_CREADR); 1346 if (first < last) { 1347 if (read < first || read >= last) 1348 break; 1349 } else if (read < first && read >= last) 1350 break; 1351 1352 if (us_left-- == 0) { 1353 /* This means timeout */ 1354 device_printf(dev, 1355 "Timeout while waiting for CMD completion.\n"); 1356 return; 1357 } 1358 DELAY(1); 1359 } 1360 } 1361 1362 1363 static struct its_cmd * 1364 its_cmd_alloc_locked(device_t dev) 1365 { 1366 struct gicv3_its_softc *sc; 1367 struct its_cmd *cmd; 1368 size_t us_left; 1369 1370 sc = device_get_softc(dev); 1371 1372 /* 1373 * XXX ARM64TODO: This is obviously a significant delay. 1374 * The reason for that is that currently the time frames for 1375 * the command to complete (and therefore free the descriptor) 1376 * are not known. 1377 */ 1378 us_left = 1000000; 1379 1380 mtx_assert(&sc->sc_its_cmd_lock, MA_OWNED); 1381 while (its_cmd_queue_full(sc)) { 1382 if (us_left-- == 0) { 1383 /* Timeout while waiting for free command */ 1384 device_printf(dev, 1385 "Timeout while waiting for free command\n"); 1386 return (NULL); 1387 } 1388 DELAY(1); 1389 } 1390 1391 cmd = &sc->sc_its_cmd_base[sc->sc_its_cmd_next_idx]; 1392 sc->sc_its_cmd_next_idx++; 1393 sc->sc_its_cmd_next_idx %= ITS_CMDQ_SIZE / sizeof(struct its_cmd); 1394 1395 return (cmd); 1396 } 1397 1398 static uint64_t 1399 its_cmd_prepare(struct its_cmd *cmd, struct its_cmd_desc *desc) 1400 { 1401 uint64_t target; 1402 uint8_t cmd_type; 1403 u_int size; 1404 1405 cmd_type = desc->cmd_type; 1406 target = ITS_TARGET_NONE; 1407 1408 switch (cmd_type) { 1409 case ITS_CMD_MOVI: /* Move interrupt ID to another collection */ 1410 target = desc->cmd_desc_movi.col->col_target; 1411 cmd_format_command(cmd, ITS_CMD_MOVI); 1412 cmd_format_id(cmd, desc->cmd_desc_movi.id); 1413 cmd_format_col(cmd, desc->cmd_desc_movi.col->col_id); 1414 cmd_format_devid(cmd, desc->cmd_desc_movi.its_dev->devid); 1415 break; 1416 case ITS_CMD_SYNC: /* Wait for previous commands completion */ 1417 target = desc->cmd_desc_sync.col->col_target; 1418 cmd_format_command(cmd, ITS_CMD_SYNC); 1419 cmd_format_target(cmd, target); 1420 break; 1421 case ITS_CMD_MAPD: /* Assign ITT to device */ 1422 cmd_format_command(cmd, ITS_CMD_MAPD); 1423 cmd_format_itt(cmd, vtophys(desc->cmd_desc_mapd.its_dev->itt)); 1424 /* 1425 * Size describes number of bits to encode interrupt IDs 1426 * supported by the device minus one. 1427 * When V (valid) bit is zero, this field should be written 1428 * as zero. 1429 */ 1430 if (desc->cmd_desc_mapd.valid != 0) { 1431 size = fls(desc->cmd_desc_mapd.its_dev->lpis.lpi_num); 1432 size = MAX(1, size) - 1; 1433 } else 1434 size = 0; 1435 1436 cmd_format_size(cmd, size); 1437 cmd_format_devid(cmd, desc->cmd_desc_mapd.its_dev->devid); 1438 cmd_format_valid(cmd, desc->cmd_desc_mapd.valid); 1439 break; 1440 case ITS_CMD_MAPC: /* Map collection to Re-Distributor */ 1441 target = desc->cmd_desc_mapc.col->col_target; 1442 cmd_format_command(cmd, ITS_CMD_MAPC); 1443 cmd_format_col(cmd, desc->cmd_desc_mapc.col->col_id); 1444 cmd_format_valid(cmd, desc->cmd_desc_mapc.valid); 1445 cmd_format_target(cmd, target); 1446 break; 1447 case ITS_CMD_MAPTI: 1448 target = desc->cmd_desc_mapvi.col->col_target; 1449 cmd_format_command(cmd, ITS_CMD_MAPTI); 1450 cmd_format_devid(cmd, desc->cmd_desc_mapvi.its_dev->devid); 1451 cmd_format_id(cmd, desc->cmd_desc_mapvi.id); 1452 cmd_format_pid(cmd, desc->cmd_desc_mapvi.pid); 1453 cmd_format_col(cmd, desc->cmd_desc_mapvi.col->col_id); 1454 break; 1455 case ITS_CMD_MAPI: 1456 target = desc->cmd_desc_mapi.col->col_target; 1457 cmd_format_command(cmd, ITS_CMD_MAPI); 1458 cmd_format_devid(cmd, desc->cmd_desc_mapi.its_dev->devid); 1459 cmd_format_id(cmd, desc->cmd_desc_mapi.pid); 1460 cmd_format_col(cmd, desc->cmd_desc_mapi.col->col_id); 1461 break; 1462 case ITS_CMD_INV: 1463 target = desc->cmd_desc_inv.col->col_target; 1464 cmd_format_command(cmd, ITS_CMD_INV); 1465 cmd_format_devid(cmd, desc->cmd_desc_inv.its_dev->devid); 1466 cmd_format_id(cmd, desc->cmd_desc_inv.pid); 1467 break; 1468 case ITS_CMD_INVALL: 1469 cmd_format_command(cmd, ITS_CMD_INVALL); 1470 cmd_format_col(cmd, desc->cmd_desc_invall.col->col_id); 1471 break; 1472 default: 1473 panic("its_cmd_prepare: Invalid command: %x", cmd_type); 1474 } 1475 1476 return (target); 1477 } 1478 1479 static int 1480 its_cmd_send(device_t dev, struct its_cmd_desc *desc) 1481 { 1482 struct gicv3_its_softc *sc; 1483 struct its_cmd *cmd, *cmd_sync, *cmd_write; 1484 struct its_col col_sync; 1485 struct its_cmd_desc desc_sync; 1486 uint64_t target, cwriter; 1487 1488 sc = device_get_softc(dev); 1489 mtx_lock_spin(&sc->sc_its_cmd_lock); 1490 cmd = its_cmd_alloc_locked(dev); 1491 if (cmd == NULL) { 1492 device_printf(dev, "could not allocate ITS command\n"); 1493 mtx_unlock_spin(&sc->sc_its_cmd_lock); 1494 return (EBUSY); 1495 } 1496 1497 target = its_cmd_prepare(cmd, desc); 1498 its_cmd_sync(sc, cmd); 1499 1500 if (target != ITS_TARGET_NONE) { 1501 cmd_sync = its_cmd_alloc_locked(dev); 1502 if (cmd_sync != NULL) { 1503 desc_sync.cmd_type = ITS_CMD_SYNC; 1504 col_sync.col_target = target; 1505 desc_sync.cmd_desc_sync.col = &col_sync; 1506 its_cmd_prepare(cmd_sync, &desc_sync); 1507 its_cmd_sync(sc, cmd_sync); 1508 } 1509 } 1510 1511 /* Update GITS_CWRITER */ 1512 cwriter = sc->sc_its_cmd_next_idx * sizeof(struct its_cmd); 1513 gic_its_write_8(sc, GITS_CWRITER, cwriter); 1514 cmd_write = &sc->sc_its_cmd_base[sc->sc_its_cmd_next_idx]; 1515 mtx_unlock_spin(&sc->sc_its_cmd_lock); 1516 1517 its_cmd_wait_completion(dev, cmd, cmd_write); 1518 1519 return (0); 1520 } 1521 1522 /* Handlers to send commands */ 1523 static void 1524 its_cmd_movi(device_t dev, struct gicv3_its_irqsrc *girq) 1525 { 1526 struct gicv3_its_softc *sc; 1527 struct its_cmd_desc desc; 1528 struct its_col *col; 1529 1530 sc = device_get_softc(dev); 1531 col = sc->sc_its_cols[CPU_FFS(&girq->gi_isrc.isrc_cpu) - 1]; 1532 1533 desc.cmd_type = ITS_CMD_MOVI; 1534 desc.cmd_desc_movi.its_dev = girq->gi_its_dev; 1535 desc.cmd_desc_movi.col = col; 1536 desc.cmd_desc_movi.id = girq->gi_irq - girq->gi_its_dev->lpis.lpi_base; 1537 1538 its_cmd_send(dev, &desc); 1539 } 1540 1541 static void 1542 its_cmd_mapc(device_t dev, struct its_col *col, uint8_t valid) 1543 { 1544 struct its_cmd_desc desc; 1545 1546 desc.cmd_type = ITS_CMD_MAPC; 1547 desc.cmd_desc_mapc.col = col; 1548 /* 1549 * Valid bit set - map the collection. 1550 * Valid bit cleared - unmap the collection. 1551 */ 1552 desc.cmd_desc_mapc.valid = valid; 1553 1554 its_cmd_send(dev, &desc); 1555 } 1556 1557 static void 1558 its_cmd_mapti(device_t dev, struct gicv3_its_irqsrc *girq) 1559 { 1560 struct gicv3_its_softc *sc; 1561 struct its_cmd_desc desc; 1562 struct its_col *col; 1563 u_int col_id; 1564 1565 sc = device_get_softc(dev); 1566 1567 col_id = CPU_FFS(&girq->gi_isrc.isrc_cpu) - 1; 1568 col = sc->sc_its_cols[col_id]; 1569 1570 desc.cmd_type = ITS_CMD_MAPTI; 1571 desc.cmd_desc_mapvi.its_dev = girq->gi_its_dev; 1572 desc.cmd_desc_mapvi.col = col; 1573 /* The EventID sent to the device */ 1574 desc.cmd_desc_mapvi.id = girq->gi_irq - girq->gi_its_dev->lpis.lpi_base; 1575 /* The physical interrupt presented to softeware */ 1576 desc.cmd_desc_mapvi.pid = girq->gi_irq + sc->sc_irq_base; 1577 1578 its_cmd_send(dev, &desc); 1579 } 1580 1581 static void 1582 its_cmd_mapd(device_t dev, struct its_dev *its_dev, uint8_t valid) 1583 { 1584 struct its_cmd_desc desc; 1585 1586 desc.cmd_type = ITS_CMD_MAPD; 1587 desc.cmd_desc_mapd.its_dev = its_dev; 1588 desc.cmd_desc_mapd.valid = valid; 1589 1590 its_cmd_send(dev, &desc); 1591 } 1592 1593 static void 1594 its_cmd_inv(device_t dev, struct its_dev *its_dev, 1595 struct gicv3_its_irqsrc *girq) 1596 { 1597 struct gicv3_its_softc *sc; 1598 struct its_cmd_desc desc; 1599 struct its_col *col; 1600 1601 sc = device_get_softc(dev); 1602 col = sc->sc_its_cols[CPU_FFS(&girq->gi_isrc.isrc_cpu) - 1]; 1603 1604 desc.cmd_type = ITS_CMD_INV; 1605 /* The EventID sent to the device */ 1606 desc.cmd_desc_inv.pid = girq->gi_irq - its_dev->lpis.lpi_base; 1607 desc.cmd_desc_inv.its_dev = its_dev; 1608 desc.cmd_desc_inv.col = col; 1609 1610 its_cmd_send(dev, &desc); 1611 } 1612 1613 static void 1614 its_cmd_invall(device_t dev, struct its_col *col) 1615 { 1616 struct its_cmd_desc desc; 1617 1618 desc.cmd_type = ITS_CMD_INVALL; 1619 desc.cmd_desc_invall.col = col; 1620 1621 its_cmd_send(dev, &desc); 1622 } 1623 1624 #ifdef FDT 1625 static device_probe_t gicv3_its_fdt_probe; 1626 static device_attach_t gicv3_its_fdt_attach; 1627 1628 static device_method_t gicv3_its_fdt_methods[] = { 1629 /* Device interface */ 1630 DEVMETHOD(device_probe, gicv3_its_fdt_probe), 1631 DEVMETHOD(device_attach, gicv3_its_fdt_attach), 1632 1633 /* End */ 1634 DEVMETHOD_END 1635 }; 1636 1637 #define its_baseclasses its_fdt_baseclasses 1638 DEFINE_CLASS_1(its, gicv3_its_fdt_driver, gicv3_its_fdt_methods, 1639 sizeof(struct gicv3_its_softc), gicv3_its_driver); 1640 #undef its_baseclasses 1641 static devclass_t gicv3_its_fdt_devclass; 1642 1643 EARLY_DRIVER_MODULE(its_fdt, gic, gicv3_its_fdt_driver, 1644 gicv3_its_fdt_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 1645 1646 static int 1647 gicv3_its_fdt_probe(device_t dev) 1648 { 1649 1650 if (!ofw_bus_status_okay(dev)) 1651 return (ENXIO); 1652 1653 if (!ofw_bus_is_compatible(dev, "arm,gic-v3-its")) 1654 return (ENXIO); 1655 1656 device_set_desc(dev, "ARM GIC Interrupt Translation Service"); 1657 return (BUS_PROBE_DEFAULT); 1658 } 1659 1660 static int 1661 gicv3_its_fdt_attach(device_t dev) 1662 { 1663 struct gicv3_its_softc *sc; 1664 phandle_t xref; 1665 int err; 1666 1667 sc = device_get_softc(dev); 1668 err = gicv3_its_attach(dev); 1669 if (err != 0) 1670 return (err); 1671 1672 /* Register this device as a interrupt controller */ 1673 xref = OF_xref_from_node(ofw_bus_get_node(dev)); 1674 sc->sc_pic = intr_pic_register(dev, xref); 1675 intr_pic_add_handler(device_get_parent(dev), sc->sc_pic, 1676 gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length); 1677 1678 /* Register this device to handle MSI interrupts */ 1679 intr_msi_register(dev, xref); 1680 1681 return (0); 1682 } 1683 #endif 1684 1685 #ifdef DEV_ACPI 1686 static device_probe_t gicv3_its_acpi_probe; 1687 static device_attach_t gicv3_its_acpi_attach; 1688 1689 static device_method_t gicv3_its_acpi_methods[] = { 1690 /* Device interface */ 1691 DEVMETHOD(device_probe, gicv3_its_acpi_probe), 1692 DEVMETHOD(device_attach, gicv3_its_acpi_attach), 1693 1694 /* End */ 1695 DEVMETHOD_END 1696 }; 1697 1698 #define its_baseclasses its_acpi_baseclasses 1699 DEFINE_CLASS_1(its, gicv3_its_acpi_driver, gicv3_its_acpi_methods, 1700 sizeof(struct gicv3_its_softc), gicv3_its_driver); 1701 #undef its_baseclasses 1702 static devclass_t gicv3_its_acpi_devclass; 1703 1704 EARLY_DRIVER_MODULE(its_acpi, gic, gicv3_its_acpi_driver, 1705 gicv3_its_acpi_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 1706 1707 static int 1708 gicv3_its_acpi_probe(device_t dev) 1709 { 1710 1711 if (gic_get_bus(dev) != GIC_BUS_ACPI) 1712 return (EINVAL); 1713 1714 if (gic_get_hw_rev(dev) < 3) 1715 return (EINVAL); 1716 1717 device_set_desc(dev, "ARM GIC Interrupt Translation Service"); 1718 return (BUS_PROBE_DEFAULT); 1719 } 1720 1721 static int 1722 gicv3_its_acpi_attach(device_t dev) 1723 { 1724 struct gicv3_its_softc *sc; 1725 struct gic_v3_devinfo *di; 1726 int err; 1727 1728 sc = device_get_softc(dev); 1729 err = gicv3_its_attach(dev); 1730 if (err != 0) 1731 return (err); 1732 1733 di = device_get_ivars(dev); 1734 sc->sc_pic = intr_pic_register(dev, di->msi_xref); 1735 intr_pic_add_handler(device_get_parent(dev), sc->sc_pic, 1736 gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length); 1737 1738 /* Register this device to handle MSI interrupts */ 1739 intr_msi_register(dev, di->msi_xref); 1740 1741 return (0); 1742 } 1743 #endif 1744