1 /*- 2 * Copyright (c) 2014 Andrew Turner 3 * Copyright (c) 2014 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by Semihalf 7 * under sponsorship of the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/pcpu.h> 38 #include <sys/sbuf.h> 39 #include <sys/smp.h> 40 #include <sys/sysctl.h> 41 #include <sys/systm.h> 42 43 #include <machine/atomic.h> 44 #include <machine/cpu.h> 45 #include <machine/cpufunc.h> 46 #include <machine/elf.h> 47 #include <machine/md_var.h> 48 #include <machine/undefined.h> 49 50 static void print_cpu_midr(struct sbuf *sb, u_int cpu); 51 static void print_cpu_features(u_int cpu); 52 static void print_cpu_caches(struct sbuf *sb, u_int); 53 #ifdef COMPAT_FREEBSD32 54 static u_long parse_cpu_features_hwcap32(void); 55 #endif 56 57 char machine[] = "arm64"; 58 59 #ifdef SCTL_MASK32 60 extern int adaptive_machine_arch; 61 #endif 62 63 static SYSCTL_NODE(_machdep, OID_AUTO, cache, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 64 "Cache management tuning"); 65 66 static int allow_dic = 1; 67 SYSCTL_INT(_machdep_cache, OID_AUTO, allow_dic, CTLFLAG_RDTUN, &allow_dic, 0, 68 "Allow optimizations based on the DIC cache bit"); 69 70 static int allow_idc = 1; 71 SYSCTL_INT(_machdep_cache, OID_AUTO, allow_idc, CTLFLAG_RDTUN, &allow_idc, 0, 72 "Allow optimizations based on the IDC cache bit"); 73 74 static void check_cpu_regs(u_int cpu); 75 76 /* 77 * The default implementation of I-cache sync assumes we have an 78 * aliasing cache until we know otherwise. 79 */ 80 void (*arm64_icache_sync_range)(vm_offset_t, vm_size_t) = 81 &arm64_aliasing_icache_sync_range; 82 83 static int 84 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 85 { 86 #ifdef SCTL_MASK32 87 static const char machine32[] = "arm"; 88 #endif 89 int error; 90 91 #ifdef SCTL_MASK32 92 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 93 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 94 else 95 #endif 96 error = SYSCTL_OUT(req, machine, sizeof(machine)); 97 return (error); 98 } 99 100 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 101 CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 102 103 static char cpu_model[64]; 104 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 105 cpu_model, sizeof(cpu_model), "Machine model"); 106 107 #define MAX_CACHES 8 /* Maximum number of caches supported 108 architecturally. */ 109 /* 110 * Per-CPU affinity as provided in MPIDR_EL1 111 * Indexed by CPU number in logical order selected by the system. 112 * Relevant fields can be extracted using CPU_AFFn macros, 113 * Aff3.Aff2.Aff1.Aff0 construct a unique CPU address in the system. 114 * 115 * Fields used by us: 116 * Aff1 - Cluster number 117 * Aff0 - CPU number in Aff1 cluster 118 */ 119 uint64_t __cpu_affinity[MAXCPU]; 120 static u_int cpu_aff_levels; 121 122 struct cpu_desc { 123 uint64_t mpidr; 124 uint64_t id_aa64afr0; 125 uint64_t id_aa64afr1; 126 uint64_t id_aa64dfr0; 127 uint64_t id_aa64dfr1; 128 uint64_t id_aa64isar0; 129 uint64_t id_aa64isar1; 130 uint64_t id_aa64mmfr0; 131 uint64_t id_aa64mmfr1; 132 uint64_t id_aa64mmfr2; 133 uint64_t id_aa64pfr0; 134 uint64_t id_aa64pfr1; 135 uint64_t ctr; 136 #ifdef COMPAT_FREEBSD32 137 uint64_t id_isar5; 138 uint64_t mvfr0; 139 uint64_t mvfr1; 140 #endif 141 uint64_t clidr; 142 uint32_t ccsidr[MAX_CACHES][2]; /* 2 possible types. */ 143 }; 144 145 static struct cpu_desc cpu_desc[MAXCPU]; 146 static struct cpu_desc kern_cpu_desc; 147 static struct cpu_desc user_cpu_desc; 148 static u_int cpu_print_regs; 149 #define PRINT_ID_AA64_AFR0 0x00000001 150 #define PRINT_ID_AA64_AFR1 0x00000002 151 #define PRINT_ID_AA64_DFR0 0x00000010 152 #define PRINT_ID_AA64_DFR1 0x00000020 153 #define PRINT_ID_AA64_ISAR0 0x00000100 154 #define PRINT_ID_AA64_ISAR1 0x00000200 155 #define PRINT_ID_AA64_MMFR0 0x00001000 156 #define PRINT_ID_AA64_MMFR1 0x00002000 157 #define PRINT_ID_AA64_MMFR2 0x00004000 158 #define PRINT_ID_AA64_PFR0 0x00010000 159 #define PRINT_ID_AA64_PFR1 0x00020000 160 #ifdef COMPAT_FREEBSD32 161 #define PRINT_ID_ISAR5 0x01000000 162 #define PRINT_MVFR0 0x02000000 163 #define PRINT_MVFR1 0x04000000 164 #endif 165 #define PRINT_CTR_EL0 0x10000000 166 167 struct cpu_parts { 168 u_int part_id; 169 const char *part_name; 170 }; 171 #define CPU_PART_NONE { 0, NULL } 172 173 struct cpu_implementers { 174 u_int impl_id; 175 const char *impl_name; 176 /* 177 * Part number is implementation defined 178 * so each vendor will have its own set of values and names. 179 */ 180 const struct cpu_parts *cpu_parts; 181 }; 182 #define CPU_IMPLEMENTER_NONE { 0, NULL, NULL } 183 184 /* 185 * Per-implementer table of (PartNum, CPU Name) pairs. 186 */ 187 /* ARM Ltd. */ 188 static const struct cpu_parts cpu_parts_arm[] = { 189 { CPU_PART_AEM_V8, "AEMv8" }, 190 { CPU_PART_FOUNDATION, "Foundation-Model" }, 191 { CPU_PART_CORTEX_A34, "Cortex-A34" }, 192 { CPU_PART_CORTEX_A35, "Cortex-A35" }, 193 { CPU_PART_CORTEX_A53, "Cortex-A53" }, 194 { CPU_PART_CORTEX_A55, "Cortex-A55" }, 195 { CPU_PART_CORTEX_A57, "Cortex-A57" }, 196 { CPU_PART_CORTEX_A65, "Cortex-A65" }, 197 { CPU_PART_CORTEX_A72, "Cortex-A72" }, 198 { CPU_PART_CORTEX_A73, "Cortex-A73" }, 199 { CPU_PART_CORTEX_A75, "Cortex-A75" }, 200 { CPU_PART_CORTEX_A76, "Cortex-A76" }, 201 { CPU_PART_CORTEX_A76AE, "Cortex-A76AE" }, 202 { CPU_PART_CORTEX_A77, "Cortex-A77" }, 203 { CPU_PART_CORTEX_A78, "Cortex-A78" }, 204 { CPU_PART_CORTEX_A78C, "Cortex-A78C" }, 205 { CPU_PART_CORTEX_A510, "Cortex-A510" }, 206 { CPU_PART_CORTEX_A710, "Cortex-A710" }, 207 { CPU_PART_CORTEX_X1, "Cortex-X1" }, 208 { CPU_PART_CORTEX_X1C, "Cortex-X1C" }, 209 { CPU_PART_CORTEX_X2, "Cortex-X2" }, 210 { CPU_PART_NEOVERSE_E1, "Neoverse-E1" }, 211 { CPU_PART_NEOVERSE_N1, "Neoverse-N1" }, 212 { CPU_PART_NEOVERSE_N2, "Neoverse-N2" }, 213 { CPU_PART_NEOVERSE_V1, "Neoverse-V1" }, 214 CPU_PART_NONE, 215 }; 216 217 /* Cavium */ 218 static const struct cpu_parts cpu_parts_cavium[] = { 219 { CPU_PART_THUNDERX, "ThunderX" }, 220 { CPU_PART_THUNDERX2, "ThunderX2" }, 221 CPU_PART_NONE, 222 }; 223 224 /* APM / Ampere */ 225 static const struct cpu_parts cpu_parts_apm[] = { 226 { CPU_PART_EMAG8180, "eMAG 8180" }, 227 CPU_PART_NONE, 228 }; 229 230 /* Unknown */ 231 static const struct cpu_parts cpu_parts_none[] = { 232 CPU_PART_NONE, 233 }; 234 235 /* 236 * Implementers table. 237 */ 238 const struct cpu_implementers cpu_implementers[] = { 239 { CPU_IMPL_AMPERE, "Ampere", cpu_parts_none }, 240 { CPU_IMPL_APPLE, "Apple", cpu_parts_none }, 241 { CPU_IMPL_APM, "APM", cpu_parts_apm }, 242 { CPU_IMPL_ARM, "ARM", cpu_parts_arm }, 243 { CPU_IMPL_BROADCOM, "Broadcom", cpu_parts_none }, 244 { CPU_IMPL_CAVIUM, "Cavium", cpu_parts_cavium }, 245 { CPU_IMPL_DEC, "DEC", cpu_parts_none }, 246 { CPU_IMPL_FREESCALE, "Freescale", cpu_parts_none }, 247 { CPU_IMPL_FUJITSU, "Fujitsu", cpu_parts_none }, 248 { CPU_IMPL_INFINEON, "IFX", cpu_parts_none }, 249 { CPU_IMPL_INTEL, "Intel", cpu_parts_none }, 250 { CPU_IMPL_MARVELL, "Marvell", cpu_parts_none }, 251 { CPU_IMPL_NVIDIA, "NVIDIA", cpu_parts_none }, 252 { CPU_IMPL_QUALCOMM, "Qualcomm", cpu_parts_none }, 253 CPU_IMPLEMENTER_NONE, 254 }; 255 256 #define MRS_TYPE_MASK 0xf 257 #define MRS_INVALID 0 258 #define MRS_EXACT 1 259 #define MRS_EXACT_VAL(x) (MRS_EXACT | ((x) << 4)) 260 #define MRS_EXACT_FIELD(x) ((x) >> 4) 261 #define MRS_LOWER 2 262 263 struct mrs_field_value { 264 uint64_t value; 265 const char *desc; 266 }; 267 268 #define MRS_FIELD_VALUE(_value, _desc) \ 269 { \ 270 .value = (_value), \ 271 .desc = (_desc), \ 272 } 273 274 #define MRS_FIELD_VALUE_NONE_IMPL(_reg, _field, _none, _impl) \ 275 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _none, ""), \ 276 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _impl, #_field) 277 278 #define MRS_FIELD_VALUE_COUNT(_reg, _field, _desc) \ 279 MRS_FIELD_VALUE(0ul << _reg ## _ ## _field ## _SHIFT, "1 " _desc), \ 280 MRS_FIELD_VALUE(1ul << _reg ## _ ## _field ## _SHIFT, "2 " _desc "s"), \ 281 MRS_FIELD_VALUE(2ul << _reg ## _ ## _field ## _SHIFT, "3 " _desc "s"), \ 282 MRS_FIELD_VALUE(3ul << _reg ## _ ## _field ## _SHIFT, "4 " _desc "s"), \ 283 MRS_FIELD_VALUE(4ul << _reg ## _ ## _field ## _SHIFT, "5 " _desc "s"), \ 284 MRS_FIELD_VALUE(5ul << _reg ## _ ## _field ## _SHIFT, "6 " _desc "s"), \ 285 MRS_FIELD_VALUE(6ul << _reg ## _ ## _field ## _SHIFT, "7 " _desc "s"), \ 286 MRS_FIELD_VALUE(7ul << _reg ## _ ## _field ## _SHIFT, "8 " _desc "s"), \ 287 MRS_FIELD_VALUE(8ul << _reg ## _ ## _field ## _SHIFT, "9 " _desc "s"), \ 288 MRS_FIELD_VALUE(9ul << _reg ## _ ## _field ## _SHIFT, "10 "_desc "s"), \ 289 MRS_FIELD_VALUE(10ul<< _reg ## _ ## _field ## _SHIFT, "11 "_desc "s"), \ 290 MRS_FIELD_VALUE(11ul<< _reg ## _ ## _field ## _SHIFT, "12 "_desc "s"), \ 291 MRS_FIELD_VALUE(12ul<< _reg ## _ ## _field ## _SHIFT, "13 "_desc "s"), \ 292 MRS_FIELD_VALUE(13ul<< _reg ## _ ## _field ## _SHIFT, "14 "_desc "s"), \ 293 MRS_FIELD_VALUE(14ul<< _reg ## _ ## _field ## _SHIFT, "15 "_desc "s"), \ 294 MRS_FIELD_VALUE(15ul<< _reg ## _ ## _field ## _SHIFT, "16 "_desc "s") 295 296 #define MRS_FIELD_VALUE_END { .desc = NULL } 297 298 struct mrs_field_hwcap { 299 u_long *hwcap; 300 uint64_t min; 301 u_long hwcap_val; 302 }; 303 304 #define MRS_HWCAP(_hwcap, _val, _min) \ 305 { \ 306 .hwcap = (_hwcap), \ 307 .hwcap_val = (_val), \ 308 .min = (_min), \ 309 } 310 311 #define MRS_HWCAP_END { .hwcap = NULL } 312 313 struct mrs_field { 314 const char *name; 315 struct mrs_field_value *values; 316 struct mrs_field_hwcap *hwcaps; 317 uint64_t mask; 318 bool sign; 319 u_int type; 320 u_int shift; 321 }; 322 323 #define MRS_FIELD_HWCAP(_register, _name, _sign, _type, _values, _hwcap) \ 324 { \ 325 .name = #_name, \ 326 .sign = (_sign), \ 327 .type = (_type), \ 328 .shift = _register ## _ ## _name ## _SHIFT, \ 329 .mask = _register ## _ ## _name ## _MASK, \ 330 .values = (_values), \ 331 .hwcaps = (_hwcap), \ 332 } 333 334 #define MRS_FIELD(_register, _name, _sign, _type, _values) \ 335 MRS_FIELD_HWCAP(_register, _name, _sign, _type, _values, NULL) 336 337 #define MRS_FIELD_END { .type = MRS_INVALID, } 338 339 /* ID_AA64AFR0_EL1 */ 340 static struct mrs_field id_aa64afr0_fields[] = { 341 MRS_FIELD_END, 342 }; 343 344 345 /* ID_AA64AFR1_EL1 */ 346 static struct mrs_field id_aa64afr1_fields[] = { 347 MRS_FIELD_END, 348 }; 349 350 351 /* ID_AA64DFR0_EL1 */ 352 static struct mrs_field_value id_aa64dfr0_tracefilt[] = { 353 MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_NONE, ""), 354 MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_8_4, "Trace v8.4"), 355 MRS_FIELD_VALUE_END, 356 }; 357 358 static struct mrs_field_value id_aa64dfr0_doublelock[] = { 359 MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_IMPL, "DoubleLock"), 360 MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_NONE, ""), 361 MRS_FIELD_VALUE_END, 362 }; 363 364 static struct mrs_field_value id_aa64dfr0_pmsver[] = { 365 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_NONE, ""), 366 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE, "SPE"), 367 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_8_3, "SPE v8.3"), 368 MRS_FIELD_VALUE_END, 369 }; 370 371 static struct mrs_field_value id_aa64dfr0_ctx_cmps[] = { 372 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, CTX_CMPs, "CTX BKPT"), 373 MRS_FIELD_VALUE_END, 374 }; 375 376 static struct mrs_field_value id_aa64dfr0_wrps[] = { 377 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, WRPs, "Watchpoint"), 378 MRS_FIELD_VALUE_END, 379 }; 380 381 static struct mrs_field_value id_aa64dfr0_brps[] = { 382 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, BRPs, "Breakpoint"), 383 MRS_FIELD_VALUE_END, 384 }; 385 386 static struct mrs_field_value id_aa64dfr0_pmuver[] = { 387 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_NONE, ""), 388 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3, "PMUv3"), 389 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_1, "PMUv3 v8.1"), 390 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_4, "PMUv3 v8.4"), 391 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_5, "PMUv3 v8.5"), 392 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_IMPL, "IMPL PMU"), 393 MRS_FIELD_VALUE_END, 394 }; 395 396 static struct mrs_field_value id_aa64dfr0_tracever[] = { 397 MRS_FIELD_VALUE(ID_AA64DFR0_TraceVer_NONE, ""), 398 MRS_FIELD_VALUE(ID_AA64DFR0_TraceVer_IMPL, "Trace"), 399 MRS_FIELD_VALUE_END, 400 }; 401 402 static struct mrs_field_value id_aa64dfr0_debugver[] = { 403 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8, "Debugv8"), 404 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_VHE, "Debugv8_VHE"), 405 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_2, "Debugv8.2"), 406 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_4, "Debugv8.4"), 407 MRS_FIELD_VALUE_END, 408 }; 409 410 static struct mrs_field id_aa64dfr0_fields[] = { 411 MRS_FIELD(ID_AA64DFR0, TraceFilt, false, MRS_EXACT, 412 id_aa64dfr0_tracefilt), 413 MRS_FIELD(ID_AA64DFR0, DoubleLock, false, MRS_EXACT, 414 id_aa64dfr0_doublelock), 415 MRS_FIELD(ID_AA64DFR0, PMSVer, false, MRS_EXACT, id_aa64dfr0_pmsver), 416 MRS_FIELD(ID_AA64DFR0, CTX_CMPs, false, MRS_EXACT, 417 id_aa64dfr0_ctx_cmps), 418 MRS_FIELD(ID_AA64DFR0, WRPs, false, MRS_LOWER, id_aa64dfr0_wrps), 419 MRS_FIELD(ID_AA64DFR0, BRPs, false, MRS_LOWER, id_aa64dfr0_brps), 420 MRS_FIELD(ID_AA64DFR0, PMUVer, false, MRS_EXACT, id_aa64dfr0_pmuver), 421 MRS_FIELD(ID_AA64DFR0, TraceVer, false, MRS_EXACT, 422 id_aa64dfr0_tracever), 423 MRS_FIELD(ID_AA64DFR0, DebugVer, false, MRS_EXACT_VAL(0x6), 424 id_aa64dfr0_debugver), 425 MRS_FIELD_END, 426 }; 427 428 429 /* ID_AA64DFR1_EL1 */ 430 static struct mrs_field id_aa64dfr1_fields[] = { 431 MRS_FIELD_END, 432 }; 433 434 435 /* ID_AA64ISAR0_EL1 */ 436 static struct mrs_field_value id_aa64isar0_rndr[] = { 437 MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_NONE, ""), 438 MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_IMPL, "RNG"), 439 MRS_FIELD_VALUE_END, 440 }; 441 442 static struct mrs_field_hwcap id_aa64isar0_rndr_caps[] = { 443 MRS_HWCAP(&elf_hwcap2, HWCAP2_RNG, ID_AA64ISAR0_RNDR_IMPL), 444 MRS_HWCAP_END 445 }; 446 447 static struct mrs_field_value id_aa64isar0_tlb[] = { 448 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_NONE, ""), 449 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOS, "TLBI-OS"), 450 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOSR, "TLBI-OSR"), 451 MRS_FIELD_VALUE_END, 452 }; 453 454 static struct mrs_field_value id_aa64isar0_ts[] = { 455 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_NONE, ""), 456 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_4, "CondM-8.4"), 457 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_5, "CondM-8.5"), 458 MRS_FIELD_VALUE_END, 459 }; 460 461 static struct mrs_field_hwcap id_aa64isar0_ts_caps[] = { 462 MRS_HWCAP(&elf_hwcap, HWCAP_FLAGM, ID_AA64ISAR0_TS_CondM_8_4), 463 MRS_HWCAP(&elf_hwcap2, HWCAP2_FLAGM2, ID_AA64ISAR0_TS_CondM_8_5), 464 MRS_HWCAP_END 465 }; 466 467 static struct mrs_field_value id_aa64isar0_fhm[] = { 468 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, FHM, NONE, IMPL), 469 MRS_FIELD_VALUE_END, 470 }; 471 472 static struct mrs_field_hwcap id_aa64isar0_fhm_caps[] = { 473 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMDFHM, ID_AA64ISAR0_FHM_IMPL), 474 MRS_HWCAP_END 475 }; 476 477 static struct mrs_field_value id_aa64isar0_dp[] = { 478 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, DP, NONE, IMPL), 479 MRS_FIELD_VALUE_END, 480 }; 481 482 static struct mrs_field_hwcap id_aa64isar0_dp_caps[] = { 483 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMDDP, ID_AA64ISAR0_DP_IMPL), 484 MRS_HWCAP_END 485 }; 486 487 static struct mrs_field_value id_aa64isar0_sm4[] = { 488 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM4, NONE, IMPL), 489 MRS_FIELD_VALUE_END, 490 }; 491 492 static struct mrs_field_hwcap id_aa64isar0_sm4_caps[] = { 493 MRS_HWCAP(&elf_hwcap, HWCAP_SM4, ID_AA64ISAR0_SM4_IMPL), 494 MRS_HWCAP_END 495 }; 496 497 static struct mrs_field_value id_aa64isar0_sm3[] = { 498 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM3, NONE, IMPL), 499 MRS_FIELD_VALUE_END, 500 }; 501 502 static struct mrs_field_hwcap id_aa64isar0_sm3_caps[] = { 503 MRS_HWCAP(&elf_hwcap, HWCAP_SM3, ID_AA64ISAR0_SM3_IMPL), 504 MRS_HWCAP_END 505 }; 506 507 static struct mrs_field_value id_aa64isar0_sha3[] = { 508 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA3, NONE, IMPL), 509 MRS_FIELD_VALUE_END, 510 }; 511 512 static struct mrs_field_hwcap id_aa64isar0_sha3_caps[] = { 513 MRS_HWCAP(&elf_hwcap, HWCAP_SHA3, ID_AA64ISAR0_SHA3_IMPL), 514 MRS_HWCAP_END 515 }; 516 517 static struct mrs_field_value id_aa64isar0_rdm[] = { 518 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, RDM, NONE, IMPL), 519 MRS_FIELD_VALUE_END, 520 }; 521 522 static struct mrs_field_hwcap id_aa64isar0_rdm_caps[] = { 523 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMDRDM, ID_AA64ISAR0_RDM_IMPL), 524 MRS_HWCAP_END 525 }; 526 527 static struct mrs_field_value id_aa64isar0_atomic[] = { 528 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, Atomic, NONE, IMPL), 529 MRS_FIELD_VALUE_END, 530 }; 531 532 static struct mrs_field_hwcap id_aa64isar0_atomic_caps[] = { 533 MRS_HWCAP(&elf_hwcap, HWCAP_ATOMICS, ID_AA64ISAR0_Atomic_IMPL), 534 MRS_HWCAP_END 535 }; 536 537 static struct mrs_field_value id_aa64isar0_crc32[] = { 538 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, CRC32, NONE, BASE), 539 MRS_FIELD_VALUE_END, 540 }; 541 542 static struct mrs_field_hwcap id_aa64isar0_crc32_caps[] = { 543 MRS_HWCAP(&elf_hwcap, HWCAP_CRC32, ID_AA64ISAR0_CRC32_BASE), 544 MRS_HWCAP_END 545 }; 546 547 static struct mrs_field_value id_aa64isar0_sha2[] = { 548 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA2, NONE, BASE), 549 MRS_FIELD_VALUE(ID_AA64ISAR0_SHA2_512, "SHA2+SHA512"), 550 MRS_FIELD_VALUE_END, 551 }; 552 553 static struct mrs_field_hwcap id_aa64isar0_sha2_caps[] = { 554 MRS_HWCAP(&elf_hwcap, HWCAP_SHA2, ID_AA64ISAR0_SHA2_BASE), 555 MRS_HWCAP(&elf_hwcap, HWCAP_SHA512, ID_AA64ISAR0_SHA2_512), 556 MRS_HWCAP_END 557 }; 558 559 static struct mrs_field_value id_aa64isar0_sha1[] = { 560 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA1, NONE, BASE), 561 MRS_FIELD_VALUE_END, 562 }; 563 564 static struct mrs_field_hwcap id_aa64isar0_sha1_caps[] = { 565 MRS_HWCAP(&elf_hwcap, HWCAP_SHA1, ID_AA64ISAR0_SHA1_BASE), 566 MRS_HWCAP_END 567 }; 568 569 static struct mrs_field_value id_aa64isar0_aes[] = { 570 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, AES, NONE, BASE), 571 MRS_FIELD_VALUE(ID_AA64ISAR0_AES_PMULL, "AES+PMULL"), 572 MRS_FIELD_VALUE_END, 573 }; 574 575 static struct mrs_field_hwcap id_aa64isar0_aes_caps[] = { 576 MRS_HWCAP(&elf_hwcap, HWCAP_AES, ID_AA64ISAR0_AES_BASE), 577 MRS_HWCAP(&elf_hwcap, HWCAP_PMULL, ID_AA64ISAR0_AES_PMULL), 578 MRS_HWCAP_END 579 }; 580 581 static struct mrs_field id_aa64isar0_fields[] = { 582 MRS_FIELD_HWCAP(ID_AA64ISAR0, RNDR, false, MRS_LOWER, 583 id_aa64isar0_rndr, id_aa64isar0_rndr_caps), 584 MRS_FIELD(ID_AA64ISAR0, TLB, false, MRS_EXACT, id_aa64isar0_tlb), 585 MRS_FIELD_HWCAP(ID_AA64ISAR0, TS, false, MRS_LOWER, id_aa64isar0_ts, 586 id_aa64isar0_ts_caps), 587 MRS_FIELD_HWCAP(ID_AA64ISAR0, FHM, false, MRS_LOWER, id_aa64isar0_fhm, 588 id_aa64isar0_fhm_caps), 589 MRS_FIELD_HWCAP(ID_AA64ISAR0, DP, false, MRS_LOWER, id_aa64isar0_dp, 590 id_aa64isar0_dp_caps), 591 MRS_FIELD_HWCAP(ID_AA64ISAR0, SM4, false, MRS_LOWER, id_aa64isar0_sm4, 592 id_aa64isar0_sm4_caps), 593 MRS_FIELD_HWCAP(ID_AA64ISAR0, SM3, false, MRS_LOWER, id_aa64isar0_sm3, 594 id_aa64isar0_sm3_caps), 595 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA3, false, MRS_LOWER, id_aa64isar0_sha3, 596 id_aa64isar0_sha3_caps), 597 MRS_FIELD_HWCAP(ID_AA64ISAR0, RDM, false, MRS_LOWER, id_aa64isar0_rdm, 598 id_aa64isar0_rdm_caps), 599 MRS_FIELD_HWCAP(ID_AA64ISAR0, Atomic, false, MRS_LOWER, 600 id_aa64isar0_atomic, id_aa64isar0_atomic_caps), 601 MRS_FIELD_HWCAP(ID_AA64ISAR0, CRC32, false, MRS_LOWER, 602 id_aa64isar0_crc32, id_aa64isar0_crc32_caps), 603 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA2, false, MRS_LOWER, id_aa64isar0_sha2, 604 id_aa64isar0_sha2_caps), 605 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA1, false, MRS_LOWER, 606 id_aa64isar0_sha1, id_aa64isar0_sha1_caps), 607 MRS_FIELD_HWCAP(ID_AA64ISAR0, AES, false, MRS_LOWER, id_aa64isar0_aes, 608 id_aa64isar0_aes_caps), 609 MRS_FIELD_END, 610 }; 611 612 613 /* ID_AA64ISAR1_EL1 */ 614 static struct mrs_field_value id_aa64isar1_i8mm[] = { 615 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, I8MM, NONE, IMPL), 616 MRS_FIELD_VALUE_END, 617 }; 618 619 static struct mrs_field_hwcap id_aa64isar1_i8mm_caps[] = { 620 MRS_HWCAP(&elf_hwcap2, HWCAP2_I8MM, ID_AA64ISAR1_I8MM_IMPL), 621 MRS_HWCAP_END 622 }; 623 624 static struct mrs_field_value id_aa64isar1_dgh[] = { 625 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, DGH, NONE, IMPL), 626 MRS_FIELD_VALUE_END, 627 }; 628 629 static struct mrs_field_hwcap id_aa64isar1_dgh_caps[] = { 630 MRS_HWCAP(&elf_hwcap2, HWCAP2_DGH, ID_AA64ISAR1_DGH_IMPL), 631 MRS_HWCAP_END 632 }; 633 634 static struct mrs_field_value id_aa64isar1_bf16[] = { 635 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, BF16, NONE, IMPL), 636 MRS_FIELD_VALUE_END, 637 }; 638 639 static struct mrs_field_hwcap id_aa64isar1_bf16_caps[] = { 640 MRS_HWCAP(&elf_hwcap2, HWCAP2_BF16, ID_AA64ISAR1_BF16_IMPL), 641 MRS_HWCAP_END 642 }; 643 644 static struct mrs_field_value id_aa64isar1_specres[] = { 645 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_NONE, ""), 646 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_IMPL, "PredInv"), 647 MRS_FIELD_VALUE_END, 648 }; 649 650 static struct mrs_field_value id_aa64isar1_sb[] = { 651 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, SB, NONE, IMPL), 652 MRS_FIELD_VALUE_END, 653 }; 654 655 static struct mrs_field_hwcap id_aa64isar1_sb_caps[] = { 656 MRS_HWCAP(&elf_hwcap, HWCAP_SB, ID_AA64ISAR1_SB_IMPL), 657 MRS_HWCAP_END 658 }; 659 660 static struct mrs_field_value id_aa64isar1_frintts[] = { 661 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FRINTTS, NONE, IMPL), 662 MRS_FIELD_VALUE_END, 663 }; 664 665 static struct mrs_field_hwcap id_aa64isar1_frintts_caps[] = { 666 MRS_HWCAP(&elf_hwcap2, HWCAP2_FRINT, ID_AA64ISAR1_FRINTTS_IMPL), 667 MRS_HWCAP_END 668 }; 669 670 static struct mrs_field_value id_aa64isar1_gpi[] = { 671 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPI, NONE, IMPL), 672 MRS_FIELD_VALUE_END, 673 }; 674 675 static struct mrs_field_hwcap id_aa64isar1_gpi_caps[] = { 676 MRS_HWCAP(&elf_hwcap, HWCAP_PACG, ID_AA64ISAR1_GPI_IMPL), 677 MRS_HWCAP_END 678 }; 679 680 static struct mrs_field_value id_aa64isar1_gpa[] = { 681 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPA, NONE, IMPL), 682 MRS_FIELD_VALUE_END, 683 }; 684 685 static struct mrs_field_hwcap id_aa64isar1_gpa_caps[] = { 686 MRS_HWCAP(&elf_hwcap, HWCAP_PACG, ID_AA64ISAR1_GPA_IMPL), 687 MRS_HWCAP_END 688 }; 689 690 static struct mrs_field_value id_aa64isar1_lrcpc[] = { 691 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_NONE, ""), 692 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_3, "RCPC-8.3"), 693 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_4, "RCPC-8.4"), 694 MRS_FIELD_VALUE_END, 695 }; 696 697 static struct mrs_field_hwcap id_aa64isar1_lrcpc_caps[] = { 698 MRS_HWCAP(&elf_hwcap, HWCAP_LRCPC, ID_AA64ISAR1_LRCPC_RCPC_8_3), 699 MRS_HWCAP(&elf_hwcap, HWCAP_ILRCPC, ID_AA64ISAR1_LRCPC_RCPC_8_4), 700 MRS_HWCAP_END 701 }; 702 703 static struct mrs_field_value id_aa64isar1_fcma[] = { 704 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FCMA, NONE, IMPL), 705 MRS_FIELD_VALUE_END, 706 }; 707 708 static struct mrs_field_hwcap id_aa64isar1_fcma_caps[] = { 709 MRS_HWCAP(&elf_hwcap, HWCAP_FCMA, ID_AA64ISAR1_FCMA_IMPL), 710 MRS_HWCAP_END 711 }; 712 713 static struct mrs_field_value id_aa64isar1_jscvt[] = { 714 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, JSCVT, NONE, IMPL), 715 MRS_FIELD_VALUE_END, 716 }; 717 718 static struct mrs_field_hwcap id_aa64isar1_jscvt_caps[] = { 719 MRS_HWCAP(&elf_hwcap, HWCAP_JSCVT, ID_AA64ISAR1_JSCVT_IMPL), 720 MRS_HWCAP_END 721 }; 722 723 static struct mrs_field_value id_aa64isar1_api[] = { 724 MRS_FIELD_VALUE(ID_AA64ISAR1_API_NONE, ""), 725 MRS_FIELD_VALUE(ID_AA64ISAR1_API_PAC, "API PAC"), 726 MRS_FIELD_VALUE(ID_AA64ISAR1_API_EPAC, "API EPAC"), 727 MRS_FIELD_VALUE(ID_AA64ISAR1_API_EPAC2, "Impl PAuth+EPAC2"), 728 MRS_FIELD_VALUE(ID_AA64ISAR1_API_FPAC, "Impl PAuth+FPAC"), 729 MRS_FIELD_VALUE(ID_AA64ISAR1_API_FPAC_COMBINED, 730 "Impl PAuth+FPAC+Combined"), 731 MRS_FIELD_VALUE_END, 732 }; 733 734 static struct mrs_field_hwcap id_aa64isar1_api_caps[] = { 735 MRS_HWCAP(&elf_hwcap, HWCAP_PACA, ID_AA64ISAR1_API_PAC), 736 MRS_HWCAP_END 737 }; 738 739 static struct mrs_field_value id_aa64isar1_apa[] = { 740 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_NONE, ""), 741 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_PAC, "APA PAC"), 742 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC, "APA EPAC"), 743 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC2, "PAuth+EPAC2"), 744 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC, "PAuth+FPAC"), 745 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC_COMBINED, 746 "PAuth+FPAC+Combined"), 747 MRS_FIELD_VALUE_END, 748 }; 749 750 static struct mrs_field_hwcap id_aa64isar1_apa_caps[] = { 751 MRS_HWCAP(&elf_hwcap, HWCAP_PACA, ID_AA64ISAR1_APA_PAC), 752 MRS_HWCAP_END 753 }; 754 755 static struct mrs_field_value id_aa64isar1_dpb[] = { 756 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_NONE, ""), 757 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVAP, "DCPoP"), 758 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVADP, "DCCVADP"), 759 MRS_FIELD_VALUE_END, 760 }; 761 762 static struct mrs_field_hwcap id_aa64isar1_dpb_caps[] = { 763 MRS_HWCAP(&elf_hwcap, HWCAP_DCPOP, ID_AA64ISAR1_DPB_DCCVAP), 764 MRS_HWCAP(&elf_hwcap2, HWCAP2_DCPODP, ID_AA64ISAR1_DPB_DCCVADP), 765 MRS_HWCAP_END 766 }; 767 768 static struct mrs_field id_aa64isar1_fields[] = { 769 MRS_FIELD_HWCAP(ID_AA64ISAR1, I8MM, false, MRS_LOWER, 770 id_aa64isar1_i8mm, id_aa64isar1_i8mm_caps), 771 MRS_FIELD_HWCAP(ID_AA64ISAR1, DGH, false, MRS_LOWER, id_aa64isar1_dgh, 772 id_aa64isar1_dgh_caps), 773 MRS_FIELD_HWCAP(ID_AA64ISAR1, BF16, false, MRS_LOWER, 774 id_aa64isar1_bf16, id_aa64isar1_bf16_caps), 775 MRS_FIELD(ID_AA64ISAR1, SPECRES, false, MRS_EXACT, 776 id_aa64isar1_specres), 777 MRS_FIELD_HWCAP(ID_AA64ISAR1, SB, false, MRS_LOWER, id_aa64isar1_sb, 778 id_aa64isar1_sb_caps), 779 MRS_FIELD_HWCAP(ID_AA64ISAR1, FRINTTS, false, MRS_LOWER, 780 id_aa64isar1_frintts, id_aa64isar1_frintts_caps), 781 MRS_FIELD_HWCAP(ID_AA64ISAR1, GPI, false, MRS_EXACT, id_aa64isar1_gpi, 782 id_aa64isar1_gpi_caps), 783 MRS_FIELD_HWCAP(ID_AA64ISAR1, GPA, false, MRS_EXACT, id_aa64isar1_gpa, 784 id_aa64isar1_gpa_caps), 785 MRS_FIELD_HWCAP(ID_AA64ISAR1, LRCPC, false, MRS_LOWER, 786 id_aa64isar1_lrcpc, id_aa64isar1_lrcpc_caps), 787 MRS_FIELD_HWCAP(ID_AA64ISAR1, FCMA, false, MRS_LOWER, 788 id_aa64isar1_fcma, id_aa64isar1_fcma_caps), 789 MRS_FIELD_HWCAP(ID_AA64ISAR1, JSCVT, false, MRS_LOWER, 790 id_aa64isar1_jscvt, id_aa64isar1_jscvt_caps), 791 MRS_FIELD_HWCAP(ID_AA64ISAR1, API, false, MRS_EXACT, id_aa64isar1_api, 792 id_aa64isar1_api_caps), 793 MRS_FIELD_HWCAP(ID_AA64ISAR1, APA, false, MRS_EXACT, id_aa64isar1_apa, 794 id_aa64isar1_apa_caps), 795 MRS_FIELD_HWCAP(ID_AA64ISAR1, DPB, false, MRS_LOWER, id_aa64isar1_dpb, 796 id_aa64isar1_dpb_caps), 797 MRS_FIELD_END, 798 }; 799 800 801 /* ID_AA64MMFR0_EL1 */ 802 static struct mrs_field_value id_aa64mmfr0_exs[] = { 803 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ExS, ALL, IMPL), 804 MRS_FIELD_VALUE_END, 805 }; 806 807 static struct mrs_field_value id_aa64mmfr0_tgran4_2[] = { 808 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_TGran4, ""), 809 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_NONE, "No S2 TGran4"), 810 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_IMPL, "S2 TGran4"), 811 MRS_FIELD_VALUE_END, 812 }; 813 814 static struct mrs_field_value id_aa64mmfr0_tgran64_2[] = { 815 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_TGran64, ""), 816 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_NONE, "No S2 TGran64"), 817 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_IMPL, "S2 TGran64"), 818 MRS_FIELD_VALUE_END, 819 }; 820 821 static struct mrs_field_value id_aa64mmfr0_tgran16_2[] = { 822 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_TGran16, ""), 823 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_NONE, "No S2 TGran16"), 824 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_IMPL, "S2 TGran16"), 825 MRS_FIELD_VALUE_END, 826 }; 827 828 static struct mrs_field_value id_aa64mmfr0_tgran4[] = { 829 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4,NONE, IMPL), 830 MRS_FIELD_VALUE_END, 831 }; 832 833 static struct mrs_field_value id_aa64mmfr0_tgran64[] = { 834 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran64, NONE, IMPL), 835 MRS_FIELD_VALUE_END, 836 }; 837 838 static struct mrs_field_value id_aa64mmfr0_tgran16[] = { 839 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran16, NONE, IMPL), 840 MRS_FIELD_VALUE_END, 841 }; 842 843 static struct mrs_field_value id_aa64mmfr0_bigendel0[] = { 844 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, BigEndEL0, FIXED, MIXED), 845 MRS_FIELD_VALUE_END, 846 }; 847 848 static struct mrs_field_value id_aa64mmfr0_snsmem[] = { 849 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, SNSMem, NONE, DISTINCT), 850 MRS_FIELD_VALUE_END, 851 }; 852 853 static struct mrs_field_value id_aa64mmfr0_bigend[] = { 854 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, BigEnd, FIXED, MIXED), 855 MRS_FIELD_VALUE_END, 856 }; 857 858 static struct mrs_field_value id_aa64mmfr0_asidbits[] = { 859 MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_8, "8bit ASID"), 860 MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_16, "16bit ASID"), 861 MRS_FIELD_VALUE_END, 862 }; 863 864 static struct mrs_field_value id_aa64mmfr0_parange[] = { 865 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4G, "4GB PA"), 866 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_64G, "64GB PA"), 867 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_1T, "1TB PA"), 868 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4T, "4TB PA"), 869 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_16T, "16TB PA"), 870 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_256T, "256TB PA"), 871 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4P, "4PB PA"), 872 MRS_FIELD_VALUE_END, 873 }; 874 875 static struct mrs_field id_aa64mmfr0_fields[] = { 876 MRS_FIELD(ID_AA64MMFR0, ExS, false, MRS_EXACT, id_aa64mmfr0_exs), 877 MRS_FIELD(ID_AA64MMFR0, TGran4_2, false, MRS_EXACT, 878 id_aa64mmfr0_tgran4_2), 879 MRS_FIELD(ID_AA64MMFR0, TGran64_2, false, MRS_EXACT, 880 id_aa64mmfr0_tgran64_2), 881 MRS_FIELD(ID_AA64MMFR0, TGran16_2, false, MRS_EXACT, 882 id_aa64mmfr0_tgran16_2), 883 MRS_FIELD(ID_AA64MMFR0, TGran4, false, MRS_EXACT, id_aa64mmfr0_tgran4), 884 MRS_FIELD(ID_AA64MMFR0, TGran64, false, MRS_EXACT, 885 id_aa64mmfr0_tgran64), 886 MRS_FIELD(ID_AA64MMFR0, TGran16, false, MRS_EXACT, 887 id_aa64mmfr0_tgran16), 888 MRS_FIELD(ID_AA64MMFR0, BigEndEL0, false, MRS_EXACT, 889 id_aa64mmfr0_bigendel0), 890 MRS_FIELD(ID_AA64MMFR0, SNSMem, false, MRS_EXACT, id_aa64mmfr0_snsmem), 891 MRS_FIELD(ID_AA64MMFR0, BigEnd, false, MRS_EXACT, id_aa64mmfr0_bigend), 892 MRS_FIELD(ID_AA64MMFR0, ASIDBits, false, MRS_EXACT, 893 id_aa64mmfr0_asidbits), 894 MRS_FIELD(ID_AA64MMFR0, PARange, false, MRS_EXACT, 895 id_aa64mmfr0_parange), 896 MRS_FIELD_END, 897 }; 898 899 900 /* ID_AA64MMFR1_EL1 */ 901 static struct mrs_field_value id_aa64mmfr1_xnx[] = { 902 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, XNX, NONE, IMPL), 903 MRS_FIELD_VALUE_END, 904 }; 905 906 static struct mrs_field_value id_aa64mmfr1_specsei[] = { 907 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, SpecSEI, NONE, IMPL), 908 MRS_FIELD_VALUE_END, 909 }; 910 911 static struct mrs_field_value id_aa64mmfr1_pan[] = { 912 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, PAN, NONE, IMPL), 913 MRS_FIELD_VALUE(ID_AA64MMFR1_PAN_ATS1E1, "PAN+ATS1E1"), 914 MRS_FIELD_VALUE_END, 915 }; 916 917 static struct mrs_field_value id_aa64mmfr1_lo[] = { 918 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, LO, NONE, IMPL), 919 MRS_FIELD_VALUE_END, 920 }; 921 922 static struct mrs_field_value id_aa64mmfr1_hpds[] = { 923 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_NONE, ""), 924 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_HPD, "HPD"), 925 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_TTPBHA, "HPD+TTPBHA"), 926 MRS_FIELD_VALUE_END, 927 }; 928 929 static struct mrs_field_value id_aa64mmfr1_vh[] = { 930 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, VH, NONE, IMPL), 931 MRS_FIELD_VALUE_END, 932 }; 933 934 static struct mrs_field_value id_aa64mmfr1_vmidbits[] = { 935 MRS_FIELD_VALUE(ID_AA64MMFR1_VMIDBits_8, "8bit VMID"), 936 MRS_FIELD_VALUE(ID_AA64MMFR1_VMIDBits_16, "16bit VMID"), 937 MRS_FIELD_VALUE_END, 938 }; 939 940 static struct mrs_field_value id_aa64mmfr1_hafdbs[] = { 941 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_NONE, ""), 942 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_AF, "HAF"), 943 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_AF_DBS, "HAF+DS"), 944 MRS_FIELD_VALUE_END, 945 }; 946 947 static struct mrs_field id_aa64mmfr1_fields[] = { 948 MRS_FIELD(ID_AA64MMFR1, XNX, false, MRS_EXACT, id_aa64mmfr1_xnx), 949 MRS_FIELD(ID_AA64MMFR1, SpecSEI, false, MRS_EXACT, 950 id_aa64mmfr1_specsei), 951 MRS_FIELD(ID_AA64MMFR1, PAN, false, MRS_EXACT, id_aa64mmfr1_pan), 952 MRS_FIELD(ID_AA64MMFR1, LO, false, MRS_EXACT, id_aa64mmfr1_lo), 953 MRS_FIELD(ID_AA64MMFR1, HPDS, false, MRS_EXACT, id_aa64mmfr1_hpds), 954 MRS_FIELD(ID_AA64MMFR1, VH, false, MRS_EXACT, id_aa64mmfr1_vh), 955 MRS_FIELD(ID_AA64MMFR1, VMIDBits, false, MRS_EXACT, 956 id_aa64mmfr1_vmidbits), 957 MRS_FIELD(ID_AA64MMFR1, HAFDBS, false, MRS_EXACT, id_aa64mmfr1_hafdbs), 958 MRS_FIELD_END, 959 }; 960 961 962 /* ID_AA64MMFR2_EL1 */ 963 static struct mrs_field_value id_aa64mmfr2_e0pd[] = { 964 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, E0PD, NONE, IMPL), 965 MRS_FIELD_VALUE_END, 966 }; 967 968 static struct mrs_field_value id_aa64mmfr2_evt[] = { 969 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_NONE, ""), 970 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_2, "EVT-8.2"), 971 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_5, "EVT-8.5"), 972 MRS_FIELD_VALUE_END, 973 }; 974 975 static struct mrs_field_value id_aa64mmfr2_bbm[] = { 976 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL0, ""), 977 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL1, "BBM level 1"), 978 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL2, "BBM level 2"), 979 MRS_FIELD_VALUE_END, 980 }; 981 982 static struct mrs_field_value id_aa64mmfr2_ttl[] = { 983 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, TTL, NONE, IMPL), 984 MRS_FIELD_VALUE_END, 985 }; 986 987 static struct mrs_field_value id_aa64mmfr2_fwb[] = { 988 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, FWB, NONE, IMPL), 989 MRS_FIELD_VALUE_END, 990 }; 991 992 static struct mrs_field_value id_aa64mmfr2_ids[] = { 993 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, IDS, NONE, IMPL), 994 MRS_FIELD_VALUE_END, 995 }; 996 997 static struct mrs_field_value id_aa64mmfr2_at[] = { 998 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, AT, NONE, IMPL), 999 MRS_FIELD_VALUE_END, 1000 }; 1001 1002 static struct mrs_field_hwcap id_aa64mmfr2_at_caps[] = { 1003 MRS_HWCAP(&elf_hwcap, HWCAP_USCAT, ID_AA64MMFR2_AT_IMPL), 1004 MRS_HWCAP_END 1005 }; 1006 1007 static struct mrs_field_value id_aa64mmfr2_st[] = { 1008 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, ST, NONE, IMPL), 1009 MRS_FIELD_VALUE_END, 1010 }; 1011 1012 static struct mrs_field_value id_aa64mmfr2_nv[] = { 1013 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, NV, NONE, 8_3), 1014 MRS_FIELD_VALUE(ID_AA64MMFR2_NV_8_4, "NV v8.4"), 1015 MRS_FIELD_VALUE_END, 1016 }; 1017 1018 static struct mrs_field_value id_aa64mmfr2_ccidx[] = { 1019 MRS_FIELD_VALUE(ID_AA64MMFR2_CCIDX_32, "32bit CCIDX"), 1020 MRS_FIELD_VALUE(ID_AA64MMFR2_CCIDX_64, "64bit CCIDX"), 1021 MRS_FIELD_VALUE_END, 1022 }; 1023 1024 static struct mrs_field_value id_aa64mmfr2_varange[] = { 1025 MRS_FIELD_VALUE(ID_AA64MMFR2_VARange_48, "48bit VA"), 1026 MRS_FIELD_VALUE(ID_AA64MMFR2_VARange_52, "52bit VA"), 1027 MRS_FIELD_VALUE_END, 1028 }; 1029 1030 static struct mrs_field_value id_aa64mmfr2_iesb[] = { 1031 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, IESB, NONE, IMPL), 1032 MRS_FIELD_VALUE_END, 1033 }; 1034 1035 static struct mrs_field_value id_aa64mmfr2_lsm[] = { 1036 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, LSM, NONE, IMPL), 1037 MRS_FIELD_VALUE_END, 1038 }; 1039 1040 static struct mrs_field_value id_aa64mmfr2_uao[] = { 1041 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, UAO, NONE, IMPL), 1042 MRS_FIELD_VALUE_END, 1043 }; 1044 1045 static struct mrs_field_value id_aa64mmfr2_cnp[] = { 1046 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, CnP, NONE, IMPL), 1047 MRS_FIELD_VALUE_END, 1048 }; 1049 1050 static struct mrs_field id_aa64mmfr2_fields[] = { 1051 MRS_FIELD(ID_AA64MMFR2, E0PD, false, MRS_EXACT, id_aa64mmfr2_e0pd), 1052 MRS_FIELD(ID_AA64MMFR2, EVT, false, MRS_EXACT, id_aa64mmfr2_evt), 1053 MRS_FIELD(ID_AA64MMFR2, BBM, false, MRS_EXACT, id_aa64mmfr2_bbm), 1054 MRS_FIELD(ID_AA64MMFR2, TTL, false, MRS_EXACT, id_aa64mmfr2_ttl), 1055 MRS_FIELD(ID_AA64MMFR2, FWB, false, MRS_EXACT, id_aa64mmfr2_fwb), 1056 MRS_FIELD(ID_AA64MMFR2, IDS, false, MRS_EXACT, id_aa64mmfr2_ids), 1057 MRS_FIELD_HWCAP(ID_AA64MMFR2, AT, false, MRS_LOWER, id_aa64mmfr2_at, 1058 id_aa64mmfr2_at_caps), 1059 MRS_FIELD(ID_AA64MMFR2, ST, false, MRS_EXACT, id_aa64mmfr2_st), 1060 MRS_FIELD(ID_AA64MMFR2, NV, false, MRS_EXACT, id_aa64mmfr2_nv), 1061 MRS_FIELD(ID_AA64MMFR2, CCIDX, false, MRS_EXACT, id_aa64mmfr2_ccidx), 1062 MRS_FIELD(ID_AA64MMFR2, VARange, false, MRS_EXACT, 1063 id_aa64mmfr2_varange), 1064 MRS_FIELD(ID_AA64MMFR2, IESB, false, MRS_EXACT, id_aa64mmfr2_iesb), 1065 MRS_FIELD(ID_AA64MMFR2, LSM, false, MRS_EXACT, id_aa64mmfr2_lsm), 1066 MRS_FIELD(ID_AA64MMFR2, UAO, false, MRS_EXACT, id_aa64mmfr2_uao), 1067 MRS_FIELD(ID_AA64MMFR2, CnP, false, MRS_EXACT, id_aa64mmfr2_cnp), 1068 MRS_FIELD_END, 1069 }; 1070 1071 1072 /* ID_AA64PFR0_EL1 */ 1073 static struct mrs_field_value id_aa64pfr0_csv3[] = { 1074 MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""), 1075 MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_ISOLATED, "CSV3"), 1076 MRS_FIELD_VALUE_END, 1077 }; 1078 1079 static struct mrs_field_value id_aa64pfr0_csv2[] = { 1080 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_NONE, ""), 1081 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_ISOLATED, "CSV2"), 1082 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_SCXTNUM, "SCXTNUM"), 1083 MRS_FIELD_VALUE_END, 1084 }; 1085 1086 static struct mrs_field_value id_aa64pfr0_dit[] = { 1087 MRS_FIELD_VALUE(ID_AA64PFR0_DIT_NONE, ""), 1088 MRS_FIELD_VALUE(ID_AA64PFR0_DIT_PSTATE, "PSTATE.DIT"), 1089 MRS_FIELD_VALUE_END, 1090 }; 1091 1092 static struct mrs_field_hwcap id_aa64pfr0_dit_caps[] = { 1093 MRS_HWCAP(&elf_hwcap, HWCAP_DIT, ID_AA64PFR0_DIT_PSTATE), 1094 MRS_HWCAP_END 1095 }; 1096 1097 static struct mrs_field_value id_aa64pfr0_amu[] = { 1098 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_NONE, ""), 1099 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1, "AMUv1"), 1100 MRS_FIELD_VALUE_END, 1101 }; 1102 1103 static struct mrs_field_value id_aa64pfr0_mpam[] = { 1104 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, MPAM, NONE, IMPL), 1105 MRS_FIELD_VALUE_END, 1106 }; 1107 1108 static struct mrs_field_value id_aa64pfr0_sel2[] = { 1109 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SEL2, NONE, IMPL), 1110 MRS_FIELD_VALUE_END, 1111 }; 1112 1113 static struct mrs_field_value id_aa64pfr0_sve[] = { 1114 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SVE, NONE, IMPL), 1115 MRS_FIELD_VALUE_END, 1116 }; 1117 1118 #if 0 1119 /* Enable when we add SVE support */ 1120 static struct mrs_field_hwcap id_aa64pfr0_sve_caps[] = { 1121 MRS_HWCAP(&elf_hwcap, HWCAP_SVE, ID_AA64PFR0_SVE_IMPL), 1122 MRS_HWCAP_END 1123 }; 1124 #endif 1125 1126 static struct mrs_field_value id_aa64pfr0_ras[] = { 1127 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_NONE, ""), 1128 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_IMPL, "RAS"), 1129 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_8_4, "RAS v8.4"), 1130 MRS_FIELD_VALUE_END, 1131 }; 1132 1133 static struct mrs_field_value id_aa64pfr0_gic[] = { 1134 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, GIC, CPUIF_NONE, CPUIF_EN), 1135 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_NONE, ""), 1136 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_EN, "GIC"), 1137 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_4_1, "GIC 4.1"), 1138 MRS_FIELD_VALUE_END, 1139 }; 1140 1141 static struct mrs_field_value id_aa64pfr0_advsimd[] = { 1142 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, AdvSIMD, NONE, IMPL), 1143 MRS_FIELD_VALUE(ID_AA64PFR0_AdvSIMD_HP, "AdvSIMD+HP"), 1144 MRS_FIELD_VALUE_END, 1145 }; 1146 1147 static struct mrs_field_hwcap id_aa64pfr0_advsimd_caps[] = { 1148 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMD, ID_AA64PFR0_AdvSIMD_IMPL), 1149 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMDHP, ID_AA64PFR0_AdvSIMD_HP), 1150 MRS_HWCAP_END 1151 }; 1152 1153 static struct mrs_field_value id_aa64pfr0_fp[] = { 1154 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, FP, NONE, IMPL), 1155 MRS_FIELD_VALUE(ID_AA64PFR0_FP_HP, "FP+HP"), 1156 MRS_FIELD_VALUE_END, 1157 }; 1158 1159 static struct mrs_field_hwcap id_aa64pfr0_fp_caps[] = { 1160 MRS_HWCAP(&elf_hwcap, HWCAP_FP, ID_AA64PFR0_FP_IMPL), 1161 MRS_HWCAP(&elf_hwcap, HWCAP_FPHP, ID_AA64PFR0_FP_HP), 1162 MRS_HWCAP_END 1163 }; 1164 1165 static struct mrs_field_value id_aa64pfr0_el3[] = { 1166 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, EL3, NONE, 64), 1167 MRS_FIELD_VALUE(ID_AA64PFR0_EL3_64_32, "EL3 32"), 1168 MRS_FIELD_VALUE_END, 1169 }; 1170 1171 static struct mrs_field_value id_aa64pfr0_el2[] = { 1172 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, EL2, NONE, 64), 1173 MRS_FIELD_VALUE(ID_AA64PFR0_EL2_64_32, "EL2 32"), 1174 MRS_FIELD_VALUE_END, 1175 }; 1176 1177 static struct mrs_field_value id_aa64pfr0_el1[] = { 1178 MRS_FIELD_VALUE(ID_AA64PFR0_EL1_64, "EL1"), 1179 MRS_FIELD_VALUE(ID_AA64PFR0_EL1_64_32, "EL1 32"), 1180 MRS_FIELD_VALUE_END, 1181 }; 1182 1183 static struct mrs_field_value id_aa64pfr0_el0[] = { 1184 MRS_FIELD_VALUE(ID_AA64PFR0_EL0_64, "EL0"), 1185 MRS_FIELD_VALUE(ID_AA64PFR0_EL0_64_32, "EL0 32"), 1186 MRS_FIELD_VALUE_END, 1187 }; 1188 1189 static struct mrs_field id_aa64pfr0_fields[] = { 1190 MRS_FIELD(ID_AA64PFR0, CSV3, false, MRS_EXACT, id_aa64pfr0_csv3), 1191 MRS_FIELD(ID_AA64PFR0, CSV2, false, MRS_EXACT, id_aa64pfr0_csv2), 1192 MRS_FIELD_HWCAP(ID_AA64PFR0, DIT, false, MRS_LOWER, id_aa64pfr0_dit, 1193 id_aa64pfr0_dit_caps), 1194 MRS_FIELD(ID_AA64PFR0, AMU, false, MRS_EXACT, id_aa64pfr0_amu), 1195 MRS_FIELD(ID_AA64PFR0, MPAM, false, MRS_EXACT, id_aa64pfr0_mpam), 1196 MRS_FIELD(ID_AA64PFR0, SEL2, false, MRS_EXACT, id_aa64pfr0_sel2), 1197 MRS_FIELD(ID_AA64PFR0, SVE, false, MRS_EXACT, id_aa64pfr0_sve), 1198 MRS_FIELD(ID_AA64PFR0, RAS, false, MRS_EXACT, id_aa64pfr0_ras), 1199 MRS_FIELD(ID_AA64PFR0, GIC, false, MRS_EXACT, id_aa64pfr0_gic), 1200 MRS_FIELD_HWCAP(ID_AA64PFR0, AdvSIMD, true, MRS_LOWER, 1201 id_aa64pfr0_advsimd, id_aa64pfr0_advsimd_caps), 1202 MRS_FIELD_HWCAP(ID_AA64PFR0, FP, true, MRS_LOWER, id_aa64pfr0_fp, 1203 id_aa64pfr0_fp_caps), 1204 MRS_FIELD(ID_AA64PFR0, EL3, false, MRS_EXACT, id_aa64pfr0_el3), 1205 MRS_FIELD(ID_AA64PFR0, EL2, false, MRS_EXACT, id_aa64pfr0_el2), 1206 MRS_FIELD(ID_AA64PFR0, EL1, false, MRS_LOWER, id_aa64pfr0_el1), 1207 MRS_FIELD(ID_AA64PFR0, EL0, false, MRS_LOWER, id_aa64pfr0_el0), 1208 MRS_FIELD_END, 1209 }; 1210 1211 1212 /* ID_AA64PFR1_EL1 */ 1213 static struct mrs_field_value id_aa64pfr1_mte[] = { 1214 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_NONE, ""), 1215 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL_EL0, "MTE EL0"), 1216 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL, "MTE"), 1217 MRS_FIELD_VALUE_END, 1218 }; 1219 1220 static struct mrs_field_value id_aa64pfr1_ssbs[] = { 1221 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_NONE, ""), 1222 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE, "PSTATE.SSBS"), 1223 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE_MSR, "PSTATE.SSBS MSR"), 1224 MRS_FIELD_VALUE_END, 1225 }; 1226 1227 static struct mrs_field_hwcap id_aa64pfr1_ssbs_caps[] = { 1228 MRS_HWCAP(&elf_hwcap, HWCAP_SSBS, ID_AA64PFR1_SSBS_PSTATE), 1229 MRS_HWCAP_END 1230 }; 1231 1232 static struct mrs_field_value id_aa64pfr1_bt[] = { 1233 MRS_FIELD_VALUE(ID_AA64PFR1_BT_NONE, ""), 1234 MRS_FIELD_VALUE(ID_AA64PFR1_BT_IMPL, "BTI"), 1235 MRS_FIELD_VALUE_END, 1236 }; 1237 1238 #if 0 1239 /* Enable when we add BTI support */ 1240 static struct mrs_field_hwcap id_aa64pfr1_bt_caps[] = { 1241 MRS_HWCAP(&elf_hwcap2, HWCAP2_BTI, ID_AA64PFR1_BT_IMPL), 1242 MRS_HWCAP_END 1243 }; 1244 #endif 1245 1246 static struct mrs_field id_aa64pfr1_fields[] = { 1247 MRS_FIELD(ID_AA64PFR1, MTE, false, MRS_EXACT, id_aa64pfr1_mte), 1248 MRS_FIELD_HWCAP(ID_AA64PFR1, SSBS, false, MRS_LOWER, id_aa64pfr1_ssbs, 1249 id_aa64pfr1_ssbs_caps), 1250 MRS_FIELD(ID_AA64PFR1, BT, false, MRS_EXACT, id_aa64pfr1_bt), 1251 MRS_FIELD_END, 1252 }; 1253 1254 #ifdef COMPAT_FREEBSD32 1255 /* ID_ISAR5_EL1 */ 1256 static struct mrs_field_value id_isar5_vcma[] = { 1257 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, VCMA, NONE, IMPL), 1258 MRS_FIELD_VALUE_END, 1259 }; 1260 1261 static struct mrs_field_value id_isar5_rdm[] = { 1262 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, RDM, NONE, IMPL), 1263 MRS_FIELD_VALUE_END, 1264 }; 1265 1266 static struct mrs_field_value id_isar5_crc32[] = { 1267 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, CRC32, NONE, IMPL), 1268 MRS_FIELD_VALUE_END, 1269 }; 1270 1271 static struct mrs_field_hwcap id_isar5_crc32_caps[] = { 1272 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_CRC32, ID_ISAR5_CRC32_IMPL), 1273 MRS_HWCAP_END 1274 }; 1275 1276 static struct mrs_field_value id_isar5_sha2[] = { 1277 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA2, NONE, IMPL), 1278 MRS_FIELD_VALUE_END, 1279 }; 1280 1281 static struct mrs_field_hwcap id_isar5_sha2_caps[] = { 1282 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_SHA2, ID_ISAR5_SHA2_IMPL), 1283 MRS_HWCAP_END 1284 }; 1285 1286 static struct mrs_field_value id_isar5_sha1[] = { 1287 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA1, NONE, IMPL), 1288 MRS_FIELD_VALUE_END, 1289 }; 1290 1291 static struct mrs_field_hwcap id_isar5_sha1_caps[] = { 1292 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_SHA1, ID_ISAR5_SHA1_IMPL), 1293 MRS_HWCAP_END 1294 }; 1295 1296 static struct mrs_field_value id_isar5_aes[] = { 1297 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, AES, NONE, BASE), 1298 MRS_FIELD_VALUE(ID_ISAR5_AES_VMULL, "AES+VMULL"), 1299 MRS_FIELD_VALUE_END, 1300 }; 1301 1302 static struct mrs_field_hwcap id_isar5_aes_caps[] = { 1303 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_AES, ID_ISAR5_AES_BASE), 1304 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_PMULL, ID_ISAR5_AES_VMULL), 1305 MRS_HWCAP_END 1306 }; 1307 1308 static struct mrs_field_value id_isar5_sevl[] = { 1309 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SEVL, NOP, IMPL), 1310 MRS_FIELD_VALUE_END, 1311 }; 1312 1313 static struct mrs_field id_isar5_fields[] = { 1314 MRS_FIELD(ID_ISAR5, VCMA, false, MRS_LOWER, id_isar5_vcma), 1315 MRS_FIELD(ID_ISAR5, RDM, false, MRS_LOWER, id_isar5_rdm), 1316 MRS_FIELD_HWCAP(ID_ISAR5, CRC32, false, MRS_LOWER, id_isar5_crc32, 1317 id_isar5_crc32_caps), 1318 MRS_FIELD_HWCAP(ID_ISAR5, SHA2, false, MRS_LOWER, id_isar5_sha2, 1319 id_isar5_sha2_caps), 1320 MRS_FIELD_HWCAP(ID_ISAR5, SHA1, false, MRS_LOWER, id_isar5_sha1, 1321 id_isar5_sha1_caps), 1322 MRS_FIELD_HWCAP(ID_ISAR5, AES, false, MRS_LOWER, id_isar5_aes, 1323 id_isar5_aes_caps), 1324 MRS_FIELD(ID_ISAR5, SEVL, false, MRS_LOWER, id_isar5_sevl), 1325 MRS_FIELD_END, 1326 }; 1327 1328 /* MVFR0 */ 1329 static struct mrs_field_value mvfr0_fpround[] = { 1330 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPRound, NONE, IMPL), 1331 MRS_FIELD_VALUE_END, 1332 }; 1333 1334 static struct mrs_field_value mvfr0_fpsqrt[] = { 1335 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPSqrt, NONE, IMPL), 1336 MRS_FIELD_VALUE_END, 1337 }; 1338 1339 static struct mrs_field_value mvfr0_fpdivide[] = { 1340 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPDivide, NONE, IMPL), 1341 MRS_FIELD_VALUE_END, 1342 }; 1343 1344 static struct mrs_field_value mvfr0_fptrap[] = { 1345 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPTrap, NONE, IMPL), 1346 MRS_FIELD_VALUE_END, 1347 }; 1348 1349 static struct mrs_field_value mvfr0_fpdp[] = { 1350 MRS_FIELD_VALUE(MVFR0_FPDP_NONE, ""), 1351 MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v2, "DP VFPv2"), 1352 MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v3_v4, "DP VFPv3+v4"), 1353 MRS_FIELD_VALUE_END, 1354 }; 1355 1356 static struct mrs_field_hwcap mvfr0_fpdp_caps[] = { 1357 MRS_HWCAP(&elf32_hwcap, HWCAP32_VFP, MVFR0_FPDP_VFP_v2), 1358 MRS_HWCAP(&elf32_hwcap, HWCAP32_VFPv3, MVFR0_FPDP_VFP_v3_v4), 1359 }; 1360 1361 static struct mrs_field_value mvfr0_fpsp[] = { 1362 MRS_FIELD_VALUE(MVFR0_FPSP_NONE, ""), 1363 MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v2, "SP VFPv2"), 1364 MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v3_v4, "SP VFPv3+v4"), 1365 MRS_FIELD_VALUE_END, 1366 }; 1367 1368 static struct mrs_field_value mvfr0_simdreg[] = { 1369 MRS_FIELD_VALUE(MVFR0_SIMDReg_NONE, ""), 1370 MRS_FIELD_VALUE(MVFR0_SIMDReg_FP, "FP 16x64"), 1371 MRS_FIELD_VALUE(MVFR0_SIMDReg_AdvSIMD, "AdvSIMD"), 1372 MRS_FIELD_VALUE_END, 1373 }; 1374 1375 static struct mrs_field mvfr0_fields[] = { 1376 MRS_FIELD(MVFR0, FPRound, false, MRS_LOWER, mvfr0_fpround), 1377 MRS_FIELD(MVFR0, FPSqrt, false, MRS_LOWER, mvfr0_fpsqrt), 1378 MRS_FIELD(MVFR0, FPDivide, false, MRS_LOWER, mvfr0_fpdivide), 1379 MRS_FIELD(MVFR0, FPTrap, false, MRS_LOWER, mvfr0_fptrap), 1380 MRS_FIELD_HWCAP(MVFR0, FPDP, false, MRS_LOWER, mvfr0_fpdp, 1381 mvfr0_fpdp_caps), 1382 MRS_FIELD(MVFR0, FPSP, false, MRS_LOWER, mvfr0_fpsp), 1383 MRS_FIELD(MVFR0, SIMDReg, false, MRS_LOWER, mvfr0_simdreg), 1384 MRS_FIELD_END, 1385 }; 1386 1387 /* MVFR1 */ 1388 static struct mrs_field_value mvfr1_simdfmac[] = { 1389 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDFMAC, NONE, IMPL), 1390 MRS_FIELD_VALUE_END, 1391 }; 1392 1393 static struct mrs_field_hwcap mvfr1_simdfmac_caps[] = { 1394 MRS_HWCAP(&elf32_hwcap, HWCAP32_VFPv4, MVFR1_SIMDFMAC_IMPL), 1395 MRS_HWCAP_END 1396 }; 1397 1398 static struct mrs_field_value mvfr1_fphp[] = { 1399 MRS_FIELD_VALUE(MVFR1_FPHP_NONE, ""), 1400 MRS_FIELD_VALUE(MVFR1_FPHP_CONV_SP, "FPHP SP Conv"), 1401 MRS_FIELD_VALUE(MVFR1_FPHP_CONV_DP, "FPHP DP Conv"), 1402 MRS_FIELD_VALUE(MVFR1_FPHP_ARITH, "FPHP Arith"), 1403 MRS_FIELD_VALUE_END, 1404 }; 1405 1406 static struct mrs_field_value mvfr1_simdhp[] = { 1407 MRS_FIELD_VALUE(MVFR1_SIMDHP_NONE, ""), 1408 MRS_FIELD_VALUE(MVFR1_SIMDHP_CONV_SP, "SIMDHP SP Conv"), 1409 MRS_FIELD_VALUE(MVFR1_SIMDHP_ARITH, "SIMDHP Arith"), 1410 MRS_FIELD_VALUE_END, 1411 }; 1412 1413 static struct mrs_field_value mvfr1_simdsp[] = { 1414 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDSP, NONE, IMPL), 1415 MRS_FIELD_VALUE_END, 1416 }; 1417 1418 static struct mrs_field_value mvfr1_simdint[] = { 1419 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDInt, NONE, IMPL), 1420 MRS_FIELD_VALUE_END, 1421 }; 1422 1423 static struct mrs_field_value mvfr1_simdls[] = { 1424 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDLS, NONE, IMPL), 1425 MRS_FIELD_VALUE_END, 1426 }; 1427 1428 static struct mrs_field_hwcap mvfr1_simdls_caps[] = { 1429 MRS_HWCAP(&elf32_hwcap, HWCAP32_VFPv4, MVFR1_SIMDFMAC_IMPL), 1430 MRS_HWCAP_END 1431 }; 1432 1433 static struct mrs_field_value mvfr1_fpdnan[] = { 1434 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPDNaN, NONE, IMPL), 1435 MRS_FIELD_VALUE_END, 1436 }; 1437 1438 static struct mrs_field_value mvfr1_fpftz[] = { 1439 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPFtZ, NONE, IMPL), 1440 MRS_FIELD_VALUE_END, 1441 }; 1442 1443 static struct mrs_field mvfr1_fields[] = { 1444 MRS_FIELD_HWCAP(MVFR1, SIMDFMAC, false, MRS_LOWER, mvfr1_simdfmac, 1445 mvfr1_simdfmac_caps), 1446 MRS_FIELD(MVFR1, FPHP, false, MRS_LOWER, mvfr1_fphp), 1447 MRS_FIELD(MVFR1, SIMDHP, false, MRS_LOWER, mvfr1_simdhp), 1448 MRS_FIELD(MVFR1, SIMDSP, false, MRS_LOWER, mvfr1_simdsp), 1449 MRS_FIELD(MVFR1, SIMDInt, false, MRS_LOWER, mvfr1_simdint), 1450 MRS_FIELD_HWCAP(MVFR1, SIMDLS, false, MRS_LOWER, mvfr1_simdls, 1451 mvfr1_simdls_caps), 1452 MRS_FIELD(MVFR1, FPDNaN, false, MRS_LOWER, mvfr1_fpdnan), 1453 MRS_FIELD(MVFR1, FPFtZ, false, MRS_LOWER, mvfr1_fpftz), 1454 MRS_FIELD_END, 1455 }; 1456 #endif /* COMPAT_FREEBSD32 */ 1457 1458 struct mrs_user_reg { 1459 u_int reg; 1460 u_int CRm; 1461 u_int Op2; 1462 size_t offset; 1463 struct mrs_field *fields; 1464 }; 1465 1466 #define USER_REG(name, field_name) \ 1467 { \ 1468 .reg = name, \ 1469 .CRm = name##_CRm, \ 1470 .Op2 = name##_op2, \ 1471 .offset = __offsetof(struct cpu_desc, field_name), \ 1472 .fields = field_name##_fields, \ 1473 } 1474 static struct mrs_user_reg user_regs[] = { 1475 USER_REG(ID_AA64DFR0_EL1, id_aa64dfr0), 1476 1477 USER_REG(ID_AA64ISAR0_EL1, id_aa64isar0), 1478 USER_REG(ID_AA64ISAR1_EL1, id_aa64isar1), 1479 1480 USER_REG(ID_AA64MMFR0_EL1, id_aa64mmfr0), 1481 USER_REG(ID_AA64MMFR1_EL1, id_aa64mmfr1), 1482 USER_REG(ID_AA64MMFR2_EL1, id_aa64mmfr2), 1483 1484 USER_REG(ID_AA64PFR0_EL1, id_aa64pfr0), 1485 USER_REG(ID_AA64PFR1_EL1, id_aa64pfr1), 1486 #ifdef COMPAT_FREEBSD32 1487 USER_REG(ID_ISAR5_EL1, id_isar5), 1488 1489 USER_REG(MVFR0_EL1, mvfr0), 1490 USER_REG(MVFR1_EL1, mvfr1), 1491 #endif /* COMPAT_FREEBSD32 */ 1492 }; 1493 1494 #define CPU_DESC_FIELD(desc, idx) \ 1495 *(uint64_t *)((char *)&(desc) + user_regs[(idx)].offset) 1496 1497 static int 1498 user_mrs_handler(vm_offset_t va, uint32_t insn, struct trapframe *frame, 1499 uint32_t esr) 1500 { 1501 uint64_t value; 1502 int CRm, Op2, i, reg; 1503 1504 if ((insn & MRS_MASK) != MRS_VALUE) 1505 return (0); 1506 1507 /* 1508 * We only emulate Op0 == 3, Op1 == 0, CRn == 0, CRm == {0, 4-7}. 1509 * These are in the EL1 CPU identification space. 1510 * CRm == 0 holds MIDR_EL1, MPIDR_EL1, and REVID_EL1. 1511 * CRm == {4-7} holds the ID_AA64 registers. 1512 * 1513 * For full details see the ARMv8 ARM (ARM DDI 0487C.a) 1514 * Table D9-2 System instruction encodings for non-Debug System 1515 * register accesses. 1516 */ 1517 if (mrs_Op0(insn) != 3 || mrs_Op1(insn) != 0 || mrs_CRn(insn) != 0) 1518 return (0); 1519 1520 CRm = mrs_CRm(insn); 1521 if (CRm > 7 || (CRm < 4 && CRm != 0)) 1522 return (0); 1523 1524 Op2 = mrs_Op2(insn); 1525 value = 0; 1526 1527 for (i = 0; i < nitems(user_regs); i++) { 1528 if (user_regs[i].CRm == CRm && user_regs[i].Op2 == Op2) { 1529 value = CPU_DESC_FIELD(user_cpu_desc, i); 1530 break; 1531 } 1532 } 1533 1534 if (CRm == 0) { 1535 switch (Op2) { 1536 case 0: 1537 value = READ_SPECIALREG(midr_el1); 1538 break; 1539 case 5: 1540 value = READ_SPECIALREG(mpidr_el1); 1541 break; 1542 case 6: 1543 value = READ_SPECIALREG(revidr_el1); 1544 break; 1545 default: 1546 return (0); 1547 } 1548 } 1549 1550 /* 1551 * We will handle this instruction, move to the next so we 1552 * don't trap here again. 1553 */ 1554 frame->tf_elr += INSN_SIZE; 1555 1556 reg = MRS_REGISTER(insn); 1557 /* If reg is 31 then write to xzr, i.e. do nothing */ 1558 if (reg == 31) 1559 return (1); 1560 1561 if (reg < nitems(frame->tf_x)) 1562 frame->tf_x[reg] = value; 1563 else if (reg == 30) 1564 frame->tf_lr = value; 1565 1566 return (1); 1567 } 1568 1569 bool 1570 extract_user_id_field(u_int reg, u_int field_shift, uint8_t *val) 1571 { 1572 uint64_t value; 1573 int i; 1574 1575 for (i = 0; i < nitems(user_regs); i++) { 1576 if (user_regs[i].reg == reg) { 1577 value = CPU_DESC_FIELD(user_cpu_desc, i); 1578 *val = value >> field_shift; 1579 return (true); 1580 } 1581 } 1582 1583 return (false); 1584 } 1585 1586 bool 1587 get_kernel_reg(u_int reg, uint64_t *val) 1588 { 1589 int i; 1590 1591 for (i = 0; i < nitems(user_regs); i++) { 1592 if (user_regs[i].reg == reg) { 1593 *val = CPU_DESC_FIELD(kern_cpu_desc, i); 1594 return (true); 1595 } 1596 } 1597 1598 return (false); 1599 } 1600 1601 /* 1602 * Compares two field values that may be signed or unsigned. 1603 * Returns: 1604 * < 0 when a is less than b 1605 * = 0 when a equals b 1606 * > 0 when a is greater than b 1607 */ 1608 static int 1609 mrs_field_cmp(uint64_t a, uint64_t b, u_int shift, int width, bool sign) 1610 { 1611 uint64_t mask; 1612 1613 KASSERT(width > 0 && width < 64, ("%s: Invalid width %d", __func__, 1614 width)); 1615 1616 mask = (1ul << width) - 1; 1617 /* Move the field to the lower bits */ 1618 a = (a >> shift) & mask; 1619 b = (b >> shift) & mask; 1620 1621 if (sign) { 1622 /* 1623 * The field is signed. Toggle the upper bit so the comparison 1624 * works on unsigned values as this makes positive numbers, 1625 * i.e. those with a 0 bit, larger than negative numbers, 1626 * i.e. those with a 1 bit, in an unsigned comparison. 1627 */ 1628 a ^= 1ul << (width - 1); 1629 b ^= 1ul << (width - 1); 1630 } 1631 1632 return (a - b); 1633 } 1634 1635 static uint64_t 1636 update_lower_register(uint64_t val, uint64_t new_val, u_int shift, 1637 int width, bool sign) 1638 { 1639 uint64_t mask; 1640 1641 KASSERT(width > 0 && width < 64, ("%s: Invalid width %d", __func__, 1642 width)); 1643 1644 /* 1645 * If the new value is less than the existing value update it. 1646 */ 1647 if (mrs_field_cmp(new_val, val, shift, width, sign) < 0) { 1648 mask = (1ul << width) - 1; 1649 val &= ~(mask << shift); 1650 val |= new_val & (mask << shift); 1651 } 1652 1653 return (val); 1654 } 1655 1656 void 1657 update_special_regs(u_int cpu) 1658 { 1659 struct mrs_field *fields; 1660 uint64_t user_reg, kern_reg, value; 1661 int i, j; 1662 1663 if (cpu == 0) { 1664 /* Create a user visible cpu description with safe values */ 1665 memset(&user_cpu_desc, 0, sizeof(user_cpu_desc)); 1666 /* Safe values for these registers */ 1667 user_cpu_desc.id_aa64pfr0 = ID_AA64PFR0_AdvSIMD_NONE | 1668 ID_AA64PFR0_FP_NONE | ID_AA64PFR0_EL1_64 | 1669 ID_AA64PFR0_EL0_64; 1670 user_cpu_desc.id_aa64dfr0 = ID_AA64DFR0_DebugVer_8; 1671 } 1672 1673 for (i = 0; i < nitems(user_regs); i++) { 1674 value = CPU_DESC_FIELD(cpu_desc[cpu], i); 1675 if (cpu == 0) { 1676 kern_reg = value; 1677 user_reg = value; 1678 } else { 1679 kern_reg = CPU_DESC_FIELD(kern_cpu_desc, i); 1680 user_reg = CPU_DESC_FIELD(user_cpu_desc, i); 1681 } 1682 1683 fields = user_regs[i].fields; 1684 for (j = 0; fields[j].type != 0; j++) { 1685 switch (fields[j].type & MRS_TYPE_MASK) { 1686 case MRS_EXACT: 1687 user_reg &= ~(0xful << fields[j].shift); 1688 user_reg |= 1689 (uint64_t)MRS_EXACT_FIELD(fields[j].type) << 1690 fields[j].shift; 1691 break; 1692 case MRS_LOWER: 1693 user_reg = update_lower_register(user_reg, 1694 value, fields[j].shift, 4, fields[j].sign); 1695 break; 1696 default: 1697 panic("Invalid field type: %d", fields[j].type); 1698 } 1699 kern_reg = update_lower_register(kern_reg, value, 1700 fields[j].shift, 4, fields[j].sign); 1701 } 1702 1703 CPU_DESC_FIELD(kern_cpu_desc, i) = kern_reg; 1704 CPU_DESC_FIELD(user_cpu_desc, i) = user_reg; 1705 } 1706 } 1707 1708 /* HWCAP */ 1709 bool __read_frequently lse_supported = false; 1710 1711 bool __read_frequently icache_aliasing = false; 1712 bool __read_frequently icache_vmid = false; 1713 1714 int64_t dcache_line_size; /* The minimum D cache line size */ 1715 int64_t icache_line_size; /* The minimum I cache line size */ 1716 int64_t idcache_line_size; /* The minimum cache line size */ 1717 1718 /* 1719 * Find the values to export to userspace as AT_HWCAP and AT_HWCAP2. 1720 */ 1721 static void 1722 parse_cpu_features(void) 1723 { 1724 struct mrs_field_hwcap *hwcaps; 1725 struct mrs_field *fields; 1726 uint64_t min, reg; 1727 int i, j, k; 1728 1729 for (i = 0; i < nitems(user_regs); i++) { 1730 reg = CPU_DESC_FIELD(user_cpu_desc, i); 1731 fields = user_regs[i].fields; 1732 for (j = 0; fields[j].type != 0; j++) { 1733 hwcaps = fields[j].hwcaps; 1734 if (hwcaps == NULL) 1735 continue; 1736 1737 for (k = 0; hwcaps[k].hwcap != NULL; k++) { 1738 min = hwcaps[k].min; 1739 1740 /* 1741 * If the field is greater than the minimum 1742 * value we can set the hwcap; 1743 */ 1744 if (mrs_field_cmp(reg, min, fields[j].shift, 1745 4, fields[j].sign) >= 0) { 1746 *hwcaps[k].hwcap |= hwcaps[k].hwcap_val; 1747 } 1748 } 1749 } 1750 } 1751 } 1752 1753 static void 1754 identify_cpu_sysinit(void *dummy __unused) 1755 { 1756 int cpu; 1757 bool dic, idc; 1758 1759 dic = (allow_dic != 0); 1760 idc = (allow_idc != 0); 1761 1762 CPU_FOREACH(cpu) { 1763 check_cpu_regs(cpu); 1764 if (cpu != 0) 1765 update_special_regs(cpu); 1766 1767 if (CTR_DIC_VAL(cpu_desc[cpu].ctr) == 0) 1768 dic = false; 1769 if (CTR_IDC_VAL(cpu_desc[cpu].ctr) == 0) 1770 idc = false; 1771 } 1772 1773 /* Find the values to export to userspace as AT_HWCAP and AT_HWCAP2 */ 1774 parse_cpu_features(); 1775 1776 #ifdef COMPAT_FREEBSD32 1777 /* Set the default caps and any that need to check multiple fields */ 1778 elf32_hwcap |= parse_cpu_features_hwcap32(); 1779 #endif 1780 1781 if (dic && idc) { 1782 arm64_icache_sync_range = &arm64_dic_idc_icache_sync_range; 1783 if (bootverbose) 1784 printf("Enabling DIC & IDC ICache sync\n"); 1785 } 1786 1787 if ((elf_hwcap & HWCAP_ATOMICS) != 0) { 1788 lse_supported = true; 1789 if (bootverbose) 1790 printf("Enabling LSE atomics in the kernel\n"); 1791 } 1792 #ifdef LSE_ATOMICS 1793 if (!lse_supported) 1794 panic("CPU does not support LSE atomic instructions"); 1795 #endif 1796 1797 install_undef_handler(true, user_mrs_handler); 1798 } 1799 SYSINIT(identify_cpu, SI_SUB_CPU, SI_ORDER_MIDDLE, identify_cpu_sysinit, NULL); 1800 1801 static void 1802 cpu_features_sysinit(void *dummy __unused) 1803 { 1804 struct sbuf sb; 1805 u_int cpu; 1806 1807 CPU_FOREACH(cpu) 1808 print_cpu_features(cpu); 1809 1810 /* Fill in cpu_model for the hw.model sysctl */ 1811 sbuf_new(&sb, cpu_model, sizeof(cpu_model), SBUF_FIXEDLEN); 1812 print_cpu_midr(&sb, 0); 1813 1814 sbuf_finish(&sb); 1815 sbuf_delete(&sb); 1816 } 1817 /* Log features before APs are released and start printing to the dmesg. */ 1818 SYSINIT(cpu_features, SI_SUB_SMP - 1, SI_ORDER_ANY, cpu_features_sysinit, NULL); 1819 1820 #ifdef COMPAT_FREEBSD32 1821 static u_long 1822 parse_cpu_features_hwcap32(void) 1823 { 1824 u_long hwcap = HWCAP32_DEFAULT; 1825 1826 if ((MVFR1_SIMDLS_VAL(user_cpu_desc.mvfr1) >= 1827 MVFR1_SIMDLS_IMPL) && 1828 (MVFR1_SIMDInt_VAL(user_cpu_desc.mvfr1) >= 1829 MVFR1_SIMDInt_IMPL) && 1830 (MVFR1_SIMDSP_VAL(user_cpu_desc.mvfr1) >= 1831 MVFR1_SIMDSP_IMPL)) 1832 hwcap |= HWCAP32_NEON; 1833 1834 return (hwcap); 1835 } 1836 #endif /* COMPAT_FREEBSD32 */ 1837 1838 static void 1839 print_ctr_fields(struct sbuf *sb, uint64_t reg, void *arg) 1840 { 1841 1842 sbuf_printf(sb, "%u byte D-cacheline,", CTR_DLINE_SIZE(reg)); 1843 sbuf_printf(sb, "%u byte I-cacheline,", CTR_ILINE_SIZE(reg)); 1844 reg &= ~(CTR_DLINE_MASK | CTR_ILINE_MASK); 1845 1846 switch(CTR_L1IP_VAL(reg)) { 1847 case CTR_L1IP_VPIPT: 1848 sbuf_printf(sb, "VPIPT"); 1849 break; 1850 case CTR_L1IP_AIVIVT: 1851 sbuf_printf(sb, "AIVIVT"); 1852 break; 1853 case CTR_L1IP_VIPT: 1854 sbuf_printf(sb, "VIPT"); 1855 break; 1856 case CTR_L1IP_PIPT: 1857 sbuf_printf(sb, "PIPT"); 1858 break; 1859 } 1860 sbuf_printf(sb, " ICache,"); 1861 reg &= ~CTR_L1IP_MASK; 1862 1863 sbuf_printf(sb, "%d byte ERG,", CTR_ERG_SIZE(reg)); 1864 sbuf_printf(sb, "%d byte CWG", CTR_CWG_SIZE(reg)); 1865 reg &= ~(CTR_ERG_MASK | CTR_CWG_MASK); 1866 1867 if (CTR_IDC_VAL(reg) != 0) 1868 sbuf_printf(sb, ",IDC"); 1869 if (CTR_DIC_VAL(reg) != 0) 1870 sbuf_printf(sb, ",DIC"); 1871 reg &= ~(CTR_IDC_MASK | CTR_DIC_MASK); 1872 reg &= ~CTR_RES1; 1873 1874 if (reg != 0) 1875 sbuf_printf(sb, ",%lx", reg); 1876 } 1877 1878 static void 1879 print_register(struct sbuf *sb, const char *reg_name, uint64_t reg, 1880 void (*print_fields)(struct sbuf *, uint64_t, void *), void *arg) 1881 { 1882 1883 sbuf_printf(sb, "%29s = <", reg_name); 1884 1885 print_fields(sb, reg, arg); 1886 1887 sbuf_finish(sb); 1888 printf("%s>\n", sbuf_data(sb)); 1889 sbuf_clear(sb); 1890 } 1891 1892 static void 1893 print_id_fields(struct sbuf *sb, uint64_t reg, void *arg) 1894 { 1895 struct mrs_field *fields = arg; 1896 struct mrs_field_value *fv; 1897 int field, i, j, printed; 1898 1899 #define SEP_STR ((printed++) == 0) ? "" : "," 1900 printed = 0; 1901 for (i = 0; fields[i].type != 0; i++) { 1902 fv = fields[i].values; 1903 1904 /* TODO: Handle with an unknown message */ 1905 if (fv == NULL) 1906 continue; 1907 1908 field = (reg & fields[i].mask) >> fields[i].shift; 1909 for (j = 0; fv[j].desc != NULL; j++) { 1910 if ((fv[j].value >> fields[i].shift) != field) 1911 continue; 1912 1913 if (fv[j].desc[0] != '\0') 1914 sbuf_printf(sb, "%s%s", SEP_STR, fv[j].desc); 1915 break; 1916 } 1917 if (fv[j].desc == NULL) 1918 sbuf_printf(sb, "%sUnknown %s(%x)", SEP_STR, 1919 fields[i].name, field); 1920 1921 reg &= ~(0xful << fields[i].shift); 1922 } 1923 1924 if (reg != 0) 1925 sbuf_printf(sb, "%s%#lx", SEP_STR, reg); 1926 #undef SEP_STR 1927 } 1928 1929 static void 1930 print_id_register(struct sbuf *sb, const char *reg_name, uint64_t reg, 1931 struct mrs_field *fields) 1932 { 1933 1934 print_register(sb, reg_name, reg, print_id_fields, fields); 1935 } 1936 1937 static void 1938 print_cpu_midr(struct sbuf *sb, u_int cpu) 1939 { 1940 const struct cpu_parts *cpu_partsp; 1941 const char *cpu_impl_name; 1942 const char *cpu_part_name; 1943 u_int midr; 1944 u_int impl_id; 1945 u_int part_id; 1946 1947 midr = pcpu_find(cpu)->pc_midr; 1948 1949 cpu_impl_name = NULL; 1950 cpu_partsp = NULL; 1951 impl_id = CPU_IMPL(midr); 1952 for (int i = 0; cpu_implementers[i].impl_name != NULL; i++) { 1953 if (impl_id == cpu_implementers[i].impl_id) { 1954 cpu_impl_name = cpu_implementers[i].impl_name; 1955 cpu_partsp = cpu_implementers[i].cpu_parts; 1956 break; 1957 } 1958 } 1959 /* Unknown implementer, so unknown part */ 1960 if (cpu_impl_name == NULL) { 1961 sbuf_printf(sb, "Unknown Implementer (midr: %08x)", midr); 1962 return; 1963 } 1964 1965 KASSERT(cpu_partsp != NULL, ("%s: No parts table for implementer %s", 1966 __func__, cpu_impl_name)); 1967 1968 cpu_part_name = NULL; 1969 part_id = CPU_PART(midr); 1970 for (int i = 0; cpu_partsp[i].part_name != NULL; i++) { 1971 if (part_id == cpu_partsp[i].part_id) { 1972 cpu_part_name = cpu_partsp[i].part_name; 1973 break; 1974 } 1975 } 1976 /* Known Implementer, Unknown part */ 1977 if (cpu_part_name == NULL) { 1978 sbuf_printf(sb, "%s Unknown CPU r%dp%d (midr: %08x)", 1979 cpu_impl_name, CPU_VAR(midr), CPU_REV(midr), midr); 1980 return; 1981 } 1982 1983 sbuf_printf(sb, "%s %s r%dp%d", cpu_impl_name, 1984 cpu_part_name, CPU_VAR(midr), CPU_REV(midr)); 1985 } 1986 1987 static void 1988 print_cpu_cache(u_int cpu, struct sbuf *sb, uint64_t ccs, bool icache, 1989 bool unified) 1990 { 1991 size_t cache_size; 1992 size_t line_size; 1993 1994 /* LineSize is Log2(S) - 4. */ 1995 line_size = 1 << ((ccs & CCSIDR_LineSize_MASK) + 4); 1996 /* 1997 * Calculate cache size (sets * ways * line size). There are different 1998 * formats depending on the FEAT_CCIDX bit in ID_AA64MMFR2 feature 1999 * register. 2000 */ 2001 if ((cpu_desc[cpu].id_aa64mmfr2 & ID_AA64MMFR2_CCIDX_64)) 2002 cache_size = (CCSIDR_NSETS_64(ccs) + 1) * 2003 (CCSIDR_ASSOC_64(ccs) + 1); 2004 else 2005 cache_size = (CCSIDR_NSETS(ccs) + 1) * (CCSIDR_ASSOC(ccs) + 1); 2006 2007 cache_size *= line_size; 2008 sbuf_printf(sb, "%zuKB (%s)", cache_size / 1024, 2009 icache ? "instruction" : unified ? "unified" : "data"); 2010 } 2011 2012 static void 2013 print_cpu_caches(struct sbuf *sb, u_int cpu) 2014 { 2015 /* Print out each cache combination */ 2016 uint64_t clidr; 2017 int i = 1; 2018 clidr = cpu_desc[cpu].clidr; 2019 2020 for (i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) { 2021 int j = 0; 2022 int ctype_m = (clidr & CLIDR_CTYPE_MASK); 2023 2024 sbuf_printf(sb, " L%d cache: ", i + 1); 2025 if ((clidr & CLIDR_CTYPE_IO)) { 2026 print_cpu_cache(cpu, sb, cpu_desc[cpu].ccsidr[i][j++], 2027 true, false); 2028 /* If there's more, add to the line. */ 2029 if ((ctype_m & ~CLIDR_CTYPE_IO) != 0) 2030 sbuf_printf(sb, ", "); 2031 } 2032 if ((ctype_m & ~CLIDR_CTYPE_IO) != 0) { 2033 print_cpu_cache(cpu, sb, cpu_desc[cpu].ccsidr[i][j], 2034 false, (clidr & CLIDR_CTYPE_UNIFIED)); 2035 } 2036 sbuf_printf(sb, "\n"); 2037 2038 } 2039 sbuf_finish(sb); 2040 printf("%s", sbuf_data(sb)); 2041 } 2042 2043 static void 2044 print_cpu_features(u_int cpu) 2045 { 2046 struct sbuf *sb; 2047 2048 sb = sbuf_new_auto(); 2049 sbuf_printf(sb, "CPU%3u: ", cpu); 2050 print_cpu_midr(sb, cpu); 2051 2052 sbuf_cat(sb, " affinity:"); 2053 switch(cpu_aff_levels) { 2054 default: 2055 case 4: 2056 sbuf_printf(sb, " %2d", CPU_AFF3(cpu_desc[cpu].mpidr)); 2057 /* FALLTHROUGH */ 2058 case 3: 2059 sbuf_printf(sb, " %2d", CPU_AFF2(cpu_desc[cpu].mpidr)); 2060 /* FALLTHROUGH */ 2061 case 2: 2062 sbuf_printf(sb, " %2d", CPU_AFF1(cpu_desc[cpu].mpidr)); 2063 /* FALLTHROUGH */ 2064 case 1: 2065 case 0: /* On UP this will be zero */ 2066 sbuf_printf(sb, " %2d", CPU_AFF0(cpu_desc[cpu].mpidr)); 2067 break; 2068 } 2069 sbuf_finish(sb); 2070 printf("%s\n", sbuf_data(sb)); 2071 sbuf_clear(sb); 2072 2073 /* 2074 * There is a hardware errata where, if one CPU is performing a TLB 2075 * invalidation while another is performing a store-exclusive the 2076 * store-exclusive may return the wrong status. A workaround seems 2077 * to be to use an IPI to invalidate on each CPU, however given the 2078 * limited number of affected units (pass 1.1 is the evaluation 2079 * hardware revision), and the lack of information from Cavium 2080 * this has not been implemented. 2081 * 2082 * At the time of writing this the only information is from: 2083 * https://lkml.org/lkml/2016/8/4/722 2084 */ 2085 /* 2086 * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 on its own also 2087 * triggers on pass 2.0+. 2088 */ 2089 if (cpu == 0 && CPU_VAR(PCPU_GET(midr)) == 0 && 2090 CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1) 2091 printf("WARNING: ThunderX Pass 1.1 detected.\nThis has known " 2092 "hardware bugs that may cause the incorrect operation of " 2093 "atomic operations.\n"); 2094 2095 /* Cache Type Register */ 2096 if (cpu == 0 || (cpu_print_regs & PRINT_CTR_EL0) != 0) { 2097 print_register(sb, "Cache Type", 2098 cpu_desc[cpu].ctr, print_ctr_fields, NULL); 2099 } 2100 2101 /* AArch64 Instruction Set Attribute Register 0 */ 2102 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR0) != 0) 2103 print_id_register(sb, "Instruction Set Attributes 0", 2104 cpu_desc[cpu].id_aa64isar0, id_aa64isar0_fields); 2105 2106 /* AArch64 Instruction Set Attribute Register 1 */ 2107 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR1) != 0) 2108 print_id_register(sb, "Instruction Set Attributes 1", 2109 cpu_desc[cpu].id_aa64isar1, id_aa64isar1_fields); 2110 2111 /* AArch64 Processor Feature Register 0 */ 2112 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR0) != 0) 2113 print_id_register(sb, "Processor Features 0", 2114 cpu_desc[cpu].id_aa64pfr0, id_aa64pfr0_fields); 2115 2116 /* AArch64 Processor Feature Register 1 */ 2117 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR1) != 0) 2118 print_id_register(sb, "Processor Features 1", 2119 cpu_desc[cpu].id_aa64pfr1, id_aa64pfr1_fields); 2120 2121 /* AArch64 Memory Model Feature Register 0 */ 2122 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR0) != 0) 2123 print_id_register(sb, "Memory Model Features 0", 2124 cpu_desc[cpu].id_aa64mmfr0, id_aa64mmfr0_fields); 2125 2126 /* AArch64 Memory Model Feature Register 1 */ 2127 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR1) != 0) 2128 print_id_register(sb, "Memory Model Features 1", 2129 cpu_desc[cpu].id_aa64mmfr1, id_aa64mmfr1_fields); 2130 2131 /* AArch64 Memory Model Feature Register 2 */ 2132 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR2) != 0) 2133 print_id_register(sb, "Memory Model Features 2", 2134 cpu_desc[cpu].id_aa64mmfr2, id_aa64mmfr2_fields); 2135 2136 /* AArch64 Debug Feature Register 0 */ 2137 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_DFR0) != 0) 2138 print_id_register(sb, "Debug Features 0", 2139 cpu_desc[cpu].id_aa64dfr0, id_aa64dfr0_fields); 2140 2141 /* AArch64 Memory Model Feature Register 1 */ 2142 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_DFR1) != 0) 2143 print_id_register(sb, "Debug Features 1", 2144 cpu_desc[cpu].id_aa64dfr1, id_aa64dfr1_fields); 2145 2146 /* AArch64 Auxiliary Feature Register 0 */ 2147 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_AFR0) != 0) 2148 print_id_register(sb, "Auxiliary Features 0", 2149 cpu_desc[cpu].id_aa64afr0, id_aa64afr0_fields); 2150 2151 /* AArch64 Auxiliary Feature Register 1 */ 2152 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_AFR1) != 0) 2153 print_id_register(sb, "Auxiliary Features 1", 2154 cpu_desc[cpu].id_aa64afr1, id_aa64afr1_fields); 2155 2156 #ifdef COMPAT_FREEBSD32 2157 /* AArch32 Instruction Set Attribute Register 5 */ 2158 if (cpu == 0 || (cpu_print_regs & PRINT_ID_ISAR5) != 0) 2159 print_id_register(sb, "AArch32 Instruction Set Attributes 5", 2160 cpu_desc[cpu].id_isar5, id_isar5_fields); 2161 2162 /* AArch32 Media and VFP Feature Register 0 */ 2163 if (cpu == 0 || (cpu_print_regs & PRINT_MVFR0) != 0) 2164 print_id_register(sb, "AArch32 Media and VFP Features 0", 2165 cpu_desc[cpu].mvfr0, mvfr0_fields); 2166 2167 /* AArch32 Media and VFP Feature Register 1 */ 2168 if (cpu == 0 || (cpu_print_regs & PRINT_MVFR1) != 0) 2169 print_id_register(sb, "AArch32 Media and VFP Features 1", 2170 cpu_desc[cpu].mvfr1, mvfr1_fields); 2171 #endif 2172 if (bootverbose) 2173 print_cpu_caches(sb, cpu); 2174 2175 sbuf_delete(sb); 2176 sb = NULL; 2177 #undef SEP_STR 2178 } 2179 2180 void 2181 identify_cache(uint64_t ctr) 2182 { 2183 2184 /* Identify the L1 cache type */ 2185 switch (CTR_L1IP_VAL(ctr)) { 2186 case CTR_L1IP_PIPT: 2187 break; 2188 case CTR_L1IP_VPIPT: 2189 icache_vmid = true; 2190 break; 2191 default: 2192 case CTR_L1IP_VIPT: 2193 icache_aliasing = true; 2194 break; 2195 } 2196 2197 if (dcache_line_size == 0) { 2198 KASSERT(icache_line_size == 0, ("%s: i-cacheline size set: %ld", 2199 __func__, icache_line_size)); 2200 2201 /* Get the D cache line size */ 2202 dcache_line_size = CTR_DLINE_SIZE(ctr); 2203 /* And the same for the I cache */ 2204 icache_line_size = CTR_ILINE_SIZE(ctr); 2205 2206 idcache_line_size = MIN(dcache_line_size, icache_line_size); 2207 } 2208 2209 if (dcache_line_size != CTR_DLINE_SIZE(ctr)) { 2210 printf("WARNING: D-cacheline size mismatch %ld != %d\n", 2211 dcache_line_size, CTR_DLINE_SIZE(ctr)); 2212 } 2213 2214 if (icache_line_size != CTR_ILINE_SIZE(ctr)) { 2215 printf("WARNING: I-cacheline size mismatch %ld != %d\n", 2216 icache_line_size, CTR_ILINE_SIZE(ctr)); 2217 } 2218 } 2219 2220 void 2221 identify_cpu(u_int cpu) 2222 { 2223 uint64_t clidr; 2224 2225 /* Save affinity for current CPU */ 2226 cpu_desc[cpu].mpidr = get_mpidr(); 2227 CPU_AFFINITY(cpu) = cpu_desc[cpu].mpidr & CPU_AFF_MASK; 2228 2229 cpu_desc[cpu].ctr = READ_SPECIALREG(ctr_el0); 2230 cpu_desc[cpu].id_aa64dfr0 = READ_SPECIALREG(id_aa64dfr0_el1); 2231 cpu_desc[cpu].id_aa64dfr1 = READ_SPECIALREG(id_aa64dfr1_el1); 2232 cpu_desc[cpu].id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1); 2233 cpu_desc[cpu].id_aa64isar1 = READ_SPECIALREG(id_aa64isar1_el1); 2234 cpu_desc[cpu].id_aa64mmfr0 = READ_SPECIALREG(id_aa64mmfr0_el1); 2235 cpu_desc[cpu].id_aa64mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1); 2236 cpu_desc[cpu].id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1); 2237 cpu_desc[cpu].id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1); 2238 cpu_desc[cpu].id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1); 2239 2240 cpu_desc[cpu].clidr = READ_SPECIALREG(clidr_el1); 2241 2242 clidr = cpu_desc[cpu].clidr; 2243 2244 for (int i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) { 2245 int j = 0; 2246 if ((clidr & CLIDR_CTYPE_IO)) { 2247 WRITE_SPECIALREG(csselr_el1, 2248 CSSELR_Level(i) | CSSELR_InD); 2249 cpu_desc[cpu].ccsidr[i][j++] = 2250 READ_SPECIALREG(ccsidr_el1); 2251 } 2252 if ((clidr & ~CLIDR_CTYPE_IO) == 0) 2253 continue; 2254 WRITE_SPECIALREG(csselr_el1, CSSELR_Level(i)); 2255 cpu_desc[cpu].ccsidr[i][j] = READ_SPECIALREG(ccsidr_el1); 2256 } 2257 2258 #ifdef COMPAT_FREEBSD32 2259 /* Only read aarch32 SRs if EL0-32 is available */ 2260 if (ID_AA64PFR0_EL0_VAL(cpu_desc[cpu].id_aa64pfr0) == 2261 ID_AA64PFR0_EL0_64_32) { 2262 cpu_desc[cpu].id_isar5 = READ_SPECIALREG(id_isar5_el1); 2263 cpu_desc[cpu].mvfr0 = READ_SPECIALREG(mvfr0_el1); 2264 cpu_desc[cpu].mvfr1 = READ_SPECIALREG(mvfr1_el1); 2265 } 2266 #endif 2267 } 2268 2269 static void 2270 check_cpu_regs(u_int cpu) 2271 { 2272 2273 switch (cpu_aff_levels) { 2274 case 0: 2275 if (CPU_AFF0(cpu_desc[cpu].mpidr) != 2276 CPU_AFF0(cpu_desc[0].mpidr)) 2277 cpu_aff_levels = 1; 2278 /* FALLTHROUGH */ 2279 case 1: 2280 if (CPU_AFF1(cpu_desc[cpu].mpidr) != 2281 CPU_AFF1(cpu_desc[0].mpidr)) 2282 cpu_aff_levels = 2; 2283 /* FALLTHROUGH */ 2284 case 2: 2285 if (CPU_AFF2(cpu_desc[cpu].mpidr) != 2286 CPU_AFF2(cpu_desc[0].mpidr)) 2287 cpu_aff_levels = 3; 2288 /* FALLTHROUGH */ 2289 case 3: 2290 if (CPU_AFF3(cpu_desc[cpu].mpidr) != 2291 CPU_AFF3(cpu_desc[0].mpidr)) 2292 cpu_aff_levels = 4; 2293 break; 2294 } 2295 2296 if (cpu_desc[cpu].id_aa64afr0 != cpu_desc[0].id_aa64afr0) 2297 cpu_print_regs |= PRINT_ID_AA64_AFR0; 2298 if (cpu_desc[cpu].id_aa64afr1 != cpu_desc[0].id_aa64afr1) 2299 cpu_print_regs |= PRINT_ID_AA64_AFR1; 2300 2301 if (cpu_desc[cpu].id_aa64dfr0 != cpu_desc[0].id_aa64dfr0) 2302 cpu_print_regs |= PRINT_ID_AA64_DFR0; 2303 if (cpu_desc[cpu].id_aa64dfr1 != cpu_desc[0].id_aa64dfr1) 2304 cpu_print_regs |= PRINT_ID_AA64_DFR1; 2305 2306 if (cpu_desc[cpu].id_aa64isar0 != cpu_desc[0].id_aa64isar0) 2307 cpu_print_regs |= PRINT_ID_AA64_ISAR0; 2308 if (cpu_desc[cpu].id_aa64isar1 != cpu_desc[0].id_aa64isar1) 2309 cpu_print_regs |= PRINT_ID_AA64_ISAR1; 2310 2311 if (cpu_desc[cpu].id_aa64mmfr0 != cpu_desc[0].id_aa64mmfr0) 2312 cpu_print_regs |= PRINT_ID_AA64_MMFR0; 2313 if (cpu_desc[cpu].id_aa64mmfr1 != cpu_desc[0].id_aa64mmfr1) 2314 cpu_print_regs |= PRINT_ID_AA64_MMFR1; 2315 if (cpu_desc[cpu].id_aa64mmfr2 != cpu_desc[0].id_aa64mmfr2) 2316 cpu_print_regs |= PRINT_ID_AA64_MMFR2; 2317 2318 if (cpu_desc[cpu].id_aa64pfr0 != cpu_desc[0].id_aa64pfr0) 2319 cpu_print_regs |= PRINT_ID_AA64_PFR0; 2320 if (cpu_desc[cpu].id_aa64pfr1 != cpu_desc[0].id_aa64pfr1) 2321 cpu_print_regs |= PRINT_ID_AA64_PFR1; 2322 2323 if (cpu_desc[cpu].ctr != cpu_desc[0].ctr) { 2324 /* 2325 * If the cache type register is different we may 2326 * have a different l1 cache type. 2327 */ 2328 identify_cache(cpu_desc[cpu].ctr); 2329 cpu_print_regs |= PRINT_CTR_EL0; 2330 } 2331 2332 #ifdef COMPAT_FREEBSD32 2333 if (cpu_desc[cpu].id_isar5 != cpu_desc[0].id_isar5) 2334 cpu_print_regs |= PRINT_ID_ISAR5; 2335 if (cpu_desc[cpu].mvfr0 != cpu_desc[0].mvfr0) 2336 cpu_print_regs |= PRINT_MVFR0; 2337 if (cpu_desc[cpu].mvfr1 != cpu_desc[0].mvfr1) 2338 cpu_print_regs |= PRINT_MVFR1; 2339 #endif 2340 } 2341