1 /*- 2 * Copyright (c) 2014 Andrew Turner 3 * Copyright (c) 2014 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by Semihalf 7 * under sponsorship of the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/pcpu.h> 38 #include <sys/sbuf.h> 39 #include <sys/smp.h> 40 #include <sys/sysctl.h> 41 #include <sys/systm.h> 42 43 #include <machine/atomic.h> 44 #include <machine/cpu.h> 45 #include <machine/cpufunc.h> 46 #include <machine/elf.h> 47 #include <machine/md_var.h> 48 #include <machine/undefined.h> 49 50 static void print_cpu_midr(struct sbuf *sb, u_int cpu); 51 static void print_cpu_features(u_int cpu); 52 static void print_cpu_caches(struct sbuf *sb, u_int); 53 #ifdef COMPAT_FREEBSD32 54 static u_long parse_cpu_features_hwcap32(void); 55 #endif 56 57 char machine[] = "arm64"; 58 59 #ifdef SCTL_MASK32 60 extern int adaptive_machine_arch; 61 #endif 62 63 static SYSCTL_NODE(_machdep, OID_AUTO, cache, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 64 "Cache management tuning"); 65 66 static int allow_dic = 1; 67 SYSCTL_INT(_machdep_cache, OID_AUTO, allow_dic, CTLFLAG_RDTUN, &allow_dic, 0, 68 "Allow optimizations based on the DIC cache bit"); 69 70 static int allow_idc = 1; 71 SYSCTL_INT(_machdep_cache, OID_AUTO, allow_idc, CTLFLAG_RDTUN, &allow_idc, 0, 72 "Allow optimizations based on the IDC cache bit"); 73 74 static void check_cpu_regs(u_int cpu); 75 76 /* 77 * The default implementation of I-cache sync assumes we have an 78 * aliasing cache until we know otherwise. 79 */ 80 void (*arm64_icache_sync_range)(vm_offset_t, vm_size_t) = 81 &arm64_aliasing_icache_sync_range; 82 83 static int 84 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 85 { 86 #ifdef SCTL_MASK32 87 static const char machine32[] = "arm"; 88 #endif 89 int error; 90 91 #ifdef SCTL_MASK32 92 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 93 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 94 else 95 #endif 96 error = SYSCTL_OUT(req, machine, sizeof(machine)); 97 return (error); 98 } 99 100 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 101 CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 102 103 static char cpu_model[64]; 104 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 105 cpu_model, sizeof(cpu_model), "Machine model"); 106 107 #define MAX_CACHES 8 /* Maximum number of caches supported 108 architecturally. */ 109 /* 110 * Per-CPU affinity as provided in MPIDR_EL1 111 * Indexed by CPU number in logical order selected by the system. 112 * Relevant fields can be extracted using CPU_AFFn macros, 113 * Aff3.Aff2.Aff1.Aff0 construct a unique CPU address in the system. 114 * 115 * Fields used by us: 116 * Aff1 - Cluster number 117 * Aff0 - CPU number in Aff1 cluster 118 */ 119 uint64_t __cpu_affinity[MAXCPU]; 120 static u_int cpu_aff_levels; 121 122 struct cpu_desc { 123 uint64_t mpidr; 124 uint64_t id_aa64afr0; 125 uint64_t id_aa64afr1; 126 uint64_t id_aa64dfr0; 127 uint64_t id_aa64dfr1; 128 uint64_t id_aa64isar0; 129 uint64_t id_aa64isar1; 130 uint64_t id_aa64isar2; 131 uint64_t id_aa64mmfr0; 132 uint64_t id_aa64mmfr1; 133 uint64_t id_aa64mmfr2; 134 uint64_t id_aa64pfr0; 135 uint64_t id_aa64pfr1; 136 uint64_t id_aa64zfr0; 137 uint64_t ctr; 138 #ifdef COMPAT_FREEBSD32 139 uint64_t id_isar5; 140 uint64_t mvfr0; 141 uint64_t mvfr1; 142 #endif 143 uint64_t clidr; 144 uint32_t ccsidr[MAX_CACHES][2]; /* 2 possible types. */ 145 bool have_sve; 146 }; 147 148 static struct cpu_desc cpu_desc[MAXCPU]; 149 static struct cpu_desc kern_cpu_desc; 150 static struct cpu_desc user_cpu_desc; 151 152 struct cpu_parts { 153 u_int part_id; 154 const char *part_name; 155 }; 156 #define CPU_PART_NONE { 0, NULL } 157 158 struct cpu_implementers { 159 u_int impl_id; 160 const char *impl_name; 161 /* 162 * Part number is implementation defined 163 * so each vendor will have its own set of values and names. 164 */ 165 const struct cpu_parts *cpu_parts; 166 }; 167 #define CPU_IMPLEMENTER_NONE { 0, NULL, NULL } 168 169 /* 170 * Per-implementer table of (PartNum, CPU Name) pairs. 171 */ 172 /* ARM Ltd. */ 173 static const struct cpu_parts cpu_parts_arm[] = { 174 { CPU_PART_AEM_V8, "AEMv8" }, 175 { CPU_PART_FOUNDATION, "Foundation-Model" }, 176 { CPU_PART_CORTEX_A34, "Cortex-A34" }, 177 { CPU_PART_CORTEX_A35, "Cortex-A35" }, 178 { CPU_PART_CORTEX_A53, "Cortex-A53" }, 179 { CPU_PART_CORTEX_A55, "Cortex-A55" }, 180 { CPU_PART_CORTEX_A57, "Cortex-A57" }, 181 { CPU_PART_CORTEX_A65, "Cortex-A65" }, 182 { CPU_PART_CORTEX_A72, "Cortex-A72" }, 183 { CPU_PART_CORTEX_A73, "Cortex-A73" }, 184 { CPU_PART_CORTEX_A75, "Cortex-A75" }, 185 { CPU_PART_CORTEX_A76, "Cortex-A76" }, 186 { CPU_PART_CORTEX_A76AE, "Cortex-A76AE" }, 187 { CPU_PART_CORTEX_A77, "Cortex-A77" }, 188 { CPU_PART_CORTEX_A78, "Cortex-A78" }, 189 { CPU_PART_CORTEX_A78C, "Cortex-A78C" }, 190 { CPU_PART_CORTEX_A510, "Cortex-A510" }, 191 { CPU_PART_CORTEX_A710, "Cortex-A710" }, 192 { CPU_PART_CORTEX_X1, "Cortex-X1" }, 193 { CPU_PART_CORTEX_X1C, "Cortex-X1C" }, 194 { CPU_PART_CORTEX_X2, "Cortex-X2" }, 195 { CPU_PART_NEOVERSE_E1, "Neoverse-E1" }, 196 { CPU_PART_NEOVERSE_N1, "Neoverse-N1" }, 197 { CPU_PART_NEOVERSE_N2, "Neoverse-N2" }, 198 { CPU_PART_NEOVERSE_V1, "Neoverse-V1" }, 199 CPU_PART_NONE, 200 }; 201 202 /* Cavium */ 203 static const struct cpu_parts cpu_parts_cavium[] = { 204 { CPU_PART_THUNDERX, "ThunderX" }, 205 { CPU_PART_THUNDERX2, "ThunderX2" }, 206 CPU_PART_NONE, 207 }; 208 209 /* APM / Ampere */ 210 static const struct cpu_parts cpu_parts_apm[] = { 211 { CPU_PART_EMAG8180, "eMAG 8180" }, 212 CPU_PART_NONE, 213 }; 214 215 /* Unknown */ 216 static const struct cpu_parts cpu_parts_none[] = { 217 CPU_PART_NONE, 218 }; 219 220 /* 221 * Implementers table. 222 */ 223 const struct cpu_implementers cpu_implementers[] = { 224 { CPU_IMPL_AMPERE, "Ampere", cpu_parts_none }, 225 { CPU_IMPL_APPLE, "Apple", cpu_parts_none }, 226 { CPU_IMPL_APM, "APM", cpu_parts_apm }, 227 { CPU_IMPL_ARM, "ARM", cpu_parts_arm }, 228 { CPU_IMPL_BROADCOM, "Broadcom", cpu_parts_none }, 229 { CPU_IMPL_CAVIUM, "Cavium", cpu_parts_cavium }, 230 { CPU_IMPL_DEC, "DEC", cpu_parts_none }, 231 { CPU_IMPL_FREESCALE, "Freescale", cpu_parts_none }, 232 { CPU_IMPL_FUJITSU, "Fujitsu", cpu_parts_none }, 233 { CPU_IMPL_INFINEON, "IFX", cpu_parts_none }, 234 { CPU_IMPL_INTEL, "Intel", cpu_parts_none }, 235 { CPU_IMPL_MARVELL, "Marvell", cpu_parts_none }, 236 { CPU_IMPL_NVIDIA, "NVIDIA", cpu_parts_none }, 237 { CPU_IMPL_QUALCOMM, "Qualcomm", cpu_parts_none }, 238 CPU_IMPLEMENTER_NONE, 239 }; 240 241 #define MRS_TYPE_MASK 0xf 242 #define MRS_INVALID 0 243 #define MRS_EXACT 1 244 #define MRS_EXACT_VAL(x) (MRS_EXACT | ((x) << 4)) 245 #define MRS_EXACT_FIELD(x) ((x) >> 4) 246 #define MRS_LOWER 2 247 248 struct mrs_field_value { 249 uint64_t value; 250 const char *desc; 251 }; 252 253 #define MRS_FIELD_VALUE(_value, _desc) \ 254 { \ 255 .value = (_value), \ 256 .desc = (_desc), \ 257 } 258 259 #define MRS_FIELD_VALUE_NONE_IMPL(_reg, _field, _none, _impl) \ 260 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _none, ""), \ 261 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _impl, #_field) 262 263 #define MRS_FIELD_VALUE_COUNT(_reg, _field, _desc) \ 264 MRS_FIELD_VALUE(0ul << _reg ## _ ## _field ## _SHIFT, "1 " _desc), \ 265 MRS_FIELD_VALUE(1ul << _reg ## _ ## _field ## _SHIFT, "2 " _desc "s"), \ 266 MRS_FIELD_VALUE(2ul << _reg ## _ ## _field ## _SHIFT, "3 " _desc "s"), \ 267 MRS_FIELD_VALUE(3ul << _reg ## _ ## _field ## _SHIFT, "4 " _desc "s"), \ 268 MRS_FIELD_VALUE(4ul << _reg ## _ ## _field ## _SHIFT, "5 " _desc "s"), \ 269 MRS_FIELD_VALUE(5ul << _reg ## _ ## _field ## _SHIFT, "6 " _desc "s"), \ 270 MRS_FIELD_VALUE(6ul << _reg ## _ ## _field ## _SHIFT, "7 " _desc "s"), \ 271 MRS_FIELD_VALUE(7ul << _reg ## _ ## _field ## _SHIFT, "8 " _desc "s"), \ 272 MRS_FIELD_VALUE(8ul << _reg ## _ ## _field ## _SHIFT, "9 " _desc "s"), \ 273 MRS_FIELD_VALUE(9ul << _reg ## _ ## _field ## _SHIFT, "10 "_desc "s"), \ 274 MRS_FIELD_VALUE(10ul<< _reg ## _ ## _field ## _SHIFT, "11 "_desc "s"), \ 275 MRS_FIELD_VALUE(11ul<< _reg ## _ ## _field ## _SHIFT, "12 "_desc "s"), \ 276 MRS_FIELD_VALUE(12ul<< _reg ## _ ## _field ## _SHIFT, "13 "_desc "s"), \ 277 MRS_FIELD_VALUE(13ul<< _reg ## _ ## _field ## _SHIFT, "14 "_desc "s"), \ 278 MRS_FIELD_VALUE(14ul<< _reg ## _ ## _field ## _SHIFT, "15 "_desc "s"), \ 279 MRS_FIELD_VALUE(15ul<< _reg ## _ ## _field ## _SHIFT, "16 "_desc "s") 280 281 #define MRS_FIELD_VALUE_END { .desc = NULL } 282 283 struct mrs_field_hwcap { 284 u_long *hwcap; 285 uint64_t min; 286 u_long hwcap_val; 287 }; 288 289 #define MRS_HWCAP(_hwcap, _val, _min) \ 290 { \ 291 .hwcap = (_hwcap), \ 292 .hwcap_val = (_val), \ 293 .min = (_min), \ 294 } 295 296 #define MRS_HWCAP_END { .hwcap = NULL } 297 298 struct mrs_field { 299 const char *name; 300 struct mrs_field_value *values; 301 struct mrs_field_hwcap *hwcaps; 302 uint64_t mask; 303 bool sign; 304 u_int type; 305 u_int shift; 306 }; 307 308 #define MRS_FIELD_HWCAP(_register, _name, _sign, _type, _values, _hwcap) \ 309 { \ 310 .name = #_name, \ 311 .sign = (_sign), \ 312 .type = (_type), \ 313 .shift = _register ## _ ## _name ## _SHIFT, \ 314 .mask = _register ## _ ## _name ## _MASK, \ 315 .values = (_values), \ 316 .hwcaps = (_hwcap), \ 317 } 318 319 #define MRS_FIELD(_register, _name, _sign, _type, _values) \ 320 MRS_FIELD_HWCAP(_register, _name, _sign, _type, _values, NULL) 321 322 #define MRS_FIELD_END { .type = MRS_INVALID, } 323 324 /* ID_AA64AFR0_EL1 */ 325 static struct mrs_field id_aa64afr0_fields[] = { 326 MRS_FIELD_END, 327 }; 328 329 330 /* ID_AA64AFR1_EL1 */ 331 static struct mrs_field id_aa64afr1_fields[] = { 332 MRS_FIELD_END, 333 }; 334 335 336 /* ID_AA64DFR0_EL1 */ 337 static struct mrs_field_value id_aa64dfr0_tracefilt[] = { 338 MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_NONE, ""), 339 MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_8_4, "Trace v8.4"), 340 MRS_FIELD_VALUE_END, 341 }; 342 343 static struct mrs_field_value id_aa64dfr0_doublelock[] = { 344 MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_IMPL, "DoubleLock"), 345 MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_NONE, ""), 346 MRS_FIELD_VALUE_END, 347 }; 348 349 static struct mrs_field_value id_aa64dfr0_pmsver[] = { 350 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_NONE, ""), 351 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE, "SPE"), 352 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_8_3, "SPE v8.3"), 353 MRS_FIELD_VALUE_END, 354 }; 355 356 static struct mrs_field_value id_aa64dfr0_ctx_cmps[] = { 357 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, CTX_CMPs, "CTX BKPT"), 358 MRS_FIELD_VALUE_END, 359 }; 360 361 static struct mrs_field_value id_aa64dfr0_wrps[] = { 362 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, WRPs, "Watchpoint"), 363 MRS_FIELD_VALUE_END, 364 }; 365 366 static struct mrs_field_value id_aa64dfr0_brps[] = { 367 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, BRPs, "Breakpoint"), 368 MRS_FIELD_VALUE_END, 369 }; 370 371 static struct mrs_field_value id_aa64dfr0_pmuver[] = { 372 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_NONE, ""), 373 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3, "PMUv3"), 374 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_1, "PMUv3 v8.1"), 375 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_4, "PMUv3 v8.4"), 376 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_5, "PMUv3 v8.5"), 377 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_IMPL, "IMPL PMU"), 378 MRS_FIELD_VALUE_END, 379 }; 380 381 static struct mrs_field_value id_aa64dfr0_tracever[] = { 382 MRS_FIELD_VALUE(ID_AA64DFR0_TraceVer_NONE, ""), 383 MRS_FIELD_VALUE(ID_AA64DFR0_TraceVer_IMPL, "Trace"), 384 MRS_FIELD_VALUE_END, 385 }; 386 387 static struct mrs_field_value id_aa64dfr0_debugver[] = { 388 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8, "Debugv8"), 389 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_VHE, "Debugv8_VHE"), 390 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_2, "Debugv8.2"), 391 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_4, "Debugv8.4"), 392 MRS_FIELD_VALUE_END, 393 }; 394 395 static struct mrs_field id_aa64dfr0_fields[] = { 396 MRS_FIELD(ID_AA64DFR0, TraceFilt, false, MRS_EXACT, 397 id_aa64dfr0_tracefilt), 398 MRS_FIELD(ID_AA64DFR0, DoubleLock, false, MRS_EXACT, 399 id_aa64dfr0_doublelock), 400 MRS_FIELD(ID_AA64DFR0, PMSVer, false, MRS_EXACT, id_aa64dfr0_pmsver), 401 MRS_FIELD(ID_AA64DFR0, CTX_CMPs, false, MRS_EXACT, 402 id_aa64dfr0_ctx_cmps), 403 MRS_FIELD(ID_AA64DFR0, WRPs, false, MRS_LOWER, id_aa64dfr0_wrps), 404 MRS_FIELD(ID_AA64DFR0, BRPs, false, MRS_LOWER, id_aa64dfr0_brps), 405 MRS_FIELD(ID_AA64DFR0, PMUVer, false, MRS_EXACT, id_aa64dfr0_pmuver), 406 MRS_FIELD(ID_AA64DFR0, TraceVer, false, MRS_EXACT, 407 id_aa64dfr0_tracever), 408 MRS_FIELD(ID_AA64DFR0, DebugVer, false, MRS_EXACT_VAL(0x6), 409 id_aa64dfr0_debugver), 410 MRS_FIELD_END, 411 }; 412 413 414 /* ID_AA64DFR1_EL1 */ 415 static struct mrs_field id_aa64dfr1_fields[] = { 416 MRS_FIELD_END, 417 }; 418 419 420 /* ID_AA64ISAR0_EL1 */ 421 static struct mrs_field_value id_aa64isar0_rndr[] = { 422 MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_NONE, ""), 423 MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_IMPL, "RNG"), 424 MRS_FIELD_VALUE_END, 425 }; 426 427 static struct mrs_field_hwcap id_aa64isar0_rndr_caps[] = { 428 MRS_HWCAP(&elf_hwcap2, HWCAP2_RNG, ID_AA64ISAR0_RNDR_IMPL), 429 MRS_HWCAP_END 430 }; 431 432 static struct mrs_field_value id_aa64isar0_tlb[] = { 433 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_NONE, ""), 434 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOS, "TLBI-OS"), 435 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOSR, "TLBI-OSR"), 436 MRS_FIELD_VALUE_END, 437 }; 438 439 static struct mrs_field_value id_aa64isar0_ts[] = { 440 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_NONE, ""), 441 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_4, "CondM-8.4"), 442 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_5, "CondM-8.5"), 443 MRS_FIELD_VALUE_END, 444 }; 445 446 static struct mrs_field_hwcap id_aa64isar0_ts_caps[] = { 447 MRS_HWCAP(&elf_hwcap, HWCAP_FLAGM, ID_AA64ISAR0_TS_CondM_8_4), 448 MRS_HWCAP(&elf_hwcap2, HWCAP2_FLAGM2, ID_AA64ISAR0_TS_CondM_8_5), 449 MRS_HWCAP_END 450 }; 451 452 static struct mrs_field_value id_aa64isar0_fhm[] = { 453 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, FHM, NONE, IMPL), 454 MRS_FIELD_VALUE_END, 455 }; 456 457 static struct mrs_field_hwcap id_aa64isar0_fhm_caps[] = { 458 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMDFHM, ID_AA64ISAR0_FHM_IMPL), 459 MRS_HWCAP_END 460 }; 461 462 static struct mrs_field_value id_aa64isar0_dp[] = { 463 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, DP, NONE, IMPL), 464 MRS_FIELD_VALUE_END, 465 }; 466 467 static struct mrs_field_hwcap id_aa64isar0_dp_caps[] = { 468 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMDDP, ID_AA64ISAR0_DP_IMPL), 469 MRS_HWCAP_END 470 }; 471 472 static struct mrs_field_value id_aa64isar0_sm4[] = { 473 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM4, NONE, IMPL), 474 MRS_FIELD_VALUE_END, 475 }; 476 477 static struct mrs_field_hwcap id_aa64isar0_sm4_caps[] = { 478 MRS_HWCAP(&elf_hwcap, HWCAP_SM4, ID_AA64ISAR0_SM4_IMPL), 479 MRS_HWCAP_END 480 }; 481 482 static struct mrs_field_value id_aa64isar0_sm3[] = { 483 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM3, NONE, IMPL), 484 MRS_FIELD_VALUE_END, 485 }; 486 487 static struct mrs_field_hwcap id_aa64isar0_sm3_caps[] = { 488 MRS_HWCAP(&elf_hwcap, HWCAP_SM3, ID_AA64ISAR0_SM3_IMPL), 489 MRS_HWCAP_END 490 }; 491 492 static struct mrs_field_value id_aa64isar0_sha3[] = { 493 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA3, NONE, IMPL), 494 MRS_FIELD_VALUE_END, 495 }; 496 497 static struct mrs_field_hwcap id_aa64isar0_sha3_caps[] = { 498 MRS_HWCAP(&elf_hwcap, HWCAP_SHA3, ID_AA64ISAR0_SHA3_IMPL), 499 MRS_HWCAP_END 500 }; 501 502 static struct mrs_field_value id_aa64isar0_rdm[] = { 503 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, RDM, NONE, IMPL), 504 MRS_FIELD_VALUE_END, 505 }; 506 507 static struct mrs_field_hwcap id_aa64isar0_rdm_caps[] = { 508 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMDRDM, ID_AA64ISAR0_RDM_IMPL), 509 MRS_HWCAP_END 510 }; 511 512 static struct mrs_field_value id_aa64isar0_atomic[] = { 513 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, Atomic, NONE, IMPL), 514 MRS_FIELD_VALUE_END, 515 }; 516 517 static struct mrs_field_hwcap id_aa64isar0_atomic_caps[] = { 518 MRS_HWCAP(&elf_hwcap, HWCAP_ATOMICS, ID_AA64ISAR0_Atomic_IMPL), 519 MRS_HWCAP_END 520 }; 521 522 static struct mrs_field_value id_aa64isar0_crc32[] = { 523 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, CRC32, NONE, BASE), 524 MRS_FIELD_VALUE_END, 525 }; 526 527 static struct mrs_field_hwcap id_aa64isar0_crc32_caps[] = { 528 MRS_HWCAP(&elf_hwcap, HWCAP_CRC32, ID_AA64ISAR0_CRC32_BASE), 529 MRS_HWCAP_END 530 }; 531 532 static struct mrs_field_value id_aa64isar0_sha2[] = { 533 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA2, NONE, BASE), 534 MRS_FIELD_VALUE(ID_AA64ISAR0_SHA2_512, "SHA2+SHA512"), 535 MRS_FIELD_VALUE_END, 536 }; 537 538 static struct mrs_field_hwcap id_aa64isar0_sha2_caps[] = { 539 MRS_HWCAP(&elf_hwcap, HWCAP_SHA2, ID_AA64ISAR0_SHA2_BASE), 540 MRS_HWCAP(&elf_hwcap, HWCAP_SHA512, ID_AA64ISAR0_SHA2_512), 541 MRS_HWCAP_END 542 }; 543 544 static struct mrs_field_value id_aa64isar0_sha1[] = { 545 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA1, NONE, BASE), 546 MRS_FIELD_VALUE_END, 547 }; 548 549 static struct mrs_field_hwcap id_aa64isar0_sha1_caps[] = { 550 MRS_HWCAP(&elf_hwcap, HWCAP_SHA1, ID_AA64ISAR0_SHA1_BASE), 551 MRS_HWCAP_END 552 }; 553 554 static struct mrs_field_value id_aa64isar0_aes[] = { 555 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, AES, NONE, BASE), 556 MRS_FIELD_VALUE(ID_AA64ISAR0_AES_PMULL, "AES+PMULL"), 557 MRS_FIELD_VALUE_END, 558 }; 559 560 static struct mrs_field_hwcap id_aa64isar0_aes_caps[] = { 561 MRS_HWCAP(&elf_hwcap, HWCAP_AES, ID_AA64ISAR0_AES_BASE), 562 MRS_HWCAP(&elf_hwcap, HWCAP_PMULL, ID_AA64ISAR0_AES_PMULL), 563 MRS_HWCAP_END 564 }; 565 566 static struct mrs_field id_aa64isar0_fields[] = { 567 MRS_FIELD_HWCAP(ID_AA64ISAR0, RNDR, false, MRS_LOWER, 568 id_aa64isar0_rndr, id_aa64isar0_rndr_caps), 569 MRS_FIELD(ID_AA64ISAR0, TLB, false, MRS_EXACT, id_aa64isar0_tlb), 570 MRS_FIELD_HWCAP(ID_AA64ISAR0, TS, false, MRS_LOWER, id_aa64isar0_ts, 571 id_aa64isar0_ts_caps), 572 MRS_FIELD_HWCAP(ID_AA64ISAR0, FHM, false, MRS_LOWER, id_aa64isar0_fhm, 573 id_aa64isar0_fhm_caps), 574 MRS_FIELD_HWCAP(ID_AA64ISAR0, DP, false, MRS_LOWER, id_aa64isar0_dp, 575 id_aa64isar0_dp_caps), 576 MRS_FIELD_HWCAP(ID_AA64ISAR0, SM4, false, MRS_LOWER, id_aa64isar0_sm4, 577 id_aa64isar0_sm4_caps), 578 MRS_FIELD_HWCAP(ID_AA64ISAR0, SM3, false, MRS_LOWER, id_aa64isar0_sm3, 579 id_aa64isar0_sm3_caps), 580 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA3, false, MRS_LOWER, id_aa64isar0_sha3, 581 id_aa64isar0_sha3_caps), 582 MRS_FIELD_HWCAP(ID_AA64ISAR0, RDM, false, MRS_LOWER, id_aa64isar0_rdm, 583 id_aa64isar0_rdm_caps), 584 MRS_FIELD_HWCAP(ID_AA64ISAR0, Atomic, false, MRS_LOWER, 585 id_aa64isar0_atomic, id_aa64isar0_atomic_caps), 586 MRS_FIELD_HWCAP(ID_AA64ISAR0, CRC32, false, MRS_LOWER, 587 id_aa64isar0_crc32, id_aa64isar0_crc32_caps), 588 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA2, false, MRS_LOWER, id_aa64isar0_sha2, 589 id_aa64isar0_sha2_caps), 590 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA1, false, MRS_LOWER, 591 id_aa64isar0_sha1, id_aa64isar0_sha1_caps), 592 MRS_FIELD_HWCAP(ID_AA64ISAR0, AES, false, MRS_LOWER, id_aa64isar0_aes, 593 id_aa64isar0_aes_caps), 594 MRS_FIELD_END, 595 }; 596 597 598 /* ID_AA64ISAR1_EL1 */ 599 static struct mrs_field_value id_aa64isar1_i8mm[] = { 600 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, I8MM, NONE, IMPL), 601 MRS_FIELD_VALUE_END, 602 }; 603 604 static struct mrs_field_hwcap id_aa64isar1_i8mm_caps[] = { 605 MRS_HWCAP(&elf_hwcap2, HWCAP2_I8MM, ID_AA64ISAR1_I8MM_IMPL), 606 MRS_HWCAP_END 607 }; 608 609 static struct mrs_field_value id_aa64isar1_dgh[] = { 610 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, DGH, NONE, IMPL), 611 MRS_FIELD_VALUE_END, 612 }; 613 614 static struct mrs_field_hwcap id_aa64isar1_dgh_caps[] = { 615 MRS_HWCAP(&elf_hwcap2, HWCAP2_DGH, ID_AA64ISAR1_DGH_IMPL), 616 MRS_HWCAP_END 617 }; 618 619 static struct mrs_field_value id_aa64isar1_bf16[] = { 620 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, BF16, NONE, IMPL), 621 MRS_FIELD_VALUE_END, 622 }; 623 624 static struct mrs_field_hwcap id_aa64isar1_bf16_caps[] = { 625 MRS_HWCAP(&elf_hwcap2, HWCAP2_BF16, ID_AA64ISAR1_BF16_IMPL), 626 MRS_HWCAP_END 627 }; 628 629 static struct mrs_field_value id_aa64isar1_specres[] = { 630 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_NONE, ""), 631 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_IMPL, "PredInv"), 632 MRS_FIELD_VALUE_END, 633 }; 634 635 static struct mrs_field_value id_aa64isar1_sb[] = { 636 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, SB, NONE, IMPL), 637 MRS_FIELD_VALUE_END, 638 }; 639 640 static struct mrs_field_hwcap id_aa64isar1_sb_caps[] = { 641 MRS_HWCAP(&elf_hwcap, HWCAP_SB, ID_AA64ISAR1_SB_IMPL), 642 MRS_HWCAP_END 643 }; 644 645 static struct mrs_field_value id_aa64isar1_frintts[] = { 646 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FRINTTS, NONE, IMPL), 647 MRS_FIELD_VALUE_END, 648 }; 649 650 static struct mrs_field_hwcap id_aa64isar1_frintts_caps[] = { 651 MRS_HWCAP(&elf_hwcap2, HWCAP2_FRINT, ID_AA64ISAR1_FRINTTS_IMPL), 652 MRS_HWCAP_END 653 }; 654 655 static struct mrs_field_value id_aa64isar1_gpi[] = { 656 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPI, NONE, IMPL), 657 MRS_FIELD_VALUE_END, 658 }; 659 660 static struct mrs_field_hwcap id_aa64isar1_gpi_caps[] = { 661 MRS_HWCAP(&elf_hwcap, HWCAP_PACG, ID_AA64ISAR1_GPI_IMPL), 662 MRS_HWCAP_END 663 }; 664 665 static struct mrs_field_value id_aa64isar1_gpa[] = { 666 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPA, NONE, IMPL), 667 MRS_FIELD_VALUE_END, 668 }; 669 670 static struct mrs_field_hwcap id_aa64isar1_gpa_caps[] = { 671 MRS_HWCAP(&elf_hwcap, HWCAP_PACG, ID_AA64ISAR1_GPA_IMPL), 672 MRS_HWCAP_END 673 }; 674 675 static struct mrs_field_value id_aa64isar1_lrcpc[] = { 676 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_NONE, ""), 677 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_3, "RCPC-8.3"), 678 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_4, "RCPC-8.4"), 679 MRS_FIELD_VALUE_END, 680 }; 681 682 static struct mrs_field_hwcap id_aa64isar1_lrcpc_caps[] = { 683 MRS_HWCAP(&elf_hwcap, HWCAP_LRCPC, ID_AA64ISAR1_LRCPC_RCPC_8_3), 684 MRS_HWCAP(&elf_hwcap, HWCAP_ILRCPC, ID_AA64ISAR1_LRCPC_RCPC_8_4), 685 MRS_HWCAP_END 686 }; 687 688 static struct mrs_field_value id_aa64isar1_fcma[] = { 689 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FCMA, NONE, IMPL), 690 MRS_FIELD_VALUE_END, 691 }; 692 693 static struct mrs_field_hwcap id_aa64isar1_fcma_caps[] = { 694 MRS_HWCAP(&elf_hwcap, HWCAP_FCMA, ID_AA64ISAR1_FCMA_IMPL), 695 MRS_HWCAP_END 696 }; 697 698 static struct mrs_field_value id_aa64isar1_jscvt[] = { 699 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, JSCVT, NONE, IMPL), 700 MRS_FIELD_VALUE_END, 701 }; 702 703 static struct mrs_field_hwcap id_aa64isar1_jscvt_caps[] = { 704 MRS_HWCAP(&elf_hwcap, HWCAP_JSCVT, ID_AA64ISAR1_JSCVT_IMPL), 705 MRS_HWCAP_END 706 }; 707 708 static struct mrs_field_value id_aa64isar1_api[] = { 709 MRS_FIELD_VALUE(ID_AA64ISAR1_API_NONE, ""), 710 MRS_FIELD_VALUE(ID_AA64ISAR1_API_PAC, "API PAC"), 711 MRS_FIELD_VALUE(ID_AA64ISAR1_API_EPAC, "API EPAC"), 712 MRS_FIELD_VALUE(ID_AA64ISAR1_API_EPAC2, "Impl PAuth+EPAC2"), 713 MRS_FIELD_VALUE(ID_AA64ISAR1_API_FPAC, "Impl PAuth+FPAC"), 714 MRS_FIELD_VALUE(ID_AA64ISAR1_API_FPAC_COMBINED, 715 "Impl PAuth+FPAC+Combined"), 716 MRS_FIELD_VALUE_END, 717 }; 718 719 static struct mrs_field_hwcap id_aa64isar1_api_caps[] = { 720 MRS_HWCAP(&elf_hwcap, HWCAP_PACA, ID_AA64ISAR1_API_PAC), 721 MRS_HWCAP_END 722 }; 723 724 static struct mrs_field_value id_aa64isar1_apa[] = { 725 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_NONE, ""), 726 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_PAC, "APA PAC"), 727 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC, "APA EPAC"), 728 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC2, "APA EPAC2"), 729 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC, "APA FPAC"), 730 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC_COMBINED, 731 "APA FPAC+Combined"), 732 MRS_FIELD_VALUE_END, 733 }; 734 735 static struct mrs_field_hwcap id_aa64isar1_apa_caps[] = { 736 MRS_HWCAP(&elf_hwcap, HWCAP_PACA, ID_AA64ISAR1_APA_PAC), 737 MRS_HWCAP_END 738 }; 739 740 static struct mrs_field_value id_aa64isar1_dpb[] = { 741 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_NONE, ""), 742 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVAP, "DCPoP"), 743 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVADP, "DCCVADP"), 744 MRS_FIELD_VALUE_END, 745 }; 746 747 static struct mrs_field_hwcap id_aa64isar1_dpb_caps[] = { 748 MRS_HWCAP(&elf_hwcap, HWCAP_DCPOP, ID_AA64ISAR1_DPB_DCCVAP), 749 MRS_HWCAP(&elf_hwcap2, HWCAP2_DCPODP, ID_AA64ISAR1_DPB_DCCVADP), 750 MRS_HWCAP_END 751 }; 752 753 static struct mrs_field id_aa64isar1_fields[] = { 754 MRS_FIELD_HWCAP(ID_AA64ISAR1, I8MM, false, MRS_LOWER, 755 id_aa64isar1_i8mm, id_aa64isar1_i8mm_caps), 756 MRS_FIELD_HWCAP(ID_AA64ISAR1, DGH, false, MRS_LOWER, id_aa64isar1_dgh, 757 id_aa64isar1_dgh_caps), 758 MRS_FIELD_HWCAP(ID_AA64ISAR1, BF16, false, MRS_LOWER, 759 id_aa64isar1_bf16, id_aa64isar1_bf16_caps), 760 MRS_FIELD(ID_AA64ISAR1, SPECRES, false, MRS_EXACT, 761 id_aa64isar1_specres), 762 MRS_FIELD_HWCAP(ID_AA64ISAR1, SB, false, MRS_LOWER, id_aa64isar1_sb, 763 id_aa64isar1_sb_caps), 764 MRS_FIELD_HWCAP(ID_AA64ISAR1, FRINTTS, false, MRS_LOWER, 765 id_aa64isar1_frintts, id_aa64isar1_frintts_caps), 766 MRS_FIELD_HWCAP(ID_AA64ISAR1, GPI, false, MRS_EXACT, id_aa64isar1_gpi, 767 id_aa64isar1_gpi_caps), 768 MRS_FIELD_HWCAP(ID_AA64ISAR1, GPA, false, MRS_EXACT, id_aa64isar1_gpa, 769 id_aa64isar1_gpa_caps), 770 MRS_FIELD_HWCAP(ID_AA64ISAR1, LRCPC, false, MRS_LOWER, 771 id_aa64isar1_lrcpc, id_aa64isar1_lrcpc_caps), 772 MRS_FIELD_HWCAP(ID_AA64ISAR1, FCMA, false, MRS_LOWER, 773 id_aa64isar1_fcma, id_aa64isar1_fcma_caps), 774 MRS_FIELD_HWCAP(ID_AA64ISAR1, JSCVT, false, MRS_LOWER, 775 id_aa64isar1_jscvt, id_aa64isar1_jscvt_caps), 776 MRS_FIELD_HWCAP(ID_AA64ISAR1, API, false, MRS_EXACT, id_aa64isar1_api, 777 id_aa64isar1_api_caps), 778 MRS_FIELD_HWCAP(ID_AA64ISAR1, APA, false, MRS_EXACT, id_aa64isar1_apa, 779 id_aa64isar1_apa_caps), 780 MRS_FIELD_HWCAP(ID_AA64ISAR1, DPB, false, MRS_LOWER, id_aa64isar1_dpb, 781 id_aa64isar1_dpb_caps), 782 MRS_FIELD_END, 783 }; 784 785 786 /* ID_AA64ISAR2_EL1 */ 787 static struct mrs_field_value id_aa64isar2_pac_frac[] = { 788 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, PAC_frac, NONE, IMPL), 789 MRS_FIELD_VALUE_END, 790 }; 791 792 static struct mrs_field_value id_aa64isar2_bc[] = { 793 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, BC, NONE, IMPL), 794 MRS_FIELD_VALUE_END, 795 }; 796 797 static struct mrs_field_value id_aa64isar2_mops[] = { 798 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, MOPS, NONE, IMPL), 799 MRS_FIELD_VALUE_END, 800 }; 801 802 static struct mrs_field_value id_aa64isar2_apa3[] = { 803 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_NONE, ""), 804 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_PAC, "APA3 PAC"), 805 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC, "APA3 EPAC"), 806 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC2, "APA3 EPAC2"), 807 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC, "APA3 FPAC"), 808 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC_COMBINED, 809 "APA3 FPAC+Combined"), 810 MRS_FIELD_VALUE_END, 811 }; 812 813 static struct mrs_field_hwcap id_aa64isar2_apa3_caps[] = { 814 MRS_HWCAP(&elf_hwcap, HWCAP_PACA, ID_AA64ISAR2_APA3_PAC), 815 MRS_HWCAP_END 816 }; 817 818 static struct mrs_field_value id_aa64isar2_gpa3[] = { 819 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, GPA3, NONE, IMPL), 820 MRS_FIELD_VALUE_END, 821 }; 822 823 static struct mrs_field_hwcap id_aa64isar2_gpa3_caps[] = { 824 MRS_HWCAP(&elf_hwcap, HWCAP_PACG, ID_AA64ISAR2_GPA3_IMPL), 825 MRS_HWCAP_END 826 }; 827 828 static struct mrs_field_value id_aa64isar2_rpres[] = { 829 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, RPRES, NONE, IMPL), 830 MRS_FIELD_VALUE_END, 831 }; 832 833 static struct mrs_field_value id_aa64isar2_wfxt[] = { 834 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, WFxT, NONE, IMPL), 835 MRS_FIELD_VALUE_END, 836 }; 837 838 static struct mrs_field id_aa64isar2_fields[] = { 839 MRS_FIELD(ID_AA64ISAR2, PAC_frac, false, MRS_EXACT, 840 id_aa64isar2_pac_frac), 841 MRS_FIELD(ID_AA64ISAR2, BC, false, MRS_EXACT, id_aa64isar2_bc), 842 MRS_FIELD(ID_AA64ISAR2, MOPS, false, MRS_EXACT, id_aa64isar2_mops), 843 MRS_FIELD_HWCAP(ID_AA64ISAR2, APA3, false, MRS_EXACT, 844 id_aa64isar2_apa3, id_aa64isar2_apa3_caps), 845 MRS_FIELD_HWCAP(ID_AA64ISAR2, GPA3, false, MRS_EXACT, 846 id_aa64isar2_gpa3, id_aa64isar2_gpa3_caps), 847 MRS_FIELD(ID_AA64ISAR2, RPRES, false, MRS_EXACT, id_aa64isar2_rpres), 848 MRS_FIELD(ID_AA64ISAR2, WFxT, false, MRS_EXACT, id_aa64isar2_wfxt), 849 MRS_FIELD_END, 850 }; 851 852 853 /* ID_AA64MMFR0_EL1 */ 854 static struct mrs_field_value id_aa64mmfr0_exs[] = { 855 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ExS, ALL, IMPL), 856 MRS_FIELD_VALUE_END, 857 }; 858 859 static struct mrs_field_value id_aa64mmfr0_tgran4_2[] = { 860 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_TGran4, ""), 861 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_NONE, "No S2 TGran4"), 862 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_IMPL, "S2 TGran4"), 863 MRS_FIELD_VALUE_END, 864 }; 865 866 static struct mrs_field_value id_aa64mmfr0_tgran64_2[] = { 867 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_TGran64, ""), 868 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_NONE, "No S2 TGran64"), 869 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_IMPL, "S2 TGran64"), 870 MRS_FIELD_VALUE_END, 871 }; 872 873 static struct mrs_field_value id_aa64mmfr0_tgran16_2[] = { 874 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_TGran16, ""), 875 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_NONE, "No S2 TGran16"), 876 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_IMPL, "S2 TGran16"), 877 MRS_FIELD_VALUE_END, 878 }; 879 880 static struct mrs_field_value id_aa64mmfr0_tgran4[] = { 881 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4,NONE, IMPL), 882 MRS_FIELD_VALUE_END, 883 }; 884 885 static struct mrs_field_value id_aa64mmfr0_tgran64[] = { 886 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran64, NONE, IMPL), 887 MRS_FIELD_VALUE_END, 888 }; 889 890 static struct mrs_field_value id_aa64mmfr0_tgran16[] = { 891 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran16, NONE, IMPL), 892 MRS_FIELD_VALUE_END, 893 }; 894 895 static struct mrs_field_value id_aa64mmfr0_bigendel0[] = { 896 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, BigEndEL0, FIXED, MIXED), 897 MRS_FIELD_VALUE_END, 898 }; 899 900 static struct mrs_field_value id_aa64mmfr0_snsmem[] = { 901 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, SNSMem, NONE, DISTINCT), 902 MRS_FIELD_VALUE_END, 903 }; 904 905 static struct mrs_field_value id_aa64mmfr0_bigend[] = { 906 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, BigEnd, FIXED, MIXED), 907 MRS_FIELD_VALUE_END, 908 }; 909 910 static struct mrs_field_value id_aa64mmfr0_asidbits[] = { 911 MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_8, "8bit ASID"), 912 MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_16, "16bit ASID"), 913 MRS_FIELD_VALUE_END, 914 }; 915 916 static struct mrs_field_value id_aa64mmfr0_parange[] = { 917 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4G, "4GB PA"), 918 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_64G, "64GB PA"), 919 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_1T, "1TB PA"), 920 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4T, "4TB PA"), 921 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_16T, "16TB PA"), 922 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_256T, "256TB PA"), 923 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4P, "4PB PA"), 924 MRS_FIELD_VALUE_END, 925 }; 926 927 static struct mrs_field id_aa64mmfr0_fields[] = { 928 MRS_FIELD(ID_AA64MMFR0, ExS, false, MRS_EXACT, id_aa64mmfr0_exs), 929 MRS_FIELD(ID_AA64MMFR0, TGran4_2, false, MRS_EXACT, 930 id_aa64mmfr0_tgran4_2), 931 MRS_FIELD(ID_AA64MMFR0, TGran64_2, false, MRS_EXACT, 932 id_aa64mmfr0_tgran64_2), 933 MRS_FIELD(ID_AA64MMFR0, TGran16_2, false, MRS_EXACT, 934 id_aa64mmfr0_tgran16_2), 935 MRS_FIELD(ID_AA64MMFR0, TGran4, false, MRS_EXACT, id_aa64mmfr0_tgran4), 936 MRS_FIELD(ID_AA64MMFR0, TGran64, false, MRS_EXACT, 937 id_aa64mmfr0_tgran64), 938 MRS_FIELD(ID_AA64MMFR0, TGran16, false, MRS_EXACT, 939 id_aa64mmfr0_tgran16), 940 MRS_FIELD(ID_AA64MMFR0, BigEndEL0, false, MRS_EXACT, 941 id_aa64mmfr0_bigendel0), 942 MRS_FIELD(ID_AA64MMFR0, SNSMem, false, MRS_EXACT, id_aa64mmfr0_snsmem), 943 MRS_FIELD(ID_AA64MMFR0, BigEnd, false, MRS_EXACT, id_aa64mmfr0_bigend), 944 MRS_FIELD(ID_AA64MMFR0, ASIDBits, false, MRS_EXACT, 945 id_aa64mmfr0_asidbits), 946 MRS_FIELD(ID_AA64MMFR0, PARange, false, MRS_EXACT, 947 id_aa64mmfr0_parange), 948 MRS_FIELD_END, 949 }; 950 951 952 /* ID_AA64MMFR1_EL1 */ 953 static struct mrs_field_value id_aa64mmfr1_xnx[] = { 954 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, XNX, NONE, IMPL), 955 MRS_FIELD_VALUE_END, 956 }; 957 958 static struct mrs_field_value id_aa64mmfr1_specsei[] = { 959 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, SpecSEI, NONE, IMPL), 960 MRS_FIELD_VALUE_END, 961 }; 962 963 static struct mrs_field_value id_aa64mmfr1_pan[] = { 964 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, PAN, NONE, IMPL), 965 MRS_FIELD_VALUE(ID_AA64MMFR1_PAN_ATS1E1, "PAN+ATS1E1"), 966 MRS_FIELD_VALUE_END, 967 }; 968 969 static struct mrs_field_value id_aa64mmfr1_lo[] = { 970 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, LO, NONE, IMPL), 971 MRS_FIELD_VALUE_END, 972 }; 973 974 static struct mrs_field_value id_aa64mmfr1_hpds[] = { 975 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_NONE, ""), 976 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_HPD, "HPD"), 977 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_TTPBHA, "HPD+TTPBHA"), 978 MRS_FIELD_VALUE_END, 979 }; 980 981 static struct mrs_field_value id_aa64mmfr1_vh[] = { 982 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, VH, NONE, IMPL), 983 MRS_FIELD_VALUE_END, 984 }; 985 986 static struct mrs_field_value id_aa64mmfr1_vmidbits[] = { 987 MRS_FIELD_VALUE(ID_AA64MMFR1_VMIDBits_8, "8bit VMID"), 988 MRS_FIELD_VALUE(ID_AA64MMFR1_VMIDBits_16, "16bit VMID"), 989 MRS_FIELD_VALUE_END, 990 }; 991 992 static struct mrs_field_value id_aa64mmfr1_hafdbs[] = { 993 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_NONE, ""), 994 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_AF, "HAF"), 995 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_AF_DBS, "HAF+DS"), 996 MRS_FIELD_VALUE_END, 997 }; 998 999 static struct mrs_field id_aa64mmfr1_fields[] = { 1000 MRS_FIELD(ID_AA64MMFR1, XNX, false, MRS_EXACT, id_aa64mmfr1_xnx), 1001 MRS_FIELD(ID_AA64MMFR1, SpecSEI, false, MRS_EXACT, 1002 id_aa64mmfr1_specsei), 1003 MRS_FIELD(ID_AA64MMFR1, PAN, false, MRS_EXACT, id_aa64mmfr1_pan), 1004 MRS_FIELD(ID_AA64MMFR1, LO, false, MRS_EXACT, id_aa64mmfr1_lo), 1005 MRS_FIELD(ID_AA64MMFR1, HPDS, false, MRS_EXACT, id_aa64mmfr1_hpds), 1006 MRS_FIELD(ID_AA64MMFR1, VH, false, MRS_EXACT, id_aa64mmfr1_vh), 1007 MRS_FIELD(ID_AA64MMFR1, VMIDBits, false, MRS_EXACT, 1008 id_aa64mmfr1_vmidbits), 1009 MRS_FIELD(ID_AA64MMFR1, HAFDBS, false, MRS_EXACT, id_aa64mmfr1_hafdbs), 1010 MRS_FIELD_END, 1011 }; 1012 1013 1014 /* ID_AA64MMFR2_EL1 */ 1015 static struct mrs_field_value id_aa64mmfr2_e0pd[] = { 1016 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, E0PD, NONE, IMPL), 1017 MRS_FIELD_VALUE_END, 1018 }; 1019 1020 static struct mrs_field_value id_aa64mmfr2_evt[] = { 1021 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_NONE, ""), 1022 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_2, "EVT-8.2"), 1023 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_5, "EVT-8.5"), 1024 MRS_FIELD_VALUE_END, 1025 }; 1026 1027 static struct mrs_field_value id_aa64mmfr2_bbm[] = { 1028 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL0, ""), 1029 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL1, "BBM level 1"), 1030 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL2, "BBM level 2"), 1031 MRS_FIELD_VALUE_END, 1032 }; 1033 1034 static struct mrs_field_value id_aa64mmfr2_ttl[] = { 1035 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, TTL, NONE, IMPL), 1036 MRS_FIELD_VALUE_END, 1037 }; 1038 1039 static struct mrs_field_value id_aa64mmfr2_fwb[] = { 1040 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, FWB, NONE, IMPL), 1041 MRS_FIELD_VALUE_END, 1042 }; 1043 1044 static struct mrs_field_value id_aa64mmfr2_ids[] = { 1045 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, IDS, NONE, IMPL), 1046 MRS_FIELD_VALUE_END, 1047 }; 1048 1049 static struct mrs_field_value id_aa64mmfr2_at[] = { 1050 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, AT, NONE, IMPL), 1051 MRS_FIELD_VALUE_END, 1052 }; 1053 1054 static struct mrs_field_hwcap id_aa64mmfr2_at_caps[] = { 1055 MRS_HWCAP(&elf_hwcap, HWCAP_USCAT, ID_AA64MMFR2_AT_IMPL), 1056 MRS_HWCAP_END 1057 }; 1058 1059 static struct mrs_field_value id_aa64mmfr2_st[] = { 1060 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, ST, NONE, IMPL), 1061 MRS_FIELD_VALUE_END, 1062 }; 1063 1064 static struct mrs_field_value id_aa64mmfr2_nv[] = { 1065 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, NV, NONE, 8_3), 1066 MRS_FIELD_VALUE(ID_AA64MMFR2_NV_8_4, "NV v8.4"), 1067 MRS_FIELD_VALUE_END, 1068 }; 1069 1070 static struct mrs_field_value id_aa64mmfr2_ccidx[] = { 1071 MRS_FIELD_VALUE(ID_AA64MMFR2_CCIDX_32, "32bit CCIDX"), 1072 MRS_FIELD_VALUE(ID_AA64MMFR2_CCIDX_64, "64bit CCIDX"), 1073 MRS_FIELD_VALUE_END, 1074 }; 1075 1076 static struct mrs_field_value id_aa64mmfr2_varange[] = { 1077 MRS_FIELD_VALUE(ID_AA64MMFR2_VARange_48, "48bit VA"), 1078 MRS_FIELD_VALUE(ID_AA64MMFR2_VARange_52, "52bit VA"), 1079 MRS_FIELD_VALUE_END, 1080 }; 1081 1082 static struct mrs_field_value id_aa64mmfr2_iesb[] = { 1083 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, IESB, NONE, IMPL), 1084 MRS_FIELD_VALUE_END, 1085 }; 1086 1087 static struct mrs_field_value id_aa64mmfr2_lsm[] = { 1088 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, LSM, NONE, IMPL), 1089 MRS_FIELD_VALUE_END, 1090 }; 1091 1092 static struct mrs_field_value id_aa64mmfr2_uao[] = { 1093 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, UAO, NONE, IMPL), 1094 MRS_FIELD_VALUE_END, 1095 }; 1096 1097 static struct mrs_field_value id_aa64mmfr2_cnp[] = { 1098 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, CnP, NONE, IMPL), 1099 MRS_FIELD_VALUE_END, 1100 }; 1101 1102 static struct mrs_field id_aa64mmfr2_fields[] = { 1103 MRS_FIELD(ID_AA64MMFR2, E0PD, false, MRS_EXACT, id_aa64mmfr2_e0pd), 1104 MRS_FIELD(ID_AA64MMFR2, EVT, false, MRS_EXACT, id_aa64mmfr2_evt), 1105 MRS_FIELD(ID_AA64MMFR2, BBM, false, MRS_EXACT, id_aa64mmfr2_bbm), 1106 MRS_FIELD(ID_AA64MMFR2, TTL, false, MRS_EXACT, id_aa64mmfr2_ttl), 1107 MRS_FIELD(ID_AA64MMFR2, FWB, false, MRS_EXACT, id_aa64mmfr2_fwb), 1108 MRS_FIELD(ID_AA64MMFR2, IDS, false, MRS_EXACT, id_aa64mmfr2_ids), 1109 MRS_FIELD_HWCAP(ID_AA64MMFR2, AT, false, MRS_LOWER, id_aa64mmfr2_at, 1110 id_aa64mmfr2_at_caps), 1111 MRS_FIELD(ID_AA64MMFR2, ST, false, MRS_EXACT, id_aa64mmfr2_st), 1112 MRS_FIELD(ID_AA64MMFR2, NV, false, MRS_EXACT, id_aa64mmfr2_nv), 1113 MRS_FIELD(ID_AA64MMFR2, CCIDX, false, MRS_EXACT, id_aa64mmfr2_ccidx), 1114 MRS_FIELD(ID_AA64MMFR2, VARange, false, MRS_EXACT, 1115 id_aa64mmfr2_varange), 1116 MRS_FIELD(ID_AA64MMFR2, IESB, false, MRS_EXACT, id_aa64mmfr2_iesb), 1117 MRS_FIELD(ID_AA64MMFR2, LSM, false, MRS_EXACT, id_aa64mmfr2_lsm), 1118 MRS_FIELD(ID_AA64MMFR2, UAO, false, MRS_EXACT, id_aa64mmfr2_uao), 1119 MRS_FIELD(ID_AA64MMFR2, CnP, false, MRS_EXACT, id_aa64mmfr2_cnp), 1120 MRS_FIELD_END, 1121 }; 1122 1123 1124 /* ID_AA64PFR0_EL1 */ 1125 static struct mrs_field_value id_aa64pfr0_csv3[] = { 1126 MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""), 1127 MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_ISOLATED, "CSV3"), 1128 MRS_FIELD_VALUE_END, 1129 }; 1130 1131 static struct mrs_field_value id_aa64pfr0_csv2[] = { 1132 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_NONE, ""), 1133 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_ISOLATED, "CSV2"), 1134 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_SCXTNUM, "SCXTNUM"), 1135 MRS_FIELD_VALUE_END, 1136 }; 1137 1138 static struct mrs_field_value id_aa64pfr0_dit[] = { 1139 MRS_FIELD_VALUE(ID_AA64PFR0_DIT_NONE, ""), 1140 MRS_FIELD_VALUE(ID_AA64PFR0_DIT_PSTATE, "PSTATE.DIT"), 1141 MRS_FIELD_VALUE_END, 1142 }; 1143 1144 static struct mrs_field_hwcap id_aa64pfr0_dit_caps[] = { 1145 MRS_HWCAP(&elf_hwcap, HWCAP_DIT, ID_AA64PFR0_DIT_PSTATE), 1146 MRS_HWCAP_END 1147 }; 1148 1149 static struct mrs_field_value id_aa64pfr0_amu[] = { 1150 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_NONE, ""), 1151 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1, "AMUv1"), 1152 MRS_FIELD_VALUE_END, 1153 }; 1154 1155 static struct mrs_field_value id_aa64pfr0_mpam[] = { 1156 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, MPAM, NONE, IMPL), 1157 MRS_FIELD_VALUE_END, 1158 }; 1159 1160 static struct mrs_field_value id_aa64pfr0_sel2[] = { 1161 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SEL2, NONE, IMPL), 1162 MRS_FIELD_VALUE_END, 1163 }; 1164 1165 static struct mrs_field_value id_aa64pfr0_sve[] = { 1166 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SVE, NONE, IMPL), 1167 MRS_FIELD_VALUE_END, 1168 }; 1169 1170 #if 0 1171 /* Enable when we add SVE support */ 1172 static struct mrs_field_hwcap id_aa64pfr0_sve_caps[] = { 1173 MRS_HWCAP(&elf_hwcap, HWCAP_SVE, ID_AA64PFR0_SVE_IMPL), 1174 MRS_HWCAP_END 1175 }; 1176 #endif 1177 1178 static struct mrs_field_value id_aa64pfr0_ras[] = { 1179 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_NONE, ""), 1180 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_IMPL, "RAS"), 1181 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_8_4, "RAS v8.4"), 1182 MRS_FIELD_VALUE_END, 1183 }; 1184 1185 static struct mrs_field_value id_aa64pfr0_gic[] = { 1186 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, GIC, CPUIF_NONE, CPUIF_EN), 1187 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_NONE, ""), 1188 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_EN, "GIC"), 1189 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_4_1, "GIC 4.1"), 1190 MRS_FIELD_VALUE_END, 1191 }; 1192 1193 static struct mrs_field_value id_aa64pfr0_advsimd[] = { 1194 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, AdvSIMD, NONE, IMPL), 1195 MRS_FIELD_VALUE(ID_AA64PFR0_AdvSIMD_HP, "AdvSIMD+HP"), 1196 MRS_FIELD_VALUE_END, 1197 }; 1198 1199 static struct mrs_field_hwcap id_aa64pfr0_advsimd_caps[] = { 1200 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMD, ID_AA64PFR0_AdvSIMD_IMPL), 1201 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMDHP, ID_AA64PFR0_AdvSIMD_HP), 1202 MRS_HWCAP_END 1203 }; 1204 1205 static struct mrs_field_value id_aa64pfr0_fp[] = { 1206 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, FP, NONE, IMPL), 1207 MRS_FIELD_VALUE(ID_AA64PFR0_FP_HP, "FP+HP"), 1208 MRS_FIELD_VALUE_END, 1209 }; 1210 1211 static struct mrs_field_hwcap id_aa64pfr0_fp_caps[] = { 1212 MRS_HWCAP(&elf_hwcap, HWCAP_FP, ID_AA64PFR0_FP_IMPL), 1213 MRS_HWCAP(&elf_hwcap, HWCAP_FPHP, ID_AA64PFR0_FP_HP), 1214 MRS_HWCAP_END 1215 }; 1216 1217 static struct mrs_field_value id_aa64pfr0_el3[] = { 1218 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, EL3, NONE, 64), 1219 MRS_FIELD_VALUE(ID_AA64PFR0_EL3_64_32, "EL3 32"), 1220 MRS_FIELD_VALUE_END, 1221 }; 1222 1223 static struct mrs_field_value id_aa64pfr0_el2[] = { 1224 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, EL2, NONE, 64), 1225 MRS_FIELD_VALUE(ID_AA64PFR0_EL2_64_32, "EL2 32"), 1226 MRS_FIELD_VALUE_END, 1227 }; 1228 1229 static struct mrs_field_value id_aa64pfr0_el1[] = { 1230 MRS_FIELD_VALUE(ID_AA64PFR0_EL1_64, "EL1"), 1231 MRS_FIELD_VALUE(ID_AA64PFR0_EL1_64_32, "EL1 32"), 1232 MRS_FIELD_VALUE_END, 1233 }; 1234 1235 static struct mrs_field_value id_aa64pfr0_el0[] = { 1236 MRS_FIELD_VALUE(ID_AA64PFR0_EL0_64, "EL0"), 1237 MRS_FIELD_VALUE(ID_AA64PFR0_EL0_64_32, "EL0 32"), 1238 MRS_FIELD_VALUE_END, 1239 }; 1240 1241 static struct mrs_field id_aa64pfr0_fields[] = { 1242 MRS_FIELD(ID_AA64PFR0, CSV3, false, MRS_EXACT, id_aa64pfr0_csv3), 1243 MRS_FIELD(ID_AA64PFR0, CSV2, false, MRS_EXACT, id_aa64pfr0_csv2), 1244 MRS_FIELD_HWCAP(ID_AA64PFR0, DIT, false, MRS_LOWER, id_aa64pfr0_dit, 1245 id_aa64pfr0_dit_caps), 1246 MRS_FIELD(ID_AA64PFR0, AMU, false, MRS_EXACT, id_aa64pfr0_amu), 1247 MRS_FIELD(ID_AA64PFR0, MPAM, false, MRS_EXACT, id_aa64pfr0_mpam), 1248 MRS_FIELD(ID_AA64PFR0, SEL2, false, MRS_EXACT, id_aa64pfr0_sel2), 1249 MRS_FIELD(ID_AA64PFR0, SVE, false, MRS_EXACT, id_aa64pfr0_sve), 1250 MRS_FIELD(ID_AA64PFR0, RAS, false, MRS_EXACT, id_aa64pfr0_ras), 1251 MRS_FIELD(ID_AA64PFR0, GIC, false, MRS_EXACT, id_aa64pfr0_gic), 1252 MRS_FIELD_HWCAP(ID_AA64PFR0, AdvSIMD, true, MRS_LOWER, 1253 id_aa64pfr0_advsimd, id_aa64pfr0_advsimd_caps), 1254 MRS_FIELD_HWCAP(ID_AA64PFR0, FP, true, MRS_LOWER, id_aa64pfr0_fp, 1255 id_aa64pfr0_fp_caps), 1256 MRS_FIELD(ID_AA64PFR0, EL3, false, MRS_EXACT, id_aa64pfr0_el3), 1257 MRS_FIELD(ID_AA64PFR0, EL2, false, MRS_EXACT, id_aa64pfr0_el2), 1258 MRS_FIELD(ID_AA64PFR0, EL1, false, MRS_LOWER, id_aa64pfr0_el1), 1259 MRS_FIELD(ID_AA64PFR0, EL0, false, MRS_LOWER, id_aa64pfr0_el0), 1260 MRS_FIELD_END, 1261 }; 1262 1263 1264 /* ID_AA64PFR1_EL1 */ 1265 static struct mrs_field_value id_aa64pfr1_mte[] = { 1266 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_NONE, ""), 1267 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL_EL0, "MTE EL0"), 1268 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL, "MTE"), 1269 MRS_FIELD_VALUE_END, 1270 }; 1271 1272 static struct mrs_field_value id_aa64pfr1_ssbs[] = { 1273 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_NONE, ""), 1274 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE, "PSTATE.SSBS"), 1275 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE_MSR, "PSTATE.SSBS MSR"), 1276 MRS_FIELD_VALUE_END, 1277 }; 1278 1279 static struct mrs_field_hwcap id_aa64pfr1_ssbs_caps[] = { 1280 MRS_HWCAP(&elf_hwcap, HWCAP_SSBS, ID_AA64PFR1_SSBS_PSTATE), 1281 MRS_HWCAP_END 1282 }; 1283 1284 static struct mrs_field_value id_aa64pfr1_bt[] = { 1285 MRS_FIELD_VALUE(ID_AA64PFR1_BT_NONE, ""), 1286 MRS_FIELD_VALUE(ID_AA64PFR1_BT_IMPL, "BTI"), 1287 MRS_FIELD_VALUE_END, 1288 }; 1289 1290 #if 0 1291 /* Enable when we add BTI support */ 1292 static struct mrs_field_hwcap id_aa64pfr1_bt_caps[] = { 1293 MRS_HWCAP(&elf_hwcap2, HWCAP2_BTI, ID_AA64PFR1_BT_IMPL), 1294 MRS_HWCAP_END 1295 }; 1296 #endif 1297 1298 static struct mrs_field id_aa64pfr1_fields[] = { 1299 MRS_FIELD(ID_AA64PFR1, MTE, false, MRS_EXACT, id_aa64pfr1_mte), 1300 MRS_FIELD_HWCAP(ID_AA64PFR1, SSBS, false, MRS_LOWER, id_aa64pfr1_ssbs, 1301 id_aa64pfr1_ssbs_caps), 1302 MRS_FIELD(ID_AA64PFR1, BT, false, MRS_EXACT, id_aa64pfr1_bt), 1303 MRS_FIELD_END, 1304 }; 1305 1306 1307 /* ID_AA64ZFR0_EL1 */ 1308 static struct mrs_field_value id_aa64zfr0_f64mm[] = { 1309 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, F64MM, NONE, IMPL), 1310 MRS_FIELD_VALUE_END, 1311 }; 1312 1313 static struct mrs_field_value id_aa64zfr0_f32mm[] = { 1314 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, F32MM, NONE, IMPL), 1315 MRS_FIELD_VALUE_END, 1316 }; 1317 1318 static struct mrs_field_value id_aa64zfr0_i8mm[] = { 1319 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, I8MM, NONE, IMPL), 1320 MRS_FIELD_VALUE_END, 1321 }; 1322 1323 static struct mrs_field_value id_aa64zfr0_sm4[] = { 1324 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, SM4, NONE, IMPL), 1325 MRS_FIELD_VALUE_END, 1326 }; 1327 1328 static struct mrs_field_value id_aa64zfr0_sha3[] = { 1329 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, SHA3, NONE, IMPL), 1330 MRS_FIELD_VALUE_END, 1331 }; 1332 1333 static struct mrs_field_value id_aa64zfr0_bf16[] = { 1334 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, BF16, NONE, BASE), 1335 MRS_FIELD_VALUE(ID_AA64ZFR0_BF16_EBF, "BF16+EBF"), 1336 MRS_FIELD_VALUE_END, 1337 }; 1338 1339 static struct mrs_field_value id_aa64zfr0_bitperm[] = { 1340 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, BitPerm, NONE, IMPL), 1341 MRS_FIELD_VALUE_END, 1342 }; 1343 1344 static struct mrs_field_value id_aa64zfr0_aes[] = { 1345 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, AES, NONE, BASE), 1346 MRS_FIELD_VALUE(ID_AA64ZFR0_AES_PMULL, "AES+PMULL"), 1347 MRS_FIELD_VALUE_END, 1348 }; 1349 1350 static struct mrs_field_value id_aa64zfr0_svever[] = { 1351 MRS_FIELD_VALUE(ID_AA64ZFR0_SVEver_SVE1, "SVE1"), 1352 MRS_FIELD_VALUE(ID_AA64ZFR0_SVEver_SVE2, "SVE2"), 1353 MRS_FIELD_VALUE_END, 1354 }; 1355 1356 static struct mrs_field id_aa64zfr0_fields[] = { 1357 MRS_FIELD(ID_AA64ZFR0, F64MM, false, MRS_EXACT, id_aa64zfr0_f64mm), 1358 MRS_FIELD(ID_AA64ZFR0, F32MM, false, MRS_EXACT, id_aa64zfr0_f32mm), 1359 MRS_FIELD(ID_AA64ZFR0, I8MM, false, MRS_EXACT, id_aa64zfr0_i8mm), 1360 MRS_FIELD(ID_AA64ZFR0, SM4, false, MRS_EXACT, id_aa64zfr0_sm4), 1361 MRS_FIELD(ID_AA64ZFR0, SHA3, false, MRS_EXACT, id_aa64zfr0_sha3), 1362 MRS_FIELD(ID_AA64ZFR0, BF16, false, MRS_EXACT, id_aa64zfr0_bf16), 1363 MRS_FIELD(ID_AA64ZFR0, BitPerm, false, MRS_EXACT, id_aa64zfr0_bitperm), 1364 MRS_FIELD(ID_AA64ZFR0, AES, false, MRS_EXACT, id_aa64zfr0_aes), 1365 MRS_FIELD(ID_AA64ZFR0, SVEver, false, MRS_EXACT, id_aa64zfr0_svever), 1366 MRS_FIELD_END, 1367 }; 1368 1369 1370 #ifdef COMPAT_FREEBSD32 1371 /* ID_ISAR5_EL1 */ 1372 static struct mrs_field_value id_isar5_vcma[] = { 1373 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, VCMA, NONE, IMPL), 1374 MRS_FIELD_VALUE_END, 1375 }; 1376 1377 static struct mrs_field_value id_isar5_rdm[] = { 1378 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, RDM, NONE, IMPL), 1379 MRS_FIELD_VALUE_END, 1380 }; 1381 1382 static struct mrs_field_value id_isar5_crc32[] = { 1383 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, CRC32, NONE, IMPL), 1384 MRS_FIELD_VALUE_END, 1385 }; 1386 1387 static struct mrs_field_hwcap id_isar5_crc32_caps[] = { 1388 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_CRC32, ID_ISAR5_CRC32_IMPL), 1389 MRS_HWCAP_END 1390 }; 1391 1392 static struct mrs_field_value id_isar5_sha2[] = { 1393 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA2, NONE, IMPL), 1394 MRS_FIELD_VALUE_END, 1395 }; 1396 1397 static struct mrs_field_hwcap id_isar5_sha2_caps[] = { 1398 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_SHA2, ID_ISAR5_SHA2_IMPL), 1399 MRS_HWCAP_END 1400 }; 1401 1402 static struct mrs_field_value id_isar5_sha1[] = { 1403 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA1, NONE, IMPL), 1404 MRS_FIELD_VALUE_END, 1405 }; 1406 1407 static struct mrs_field_hwcap id_isar5_sha1_caps[] = { 1408 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_SHA1, ID_ISAR5_SHA1_IMPL), 1409 MRS_HWCAP_END 1410 }; 1411 1412 static struct mrs_field_value id_isar5_aes[] = { 1413 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, AES, NONE, BASE), 1414 MRS_FIELD_VALUE(ID_ISAR5_AES_VMULL, "AES+VMULL"), 1415 MRS_FIELD_VALUE_END, 1416 }; 1417 1418 static struct mrs_field_hwcap id_isar5_aes_caps[] = { 1419 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_AES, ID_ISAR5_AES_BASE), 1420 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_PMULL, ID_ISAR5_AES_VMULL), 1421 MRS_HWCAP_END 1422 }; 1423 1424 static struct mrs_field_value id_isar5_sevl[] = { 1425 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SEVL, NOP, IMPL), 1426 MRS_FIELD_VALUE_END, 1427 }; 1428 1429 static struct mrs_field id_isar5_fields[] = { 1430 MRS_FIELD(ID_ISAR5, VCMA, false, MRS_LOWER, id_isar5_vcma), 1431 MRS_FIELD(ID_ISAR5, RDM, false, MRS_LOWER, id_isar5_rdm), 1432 MRS_FIELD_HWCAP(ID_ISAR5, CRC32, false, MRS_LOWER, id_isar5_crc32, 1433 id_isar5_crc32_caps), 1434 MRS_FIELD_HWCAP(ID_ISAR5, SHA2, false, MRS_LOWER, id_isar5_sha2, 1435 id_isar5_sha2_caps), 1436 MRS_FIELD_HWCAP(ID_ISAR5, SHA1, false, MRS_LOWER, id_isar5_sha1, 1437 id_isar5_sha1_caps), 1438 MRS_FIELD_HWCAP(ID_ISAR5, AES, false, MRS_LOWER, id_isar5_aes, 1439 id_isar5_aes_caps), 1440 MRS_FIELD(ID_ISAR5, SEVL, false, MRS_LOWER, id_isar5_sevl), 1441 MRS_FIELD_END, 1442 }; 1443 1444 /* MVFR0 */ 1445 static struct mrs_field_value mvfr0_fpround[] = { 1446 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPRound, NONE, IMPL), 1447 MRS_FIELD_VALUE_END, 1448 }; 1449 1450 static struct mrs_field_value mvfr0_fpsqrt[] = { 1451 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPSqrt, NONE, IMPL), 1452 MRS_FIELD_VALUE_END, 1453 }; 1454 1455 static struct mrs_field_value mvfr0_fpdivide[] = { 1456 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPDivide, NONE, IMPL), 1457 MRS_FIELD_VALUE_END, 1458 }; 1459 1460 static struct mrs_field_value mvfr0_fptrap[] = { 1461 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPTrap, NONE, IMPL), 1462 MRS_FIELD_VALUE_END, 1463 }; 1464 1465 static struct mrs_field_value mvfr0_fpdp[] = { 1466 MRS_FIELD_VALUE(MVFR0_FPDP_NONE, ""), 1467 MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v2, "DP VFPv2"), 1468 MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v3_v4, "DP VFPv3+v4"), 1469 MRS_FIELD_VALUE_END, 1470 }; 1471 1472 static struct mrs_field_hwcap mvfr0_fpdp_caps[] = { 1473 MRS_HWCAP(&elf32_hwcap, HWCAP32_VFP, MVFR0_FPDP_VFP_v2), 1474 MRS_HWCAP(&elf32_hwcap, HWCAP32_VFPv3, MVFR0_FPDP_VFP_v3_v4), 1475 }; 1476 1477 static struct mrs_field_value mvfr0_fpsp[] = { 1478 MRS_FIELD_VALUE(MVFR0_FPSP_NONE, ""), 1479 MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v2, "SP VFPv2"), 1480 MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v3_v4, "SP VFPv3+v4"), 1481 MRS_FIELD_VALUE_END, 1482 }; 1483 1484 static struct mrs_field_value mvfr0_simdreg[] = { 1485 MRS_FIELD_VALUE(MVFR0_SIMDReg_NONE, ""), 1486 MRS_FIELD_VALUE(MVFR0_SIMDReg_FP, "FP 16x64"), 1487 MRS_FIELD_VALUE(MVFR0_SIMDReg_AdvSIMD, "AdvSIMD"), 1488 MRS_FIELD_VALUE_END, 1489 }; 1490 1491 static struct mrs_field mvfr0_fields[] = { 1492 MRS_FIELD(MVFR0, FPRound, false, MRS_LOWER, mvfr0_fpround), 1493 MRS_FIELD(MVFR0, FPSqrt, false, MRS_LOWER, mvfr0_fpsqrt), 1494 MRS_FIELD(MVFR0, FPDivide, false, MRS_LOWER, mvfr0_fpdivide), 1495 MRS_FIELD(MVFR0, FPTrap, false, MRS_LOWER, mvfr0_fptrap), 1496 MRS_FIELD_HWCAP(MVFR0, FPDP, false, MRS_LOWER, mvfr0_fpdp, 1497 mvfr0_fpdp_caps), 1498 MRS_FIELD(MVFR0, FPSP, false, MRS_LOWER, mvfr0_fpsp), 1499 MRS_FIELD(MVFR0, SIMDReg, false, MRS_LOWER, mvfr0_simdreg), 1500 MRS_FIELD_END, 1501 }; 1502 1503 /* MVFR1 */ 1504 static struct mrs_field_value mvfr1_simdfmac[] = { 1505 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDFMAC, NONE, IMPL), 1506 MRS_FIELD_VALUE_END, 1507 }; 1508 1509 static struct mrs_field_hwcap mvfr1_simdfmac_caps[] = { 1510 MRS_HWCAP(&elf32_hwcap, HWCAP32_VFPv4, MVFR1_SIMDFMAC_IMPL), 1511 MRS_HWCAP_END 1512 }; 1513 1514 static struct mrs_field_value mvfr1_fphp[] = { 1515 MRS_FIELD_VALUE(MVFR1_FPHP_NONE, ""), 1516 MRS_FIELD_VALUE(MVFR1_FPHP_CONV_SP, "FPHP SP Conv"), 1517 MRS_FIELD_VALUE(MVFR1_FPHP_CONV_DP, "FPHP DP Conv"), 1518 MRS_FIELD_VALUE(MVFR1_FPHP_ARITH, "FPHP Arith"), 1519 MRS_FIELD_VALUE_END, 1520 }; 1521 1522 static struct mrs_field_value mvfr1_simdhp[] = { 1523 MRS_FIELD_VALUE(MVFR1_SIMDHP_NONE, ""), 1524 MRS_FIELD_VALUE(MVFR1_SIMDHP_CONV_SP, "SIMDHP SP Conv"), 1525 MRS_FIELD_VALUE(MVFR1_SIMDHP_ARITH, "SIMDHP Arith"), 1526 MRS_FIELD_VALUE_END, 1527 }; 1528 1529 static struct mrs_field_value mvfr1_simdsp[] = { 1530 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDSP, NONE, IMPL), 1531 MRS_FIELD_VALUE_END, 1532 }; 1533 1534 static struct mrs_field_value mvfr1_simdint[] = { 1535 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDInt, NONE, IMPL), 1536 MRS_FIELD_VALUE_END, 1537 }; 1538 1539 static struct mrs_field_value mvfr1_simdls[] = { 1540 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDLS, NONE, IMPL), 1541 MRS_FIELD_VALUE_END, 1542 }; 1543 1544 static struct mrs_field_hwcap mvfr1_simdls_caps[] = { 1545 MRS_HWCAP(&elf32_hwcap, HWCAP32_VFPv4, MVFR1_SIMDFMAC_IMPL), 1546 MRS_HWCAP_END 1547 }; 1548 1549 static struct mrs_field_value mvfr1_fpdnan[] = { 1550 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPDNaN, NONE, IMPL), 1551 MRS_FIELD_VALUE_END, 1552 }; 1553 1554 static struct mrs_field_value mvfr1_fpftz[] = { 1555 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPFtZ, NONE, IMPL), 1556 MRS_FIELD_VALUE_END, 1557 }; 1558 1559 static struct mrs_field mvfr1_fields[] = { 1560 MRS_FIELD_HWCAP(MVFR1, SIMDFMAC, false, MRS_LOWER, mvfr1_simdfmac, 1561 mvfr1_simdfmac_caps), 1562 MRS_FIELD(MVFR1, FPHP, false, MRS_LOWER, mvfr1_fphp), 1563 MRS_FIELD(MVFR1, SIMDHP, false, MRS_LOWER, mvfr1_simdhp), 1564 MRS_FIELD(MVFR1, SIMDSP, false, MRS_LOWER, mvfr1_simdsp), 1565 MRS_FIELD(MVFR1, SIMDInt, false, MRS_LOWER, mvfr1_simdint), 1566 MRS_FIELD_HWCAP(MVFR1, SIMDLS, false, MRS_LOWER, mvfr1_simdls, 1567 mvfr1_simdls_caps), 1568 MRS_FIELD(MVFR1, FPDNaN, false, MRS_LOWER, mvfr1_fpdnan), 1569 MRS_FIELD(MVFR1, FPFtZ, false, MRS_LOWER, mvfr1_fpftz), 1570 MRS_FIELD_END, 1571 }; 1572 #endif /* COMPAT_FREEBSD32 */ 1573 1574 struct mrs_user_reg { 1575 u_int reg; 1576 u_int CRm; 1577 u_int Op2; 1578 size_t offset; 1579 struct mrs_field *fields; 1580 }; 1581 1582 #define USER_REG(name, field_name) \ 1583 { \ 1584 .reg = name, \ 1585 .CRm = name##_CRm, \ 1586 .Op2 = name##_op2, \ 1587 .offset = __offsetof(struct cpu_desc, field_name), \ 1588 .fields = field_name##_fields, \ 1589 } 1590 static struct mrs_user_reg user_regs[] = { 1591 USER_REG(ID_AA64DFR0_EL1, id_aa64dfr0), 1592 1593 USER_REG(ID_AA64ISAR0_EL1, id_aa64isar0), 1594 USER_REG(ID_AA64ISAR1_EL1, id_aa64isar1), 1595 1596 USER_REG(ID_AA64MMFR0_EL1, id_aa64mmfr0), 1597 USER_REG(ID_AA64MMFR1_EL1, id_aa64mmfr1), 1598 USER_REG(ID_AA64MMFR2_EL1, id_aa64mmfr2), 1599 1600 USER_REG(ID_AA64PFR0_EL1, id_aa64pfr0), 1601 USER_REG(ID_AA64PFR1_EL1, id_aa64pfr1), 1602 #ifdef COMPAT_FREEBSD32 1603 USER_REG(ID_ISAR5_EL1, id_isar5), 1604 1605 USER_REG(MVFR0_EL1, mvfr0), 1606 USER_REG(MVFR1_EL1, mvfr1), 1607 #endif /* COMPAT_FREEBSD32 */ 1608 }; 1609 1610 #define CPU_DESC_FIELD(desc, idx) \ 1611 *(uint64_t *)((char *)&(desc) + user_regs[(idx)].offset) 1612 1613 static int 1614 user_mrs_handler(vm_offset_t va, uint32_t insn, struct trapframe *frame, 1615 uint32_t esr) 1616 { 1617 uint64_t value; 1618 int CRm, Op2, i, reg; 1619 1620 if ((insn & MRS_MASK) != MRS_VALUE) 1621 return (0); 1622 1623 /* 1624 * We only emulate Op0 == 3, Op1 == 0, CRn == 0, CRm == {0, 4-7}. 1625 * These are in the EL1 CPU identification space. 1626 * CRm == 0 holds MIDR_EL1, MPIDR_EL1, and REVID_EL1. 1627 * CRm == {4-7} holds the ID_AA64 registers. 1628 * 1629 * For full details see the ARMv8 ARM (ARM DDI 0487C.a) 1630 * Table D9-2 System instruction encodings for non-Debug System 1631 * register accesses. 1632 */ 1633 if (mrs_Op0(insn) != 3 || mrs_Op1(insn) != 0 || mrs_CRn(insn) != 0) 1634 return (0); 1635 1636 CRm = mrs_CRm(insn); 1637 if (CRm > 7 || (CRm < 4 && CRm != 0)) 1638 return (0); 1639 1640 Op2 = mrs_Op2(insn); 1641 value = 0; 1642 1643 for (i = 0; i < nitems(user_regs); i++) { 1644 if (user_regs[i].CRm == CRm && user_regs[i].Op2 == Op2) { 1645 value = CPU_DESC_FIELD(user_cpu_desc, i); 1646 break; 1647 } 1648 } 1649 1650 if (CRm == 0) { 1651 switch (Op2) { 1652 case 0: 1653 value = READ_SPECIALREG(midr_el1); 1654 break; 1655 case 5: 1656 value = READ_SPECIALREG(mpidr_el1); 1657 break; 1658 case 6: 1659 value = READ_SPECIALREG(revidr_el1); 1660 break; 1661 default: 1662 return (0); 1663 } 1664 } 1665 1666 /* 1667 * We will handle this instruction, move to the next so we 1668 * don't trap here again. 1669 */ 1670 frame->tf_elr += INSN_SIZE; 1671 1672 reg = MRS_REGISTER(insn); 1673 /* If reg is 31 then write to xzr, i.e. do nothing */ 1674 if (reg == 31) 1675 return (1); 1676 1677 if (reg < nitems(frame->tf_x)) 1678 frame->tf_x[reg] = value; 1679 else if (reg == 30) 1680 frame->tf_lr = value; 1681 1682 return (1); 1683 } 1684 1685 bool 1686 extract_user_id_field(u_int reg, u_int field_shift, uint8_t *val) 1687 { 1688 uint64_t value; 1689 int i; 1690 1691 for (i = 0; i < nitems(user_regs); i++) { 1692 if (user_regs[i].reg == reg) { 1693 value = CPU_DESC_FIELD(user_cpu_desc, i); 1694 *val = value >> field_shift; 1695 return (true); 1696 } 1697 } 1698 1699 return (false); 1700 } 1701 1702 bool 1703 get_kernel_reg(u_int reg, uint64_t *val) 1704 { 1705 int i; 1706 1707 for (i = 0; i < nitems(user_regs); i++) { 1708 if (user_regs[i].reg == reg) { 1709 *val = CPU_DESC_FIELD(kern_cpu_desc, i); 1710 return (true); 1711 } 1712 } 1713 1714 return (false); 1715 } 1716 1717 /* 1718 * Compares two field values that may be signed or unsigned. 1719 * Returns: 1720 * < 0 when a is less than b 1721 * = 0 when a equals b 1722 * > 0 when a is greater than b 1723 */ 1724 static int 1725 mrs_field_cmp(uint64_t a, uint64_t b, u_int shift, int width, bool sign) 1726 { 1727 uint64_t mask; 1728 1729 KASSERT(width > 0 && width < 64, ("%s: Invalid width %d", __func__, 1730 width)); 1731 1732 mask = (1ul << width) - 1; 1733 /* Move the field to the lower bits */ 1734 a = (a >> shift) & mask; 1735 b = (b >> shift) & mask; 1736 1737 if (sign) { 1738 /* 1739 * The field is signed. Toggle the upper bit so the comparison 1740 * works on unsigned values as this makes positive numbers, 1741 * i.e. those with a 0 bit, larger than negative numbers, 1742 * i.e. those with a 1 bit, in an unsigned comparison. 1743 */ 1744 a ^= 1ul << (width - 1); 1745 b ^= 1ul << (width - 1); 1746 } 1747 1748 return (a - b); 1749 } 1750 1751 static uint64_t 1752 update_lower_register(uint64_t val, uint64_t new_val, u_int shift, 1753 int width, bool sign) 1754 { 1755 uint64_t mask; 1756 1757 KASSERT(width > 0 && width < 64, ("%s: Invalid width %d", __func__, 1758 width)); 1759 1760 /* 1761 * If the new value is less than the existing value update it. 1762 */ 1763 if (mrs_field_cmp(new_val, val, shift, width, sign) < 0) { 1764 mask = (1ul << width) - 1; 1765 val &= ~(mask << shift); 1766 val |= new_val & (mask << shift); 1767 } 1768 1769 return (val); 1770 } 1771 1772 void 1773 update_special_regs(u_int cpu) 1774 { 1775 struct mrs_field *fields; 1776 uint64_t user_reg, kern_reg, value; 1777 int i, j; 1778 1779 if (cpu == 0) { 1780 /* Create a user visible cpu description with safe values */ 1781 memset(&user_cpu_desc, 0, sizeof(user_cpu_desc)); 1782 /* Safe values for these registers */ 1783 user_cpu_desc.id_aa64pfr0 = ID_AA64PFR0_AdvSIMD_NONE | 1784 ID_AA64PFR0_FP_NONE | ID_AA64PFR0_EL1_64 | 1785 ID_AA64PFR0_EL0_64; 1786 user_cpu_desc.id_aa64dfr0 = ID_AA64DFR0_DebugVer_8; 1787 } 1788 1789 for (i = 0; i < nitems(user_regs); i++) { 1790 value = CPU_DESC_FIELD(cpu_desc[cpu], i); 1791 if (cpu == 0) { 1792 kern_reg = value; 1793 user_reg = value; 1794 } else { 1795 kern_reg = CPU_DESC_FIELD(kern_cpu_desc, i); 1796 user_reg = CPU_DESC_FIELD(user_cpu_desc, i); 1797 } 1798 1799 fields = user_regs[i].fields; 1800 for (j = 0; fields[j].type != 0; j++) { 1801 switch (fields[j].type & MRS_TYPE_MASK) { 1802 case MRS_EXACT: 1803 user_reg &= ~(0xful << fields[j].shift); 1804 user_reg |= 1805 (uint64_t)MRS_EXACT_FIELD(fields[j].type) << 1806 fields[j].shift; 1807 break; 1808 case MRS_LOWER: 1809 user_reg = update_lower_register(user_reg, 1810 value, fields[j].shift, 4, fields[j].sign); 1811 break; 1812 default: 1813 panic("Invalid field type: %d", fields[j].type); 1814 } 1815 kern_reg = update_lower_register(kern_reg, value, 1816 fields[j].shift, 4, fields[j].sign); 1817 } 1818 1819 CPU_DESC_FIELD(kern_cpu_desc, i) = kern_reg; 1820 CPU_DESC_FIELD(user_cpu_desc, i) = user_reg; 1821 } 1822 } 1823 1824 /* HWCAP */ 1825 bool __read_frequently lse_supported = false; 1826 1827 bool __read_frequently icache_aliasing = false; 1828 bool __read_frequently icache_vmid = false; 1829 1830 int64_t dcache_line_size; /* The minimum D cache line size */ 1831 int64_t icache_line_size; /* The minimum I cache line size */ 1832 int64_t idcache_line_size; /* The minimum cache line size */ 1833 1834 /* 1835 * Find the values to export to userspace as AT_HWCAP and AT_HWCAP2. 1836 */ 1837 static void 1838 parse_cpu_features(void) 1839 { 1840 struct mrs_field_hwcap *hwcaps; 1841 struct mrs_field *fields; 1842 uint64_t min, reg; 1843 int i, j, k; 1844 1845 for (i = 0; i < nitems(user_regs); i++) { 1846 reg = CPU_DESC_FIELD(user_cpu_desc, i); 1847 fields = user_regs[i].fields; 1848 for (j = 0; fields[j].type != 0; j++) { 1849 hwcaps = fields[j].hwcaps; 1850 if (hwcaps == NULL) 1851 continue; 1852 1853 for (k = 0; hwcaps[k].hwcap != NULL; k++) { 1854 min = hwcaps[k].min; 1855 1856 /* 1857 * If the field is greater than the minimum 1858 * value we can set the hwcap; 1859 */ 1860 if (mrs_field_cmp(reg, min, fields[j].shift, 1861 4, fields[j].sign) >= 0) { 1862 *hwcaps[k].hwcap |= hwcaps[k].hwcap_val; 1863 } 1864 } 1865 } 1866 } 1867 } 1868 1869 static void 1870 identify_cpu_sysinit(void *dummy __unused) 1871 { 1872 int cpu; 1873 bool dic, idc; 1874 1875 dic = (allow_dic != 0); 1876 idc = (allow_idc != 0); 1877 1878 CPU_FOREACH(cpu) { 1879 check_cpu_regs(cpu); 1880 if (cpu != 0) 1881 update_special_regs(cpu); 1882 1883 if (CTR_DIC_VAL(cpu_desc[cpu].ctr) == 0) 1884 dic = false; 1885 if (CTR_IDC_VAL(cpu_desc[cpu].ctr) == 0) 1886 idc = false; 1887 } 1888 1889 /* Find the values to export to userspace as AT_HWCAP and AT_HWCAP2 */ 1890 parse_cpu_features(); 1891 1892 #ifdef COMPAT_FREEBSD32 1893 /* Set the default caps and any that need to check multiple fields */ 1894 elf32_hwcap |= parse_cpu_features_hwcap32(); 1895 #endif 1896 1897 if (dic && idc) { 1898 arm64_icache_sync_range = &arm64_dic_idc_icache_sync_range; 1899 if (bootverbose) 1900 printf("Enabling DIC & IDC ICache sync\n"); 1901 } else if (idc) { 1902 arm64_icache_sync_range = &arm64_idc_aliasing_icache_sync_range; 1903 if (bootverbose) 1904 printf("Enabling IDC ICache sync\n"); 1905 } 1906 1907 if ((elf_hwcap & HWCAP_ATOMICS) != 0) { 1908 lse_supported = true; 1909 if (bootverbose) 1910 printf("Enabling LSE atomics in the kernel\n"); 1911 } 1912 #ifdef LSE_ATOMICS 1913 if (!lse_supported) 1914 panic("CPU does not support LSE atomic instructions"); 1915 #endif 1916 1917 install_undef_handler(true, user_mrs_handler); 1918 } 1919 SYSINIT(identify_cpu, SI_SUB_CPU, SI_ORDER_MIDDLE, identify_cpu_sysinit, NULL); 1920 1921 static void 1922 cpu_features_sysinit(void *dummy __unused) 1923 { 1924 struct sbuf sb; 1925 u_int cpu; 1926 1927 CPU_FOREACH(cpu) 1928 print_cpu_features(cpu); 1929 1930 /* Fill in cpu_model for the hw.model sysctl */ 1931 sbuf_new(&sb, cpu_model, sizeof(cpu_model), SBUF_FIXEDLEN); 1932 print_cpu_midr(&sb, 0); 1933 1934 sbuf_finish(&sb); 1935 sbuf_delete(&sb); 1936 } 1937 /* Log features before APs are released and start printing to the dmesg. */ 1938 SYSINIT(cpu_features, SI_SUB_SMP - 1, SI_ORDER_ANY, cpu_features_sysinit, NULL); 1939 1940 #ifdef COMPAT_FREEBSD32 1941 static u_long 1942 parse_cpu_features_hwcap32(void) 1943 { 1944 u_long hwcap = HWCAP32_DEFAULT; 1945 1946 if ((MVFR1_SIMDLS_VAL(user_cpu_desc.mvfr1) >= 1947 MVFR1_SIMDLS_IMPL) && 1948 (MVFR1_SIMDInt_VAL(user_cpu_desc.mvfr1) >= 1949 MVFR1_SIMDInt_IMPL) && 1950 (MVFR1_SIMDSP_VAL(user_cpu_desc.mvfr1) >= 1951 MVFR1_SIMDSP_IMPL)) 1952 hwcap |= HWCAP32_NEON; 1953 1954 return (hwcap); 1955 } 1956 #endif /* COMPAT_FREEBSD32 */ 1957 1958 static void 1959 print_ctr_fields(struct sbuf *sb, uint64_t reg, void *arg) 1960 { 1961 1962 sbuf_printf(sb, "%u byte D-cacheline,", CTR_DLINE_SIZE(reg)); 1963 sbuf_printf(sb, "%u byte I-cacheline,", CTR_ILINE_SIZE(reg)); 1964 reg &= ~(CTR_DLINE_MASK | CTR_ILINE_MASK); 1965 1966 switch(CTR_L1IP_VAL(reg)) { 1967 case CTR_L1IP_VPIPT: 1968 sbuf_printf(sb, "VPIPT"); 1969 break; 1970 case CTR_L1IP_AIVIVT: 1971 sbuf_printf(sb, "AIVIVT"); 1972 break; 1973 case CTR_L1IP_VIPT: 1974 sbuf_printf(sb, "VIPT"); 1975 break; 1976 case CTR_L1IP_PIPT: 1977 sbuf_printf(sb, "PIPT"); 1978 break; 1979 } 1980 sbuf_printf(sb, " ICache,"); 1981 reg &= ~CTR_L1IP_MASK; 1982 1983 sbuf_printf(sb, "%d byte ERG,", CTR_ERG_SIZE(reg)); 1984 sbuf_printf(sb, "%d byte CWG", CTR_CWG_SIZE(reg)); 1985 reg &= ~(CTR_ERG_MASK | CTR_CWG_MASK); 1986 1987 if (CTR_IDC_VAL(reg) != 0) 1988 sbuf_printf(sb, ",IDC"); 1989 if (CTR_DIC_VAL(reg) != 0) 1990 sbuf_printf(sb, ",DIC"); 1991 reg &= ~(CTR_IDC_MASK | CTR_DIC_MASK); 1992 reg &= ~CTR_RES1; 1993 1994 if (reg != 0) 1995 sbuf_printf(sb, ",%lx", reg); 1996 } 1997 1998 static void 1999 print_register(struct sbuf *sb, const char *reg_name, uint64_t reg, 2000 void (*print_fields)(struct sbuf *, uint64_t, void *), void *arg) 2001 { 2002 2003 sbuf_printf(sb, "%29s = <", reg_name); 2004 2005 print_fields(sb, reg, arg); 2006 2007 sbuf_finish(sb); 2008 printf("%s>\n", sbuf_data(sb)); 2009 sbuf_clear(sb); 2010 } 2011 2012 static void 2013 print_id_fields(struct sbuf *sb, uint64_t reg, void *arg) 2014 { 2015 struct mrs_field *fields = arg; 2016 struct mrs_field_value *fv; 2017 int field, i, j, printed; 2018 2019 #define SEP_STR ((printed++) == 0) ? "" : "," 2020 printed = 0; 2021 for (i = 0; fields[i].type != 0; i++) { 2022 fv = fields[i].values; 2023 2024 /* TODO: Handle with an unknown message */ 2025 if (fv == NULL) 2026 continue; 2027 2028 field = (reg & fields[i].mask) >> fields[i].shift; 2029 for (j = 0; fv[j].desc != NULL; j++) { 2030 if ((fv[j].value >> fields[i].shift) != field) 2031 continue; 2032 2033 if (fv[j].desc[0] != '\0') 2034 sbuf_printf(sb, "%s%s", SEP_STR, fv[j].desc); 2035 break; 2036 } 2037 if (fv[j].desc == NULL) 2038 sbuf_printf(sb, "%sUnknown %s(%x)", SEP_STR, 2039 fields[i].name, field); 2040 2041 reg &= ~(0xful << fields[i].shift); 2042 } 2043 2044 if (reg != 0) 2045 sbuf_printf(sb, "%s%#lx", SEP_STR, reg); 2046 #undef SEP_STR 2047 } 2048 2049 static void 2050 print_id_register(struct sbuf *sb, const char *reg_name, uint64_t reg, 2051 struct mrs_field *fields) 2052 { 2053 2054 print_register(sb, reg_name, reg, print_id_fields, fields); 2055 } 2056 2057 static void 2058 print_cpu_midr(struct sbuf *sb, u_int cpu) 2059 { 2060 const struct cpu_parts *cpu_partsp; 2061 const char *cpu_impl_name; 2062 const char *cpu_part_name; 2063 u_int midr; 2064 u_int impl_id; 2065 u_int part_id; 2066 2067 midr = pcpu_find(cpu)->pc_midr; 2068 2069 cpu_impl_name = NULL; 2070 cpu_partsp = NULL; 2071 impl_id = CPU_IMPL(midr); 2072 for (int i = 0; cpu_implementers[i].impl_name != NULL; i++) { 2073 if (impl_id == cpu_implementers[i].impl_id) { 2074 cpu_impl_name = cpu_implementers[i].impl_name; 2075 cpu_partsp = cpu_implementers[i].cpu_parts; 2076 break; 2077 } 2078 } 2079 /* Unknown implementer, so unknown part */ 2080 if (cpu_impl_name == NULL) { 2081 sbuf_printf(sb, "Unknown Implementer (midr: %08x)", midr); 2082 return; 2083 } 2084 2085 KASSERT(cpu_partsp != NULL, ("%s: No parts table for implementer %s", 2086 __func__, cpu_impl_name)); 2087 2088 cpu_part_name = NULL; 2089 part_id = CPU_PART(midr); 2090 for (int i = 0; cpu_partsp[i].part_name != NULL; i++) { 2091 if (part_id == cpu_partsp[i].part_id) { 2092 cpu_part_name = cpu_partsp[i].part_name; 2093 break; 2094 } 2095 } 2096 /* Known Implementer, Unknown part */ 2097 if (cpu_part_name == NULL) { 2098 sbuf_printf(sb, "%s Unknown CPU r%dp%d (midr: %08x)", 2099 cpu_impl_name, CPU_VAR(midr), CPU_REV(midr), midr); 2100 return; 2101 } 2102 2103 sbuf_printf(sb, "%s %s r%dp%d", cpu_impl_name, 2104 cpu_part_name, CPU_VAR(midr), CPU_REV(midr)); 2105 } 2106 2107 static void 2108 print_cpu_cache(u_int cpu, struct sbuf *sb, uint64_t ccs, bool icache, 2109 bool unified) 2110 { 2111 size_t cache_size; 2112 size_t line_size; 2113 2114 /* LineSize is Log2(S) - 4. */ 2115 line_size = 1 << ((ccs & CCSIDR_LineSize_MASK) + 4); 2116 /* 2117 * Calculate cache size (sets * ways * line size). There are different 2118 * formats depending on the FEAT_CCIDX bit in ID_AA64MMFR2 feature 2119 * register. 2120 */ 2121 if ((cpu_desc[cpu].id_aa64mmfr2 & ID_AA64MMFR2_CCIDX_64)) 2122 cache_size = (CCSIDR_NSETS_64(ccs) + 1) * 2123 (CCSIDR_ASSOC_64(ccs) + 1); 2124 else 2125 cache_size = (CCSIDR_NSETS(ccs) + 1) * (CCSIDR_ASSOC(ccs) + 1); 2126 2127 cache_size *= line_size; 2128 sbuf_printf(sb, "%zuKB (%s)", cache_size / 1024, 2129 icache ? "instruction" : unified ? "unified" : "data"); 2130 } 2131 2132 static void 2133 print_cpu_caches(struct sbuf *sb, u_int cpu) 2134 { 2135 /* Print out each cache combination */ 2136 uint64_t clidr; 2137 int i = 1; 2138 clidr = cpu_desc[cpu].clidr; 2139 2140 for (i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) { 2141 int j = 0; 2142 int ctype_m = (clidr & CLIDR_CTYPE_MASK); 2143 2144 sbuf_printf(sb, " L%d cache: ", i + 1); 2145 if ((clidr & CLIDR_CTYPE_IO)) { 2146 print_cpu_cache(cpu, sb, cpu_desc[cpu].ccsidr[i][j++], 2147 true, false); 2148 /* If there's more, add to the line. */ 2149 if ((ctype_m & ~CLIDR_CTYPE_IO) != 0) 2150 sbuf_printf(sb, ", "); 2151 } 2152 if ((ctype_m & ~CLIDR_CTYPE_IO) != 0) { 2153 print_cpu_cache(cpu, sb, cpu_desc[cpu].ccsidr[i][j], 2154 false, (clidr & CLIDR_CTYPE_UNIFIED)); 2155 } 2156 sbuf_printf(sb, "\n"); 2157 2158 } 2159 sbuf_finish(sb); 2160 printf("%s", sbuf_data(sb)); 2161 } 2162 2163 static void 2164 print_cpu_features(u_int cpu) 2165 { 2166 struct sbuf *sb; 2167 2168 sb = sbuf_new_auto(); 2169 sbuf_printf(sb, "CPU%3u: ", cpu); 2170 print_cpu_midr(sb, cpu); 2171 2172 sbuf_cat(sb, " affinity:"); 2173 switch(cpu_aff_levels) { 2174 default: 2175 case 4: 2176 sbuf_printf(sb, " %2d", CPU_AFF3(cpu_desc[cpu].mpidr)); 2177 /* FALLTHROUGH */ 2178 case 3: 2179 sbuf_printf(sb, " %2d", CPU_AFF2(cpu_desc[cpu].mpidr)); 2180 /* FALLTHROUGH */ 2181 case 2: 2182 sbuf_printf(sb, " %2d", CPU_AFF1(cpu_desc[cpu].mpidr)); 2183 /* FALLTHROUGH */ 2184 case 1: 2185 case 0: /* On UP this will be zero */ 2186 sbuf_printf(sb, " %2d", CPU_AFF0(cpu_desc[cpu].mpidr)); 2187 break; 2188 } 2189 sbuf_finish(sb); 2190 printf("%s\n", sbuf_data(sb)); 2191 sbuf_clear(sb); 2192 2193 /* 2194 * There is a hardware errata where, if one CPU is performing a TLB 2195 * invalidation while another is performing a store-exclusive the 2196 * store-exclusive may return the wrong status. A workaround seems 2197 * to be to use an IPI to invalidate on each CPU, however given the 2198 * limited number of affected units (pass 1.1 is the evaluation 2199 * hardware revision), and the lack of information from Cavium 2200 * this has not been implemented. 2201 * 2202 * At the time of writing this the only information is from: 2203 * https://lkml.org/lkml/2016/8/4/722 2204 */ 2205 /* 2206 * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 on its own also 2207 * triggers on pass 2.0+. 2208 */ 2209 if (cpu == 0 && CPU_VAR(PCPU_GET(midr)) == 0 && 2210 CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1) 2211 printf("WARNING: ThunderX Pass 1.1 detected.\nThis has known " 2212 "hardware bugs that may cause the incorrect operation of " 2213 "atomic operations.\n"); 2214 2215 #define SHOULD_PRINT_REG(_reg) \ 2216 (cpu == 0 || cpu_desc[cpu]._reg != cpu_desc[cpu - 1]._reg) 2217 2218 /* Cache Type Register */ 2219 if (SHOULD_PRINT_REG(ctr)) { 2220 print_register(sb, "Cache Type", 2221 cpu_desc[cpu].ctr, print_ctr_fields, NULL); 2222 } 2223 2224 /* AArch64 Instruction Set Attribute Register 0 */ 2225 if (SHOULD_PRINT_REG(id_aa64isar0)) 2226 print_id_register(sb, "Instruction Set Attributes 0", 2227 cpu_desc[cpu].id_aa64isar0, id_aa64isar0_fields); 2228 2229 /* AArch64 Instruction Set Attribute Register 1 */ 2230 if (SHOULD_PRINT_REG(id_aa64isar1)) 2231 print_id_register(sb, "Instruction Set Attributes 1", 2232 cpu_desc[cpu].id_aa64isar1, id_aa64isar1_fields); 2233 2234 /* AArch64 Instruction Set Attribute Register 2 */ 2235 if (SHOULD_PRINT_REG(id_aa64isar2)) 2236 print_id_register(sb, "Instruction Set Attributes 2", 2237 cpu_desc[cpu].id_aa64isar2, id_aa64isar2_fields); 2238 2239 /* AArch64 Processor Feature Register 0 */ 2240 if (SHOULD_PRINT_REG(id_aa64pfr0)) 2241 print_id_register(sb, "Processor Features 0", 2242 cpu_desc[cpu].id_aa64pfr0, id_aa64pfr0_fields); 2243 2244 /* AArch64 Processor Feature Register 1 */ 2245 if (SHOULD_PRINT_REG(id_aa64pfr1)) 2246 print_id_register(sb, "Processor Features 1", 2247 cpu_desc[cpu].id_aa64pfr1, id_aa64pfr1_fields); 2248 2249 /* AArch64 Memory Model Feature Register 0 */ 2250 if (SHOULD_PRINT_REG(id_aa64mmfr0)) 2251 print_id_register(sb, "Memory Model Features 0", 2252 cpu_desc[cpu].id_aa64mmfr0, id_aa64mmfr0_fields); 2253 2254 /* AArch64 Memory Model Feature Register 1 */ 2255 if (SHOULD_PRINT_REG(id_aa64mmfr1)) 2256 print_id_register(sb, "Memory Model Features 1", 2257 cpu_desc[cpu].id_aa64mmfr1, id_aa64mmfr1_fields); 2258 2259 /* AArch64 Memory Model Feature Register 2 */ 2260 if (SHOULD_PRINT_REG(id_aa64mmfr2)) 2261 print_id_register(sb, "Memory Model Features 2", 2262 cpu_desc[cpu].id_aa64mmfr2, id_aa64mmfr2_fields); 2263 2264 /* AArch64 Debug Feature Register 0 */ 2265 if (SHOULD_PRINT_REG(id_aa64dfr0)) 2266 print_id_register(sb, "Debug Features 0", 2267 cpu_desc[cpu].id_aa64dfr0, id_aa64dfr0_fields); 2268 2269 /* AArch64 Memory Model Feature Register 1 */ 2270 if (SHOULD_PRINT_REG(id_aa64dfr1)) 2271 print_id_register(sb, "Debug Features 1", 2272 cpu_desc[cpu].id_aa64dfr1, id_aa64dfr1_fields); 2273 2274 /* AArch64 Auxiliary Feature Register 0 */ 2275 if (SHOULD_PRINT_REG(id_aa64afr0)) 2276 print_id_register(sb, "Auxiliary Features 0", 2277 cpu_desc[cpu].id_aa64afr0, id_aa64afr0_fields); 2278 2279 /* AArch64 Auxiliary Feature Register 1 */ 2280 if (SHOULD_PRINT_REG(id_aa64afr1)) 2281 print_id_register(sb, "Auxiliary Features 1", 2282 cpu_desc[cpu].id_aa64afr1, id_aa64afr1_fields); 2283 2284 /* AArch64 SVE Feature Register 0 */ 2285 if (cpu_desc[cpu].have_sve) { 2286 if (SHOULD_PRINT_REG(id_aa64zfr0) || 2287 !cpu_desc[cpu - 1].have_sve) { 2288 print_id_register(sb, "SVE Features 0", 2289 cpu_desc[cpu].id_aa64zfr0, id_aa64zfr0_fields); 2290 } 2291 } 2292 2293 #ifdef COMPAT_FREEBSD32 2294 /* AArch32 Instruction Set Attribute Register 5 */ 2295 if (SHOULD_PRINT_REG(id_isar5)) 2296 print_id_register(sb, "AArch32 Instruction Set Attributes 5", 2297 cpu_desc[cpu].id_isar5, id_isar5_fields); 2298 2299 /* AArch32 Media and VFP Feature Register 0 */ 2300 if (SHOULD_PRINT_REG(mvfr0)) 2301 print_id_register(sb, "AArch32 Media and VFP Features 0", 2302 cpu_desc[cpu].mvfr0, mvfr0_fields); 2303 2304 /* AArch32 Media and VFP Feature Register 1 */ 2305 if (SHOULD_PRINT_REG(mvfr1)) 2306 print_id_register(sb, "AArch32 Media and VFP Features 1", 2307 cpu_desc[cpu].mvfr1, mvfr1_fields); 2308 #endif 2309 if (bootverbose) 2310 print_cpu_caches(sb, cpu); 2311 2312 sbuf_delete(sb); 2313 sb = NULL; 2314 #undef SHOULD_PRINT_REG 2315 #undef SEP_STR 2316 } 2317 2318 void 2319 identify_cache(uint64_t ctr) 2320 { 2321 2322 /* Identify the L1 cache type */ 2323 switch (CTR_L1IP_VAL(ctr)) { 2324 case CTR_L1IP_PIPT: 2325 break; 2326 case CTR_L1IP_VPIPT: 2327 icache_vmid = true; 2328 break; 2329 default: 2330 case CTR_L1IP_VIPT: 2331 icache_aliasing = true; 2332 break; 2333 } 2334 2335 if (dcache_line_size == 0) { 2336 KASSERT(icache_line_size == 0, ("%s: i-cacheline size set: %ld", 2337 __func__, icache_line_size)); 2338 2339 /* Get the D cache line size */ 2340 dcache_line_size = CTR_DLINE_SIZE(ctr); 2341 /* And the same for the I cache */ 2342 icache_line_size = CTR_ILINE_SIZE(ctr); 2343 2344 idcache_line_size = MIN(dcache_line_size, icache_line_size); 2345 } 2346 2347 if (dcache_line_size != CTR_DLINE_SIZE(ctr)) { 2348 printf("WARNING: D-cacheline size mismatch %ld != %d\n", 2349 dcache_line_size, CTR_DLINE_SIZE(ctr)); 2350 } 2351 2352 if (icache_line_size != CTR_ILINE_SIZE(ctr)) { 2353 printf("WARNING: I-cacheline size mismatch %ld != %d\n", 2354 icache_line_size, CTR_ILINE_SIZE(ctr)); 2355 } 2356 } 2357 2358 void 2359 identify_cpu(u_int cpu) 2360 { 2361 uint64_t clidr; 2362 2363 /* Save affinity for current CPU */ 2364 cpu_desc[cpu].mpidr = get_mpidr(); 2365 CPU_AFFINITY(cpu) = cpu_desc[cpu].mpidr & CPU_AFF_MASK; 2366 2367 cpu_desc[cpu].ctr = READ_SPECIALREG(ctr_el0); 2368 cpu_desc[cpu].id_aa64dfr0 = READ_SPECIALREG(id_aa64dfr0_el1); 2369 cpu_desc[cpu].id_aa64dfr1 = READ_SPECIALREG(id_aa64dfr1_el1); 2370 cpu_desc[cpu].id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1); 2371 cpu_desc[cpu].id_aa64isar1 = READ_SPECIALREG(id_aa64isar1_el1); 2372 cpu_desc[cpu].id_aa64isar2 = READ_SPECIALREG(id_aa64isar2_el1); 2373 cpu_desc[cpu].id_aa64mmfr0 = READ_SPECIALREG(id_aa64mmfr0_el1); 2374 cpu_desc[cpu].id_aa64mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1); 2375 cpu_desc[cpu].id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1); 2376 cpu_desc[cpu].id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1); 2377 cpu_desc[cpu].id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1); 2378 2379 /* 2380 * ID_AA64ZFR0_EL1 is only valid when at least one of: 2381 * - ID_AA64PFR0_EL1.SVE is non-zero 2382 * - ID_AA64PFR1_EL1.SME is non-zero 2383 * In other cases it is zero, but still safe to read 2384 */ 2385 cpu_desc[cpu].have_sve = 2386 (ID_AA64PFR0_SVE_VAL(cpu_desc[cpu].id_aa64pfr0) != 0); 2387 cpu_desc[cpu].id_aa64zfr0 = READ_SPECIALREG(ID_AA64ZFR0_EL1_REG); 2388 2389 cpu_desc[cpu].clidr = READ_SPECIALREG(clidr_el1); 2390 2391 clidr = cpu_desc[cpu].clidr; 2392 2393 for (int i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) { 2394 int j = 0; 2395 if ((clidr & CLIDR_CTYPE_IO)) { 2396 WRITE_SPECIALREG(csselr_el1, 2397 CSSELR_Level(i) | CSSELR_InD); 2398 cpu_desc[cpu].ccsidr[i][j++] = 2399 READ_SPECIALREG(ccsidr_el1); 2400 } 2401 if ((clidr & ~CLIDR_CTYPE_IO) == 0) 2402 continue; 2403 WRITE_SPECIALREG(csselr_el1, CSSELR_Level(i)); 2404 cpu_desc[cpu].ccsidr[i][j] = READ_SPECIALREG(ccsidr_el1); 2405 } 2406 2407 #ifdef COMPAT_FREEBSD32 2408 /* Only read aarch32 SRs if EL0-32 is available */ 2409 if (ID_AA64PFR0_EL0_VAL(cpu_desc[cpu].id_aa64pfr0) == 2410 ID_AA64PFR0_EL0_64_32) { 2411 cpu_desc[cpu].id_isar5 = READ_SPECIALREG(id_isar5_el1); 2412 cpu_desc[cpu].mvfr0 = READ_SPECIALREG(mvfr0_el1); 2413 cpu_desc[cpu].mvfr1 = READ_SPECIALREG(mvfr1_el1); 2414 } 2415 #endif 2416 } 2417 2418 static void 2419 check_cpu_regs(u_int cpu) 2420 { 2421 2422 switch (cpu_aff_levels) { 2423 case 0: 2424 if (CPU_AFF0(cpu_desc[cpu].mpidr) != 2425 CPU_AFF0(cpu_desc[0].mpidr)) 2426 cpu_aff_levels = 1; 2427 /* FALLTHROUGH */ 2428 case 1: 2429 if (CPU_AFF1(cpu_desc[cpu].mpidr) != 2430 CPU_AFF1(cpu_desc[0].mpidr)) 2431 cpu_aff_levels = 2; 2432 /* FALLTHROUGH */ 2433 case 2: 2434 if (CPU_AFF2(cpu_desc[cpu].mpidr) != 2435 CPU_AFF2(cpu_desc[0].mpidr)) 2436 cpu_aff_levels = 3; 2437 /* FALLTHROUGH */ 2438 case 3: 2439 if (CPU_AFF3(cpu_desc[cpu].mpidr) != 2440 CPU_AFF3(cpu_desc[0].mpidr)) 2441 cpu_aff_levels = 4; 2442 break; 2443 } 2444 2445 if (cpu_desc[cpu].ctr != cpu_desc[0].ctr) { 2446 /* 2447 * If the cache type register is different we may 2448 * have a different l1 cache type. 2449 */ 2450 identify_cache(cpu_desc[cpu].ctr); 2451 } 2452 } 2453