1 /*- 2 * Copyright (c) 2014 Andrew Turner 3 * Copyright (c) 2014 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by Semihalf 7 * under sponsorship of the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/pcpu.h> 38 #include <sys/sbuf.h> 39 #include <sys/smp.h> 40 #include <sys/sysctl.h> 41 #include <sys/systm.h> 42 43 #include <machine/atomic.h> 44 #include <machine/cpu.h> 45 #include <machine/cpufunc.h> 46 #include <machine/elf.h> 47 #include <machine/md_var.h> 48 #include <machine/undefined.h> 49 50 static void print_cpu_midr(struct sbuf *sb, u_int cpu); 51 static void print_cpu_features(u_int cpu); 52 static void print_cpu_caches(struct sbuf *sb, u_int); 53 #ifdef COMPAT_FREEBSD32 54 static u_long parse_cpu_features_hwcap32(void); 55 #endif 56 57 char machine[] = "arm64"; 58 59 #ifdef SCTL_MASK32 60 extern int adaptive_machine_arch; 61 #endif 62 63 static SYSCTL_NODE(_machdep, OID_AUTO, cache, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 64 "Cache management tuning"); 65 66 static int allow_dic = 1; 67 SYSCTL_INT(_machdep_cache, OID_AUTO, allow_dic, CTLFLAG_RDTUN, &allow_dic, 0, 68 "Allow optimizations based on the DIC cache bit"); 69 70 static int allow_idc = 1; 71 SYSCTL_INT(_machdep_cache, OID_AUTO, allow_idc, CTLFLAG_RDTUN, &allow_idc, 0, 72 "Allow optimizations based on the IDC cache bit"); 73 74 static void check_cpu_regs(u_int cpu); 75 76 /* 77 * The default implementation of I-cache sync assumes we have an 78 * aliasing cache until we know otherwise. 79 */ 80 void (*arm64_icache_sync_range)(vm_offset_t, vm_size_t) = 81 &arm64_aliasing_icache_sync_range; 82 83 static int 84 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 85 { 86 #ifdef SCTL_MASK32 87 static const char machine32[] = "arm"; 88 #endif 89 int error; 90 91 #ifdef SCTL_MASK32 92 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 93 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 94 else 95 #endif 96 error = SYSCTL_OUT(req, machine, sizeof(machine)); 97 return (error); 98 } 99 100 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 101 CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 102 103 static char cpu_model[64]; 104 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 105 cpu_model, sizeof(cpu_model), "Machine model"); 106 107 #define MAX_CACHES 8 /* Maximum number of caches supported 108 architecturally. */ 109 /* 110 * Per-CPU affinity as provided in MPIDR_EL1 111 * Indexed by CPU number in logical order selected by the system. 112 * Relevant fields can be extracted using CPU_AFFn macros, 113 * Aff3.Aff2.Aff1.Aff0 construct a unique CPU address in the system. 114 * 115 * Fields used by us: 116 * Aff1 - Cluster number 117 * Aff0 - CPU number in Aff1 cluster 118 */ 119 uint64_t __cpu_affinity[MAXCPU]; 120 static u_int cpu_aff_levels; 121 122 struct cpu_desc { 123 uint64_t mpidr; 124 uint64_t id_aa64afr0; 125 uint64_t id_aa64afr1; 126 uint64_t id_aa64dfr0; 127 uint64_t id_aa64dfr1; 128 uint64_t id_aa64isar0; 129 uint64_t id_aa64isar1; 130 uint64_t id_aa64isar2; 131 uint64_t id_aa64mmfr0; 132 uint64_t id_aa64mmfr1; 133 uint64_t id_aa64mmfr2; 134 uint64_t id_aa64pfr0; 135 uint64_t id_aa64pfr1; 136 uint64_t id_aa64zfr0; 137 uint64_t ctr; 138 #ifdef COMPAT_FREEBSD32 139 uint64_t id_isar5; 140 uint64_t mvfr0; 141 uint64_t mvfr1; 142 #endif 143 uint64_t clidr; 144 uint32_t ccsidr[MAX_CACHES][2]; /* 2 possible types. */ 145 bool have_sve; 146 }; 147 148 static struct cpu_desc cpu_desc[MAXCPU]; 149 static struct cpu_desc kern_cpu_desc; 150 static struct cpu_desc user_cpu_desc; 151 static u_int cpu_print_regs; 152 #define PRINT_ID_AA64_AFR0 0x00000001 153 #define PRINT_ID_AA64_AFR1 0x00000002 154 #define PRINT_ID_AA64_DFR0 0x00000010 155 #define PRINT_ID_AA64_DFR1 0x00000020 156 #define PRINT_ID_AA64_ISAR0 0x00000100 157 #define PRINT_ID_AA64_ISAR1 0x00000200 158 #define PRINT_ID_AA64_ISAR2 0x00000400 159 #define PRINT_ID_AA64_MMFR0 0x00001000 160 #define PRINT_ID_AA64_MMFR1 0x00002000 161 #define PRINT_ID_AA64_MMFR2 0x00004000 162 #define PRINT_ID_AA64_PFR0 0x00010000 163 #define PRINT_ID_AA64_PFR1 0x00020000 164 #define PRINT_ID_AA64_ZFR0 0x00100000 165 #ifdef COMPAT_FREEBSD32 166 #define PRINT_ID_ISAR5 0x01000000 167 #define PRINT_MVFR0 0x02000000 168 #define PRINT_MVFR1 0x04000000 169 #endif 170 #define PRINT_CTR_EL0 0x10000000 171 172 struct cpu_parts { 173 u_int part_id; 174 const char *part_name; 175 }; 176 #define CPU_PART_NONE { 0, NULL } 177 178 struct cpu_implementers { 179 u_int impl_id; 180 const char *impl_name; 181 /* 182 * Part number is implementation defined 183 * so each vendor will have its own set of values and names. 184 */ 185 const struct cpu_parts *cpu_parts; 186 }; 187 #define CPU_IMPLEMENTER_NONE { 0, NULL, NULL } 188 189 /* 190 * Per-implementer table of (PartNum, CPU Name) pairs. 191 */ 192 /* ARM Ltd. */ 193 static const struct cpu_parts cpu_parts_arm[] = { 194 { CPU_PART_AEM_V8, "AEMv8" }, 195 { CPU_PART_FOUNDATION, "Foundation-Model" }, 196 { CPU_PART_CORTEX_A34, "Cortex-A34" }, 197 { CPU_PART_CORTEX_A35, "Cortex-A35" }, 198 { CPU_PART_CORTEX_A53, "Cortex-A53" }, 199 { CPU_PART_CORTEX_A55, "Cortex-A55" }, 200 { CPU_PART_CORTEX_A57, "Cortex-A57" }, 201 { CPU_PART_CORTEX_A65, "Cortex-A65" }, 202 { CPU_PART_CORTEX_A72, "Cortex-A72" }, 203 { CPU_PART_CORTEX_A73, "Cortex-A73" }, 204 { CPU_PART_CORTEX_A75, "Cortex-A75" }, 205 { CPU_PART_CORTEX_A76, "Cortex-A76" }, 206 { CPU_PART_CORTEX_A76AE, "Cortex-A76AE" }, 207 { CPU_PART_CORTEX_A77, "Cortex-A77" }, 208 { CPU_PART_CORTEX_A78, "Cortex-A78" }, 209 { CPU_PART_CORTEX_A78C, "Cortex-A78C" }, 210 { CPU_PART_CORTEX_A510, "Cortex-A510" }, 211 { CPU_PART_CORTEX_A710, "Cortex-A710" }, 212 { CPU_PART_CORTEX_X1, "Cortex-X1" }, 213 { CPU_PART_CORTEX_X1C, "Cortex-X1C" }, 214 { CPU_PART_CORTEX_X2, "Cortex-X2" }, 215 { CPU_PART_NEOVERSE_E1, "Neoverse-E1" }, 216 { CPU_PART_NEOVERSE_N1, "Neoverse-N1" }, 217 { CPU_PART_NEOVERSE_N2, "Neoverse-N2" }, 218 { CPU_PART_NEOVERSE_V1, "Neoverse-V1" }, 219 CPU_PART_NONE, 220 }; 221 222 /* Cavium */ 223 static const struct cpu_parts cpu_parts_cavium[] = { 224 { CPU_PART_THUNDERX, "ThunderX" }, 225 { CPU_PART_THUNDERX2, "ThunderX2" }, 226 CPU_PART_NONE, 227 }; 228 229 /* APM / Ampere */ 230 static const struct cpu_parts cpu_parts_apm[] = { 231 { CPU_PART_EMAG8180, "eMAG 8180" }, 232 CPU_PART_NONE, 233 }; 234 235 /* Unknown */ 236 static const struct cpu_parts cpu_parts_none[] = { 237 CPU_PART_NONE, 238 }; 239 240 /* 241 * Implementers table. 242 */ 243 const struct cpu_implementers cpu_implementers[] = { 244 { CPU_IMPL_AMPERE, "Ampere", cpu_parts_none }, 245 { CPU_IMPL_APPLE, "Apple", cpu_parts_none }, 246 { CPU_IMPL_APM, "APM", cpu_parts_apm }, 247 { CPU_IMPL_ARM, "ARM", cpu_parts_arm }, 248 { CPU_IMPL_BROADCOM, "Broadcom", cpu_parts_none }, 249 { CPU_IMPL_CAVIUM, "Cavium", cpu_parts_cavium }, 250 { CPU_IMPL_DEC, "DEC", cpu_parts_none }, 251 { CPU_IMPL_FREESCALE, "Freescale", cpu_parts_none }, 252 { CPU_IMPL_FUJITSU, "Fujitsu", cpu_parts_none }, 253 { CPU_IMPL_INFINEON, "IFX", cpu_parts_none }, 254 { CPU_IMPL_INTEL, "Intel", cpu_parts_none }, 255 { CPU_IMPL_MARVELL, "Marvell", cpu_parts_none }, 256 { CPU_IMPL_NVIDIA, "NVIDIA", cpu_parts_none }, 257 { CPU_IMPL_QUALCOMM, "Qualcomm", cpu_parts_none }, 258 CPU_IMPLEMENTER_NONE, 259 }; 260 261 #define MRS_TYPE_MASK 0xf 262 #define MRS_INVALID 0 263 #define MRS_EXACT 1 264 #define MRS_EXACT_VAL(x) (MRS_EXACT | ((x) << 4)) 265 #define MRS_EXACT_FIELD(x) ((x) >> 4) 266 #define MRS_LOWER 2 267 268 struct mrs_field_value { 269 uint64_t value; 270 const char *desc; 271 }; 272 273 #define MRS_FIELD_VALUE(_value, _desc) \ 274 { \ 275 .value = (_value), \ 276 .desc = (_desc), \ 277 } 278 279 #define MRS_FIELD_VALUE_NONE_IMPL(_reg, _field, _none, _impl) \ 280 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _none, ""), \ 281 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _impl, #_field) 282 283 #define MRS_FIELD_VALUE_COUNT(_reg, _field, _desc) \ 284 MRS_FIELD_VALUE(0ul << _reg ## _ ## _field ## _SHIFT, "1 " _desc), \ 285 MRS_FIELD_VALUE(1ul << _reg ## _ ## _field ## _SHIFT, "2 " _desc "s"), \ 286 MRS_FIELD_VALUE(2ul << _reg ## _ ## _field ## _SHIFT, "3 " _desc "s"), \ 287 MRS_FIELD_VALUE(3ul << _reg ## _ ## _field ## _SHIFT, "4 " _desc "s"), \ 288 MRS_FIELD_VALUE(4ul << _reg ## _ ## _field ## _SHIFT, "5 " _desc "s"), \ 289 MRS_FIELD_VALUE(5ul << _reg ## _ ## _field ## _SHIFT, "6 " _desc "s"), \ 290 MRS_FIELD_VALUE(6ul << _reg ## _ ## _field ## _SHIFT, "7 " _desc "s"), \ 291 MRS_FIELD_VALUE(7ul << _reg ## _ ## _field ## _SHIFT, "8 " _desc "s"), \ 292 MRS_FIELD_VALUE(8ul << _reg ## _ ## _field ## _SHIFT, "9 " _desc "s"), \ 293 MRS_FIELD_VALUE(9ul << _reg ## _ ## _field ## _SHIFT, "10 "_desc "s"), \ 294 MRS_FIELD_VALUE(10ul<< _reg ## _ ## _field ## _SHIFT, "11 "_desc "s"), \ 295 MRS_FIELD_VALUE(11ul<< _reg ## _ ## _field ## _SHIFT, "12 "_desc "s"), \ 296 MRS_FIELD_VALUE(12ul<< _reg ## _ ## _field ## _SHIFT, "13 "_desc "s"), \ 297 MRS_FIELD_VALUE(13ul<< _reg ## _ ## _field ## _SHIFT, "14 "_desc "s"), \ 298 MRS_FIELD_VALUE(14ul<< _reg ## _ ## _field ## _SHIFT, "15 "_desc "s"), \ 299 MRS_FIELD_VALUE(15ul<< _reg ## _ ## _field ## _SHIFT, "16 "_desc "s") 300 301 #define MRS_FIELD_VALUE_END { .desc = NULL } 302 303 struct mrs_field_hwcap { 304 u_long *hwcap; 305 uint64_t min; 306 u_long hwcap_val; 307 }; 308 309 #define MRS_HWCAP(_hwcap, _val, _min) \ 310 { \ 311 .hwcap = (_hwcap), \ 312 .hwcap_val = (_val), \ 313 .min = (_min), \ 314 } 315 316 #define MRS_HWCAP_END { .hwcap = NULL } 317 318 struct mrs_field { 319 const char *name; 320 struct mrs_field_value *values; 321 struct mrs_field_hwcap *hwcaps; 322 uint64_t mask; 323 bool sign; 324 u_int type; 325 u_int shift; 326 }; 327 328 #define MRS_FIELD_HWCAP(_register, _name, _sign, _type, _values, _hwcap) \ 329 { \ 330 .name = #_name, \ 331 .sign = (_sign), \ 332 .type = (_type), \ 333 .shift = _register ## _ ## _name ## _SHIFT, \ 334 .mask = _register ## _ ## _name ## _MASK, \ 335 .values = (_values), \ 336 .hwcaps = (_hwcap), \ 337 } 338 339 #define MRS_FIELD(_register, _name, _sign, _type, _values) \ 340 MRS_FIELD_HWCAP(_register, _name, _sign, _type, _values, NULL) 341 342 #define MRS_FIELD_END { .type = MRS_INVALID, } 343 344 /* ID_AA64AFR0_EL1 */ 345 static struct mrs_field id_aa64afr0_fields[] = { 346 MRS_FIELD_END, 347 }; 348 349 350 /* ID_AA64AFR1_EL1 */ 351 static struct mrs_field id_aa64afr1_fields[] = { 352 MRS_FIELD_END, 353 }; 354 355 356 /* ID_AA64DFR0_EL1 */ 357 static struct mrs_field_value id_aa64dfr0_tracefilt[] = { 358 MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_NONE, ""), 359 MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_8_4, "Trace v8.4"), 360 MRS_FIELD_VALUE_END, 361 }; 362 363 static struct mrs_field_value id_aa64dfr0_doublelock[] = { 364 MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_IMPL, "DoubleLock"), 365 MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_NONE, ""), 366 MRS_FIELD_VALUE_END, 367 }; 368 369 static struct mrs_field_value id_aa64dfr0_pmsver[] = { 370 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_NONE, ""), 371 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE, "SPE"), 372 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_8_3, "SPE v8.3"), 373 MRS_FIELD_VALUE_END, 374 }; 375 376 static struct mrs_field_value id_aa64dfr0_ctx_cmps[] = { 377 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, CTX_CMPs, "CTX BKPT"), 378 MRS_FIELD_VALUE_END, 379 }; 380 381 static struct mrs_field_value id_aa64dfr0_wrps[] = { 382 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, WRPs, "Watchpoint"), 383 MRS_FIELD_VALUE_END, 384 }; 385 386 static struct mrs_field_value id_aa64dfr0_brps[] = { 387 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, BRPs, "Breakpoint"), 388 MRS_FIELD_VALUE_END, 389 }; 390 391 static struct mrs_field_value id_aa64dfr0_pmuver[] = { 392 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_NONE, ""), 393 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3, "PMUv3"), 394 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_1, "PMUv3 v8.1"), 395 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_4, "PMUv3 v8.4"), 396 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_5, "PMUv3 v8.5"), 397 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_IMPL, "IMPL PMU"), 398 MRS_FIELD_VALUE_END, 399 }; 400 401 static struct mrs_field_value id_aa64dfr0_tracever[] = { 402 MRS_FIELD_VALUE(ID_AA64DFR0_TraceVer_NONE, ""), 403 MRS_FIELD_VALUE(ID_AA64DFR0_TraceVer_IMPL, "Trace"), 404 MRS_FIELD_VALUE_END, 405 }; 406 407 static struct mrs_field_value id_aa64dfr0_debugver[] = { 408 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8, "Debugv8"), 409 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_VHE, "Debugv8_VHE"), 410 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_2, "Debugv8.2"), 411 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_4, "Debugv8.4"), 412 MRS_FIELD_VALUE_END, 413 }; 414 415 static struct mrs_field id_aa64dfr0_fields[] = { 416 MRS_FIELD(ID_AA64DFR0, TraceFilt, false, MRS_EXACT, 417 id_aa64dfr0_tracefilt), 418 MRS_FIELD(ID_AA64DFR0, DoubleLock, false, MRS_EXACT, 419 id_aa64dfr0_doublelock), 420 MRS_FIELD(ID_AA64DFR0, PMSVer, false, MRS_EXACT, id_aa64dfr0_pmsver), 421 MRS_FIELD(ID_AA64DFR0, CTX_CMPs, false, MRS_EXACT, 422 id_aa64dfr0_ctx_cmps), 423 MRS_FIELD(ID_AA64DFR0, WRPs, false, MRS_LOWER, id_aa64dfr0_wrps), 424 MRS_FIELD(ID_AA64DFR0, BRPs, false, MRS_LOWER, id_aa64dfr0_brps), 425 MRS_FIELD(ID_AA64DFR0, PMUVer, false, MRS_EXACT, id_aa64dfr0_pmuver), 426 MRS_FIELD(ID_AA64DFR0, TraceVer, false, MRS_EXACT, 427 id_aa64dfr0_tracever), 428 MRS_FIELD(ID_AA64DFR0, DebugVer, false, MRS_EXACT_VAL(0x6), 429 id_aa64dfr0_debugver), 430 MRS_FIELD_END, 431 }; 432 433 434 /* ID_AA64DFR1_EL1 */ 435 static struct mrs_field id_aa64dfr1_fields[] = { 436 MRS_FIELD_END, 437 }; 438 439 440 /* ID_AA64ISAR0_EL1 */ 441 static struct mrs_field_value id_aa64isar0_rndr[] = { 442 MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_NONE, ""), 443 MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_IMPL, "RNG"), 444 MRS_FIELD_VALUE_END, 445 }; 446 447 static struct mrs_field_hwcap id_aa64isar0_rndr_caps[] = { 448 MRS_HWCAP(&elf_hwcap2, HWCAP2_RNG, ID_AA64ISAR0_RNDR_IMPL), 449 MRS_HWCAP_END 450 }; 451 452 static struct mrs_field_value id_aa64isar0_tlb[] = { 453 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_NONE, ""), 454 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOS, "TLBI-OS"), 455 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOSR, "TLBI-OSR"), 456 MRS_FIELD_VALUE_END, 457 }; 458 459 static struct mrs_field_value id_aa64isar0_ts[] = { 460 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_NONE, ""), 461 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_4, "CondM-8.4"), 462 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_5, "CondM-8.5"), 463 MRS_FIELD_VALUE_END, 464 }; 465 466 static struct mrs_field_hwcap id_aa64isar0_ts_caps[] = { 467 MRS_HWCAP(&elf_hwcap, HWCAP_FLAGM, ID_AA64ISAR0_TS_CondM_8_4), 468 MRS_HWCAP(&elf_hwcap2, HWCAP2_FLAGM2, ID_AA64ISAR0_TS_CondM_8_5), 469 MRS_HWCAP_END 470 }; 471 472 static struct mrs_field_value id_aa64isar0_fhm[] = { 473 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, FHM, NONE, IMPL), 474 MRS_FIELD_VALUE_END, 475 }; 476 477 static struct mrs_field_hwcap id_aa64isar0_fhm_caps[] = { 478 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMDFHM, ID_AA64ISAR0_FHM_IMPL), 479 MRS_HWCAP_END 480 }; 481 482 static struct mrs_field_value id_aa64isar0_dp[] = { 483 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, DP, NONE, IMPL), 484 MRS_FIELD_VALUE_END, 485 }; 486 487 static struct mrs_field_hwcap id_aa64isar0_dp_caps[] = { 488 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMDDP, ID_AA64ISAR0_DP_IMPL), 489 MRS_HWCAP_END 490 }; 491 492 static struct mrs_field_value id_aa64isar0_sm4[] = { 493 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM4, NONE, IMPL), 494 MRS_FIELD_VALUE_END, 495 }; 496 497 static struct mrs_field_hwcap id_aa64isar0_sm4_caps[] = { 498 MRS_HWCAP(&elf_hwcap, HWCAP_SM4, ID_AA64ISAR0_SM4_IMPL), 499 MRS_HWCAP_END 500 }; 501 502 static struct mrs_field_value id_aa64isar0_sm3[] = { 503 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM3, NONE, IMPL), 504 MRS_FIELD_VALUE_END, 505 }; 506 507 static struct mrs_field_hwcap id_aa64isar0_sm3_caps[] = { 508 MRS_HWCAP(&elf_hwcap, HWCAP_SM3, ID_AA64ISAR0_SM3_IMPL), 509 MRS_HWCAP_END 510 }; 511 512 static struct mrs_field_value id_aa64isar0_sha3[] = { 513 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA3, NONE, IMPL), 514 MRS_FIELD_VALUE_END, 515 }; 516 517 static struct mrs_field_hwcap id_aa64isar0_sha3_caps[] = { 518 MRS_HWCAP(&elf_hwcap, HWCAP_SHA3, ID_AA64ISAR0_SHA3_IMPL), 519 MRS_HWCAP_END 520 }; 521 522 static struct mrs_field_value id_aa64isar0_rdm[] = { 523 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, RDM, NONE, IMPL), 524 MRS_FIELD_VALUE_END, 525 }; 526 527 static struct mrs_field_hwcap id_aa64isar0_rdm_caps[] = { 528 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMDRDM, ID_AA64ISAR0_RDM_IMPL), 529 MRS_HWCAP_END 530 }; 531 532 static struct mrs_field_value id_aa64isar0_atomic[] = { 533 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, Atomic, NONE, IMPL), 534 MRS_FIELD_VALUE_END, 535 }; 536 537 static struct mrs_field_hwcap id_aa64isar0_atomic_caps[] = { 538 MRS_HWCAP(&elf_hwcap, HWCAP_ATOMICS, ID_AA64ISAR0_Atomic_IMPL), 539 MRS_HWCAP_END 540 }; 541 542 static struct mrs_field_value id_aa64isar0_crc32[] = { 543 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, CRC32, NONE, BASE), 544 MRS_FIELD_VALUE_END, 545 }; 546 547 static struct mrs_field_hwcap id_aa64isar0_crc32_caps[] = { 548 MRS_HWCAP(&elf_hwcap, HWCAP_CRC32, ID_AA64ISAR0_CRC32_BASE), 549 MRS_HWCAP_END 550 }; 551 552 static struct mrs_field_value id_aa64isar0_sha2[] = { 553 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA2, NONE, BASE), 554 MRS_FIELD_VALUE(ID_AA64ISAR0_SHA2_512, "SHA2+SHA512"), 555 MRS_FIELD_VALUE_END, 556 }; 557 558 static struct mrs_field_hwcap id_aa64isar0_sha2_caps[] = { 559 MRS_HWCAP(&elf_hwcap, HWCAP_SHA2, ID_AA64ISAR0_SHA2_BASE), 560 MRS_HWCAP(&elf_hwcap, HWCAP_SHA512, ID_AA64ISAR0_SHA2_512), 561 MRS_HWCAP_END 562 }; 563 564 static struct mrs_field_value id_aa64isar0_sha1[] = { 565 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA1, NONE, BASE), 566 MRS_FIELD_VALUE_END, 567 }; 568 569 static struct mrs_field_hwcap id_aa64isar0_sha1_caps[] = { 570 MRS_HWCAP(&elf_hwcap, HWCAP_SHA1, ID_AA64ISAR0_SHA1_BASE), 571 MRS_HWCAP_END 572 }; 573 574 static struct mrs_field_value id_aa64isar0_aes[] = { 575 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, AES, NONE, BASE), 576 MRS_FIELD_VALUE(ID_AA64ISAR0_AES_PMULL, "AES+PMULL"), 577 MRS_FIELD_VALUE_END, 578 }; 579 580 static struct mrs_field_hwcap id_aa64isar0_aes_caps[] = { 581 MRS_HWCAP(&elf_hwcap, HWCAP_AES, ID_AA64ISAR0_AES_BASE), 582 MRS_HWCAP(&elf_hwcap, HWCAP_PMULL, ID_AA64ISAR0_AES_PMULL), 583 MRS_HWCAP_END 584 }; 585 586 static struct mrs_field id_aa64isar0_fields[] = { 587 MRS_FIELD_HWCAP(ID_AA64ISAR0, RNDR, false, MRS_LOWER, 588 id_aa64isar0_rndr, id_aa64isar0_rndr_caps), 589 MRS_FIELD(ID_AA64ISAR0, TLB, false, MRS_EXACT, id_aa64isar0_tlb), 590 MRS_FIELD_HWCAP(ID_AA64ISAR0, TS, false, MRS_LOWER, id_aa64isar0_ts, 591 id_aa64isar0_ts_caps), 592 MRS_FIELD_HWCAP(ID_AA64ISAR0, FHM, false, MRS_LOWER, id_aa64isar0_fhm, 593 id_aa64isar0_fhm_caps), 594 MRS_FIELD_HWCAP(ID_AA64ISAR0, DP, false, MRS_LOWER, id_aa64isar0_dp, 595 id_aa64isar0_dp_caps), 596 MRS_FIELD_HWCAP(ID_AA64ISAR0, SM4, false, MRS_LOWER, id_aa64isar0_sm4, 597 id_aa64isar0_sm4_caps), 598 MRS_FIELD_HWCAP(ID_AA64ISAR0, SM3, false, MRS_LOWER, id_aa64isar0_sm3, 599 id_aa64isar0_sm3_caps), 600 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA3, false, MRS_LOWER, id_aa64isar0_sha3, 601 id_aa64isar0_sha3_caps), 602 MRS_FIELD_HWCAP(ID_AA64ISAR0, RDM, false, MRS_LOWER, id_aa64isar0_rdm, 603 id_aa64isar0_rdm_caps), 604 MRS_FIELD_HWCAP(ID_AA64ISAR0, Atomic, false, MRS_LOWER, 605 id_aa64isar0_atomic, id_aa64isar0_atomic_caps), 606 MRS_FIELD_HWCAP(ID_AA64ISAR0, CRC32, false, MRS_LOWER, 607 id_aa64isar0_crc32, id_aa64isar0_crc32_caps), 608 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA2, false, MRS_LOWER, id_aa64isar0_sha2, 609 id_aa64isar0_sha2_caps), 610 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA1, false, MRS_LOWER, 611 id_aa64isar0_sha1, id_aa64isar0_sha1_caps), 612 MRS_FIELD_HWCAP(ID_AA64ISAR0, AES, false, MRS_LOWER, id_aa64isar0_aes, 613 id_aa64isar0_aes_caps), 614 MRS_FIELD_END, 615 }; 616 617 618 /* ID_AA64ISAR1_EL1 */ 619 static struct mrs_field_value id_aa64isar1_i8mm[] = { 620 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, I8MM, NONE, IMPL), 621 MRS_FIELD_VALUE_END, 622 }; 623 624 static struct mrs_field_hwcap id_aa64isar1_i8mm_caps[] = { 625 MRS_HWCAP(&elf_hwcap2, HWCAP2_I8MM, ID_AA64ISAR1_I8MM_IMPL), 626 MRS_HWCAP_END 627 }; 628 629 static struct mrs_field_value id_aa64isar1_dgh[] = { 630 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, DGH, NONE, IMPL), 631 MRS_FIELD_VALUE_END, 632 }; 633 634 static struct mrs_field_hwcap id_aa64isar1_dgh_caps[] = { 635 MRS_HWCAP(&elf_hwcap2, HWCAP2_DGH, ID_AA64ISAR1_DGH_IMPL), 636 MRS_HWCAP_END 637 }; 638 639 static struct mrs_field_value id_aa64isar1_bf16[] = { 640 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, BF16, NONE, IMPL), 641 MRS_FIELD_VALUE_END, 642 }; 643 644 static struct mrs_field_hwcap id_aa64isar1_bf16_caps[] = { 645 MRS_HWCAP(&elf_hwcap2, HWCAP2_BF16, ID_AA64ISAR1_BF16_IMPL), 646 MRS_HWCAP_END 647 }; 648 649 static struct mrs_field_value id_aa64isar1_specres[] = { 650 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_NONE, ""), 651 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_IMPL, "PredInv"), 652 MRS_FIELD_VALUE_END, 653 }; 654 655 static struct mrs_field_value id_aa64isar1_sb[] = { 656 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, SB, NONE, IMPL), 657 MRS_FIELD_VALUE_END, 658 }; 659 660 static struct mrs_field_hwcap id_aa64isar1_sb_caps[] = { 661 MRS_HWCAP(&elf_hwcap, HWCAP_SB, ID_AA64ISAR1_SB_IMPL), 662 MRS_HWCAP_END 663 }; 664 665 static struct mrs_field_value id_aa64isar1_frintts[] = { 666 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FRINTTS, NONE, IMPL), 667 MRS_FIELD_VALUE_END, 668 }; 669 670 static struct mrs_field_hwcap id_aa64isar1_frintts_caps[] = { 671 MRS_HWCAP(&elf_hwcap2, HWCAP2_FRINT, ID_AA64ISAR1_FRINTTS_IMPL), 672 MRS_HWCAP_END 673 }; 674 675 static struct mrs_field_value id_aa64isar1_gpi[] = { 676 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPI, NONE, IMPL), 677 MRS_FIELD_VALUE_END, 678 }; 679 680 static struct mrs_field_hwcap id_aa64isar1_gpi_caps[] = { 681 MRS_HWCAP(&elf_hwcap, HWCAP_PACG, ID_AA64ISAR1_GPI_IMPL), 682 MRS_HWCAP_END 683 }; 684 685 static struct mrs_field_value id_aa64isar1_gpa[] = { 686 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPA, NONE, IMPL), 687 MRS_FIELD_VALUE_END, 688 }; 689 690 static struct mrs_field_hwcap id_aa64isar1_gpa_caps[] = { 691 MRS_HWCAP(&elf_hwcap, HWCAP_PACG, ID_AA64ISAR1_GPA_IMPL), 692 MRS_HWCAP_END 693 }; 694 695 static struct mrs_field_value id_aa64isar1_lrcpc[] = { 696 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_NONE, ""), 697 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_3, "RCPC-8.3"), 698 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_4, "RCPC-8.4"), 699 MRS_FIELD_VALUE_END, 700 }; 701 702 static struct mrs_field_hwcap id_aa64isar1_lrcpc_caps[] = { 703 MRS_HWCAP(&elf_hwcap, HWCAP_LRCPC, ID_AA64ISAR1_LRCPC_RCPC_8_3), 704 MRS_HWCAP(&elf_hwcap, HWCAP_ILRCPC, ID_AA64ISAR1_LRCPC_RCPC_8_4), 705 MRS_HWCAP_END 706 }; 707 708 static struct mrs_field_value id_aa64isar1_fcma[] = { 709 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FCMA, NONE, IMPL), 710 MRS_FIELD_VALUE_END, 711 }; 712 713 static struct mrs_field_hwcap id_aa64isar1_fcma_caps[] = { 714 MRS_HWCAP(&elf_hwcap, HWCAP_FCMA, ID_AA64ISAR1_FCMA_IMPL), 715 MRS_HWCAP_END 716 }; 717 718 static struct mrs_field_value id_aa64isar1_jscvt[] = { 719 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, JSCVT, NONE, IMPL), 720 MRS_FIELD_VALUE_END, 721 }; 722 723 static struct mrs_field_hwcap id_aa64isar1_jscvt_caps[] = { 724 MRS_HWCAP(&elf_hwcap, HWCAP_JSCVT, ID_AA64ISAR1_JSCVT_IMPL), 725 MRS_HWCAP_END 726 }; 727 728 static struct mrs_field_value id_aa64isar1_api[] = { 729 MRS_FIELD_VALUE(ID_AA64ISAR1_API_NONE, ""), 730 MRS_FIELD_VALUE(ID_AA64ISAR1_API_PAC, "API PAC"), 731 MRS_FIELD_VALUE(ID_AA64ISAR1_API_EPAC, "API EPAC"), 732 MRS_FIELD_VALUE(ID_AA64ISAR1_API_EPAC2, "Impl PAuth+EPAC2"), 733 MRS_FIELD_VALUE(ID_AA64ISAR1_API_FPAC, "Impl PAuth+FPAC"), 734 MRS_FIELD_VALUE(ID_AA64ISAR1_API_FPAC_COMBINED, 735 "Impl PAuth+FPAC+Combined"), 736 MRS_FIELD_VALUE_END, 737 }; 738 739 static struct mrs_field_hwcap id_aa64isar1_api_caps[] = { 740 MRS_HWCAP(&elf_hwcap, HWCAP_PACA, ID_AA64ISAR1_API_PAC), 741 MRS_HWCAP_END 742 }; 743 744 static struct mrs_field_value id_aa64isar1_apa[] = { 745 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_NONE, ""), 746 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_PAC, "APA PAC"), 747 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC, "APA EPAC"), 748 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC2, "APA EPAC2"), 749 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC, "APA FPAC"), 750 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC_COMBINED, 751 "APA FPAC+Combined"), 752 MRS_FIELD_VALUE_END, 753 }; 754 755 static struct mrs_field_hwcap id_aa64isar1_apa_caps[] = { 756 MRS_HWCAP(&elf_hwcap, HWCAP_PACA, ID_AA64ISAR1_APA_PAC), 757 MRS_HWCAP_END 758 }; 759 760 static struct mrs_field_value id_aa64isar1_dpb[] = { 761 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_NONE, ""), 762 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVAP, "DCPoP"), 763 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVADP, "DCCVADP"), 764 MRS_FIELD_VALUE_END, 765 }; 766 767 static struct mrs_field_hwcap id_aa64isar1_dpb_caps[] = { 768 MRS_HWCAP(&elf_hwcap, HWCAP_DCPOP, ID_AA64ISAR1_DPB_DCCVAP), 769 MRS_HWCAP(&elf_hwcap2, HWCAP2_DCPODP, ID_AA64ISAR1_DPB_DCCVADP), 770 MRS_HWCAP_END 771 }; 772 773 static struct mrs_field id_aa64isar1_fields[] = { 774 MRS_FIELD_HWCAP(ID_AA64ISAR1, I8MM, false, MRS_LOWER, 775 id_aa64isar1_i8mm, id_aa64isar1_i8mm_caps), 776 MRS_FIELD_HWCAP(ID_AA64ISAR1, DGH, false, MRS_LOWER, id_aa64isar1_dgh, 777 id_aa64isar1_dgh_caps), 778 MRS_FIELD_HWCAP(ID_AA64ISAR1, BF16, false, MRS_LOWER, 779 id_aa64isar1_bf16, id_aa64isar1_bf16_caps), 780 MRS_FIELD(ID_AA64ISAR1, SPECRES, false, MRS_EXACT, 781 id_aa64isar1_specres), 782 MRS_FIELD_HWCAP(ID_AA64ISAR1, SB, false, MRS_LOWER, id_aa64isar1_sb, 783 id_aa64isar1_sb_caps), 784 MRS_FIELD_HWCAP(ID_AA64ISAR1, FRINTTS, false, MRS_LOWER, 785 id_aa64isar1_frintts, id_aa64isar1_frintts_caps), 786 MRS_FIELD_HWCAP(ID_AA64ISAR1, GPI, false, MRS_EXACT, id_aa64isar1_gpi, 787 id_aa64isar1_gpi_caps), 788 MRS_FIELD_HWCAP(ID_AA64ISAR1, GPA, false, MRS_EXACT, id_aa64isar1_gpa, 789 id_aa64isar1_gpa_caps), 790 MRS_FIELD_HWCAP(ID_AA64ISAR1, LRCPC, false, MRS_LOWER, 791 id_aa64isar1_lrcpc, id_aa64isar1_lrcpc_caps), 792 MRS_FIELD_HWCAP(ID_AA64ISAR1, FCMA, false, MRS_LOWER, 793 id_aa64isar1_fcma, id_aa64isar1_fcma_caps), 794 MRS_FIELD_HWCAP(ID_AA64ISAR1, JSCVT, false, MRS_LOWER, 795 id_aa64isar1_jscvt, id_aa64isar1_jscvt_caps), 796 MRS_FIELD_HWCAP(ID_AA64ISAR1, API, false, MRS_EXACT, id_aa64isar1_api, 797 id_aa64isar1_api_caps), 798 MRS_FIELD_HWCAP(ID_AA64ISAR1, APA, false, MRS_EXACT, id_aa64isar1_apa, 799 id_aa64isar1_apa_caps), 800 MRS_FIELD_HWCAP(ID_AA64ISAR1, DPB, false, MRS_LOWER, id_aa64isar1_dpb, 801 id_aa64isar1_dpb_caps), 802 MRS_FIELD_END, 803 }; 804 805 806 /* ID_AA64ISAR2_EL1 */ 807 static struct mrs_field_value id_aa64isar2_pac_frac[] = { 808 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, PAC_frac, NONE, IMPL), 809 MRS_FIELD_VALUE_END, 810 }; 811 812 static struct mrs_field_value id_aa64isar2_bc[] = { 813 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, BC, NONE, IMPL), 814 MRS_FIELD_VALUE_END, 815 }; 816 817 static struct mrs_field_value id_aa64isar2_mops[] = { 818 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, MOPS, NONE, IMPL), 819 MRS_FIELD_VALUE_END, 820 }; 821 822 static struct mrs_field_value id_aa64isar2_apa3[] = { 823 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_NONE, ""), 824 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_PAC, "APA3 PAC"), 825 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC, "APA3 EPAC"), 826 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC2, "APA3 EPAC2"), 827 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC, "APA3 FPAC"), 828 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC_COMBINED, 829 "APA3 FPAC+Combined"), 830 MRS_FIELD_VALUE_END, 831 }; 832 833 static struct mrs_field_hwcap id_aa64isar2_apa3_caps[] = { 834 MRS_HWCAP(&elf_hwcap, HWCAP_PACA, ID_AA64ISAR2_APA3_PAC), 835 MRS_HWCAP_END 836 }; 837 838 static struct mrs_field_value id_aa64isar2_gpa3[] = { 839 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, GPA3, NONE, IMPL), 840 MRS_FIELD_VALUE_END, 841 }; 842 843 static struct mrs_field_hwcap id_aa64isar2_gpa3_caps[] = { 844 MRS_HWCAP(&elf_hwcap, HWCAP_PACG, ID_AA64ISAR2_GPA3_IMPL), 845 MRS_HWCAP_END 846 }; 847 848 static struct mrs_field_value id_aa64isar2_rpres[] = { 849 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, RPRES, NONE, IMPL), 850 MRS_FIELD_VALUE_END, 851 }; 852 853 static struct mrs_field_value id_aa64isar2_wfxt[] = { 854 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, WFxT, NONE, IMPL), 855 MRS_FIELD_VALUE_END, 856 }; 857 858 static struct mrs_field id_aa64isar2_fields[] = { 859 MRS_FIELD(ID_AA64ISAR2, PAC_frac, false, MRS_EXACT, 860 id_aa64isar2_pac_frac), 861 MRS_FIELD(ID_AA64ISAR2, BC, false, MRS_EXACT, id_aa64isar2_bc), 862 MRS_FIELD(ID_AA64ISAR2, MOPS, false, MRS_EXACT, id_aa64isar2_mops), 863 MRS_FIELD_HWCAP(ID_AA64ISAR2, APA3, false, MRS_EXACT, 864 id_aa64isar2_apa3, id_aa64isar2_apa3_caps), 865 MRS_FIELD_HWCAP(ID_AA64ISAR2, GPA3, false, MRS_EXACT, 866 id_aa64isar2_gpa3, id_aa64isar2_gpa3_caps), 867 MRS_FIELD(ID_AA64ISAR2, RPRES, false, MRS_EXACT, id_aa64isar2_rpres), 868 MRS_FIELD(ID_AA64ISAR2, WFxT, false, MRS_EXACT, id_aa64isar2_wfxt), 869 MRS_FIELD_END, 870 }; 871 872 873 /* ID_AA64MMFR0_EL1 */ 874 static struct mrs_field_value id_aa64mmfr0_exs[] = { 875 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ExS, ALL, IMPL), 876 MRS_FIELD_VALUE_END, 877 }; 878 879 static struct mrs_field_value id_aa64mmfr0_tgran4_2[] = { 880 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_TGran4, ""), 881 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_NONE, "No S2 TGran4"), 882 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_IMPL, "S2 TGran4"), 883 MRS_FIELD_VALUE_END, 884 }; 885 886 static struct mrs_field_value id_aa64mmfr0_tgran64_2[] = { 887 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_TGran64, ""), 888 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_NONE, "No S2 TGran64"), 889 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_IMPL, "S2 TGran64"), 890 MRS_FIELD_VALUE_END, 891 }; 892 893 static struct mrs_field_value id_aa64mmfr0_tgran16_2[] = { 894 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_TGran16, ""), 895 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_NONE, "No S2 TGran16"), 896 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_IMPL, "S2 TGran16"), 897 MRS_FIELD_VALUE_END, 898 }; 899 900 static struct mrs_field_value id_aa64mmfr0_tgran4[] = { 901 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4,NONE, IMPL), 902 MRS_FIELD_VALUE_END, 903 }; 904 905 static struct mrs_field_value id_aa64mmfr0_tgran64[] = { 906 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran64, NONE, IMPL), 907 MRS_FIELD_VALUE_END, 908 }; 909 910 static struct mrs_field_value id_aa64mmfr0_tgran16[] = { 911 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran16, NONE, IMPL), 912 MRS_FIELD_VALUE_END, 913 }; 914 915 static struct mrs_field_value id_aa64mmfr0_bigendel0[] = { 916 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, BigEndEL0, FIXED, MIXED), 917 MRS_FIELD_VALUE_END, 918 }; 919 920 static struct mrs_field_value id_aa64mmfr0_snsmem[] = { 921 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, SNSMem, NONE, DISTINCT), 922 MRS_FIELD_VALUE_END, 923 }; 924 925 static struct mrs_field_value id_aa64mmfr0_bigend[] = { 926 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, BigEnd, FIXED, MIXED), 927 MRS_FIELD_VALUE_END, 928 }; 929 930 static struct mrs_field_value id_aa64mmfr0_asidbits[] = { 931 MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_8, "8bit ASID"), 932 MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_16, "16bit ASID"), 933 MRS_FIELD_VALUE_END, 934 }; 935 936 static struct mrs_field_value id_aa64mmfr0_parange[] = { 937 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4G, "4GB PA"), 938 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_64G, "64GB PA"), 939 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_1T, "1TB PA"), 940 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4T, "4TB PA"), 941 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_16T, "16TB PA"), 942 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_256T, "256TB PA"), 943 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4P, "4PB PA"), 944 MRS_FIELD_VALUE_END, 945 }; 946 947 static struct mrs_field id_aa64mmfr0_fields[] = { 948 MRS_FIELD(ID_AA64MMFR0, ExS, false, MRS_EXACT, id_aa64mmfr0_exs), 949 MRS_FIELD(ID_AA64MMFR0, TGran4_2, false, MRS_EXACT, 950 id_aa64mmfr0_tgran4_2), 951 MRS_FIELD(ID_AA64MMFR0, TGran64_2, false, MRS_EXACT, 952 id_aa64mmfr0_tgran64_2), 953 MRS_FIELD(ID_AA64MMFR0, TGran16_2, false, MRS_EXACT, 954 id_aa64mmfr0_tgran16_2), 955 MRS_FIELD(ID_AA64MMFR0, TGran4, false, MRS_EXACT, id_aa64mmfr0_tgran4), 956 MRS_FIELD(ID_AA64MMFR0, TGran64, false, MRS_EXACT, 957 id_aa64mmfr0_tgran64), 958 MRS_FIELD(ID_AA64MMFR0, TGran16, false, MRS_EXACT, 959 id_aa64mmfr0_tgran16), 960 MRS_FIELD(ID_AA64MMFR0, BigEndEL0, false, MRS_EXACT, 961 id_aa64mmfr0_bigendel0), 962 MRS_FIELD(ID_AA64MMFR0, SNSMem, false, MRS_EXACT, id_aa64mmfr0_snsmem), 963 MRS_FIELD(ID_AA64MMFR0, BigEnd, false, MRS_EXACT, id_aa64mmfr0_bigend), 964 MRS_FIELD(ID_AA64MMFR0, ASIDBits, false, MRS_EXACT, 965 id_aa64mmfr0_asidbits), 966 MRS_FIELD(ID_AA64MMFR0, PARange, false, MRS_EXACT, 967 id_aa64mmfr0_parange), 968 MRS_FIELD_END, 969 }; 970 971 972 /* ID_AA64MMFR1_EL1 */ 973 static struct mrs_field_value id_aa64mmfr1_xnx[] = { 974 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, XNX, NONE, IMPL), 975 MRS_FIELD_VALUE_END, 976 }; 977 978 static struct mrs_field_value id_aa64mmfr1_specsei[] = { 979 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, SpecSEI, NONE, IMPL), 980 MRS_FIELD_VALUE_END, 981 }; 982 983 static struct mrs_field_value id_aa64mmfr1_pan[] = { 984 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, PAN, NONE, IMPL), 985 MRS_FIELD_VALUE(ID_AA64MMFR1_PAN_ATS1E1, "PAN+ATS1E1"), 986 MRS_FIELD_VALUE_END, 987 }; 988 989 static struct mrs_field_value id_aa64mmfr1_lo[] = { 990 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, LO, NONE, IMPL), 991 MRS_FIELD_VALUE_END, 992 }; 993 994 static struct mrs_field_value id_aa64mmfr1_hpds[] = { 995 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_NONE, ""), 996 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_HPD, "HPD"), 997 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_TTPBHA, "HPD+TTPBHA"), 998 MRS_FIELD_VALUE_END, 999 }; 1000 1001 static struct mrs_field_value id_aa64mmfr1_vh[] = { 1002 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, VH, NONE, IMPL), 1003 MRS_FIELD_VALUE_END, 1004 }; 1005 1006 static struct mrs_field_value id_aa64mmfr1_vmidbits[] = { 1007 MRS_FIELD_VALUE(ID_AA64MMFR1_VMIDBits_8, "8bit VMID"), 1008 MRS_FIELD_VALUE(ID_AA64MMFR1_VMIDBits_16, "16bit VMID"), 1009 MRS_FIELD_VALUE_END, 1010 }; 1011 1012 static struct mrs_field_value id_aa64mmfr1_hafdbs[] = { 1013 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_NONE, ""), 1014 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_AF, "HAF"), 1015 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_AF_DBS, "HAF+DS"), 1016 MRS_FIELD_VALUE_END, 1017 }; 1018 1019 static struct mrs_field id_aa64mmfr1_fields[] = { 1020 MRS_FIELD(ID_AA64MMFR1, XNX, false, MRS_EXACT, id_aa64mmfr1_xnx), 1021 MRS_FIELD(ID_AA64MMFR1, SpecSEI, false, MRS_EXACT, 1022 id_aa64mmfr1_specsei), 1023 MRS_FIELD(ID_AA64MMFR1, PAN, false, MRS_EXACT, id_aa64mmfr1_pan), 1024 MRS_FIELD(ID_AA64MMFR1, LO, false, MRS_EXACT, id_aa64mmfr1_lo), 1025 MRS_FIELD(ID_AA64MMFR1, HPDS, false, MRS_EXACT, id_aa64mmfr1_hpds), 1026 MRS_FIELD(ID_AA64MMFR1, VH, false, MRS_EXACT, id_aa64mmfr1_vh), 1027 MRS_FIELD(ID_AA64MMFR1, VMIDBits, false, MRS_EXACT, 1028 id_aa64mmfr1_vmidbits), 1029 MRS_FIELD(ID_AA64MMFR1, HAFDBS, false, MRS_EXACT, id_aa64mmfr1_hafdbs), 1030 MRS_FIELD_END, 1031 }; 1032 1033 1034 /* ID_AA64MMFR2_EL1 */ 1035 static struct mrs_field_value id_aa64mmfr2_e0pd[] = { 1036 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, E0PD, NONE, IMPL), 1037 MRS_FIELD_VALUE_END, 1038 }; 1039 1040 static struct mrs_field_value id_aa64mmfr2_evt[] = { 1041 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_NONE, ""), 1042 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_2, "EVT-8.2"), 1043 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_5, "EVT-8.5"), 1044 MRS_FIELD_VALUE_END, 1045 }; 1046 1047 static struct mrs_field_value id_aa64mmfr2_bbm[] = { 1048 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL0, ""), 1049 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL1, "BBM level 1"), 1050 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL2, "BBM level 2"), 1051 MRS_FIELD_VALUE_END, 1052 }; 1053 1054 static struct mrs_field_value id_aa64mmfr2_ttl[] = { 1055 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, TTL, NONE, IMPL), 1056 MRS_FIELD_VALUE_END, 1057 }; 1058 1059 static struct mrs_field_value id_aa64mmfr2_fwb[] = { 1060 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, FWB, NONE, IMPL), 1061 MRS_FIELD_VALUE_END, 1062 }; 1063 1064 static struct mrs_field_value id_aa64mmfr2_ids[] = { 1065 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, IDS, NONE, IMPL), 1066 MRS_FIELD_VALUE_END, 1067 }; 1068 1069 static struct mrs_field_value id_aa64mmfr2_at[] = { 1070 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, AT, NONE, IMPL), 1071 MRS_FIELD_VALUE_END, 1072 }; 1073 1074 static struct mrs_field_hwcap id_aa64mmfr2_at_caps[] = { 1075 MRS_HWCAP(&elf_hwcap, HWCAP_USCAT, ID_AA64MMFR2_AT_IMPL), 1076 MRS_HWCAP_END 1077 }; 1078 1079 static struct mrs_field_value id_aa64mmfr2_st[] = { 1080 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, ST, NONE, IMPL), 1081 MRS_FIELD_VALUE_END, 1082 }; 1083 1084 static struct mrs_field_value id_aa64mmfr2_nv[] = { 1085 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, NV, NONE, 8_3), 1086 MRS_FIELD_VALUE(ID_AA64MMFR2_NV_8_4, "NV v8.4"), 1087 MRS_FIELD_VALUE_END, 1088 }; 1089 1090 static struct mrs_field_value id_aa64mmfr2_ccidx[] = { 1091 MRS_FIELD_VALUE(ID_AA64MMFR2_CCIDX_32, "32bit CCIDX"), 1092 MRS_FIELD_VALUE(ID_AA64MMFR2_CCIDX_64, "64bit CCIDX"), 1093 MRS_FIELD_VALUE_END, 1094 }; 1095 1096 static struct mrs_field_value id_aa64mmfr2_varange[] = { 1097 MRS_FIELD_VALUE(ID_AA64MMFR2_VARange_48, "48bit VA"), 1098 MRS_FIELD_VALUE(ID_AA64MMFR2_VARange_52, "52bit VA"), 1099 MRS_FIELD_VALUE_END, 1100 }; 1101 1102 static struct mrs_field_value id_aa64mmfr2_iesb[] = { 1103 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, IESB, NONE, IMPL), 1104 MRS_FIELD_VALUE_END, 1105 }; 1106 1107 static struct mrs_field_value id_aa64mmfr2_lsm[] = { 1108 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, LSM, NONE, IMPL), 1109 MRS_FIELD_VALUE_END, 1110 }; 1111 1112 static struct mrs_field_value id_aa64mmfr2_uao[] = { 1113 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, UAO, NONE, IMPL), 1114 MRS_FIELD_VALUE_END, 1115 }; 1116 1117 static struct mrs_field_value id_aa64mmfr2_cnp[] = { 1118 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, CnP, NONE, IMPL), 1119 MRS_FIELD_VALUE_END, 1120 }; 1121 1122 static struct mrs_field id_aa64mmfr2_fields[] = { 1123 MRS_FIELD(ID_AA64MMFR2, E0PD, false, MRS_EXACT, id_aa64mmfr2_e0pd), 1124 MRS_FIELD(ID_AA64MMFR2, EVT, false, MRS_EXACT, id_aa64mmfr2_evt), 1125 MRS_FIELD(ID_AA64MMFR2, BBM, false, MRS_EXACT, id_aa64mmfr2_bbm), 1126 MRS_FIELD(ID_AA64MMFR2, TTL, false, MRS_EXACT, id_aa64mmfr2_ttl), 1127 MRS_FIELD(ID_AA64MMFR2, FWB, false, MRS_EXACT, id_aa64mmfr2_fwb), 1128 MRS_FIELD(ID_AA64MMFR2, IDS, false, MRS_EXACT, id_aa64mmfr2_ids), 1129 MRS_FIELD_HWCAP(ID_AA64MMFR2, AT, false, MRS_LOWER, id_aa64mmfr2_at, 1130 id_aa64mmfr2_at_caps), 1131 MRS_FIELD(ID_AA64MMFR2, ST, false, MRS_EXACT, id_aa64mmfr2_st), 1132 MRS_FIELD(ID_AA64MMFR2, NV, false, MRS_EXACT, id_aa64mmfr2_nv), 1133 MRS_FIELD(ID_AA64MMFR2, CCIDX, false, MRS_EXACT, id_aa64mmfr2_ccidx), 1134 MRS_FIELD(ID_AA64MMFR2, VARange, false, MRS_EXACT, 1135 id_aa64mmfr2_varange), 1136 MRS_FIELD(ID_AA64MMFR2, IESB, false, MRS_EXACT, id_aa64mmfr2_iesb), 1137 MRS_FIELD(ID_AA64MMFR2, LSM, false, MRS_EXACT, id_aa64mmfr2_lsm), 1138 MRS_FIELD(ID_AA64MMFR2, UAO, false, MRS_EXACT, id_aa64mmfr2_uao), 1139 MRS_FIELD(ID_AA64MMFR2, CnP, false, MRS_EXACT, id_aa64mmfr2_cnp), 1140 MRS_FIELD_END, 1141 }; 1142 1143 1144 /* ID_AA64PFR0_EL1 */ 1145 static struct mrs_field_value id_aa64pfr0_csv3[] = { 1146 MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""), 1147 MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_ISOLATED, "CSV3"), 1148 MRS_FIELD_VALUE_END, 1149 }; 1150 1151 static struct mrs_field_value id_aa64pfr0_csv2[] = { 1152 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_NONE, ""), 1153 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_ISOLATED, "CSV2"), 1154 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_SCXTNUM, "SCXTNUM"), 1155 MRS_FIELD_VALUE_END, 1156 }; 1157 1158 static struct mrs_field_value id_aa64pfr0_dit[] = { 1159 MRS_FIELD_VALUE(ID_AA64PFR0_DIT_NONE, ""), 1160 MRS_FIELD_VALUE(ID_AA64PFR0_DIT_PSTATE, "PSTATE.DIT"), 1161 MRS_FIELD_VALUE_END, 1162 }; 1163 1164 static struct mrs_field_hwcap id_aa64pfr0_dit_caps[] = { 1165 MRS_HWCAP(&elf_hwcap, HWCAP_DIT, ID_AA64PFR0_DIT_PSTATE), 1166 MRS_HWCAP_END 1167 }; 1168 1169 static struct mrs_field_value id_aa64pfr0_amu[] = { 1170 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_NONE, ""), 1171 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1, "AMUv1"), 1172 MRS_FIELD_VALUE_END, 1173 }; 1174 1175 static struct mrs_field_value id_aa64pfr0_mpam[] = { 1176 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, MPAM, NONE, IMPL), 1177 MRS_FIELD_VALUE_END, 1178 }; 1179 1180 static struct mrs_field_value id_aa64pfr0_sel2[] = { 1181 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SEL2, NONE, IMPL), 1182 MRS_FIELD_VALUE_END, 1183 }; 1184 1185 static struct mrs_field_value id_aa64pfr0_sve[] = { 1186 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SVE, NONE, IMPL), 1187 MRS_FIELD_VALUE_END, 1188 }; 1189 1190 #if 0 1191 /* Enable when we add SVE support */ 1192 static struct mrs_field_hwcap id_aa64pfr0_sve_caps[] = { 1193 MRS_HWCAP(&elf_hwcap, HWCAP_SVE, ID_AA64PFR0_SVE_IMPL), 1194 MRS_HWCAP_END 1195 }; 1196 #endif 1197 1198 static struct mrs_field_value id_aa64pfr0_ras[] = { 1199 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_NONE, ""), 1200 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_IMPL, "RAS"), 1201 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_8_4, "RAS v8.4"), 1202 MRS_FIELD_VALUE_END, 1203 }; 1204 1205 static struct mrs_field_value id_aa64pfr0_gic[] = { 1206 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, GIC, CPUIF_NONE, CPUIF_EN), 1207 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_NONE, ""), 1208 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_EN, "GIC"), 1209 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_4_1, "GIC 4.1"), 1210 MRS_FIELD_VALUE_END, 1211 }; 1212 1213 static struct mrs_field_value id_aa64pfr0_advsimd[] = { 1214 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, AdvSIMD, NONE, IMPL), 1215 MRS_FIELD_VALUE(ID_AA64PFR0_AdvSIMD_HP, "AdvSIMD+HP"), 1216 MRS_FIELD_VALUE_END, 1217 }; 1218 1219 static struct mrs_field_hwcap id_aa64pfr0_advsimd_caps[] = { 1220 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMD, ID_AA64PFR0_AdvSIMD_IMPL), 1221 MRS_HWCAP(&elf_hwcap, HWCAP_ASIMDHP, ID_AA64PFR0_AdvSIMD_HP), 1222 MRS_HWCAP_END 1223 }; 1224 1225 static struct mrs_field_value id_aa64pfr0_fp[] = { 1226 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, FP, NONE, IMPL), 1227 MRS_FIELD_VALUE(ID_AA64PFR0_FP_HP, "FP+HP"), 1228 MRS_FIELD_VALUE_END, 1229 }; 1230 1231 static struct mrs_field_hwcap id_aa64pfr0_fp_caps[] = { 1232 MRS_HWCAP(&elf_hwcap, HWCAP_FP, ID_AA64PFR0_FP_IMPL), 1233 MRS_HWCAP(&elf_hwcap, HWCAP_FPHP, ID_AA64PFR0_FP_HP), 1234 MRS_HWCAP_END 1235 }; 1236 1237 static struct mrs_field_value id_aa64pfr0_el3[] = { 1238 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, EL3, NONE, 64), 1239 MRS_FIELD_VALUE(ID_AA64PFR0_EL3_64_32, "EL3 32"), 1240 MRS_FIELD_VALUE_END, 1241 }; 1242 1243 static struct mrs_field_value id_aa64pfr0_el2[] = { 1244 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, EL2, NONE, 64), 1245 MRS_FIELD_VALUE(ID_AA64PFR0_EL2_64_32, "EL2 32"), 1246 MRS_FIELD_VALUE_END, 1247 }; 1248 1249 static struct mrs_field_value id_aa64pfr0_el1[] = { 1250 MRS_FIELD_VALUE(ID_AA64PFR0_EL1_64, "EL1"), 1251 MRS_FIELD_VALUE(ID_AA64PFR0_EL1_64_32, "EL1 32"), 1252 MRS_FIELD_VALUE_END, 1253 }; 1254 1255 static struct mrs_field_value id_aa64pfr0_el0[] = { 1256 MRS_FIELD_VALUE(ID_AA64PFR0_EL0_64, "EL0"), 1257 MRS_FIELD_VALUE(ID_AA64PFR0_EL0_64_32, "EL0 32"), 1258 MRS_FIELD_VALUE_END, 1259 }; 1260 1261 static struct mrs_field id_aa64pfr0_fields[] = { 1262 MRS_FIELD(ID_AA64PFR0, CSV3, false, MRS_EXACT, id_aa64pfr0_csv3), 1263 MRS_FIELD(ID_AA64PFR0, CSV2, false, MRS_EXACT, id_aa64pfr0_csv2), 1264 MRS_FIELD_HWCAP(ID_AA64PFR0, DIT, false, MRS_LOWER, id_aa64pfr0_dit, 1265 id_aa64pfr0_dit_caps), 1266 MRS_FIELD(ID_AA64PFR0, AMU, false, MRS_EXACT, id_aa64pfr0_amu), 1267 MRS_FIELD(ID_AA64PFR0, MPAM, false, MRS_EXACT, id_aa64pfr0_mpam), 1268 MRS_FIELD(ID_AA64PFR0, SEL2, false, MRS_EXACT, id_aa64pfr0_sel2), 1269 MRS_FIELD(ID_AA64PFR0, SVE, false, MRS_EXACT, id_aa64pfr0_sve), 1270 MRS_FIELD(ID_AA64PFR0, RAS, false, MRS_EXACT, id_aa64pfr0_ras), 1271 MRS_FIELD(ID_AA64PFR0, GIC, false, MRS_EXACT, id_aa64pfr0_gic), 1272 MRS_FIELD_HWCAP(ID_AA64PFR0, AdvSIMD, true, MRS_LOWER, 1273 id_aa64pfr0_advsimd, id_aa64pfr0_advsimd_caps), 1274 MRS_FIELD_HWCAP(ID_AA64PFR0, FP, true, MRS_LOWER, id_aa64pfr0_fp, 1275 id_aa64pfr0_fp_caps), 1276 MRS_FIELD(ID_AA64PFR0, EL3, false, MRS_EXACT, id_aa64pfr0_el3), 1277 MRS_FIELD(ID_AA64PFR0, EL2, false, MRS_EXACT, id_aa64pfr0_el2), 1278 MRS_FIELD(ID_AA64PFR0, EL1, false, MRS_LOWER, id_aa64pfr0_el1), 1279 MRS_FIELD(ID_AA64PFR0, EL0, false, MRS_LOWER, id_aa64pfr0_el0), 1280 MRS_FIELD_END, 1281 }; 1282 1283 1284 /* ID_AA64PFR1_EL1 */ 1285 static struct mrs_field_value id_aa64pfr1_mte[] = { 1286 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_NONE, ""), 1287 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL_EL0, "MTE EL0"), 1288 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL, "MTE"), 1289 MRS_FIELD_VALUE_END, 1290 }; 1291 1292 static struct mrs_field_value id_aa64pfr1_ssbs[] = { 1293 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_NONE, ""), 1294 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE, "PSTATE.SSBS"), 1295 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE_MSR, "PSTATE.SSBS MSR"), 1296 MRS_FIELD_VALUE_END, 1297 }; 1298 1299 static struct mrs_field_hwcap id_aa64pfr1_ssbs_caps[] = { 1300 MRS_HWCAP(&elf_hwcap, HWCAP_SSBS, ID_AA64PFR1_SSBS_PSTATE), 1301 MRS_HWCAP_END 1302 }; 1303 1304 static struct mrs_field_value id_aa64pfr1_bt[] = { 1305 MRS_FIELD_VALUE(ID_AA64PFR1_BT_NONE, ""), 1306 MRS_FIELD_VALUE(ID_AA64PFR1_BT_IMPL, "BTI"), 1307 MRS_FIELD_VALUE_END, 1308 }; 1309 1310 #if 0 1311 /* Enable when we add BTI support */ 1312 static struct mrs_field_hwcap id_aa64pfr1_bt_caps[] = { 1313 MRS_HWCAP(&elf_hwcap2, HWCAP2_BTI, ID_AA64PFR1_BT_IMPL), 1314 MRS_HWCAP_END 1315 }; 1316 #endif 1317 1318 static struct mrs_field id_aa64pfr1_fields[] = { 1319 MRS_FIELD(ID_AA64PFR1, MTE, false, MRS_EXACT, id_aa64pfr1_mte), 1320 MRS_FIELD_HWCAP(ID_AA64PFR1, SSBS, false, MRS_LOWER, id_aa64pfr1_ssbs, 1321 id_aa64pfr1_ssbs_caps), 1322 MRS_FIELD(ID_AA64PFR1, BT, false, MRS_EXACT, id_aa64pfr1_bt), 1323 MRS_FIELD_END, 1324 }; 1325 1326 1327 /* ID_AA64ZFR0_EL1 */ 1328 static struct mrs_field_value id_aa64zfr0_f64mm[] = { 1329 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, F64MM, NONE, IMPL), 1330 MRS_FIELD_VALUE_END, 1331 }; 1332 1333 static struct mrs_field_value id_aa64zfr0_f32mm[] = { 1334 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, F32MM, NONE, IMPL), 1335 MRS_FIELD_VALUE_END, 1336 }; 1337 1338 static struct mrs_field_value id_aa64zfr0_i8mm[] = { 1339 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, I8MM, NONE, IMPL), 1340 MRS_FIELD_VALUE_END, 1341 }; 1342 1343 static struct mrs_field_value id_aa64zfr0_sm4[] = { 1344 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, SM4, NONE, IMPL), 1345 MRS_FIELD_VALUE_END, 1346 }; 1347 1348 static struct mrs_field_value id_aa64zfr0_sha3[] = { 1349 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, SHA3, NONE, IMPL), 1350 MRS_FIELD_VALUE_END, 1351 }; 1352 1353 static struct mrs_field_value id_aa64zfr0_bf16[] = { 1354 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, BF16, NONE, BASE), 1355 MRS_FIELD_VALUE(ID_AA64ZFR0_BF16_EBF, "BF16+EBF"), 1356 MRS_FIELD_VALUE_END, 1357 }; 1358 1359 static struct mrs_field_value id_aa64zfr0_bitperm[] = { 1360 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, BitPerm, NONE, IMPL), 1361 MRS_FIELD_VALUE_END, 1362 }; 1363 1364 static struct mrs_field_value id_aa64zfr0_aes[] = { 1365 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, AES, NONE, BASE), 1366 MRS_FIELD_VALUE(ID_AA64ZFR0_AES_PMULL, "AES+PMULL"), 1367 MRS_FIELD_VALUE_END, 1368 }; 1369 1370 static struct mrs_field_value id_aa64zfr0_svever[] = { 1371 MRS_FIELD_VALUE(ID_AA64ZFR0_SVEver_SVE1, "SVE1"), 1372 MRS_FIELD_VALUE(ID_AA64ZFR0_SVEver_SVE2, "SVE2"), 1373 MRS_FIELD_VALUE_END, 1374 }; 1375 1376 static struct mrs_field id_aa64zfr0_fields[] = { 1377 MRS_FIELD(ID_AA64ZFR0, F64MM, false, MRS_EXACT, id_aa64zfr0_f64mm), 1378 MRS_FIELD(ID_AA64ZFR0, F32MM, false, MRS_EXACT, id_aa64zfr0_f32mm), 1379 MRS_FIELD(ID_AA64ZFR0, I8MM, false, MRS_EXACT, id_aa64zfr0_i8mm), 1380 MRS_FIELD(ID_AA64ZFR0, SM4, false, MRS_EXACT, id_aa64zfr0_sm4), 1381 MRS_FIELD(ID_AA64ZFR0, SHA3, false, MRS_EXACT, id_aa64zfr0_sha3), 1382 MRS_FIELD(ID_AA64ZFR0, BF16, false, MRS_EXACT, id_aa64zfr0_bf16), 1383 MRS_FIELD(ID_AA64ZFR0, BitPerm, false, MRS_EXACT, id_aa64zfr0_bitperm), 1384 MRS_FIELD(ID_AA64ZFR0, AES, false, MRS_EXACT, id_aa64zfr0_aes), 1385 MRS_FIELD(ID_AA64ZFR0, SVEver, false, MRS_EXACT, id_aa64zfr0_svever), 1386 MRS_FIELD_END, 1387 }; 1388 1389 1390 #ifdef COMPAT_FREEBSD32 1391 /* ID_ISAR5_EL1 */ 1392 static struct mrs_field_value id_isar5_vcma[] = { 1393 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, VCMA, NONE, IMPL), 1394 MRS_FIELD_VALUE_END, 1395 }; 1396 1397 static struct mrs_field_value id_isar5_rdm[] = { 1398 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, RDM, NONE, IMPL), 1399 MRS_FIELD_VALUE_END, 1400 }; 1401 1402 static struct mrs_field_value id_isar5_crc32[] = { 1403 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, CRC32, NONE, IMPL), 1404 MRS_FIELD_VALUE_END, 1405 }; 1406 1407 static struct mrs_field_hwcap id_isar5_crc32_caps[] = { 1408 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_CRC32, ID_ISAR5_CRC32_IMPL), 1409 MRS_HWCAP_END 1410 }; 1411 1412 static struct mrs_field_value id_isar5_sha2[] = { 1413 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA2, NONE, IMPL), 1414 MRS_FIELD_VALUE_END, 1415 }; 1416 1417 static struct mrs_field_hwcap id_isar5_sha2_caps[] = { 1418 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_SHA2, ID_ISAR5_SHA2_IMPL), 1419 MRS_HWCAP_END 1420 }; 1421 1422 static struct mrs_field_value id_isar5_sha1[] = { 1423 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA1, NONE, IMPL), 1424 MRS_FIELD_VALUE_END, 1425 }; 1426 1427 static struct mrs_field_hwcap id_isar5_sha1_caps[] = { 1428 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_SHA1, ID_ISAR5_SHA1_IMPL), 1429 MRS_HWCAP_END 1430 }; 1431 1432 static struct mrs_field_value id_isar5_aes[] = { 1433 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, AES, NONE, BASE), 1434 MRS_FIELD_VALUE(ID_ISAR5_AES_VMULL, "AES+VMULL"), 1435 MRS_FIELD_VALUE_END, 1436 }; 1437 1438 static struct mrs_field_hwcap id_isar5_aes_caps[] = { 1439 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_AES, ID_ISAR5_AES_BASE), 1440 MRS_HWCAP(&elf32_hwcap2, HWCAP32_2_PMULL, ID_ISAR5_AES_VMULL), 1441 MRS_HWCAP_END 1442 }; 1443 1444 static struct mrs_field_value id_isar5_sevl[] = { 1445 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SEVL, NOP, IMPL), 1446 MRS_FIELD_VALUE_END, 1447 }; 1448 1449 static struct mrs_field id_isar5_fields[] = { 1450 MRS_FIELD(ID_ISAR5, VCMA, false, MRS_LOWER, id_isar5_vcma), 1451 MRS_FIELD(ID_ISAR5, RDM, false, MRS_LOWER, id_isar5_rdm), 1452 MRS_FIELD_HWCAP(ID_ISAR5, CRC32, false, MRS_LOWER, id_isar5_crc32, 1453 id_isar5_crc32_caps), 1454 MRS_FIELD_HWCAP(ID_ISAR5, SHA2, false, MRS_LOWER, id_isar5_sha2, 1455 id_isar5_sha2_caps), 1456 MRS_FIELD_HWCAP(ID_ISAR5, SHA1, false, MRS_LOWER, id_isar5_sha1, 1457 id_isar5_sha1_caps), 1458 MRS_FIELD_HWCAP(ID_ISAR5, AES, false, MRS_LOWER, id_isar5_aes, 1459 id_isar5_aes_caps), 1460 MRS_FIELD(ID_ISAR5, SEVL, false, MRS_LOWER, id_isar5_sevl), 1461 MRS_FIELD_END, 1462 }; 1463 1464 /* MVFR0 */ 1465 static struct mrs_field_value mvfr0_fpround[] = { 1466 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPRound, NONE, IMPL), 1467 MRS_FIELD_VALUE_END, 1468 }; 1469 1470 static struct mrs_field_value mvfr0_fpsqrt[] = { 1471 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPSqrt, NONE, IMPL), 1472 MRS_FIELD_VALUE_END, 1473 }; 1474 1475 static struct mrs_field_value mvfr0_fpdivide[] = { 1476 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPDivide, NONE, IMPL), 1477 MRS_FIELD_VALUE_END, 1478 }; 1479 1480 static struct mrs_field_value mvfr0_fptrap[] = { 1481 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPTrap, NONE, IMPL), 1482 MRS_FIELD_VALUE_END, 1483 }; 1484 1485 static struct mrs_field_value mvfr0_fpdp[] = { 1486 MRS_FIELD_VALUE(MVFR0_FPDP_NONE, ""), 1487 MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v2, "DP VFPv2"), 1488 MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v3_v4, "DP VFPv3+v4"), 1489 MRS_FIELD_VALUE_END, 1490 }; 1491 1492 static struct mrs_field_hwcap mvfr0_fpdp_caps[] = { 1493 MRS_HWCAP(&elf32_hwcap, HWCAP32_VFP, MVFR0_FPDP_VFP_v2), 1494 MRS_HWCAP(&elf32_hwcap, HWCAP32_VFPv3, MVFR0_FPDP_VFP_v3_v4), 1495 }; 1496 1497 static struct mrs_field_value mvfr0_fpsp[] = { 1498 MRS_FIELD_VALUE(MVFR0_FPSP_NONE, ""), 1499 MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v2, "SP VFPv2"), 1500 MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v3_v4, "SP VFPv3+v4"), 1501 MRS_FIELD_VALUE_END, 1502 }; 1503 1504 static struct mrs_field_value mvfr0_simdreg[] = { 1505 MRS_FIELD_VALUE(MVFR0_SIMDReg_NONE, ""), 1506 MRS_FIELD_VALUE(MVFR0_SIMDReg_FP, "FP 16x64"), 1507 MRS_FIELD_VALUE(MVFR0_SIMDReg_AdvSIMD, "AdvSIMD"), 1508 MRS_FIELD_VALUE_END, 1509 }; 1510 1511 static struct mrs_field mvfr0_fields[] = { 1512 MRS_FIELD(MVFR0, FPRound, false, MRS_LOWER, mvfr0_fpround), 1513 MRS_FIELD(MVFR0, FPSqrt, false, MRS_LOWER, mvfr0_fpsqrt), 1514 MRS_FIELD(MVFR0, FPDivide, false, MRS_LOWER, mvfr0_fpdivide), 1515 MRS_FIELD(MVFR0, FPTrap, false, MRS_LOWER, mvfr0_fptrap), 1516 MRS_FIELD_HWCAP(MVFR0, FPDP, false, MRS_LOWER, mvfr0_fpdp, 1517 mvfr0_fpdp_caps), 1518 MRS_FIELD(MVFR0, FPSP, false, MRS_LOWER, mvfr0_fpsp), 1519 MRS_FIELD(MVFR0, SIMDReg, false, MRS_LOWER, mvfr0_simdreg), 1520 MRS_FIELD_END, 1521 }; 1522 1523 /* MVFR1 */ 1524 static struct mrs_field_value mvfr1_simdfmac[] = { 1525 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDFMAC, NONE, IMPL), 1526 MRS_FIELD_VALUE_END, 1527 }; 1528 1529 static struct mrs_field_hwcap mvfr1_simdfmac_caps[] = { 1530 MRS_HWCAP(&elf32_hwcap, HWCAP32_VFPv4, MVFR1_SIMDFMAC_IMPL), 1531 MRS_HWCAP_END 1532 }; 1533 1534 static struct mrs_field_value mvfr1_fphp[] = { 1535 MRS_FIELD_VALUE(MVFR1_FPHP_NONE, ""), 1536 MRS_FIELD_VALUE(MVFR1_FPHP_CONV_SP, "FPHP SP Conv"), 1537 MRS_FIELD_VALUE(MVFR1_FPHP_CONV_DP, "FPHP DP Conv"), 1538 MRS_FIELD_VALUE(MVFR1_FPHP_ARITH, "FPHP Arith"), 1539 MRS_FIELD_VALUE_END, 1540 }; 1541 1542 static struct mrs_field_value mvfr1_simdhp[] = { 1543 MRS_FIELD_VALUE(MVFR1_SIMDHP_NONE, ""), 1544 MRS_FIELD_VALUE(MVFR1_SIMDHP_CONV_SP, "SIMDHP SP Conv"), 1545 MRS_FIELD_VALUE(MVFR1_SIMDHP_ARITH, "SIMDHP Arith"), 1546 MRS_FIELD_VALUE_END, 1547 }; 1548 1549 static struct mrs_field_value mvfr1_simdsp[] = { 1550 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDSP, NONE, IMPL), 1551 MRS_FIELD_VALUE_END, 1552 }; 1553 1554 static struct mrs_field_value mvfr1_simdint[] = { 1555 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDInt, NONE, IMPL), 1556 MRS_FIELD_VALUE_END, 1557 }; 1558 1559 static struct mrs_field_value mvfr1_simdls[] = { 1560 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDLS, NONE, IMPL), 1561 MRS_FIELD_VALUE_END, 1562 }; 1563 1564 static struct mrs_field_hwcap mvfr1_simdls_caps[] = { 1565 MRS_HWCAP(&elf32_hwcap, HWCAP32_VFPv4, MVFR1_SIMDFMAC_IMPL), 1566 MRS_HWCAP_END 1567 }; 1568 1569 static struct mrs_field_value mvfr1_fpdnan[] = { 1570 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPDNaN, NONE, IMPL), 1571 MRS_FIELD_VALUE_END, 1572 }; 1573 1574 static struct mrs_field_value mvfr1_fpftz[] = { 1575 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPFtZ, NONE, IMPL), 1576 MRS_FIELD_VALUE_END, 1577 }; 1578 1579 static struct mrs_field mvfr1_fields[] = { 1580 MRS_FIELD_HWCAP(MVFR1, SIMDFMAC, false, MRS_LOWER, mvfr1_simdfmac, 1581 mvfr1_simdfmac_caps), 1582 MRS_FIELD(MVFR1, FPHP, false, MRS_LOWER, mvfr1_fphp), 1583 MRS_FIELD(MVFR1, SIMDHP, false, MRS_LOWER, mvfr1_simdhp), 1584 MRS_FIELD(MVFR1, SIMDSP, false, MRS_LOWER, mvfr1_simdsp), 1585 MRS_FIELD(MVFR1, SIMDInt, false, MRS_LOWER, mvfr1_simdint), 1586 MRS_FIELD_HWCAP(MVFR1, SIMDLS, false, MRS_LOWER, mvfr1_simdls, 1587 mvfr1_simdls_caps), 1588 MRS_FIELD(MVFR1, FPDNaN, false, MRS_LOWER, mvfr1_fpdnan), 1589 MRS_FIELD(MVFR1, FPFtZ, false, MRS_LOWER, mvfr1_fpftz), 1590 MRS_FIELD_END, 1591 }; 1592 #endif /* COMPAT_FREEBSD32 */ 1593 1594 struct mrs_user_reg { 1595 u_int reg; 1596 u_int CRm; 1597 u_int Op2; 1598 size_t offset; 1599 struct mrs_field *fields; 1600 }; 1601 1602 #define USER_REG(name, field_name) \ 1603 { \ 1604 .reg = name, \ 1605 .CRm = name##_CRm, \ 1606 .Op2 = name##_op2, \ 1607 .offset = __offsetof(struct cpu_desc, field_name), \ 1608 .fields = field_name##_fields, \ 1609 } 1610 static struct mrs_user_reg user_regs[] = { 1611 USER_REG(ID_AA64DFR0_EL1, id_aa64dfr0), 1612 1613 USER_REG(ID_AA64ISAR0_EL1, id_aa64isar0), 1614 USER_REG(ID_AA64ISAR1_EL1, id_aa64isar1), 1615 1616 USER_REG(ID_AA64MMFR0_EL1, id_aa64mmfr0), 1617 USER_REG(ID_AA64MMFR1_EL1, id_aa64mmfr1), 1618 USER_REG(ID_AA64MMFR2_EL1, id_aa64mmfr2), 1619 1620 USER_REG(ID_AA64PFR0_EL1, id_aa64pfr0), 1621 USER_REG(ID_AA64PFR1_EL1, id_aa64pfr1), 1622 #ifdef COMPAT_FREEBSD32 1623 USER_REG(ID_ISAR5_EL1, id_isar5), 1624 1625 USER_REG(MVFR0_EL1, mvfr0), 1626 USER_REG(MVFR1_EL1, mvfr1), 1627 #endif /* COMPAT_FREEBSD32 */ 1628 }; 1629 1630 #define CPU_DESC_FIELD(desc, idx) \ 1631 *(uint64_t *)((char *)&(desc) + user_regs[(idx)].offset) 1632 1633 static int 1634 user_mrs_handler(vm_offset_t va, uint32_t insn, struct trapframe *frame, 1635 uint32_t esr) 1636 { 1637 uint64_t value; 1638 int CRm, Op2, i, reg; 1639 1640 if ((insn & MRS_MASK) != MRS_VALUE) 1641 return (0); 1642 1643 /* 1644 * We only emulate Op0 == 3, Op1 == 0, CRn == 0, CRm == {0, 4-7}. 1645 * These are in the EL1 CPU identification space. 1646 * CRm == 0 holds MIDR_EL1, MPIDR_EL1, and REVID_EL1. 1647 * CRm == {4-7} holds the ID_AA64 registers. 1648 * 1649 * For full details see the ARMv8 ARM (ARM DDI 0487C.a) 1650 * Table D9-2 System instruction encodings for non-Debug System 1651 * register accesses. 1652 */ 1653 if (mrs_Op0(insn) != 3 || mrs_Op1(insn) != 0 || mrs_CRn(insn) != 0) 1654 return (0); 1655 1656 CRm = mrs_CRm(insn); 1657 if (CRm > 7 || (CRm < 4 && CRm != 0)) 1658 return (0); 1659 1660 Op2 = mrs_Op2(insn); 1661 value = 0; 1662 1663 for (i = 0; i < nitems(user_regs); i++) { 1664 if (user_regs[i].CRm == CRm && user_regs[i].Op2 == Op2) { 1665 value = CPU_DESC_FIELD(user_cpu_desc, i); 1666 break; 1667 } 1668 } 1669 1670 if (CRm == 0) { 1671 switch (Op2) { 1672 case 0: 1673 value = READ_SPECIALREG(midr_el1); 1674 break; 1675 case 5: 1676 value = READ_SPECIALREG(mpidr_el1); 1677 break; 1678 case 6: 1679 value = READ_SPECIALREG(revidr_el1); 1680 break; 1681 default: 1682 return (0); 1683 } 1684 } 1685 1686 /* 1687 * We will handle this instruction, move to the next so we 1688 * don't trap here again. 1689 */ 1690 frame->tf_elr += INSN_SIZE; 1691 1692 reg = MRS_REGISTER(insn); 1693 /* If reg is 31 then write to xzr, i.e. do nothing */ 1694 if (reg == 31) 1695 return (1); 1696 1697 if (reg < nitems(frame->tf_x)) 1698 frame->tf_x[reg] = value; 1699 else if (reg == 30) 1700 frame->tf_lr = value; 1701 1702 return (1); 1703 } 1704 1705 bool 1706 extract_user_id_field(u_int reg, u_int field_shift, uint8_t *val) 1707 { 1708 uint64_t value; 1709 int i; 1710 1711 for (i = 0; i < nitems(user_regs); i++) { 1712 if (user_regs[i].reg == reg) { 1713 value = CPU_DESC_FIELD(user_cpu_desc, i); 1714 *val = value >> field_shift; 1715 return (true); 1716 } 1717 } 1718 1719 return (false); 1720 } 1721 1722 bool 1723 get_kernel_reg(u_int reg, uint64_t *val) 1724 { 1725 int i; 1726 1727 for (i = 0; i < nitems(user_regs); i++) { 1728 if (user_regs[i].reg == reg) { 1729 *val = CPU_DESC_FIELD(kern_cpu_desc, i); 1730 return (true); 1731 } 1732 } 1733 1734 return (false); 1735 } 1736 1737 /* 1738 * Compares two field values that may be signed or unsigned. 1739 * Returns: 1740 * < 0 when a is less than b 1741 * = 0 when a equals b 1742 * > 0 when a is greater than b 1743 */ 1744 static int 1745 mrs_field_cmp(uint64_t a, uint64_t b, u_int shift, int width, bool sign) 1746 { 1747 uint64_t mask; 1748 1749 KASSERT(width > 0 && width < 64, ("%s: Invalid width %d", __func__, 1750 width)); 1751 1752 mask = (1ul << width) - 1; 1753 /* Move the field to the lower bits */ 1754 a = (a >> shift) & mask; 1755 b = (b >> shift) & mask; 1756 1757 if (sign) { 1758 /* 1759 * The field is signed. Toggle the upper bit so the comparison 1760 * works on unsigned values as this makes positive numbers, 1761 * i.e. those with a 0 bit, larger than negative numbers, 1762 * i.e. those with a 1 bit, in an unsigned comparison. 1763 */ 1764 a ^= 1ul << (width - 1); 1765 b ^= 1ul << (width - 1); 1766 } 1767 1768 return (a - b); 1769 } 1770 1771 static uint64_t 1772 update_lower_register(uint64_t val, uint64_t new_val, u_int shift, 1773 int width, bool sign) 1774 { 1775 uint64_t mask; 1776 1777 KASSERT(width > 0 && width < 64, ("%s: Invalid width %d", __func__, 1778 width)); 1779 1780 /* 1781 * If the new value is less than the existing value update it. 1782 */ 1783 if (mrs_field_cmp(new_val, val, shift, width, sign) < 0) { 1784 mask = (1ul << width) - 1; 1785 val &= ~(mask << shift); 1786 val |= new_val & (mask << shift); 1787 } 1788 1789 return (val); 1790 } 1791 1792 void 1793 update_special_regs(u_int cpu) 1794 { 1795 struct mrs_field *fields; 1796 uint64_t user_reg, kern_reg, value; 1797 int i, j; 1798 1799 if (cpu == 0) { 1800 /* Create a user visible cpu description with safe values */ 1801 memset(&user_cpu_desc, 0, sizeof(user_cpu_desc)); 1802 /* Safe values for these registers */ 1803 user_cpu_desc.id_aa64pfr0 = ID_AA64PFR0_AdvSIMD_NONE | 1804 ID_AA64PFR0_FP_NONE | ID_AA64PFR0_EL1_64 | 1805 ID_AA64PFR0_EL0_64; 1806 user_cpu_desc.id_aa64dfr0 = ID_AA64DFR0_DebugVer_8; 1807 } 1808 1809 for (i = 0; i < nitems(user_regs); i++) { 1810 value = CPU_DESC_FIELD(cpu_desc[cpu], i); 1811 if (cpu == 0) { 1812 kern_reg = value; 1813 user_reg = value; 1814 } else { 1815 kern_reg = CPU_DESC_FIELD(kern_cpu_desc, i); 1816 user_reg = CPU_DESC_FIELD(user_cpu_desc, i); 1817 } 1818 1819 fields = user_regs[i].fields; 1820 for (j = 0; fields[j].type != 0; j++) { 1821 switch (fields[j].type & MRS_TYPE_MASK) { 1822 case MRS_EXACT: 1823 user_reg &= ~(0xful << fields[j].shift); 1824 user_reg |= 1825 (uint64_t)MRS_EXACT_FIELD(fields[j].type) << 1826 fields[j].shift; 1827 break; 1828 case MRS_LOWER: 1829 user_reg = update_lower_register(user_reg, 1830 value, fields[j].shift, 4, fields[j].sign); 1831 break; 1832 default: 1833 panic("Invalid field type: %d", fields[j].type); 1834 } 1835 kern_reg = update_lower_register(kern_reg, value, 1836 fields[j].shift, 4, fields[j].sign); 1837 } 1838 1839 CPU_DESC_FIELD(kern_cpu_desc, i) = kern_reg; 1840 CPU_DESC_FIELD(user_cpu_desc, i) = user_reg; 1841 } 1842 } 1843 1844 /* HWCAP */ 1845 bool __read_frequently lse_supported = false; 1846 1847 bool __read_frequently icache_aliasing = false; 1848 bool __read_frequently icache_vmid = false; 1849 1850 int64_t dcache_line_size; /* The minimum D cache line size */ 1851 int64_t icache_line_size; /* The minimum I cache line size */ 1852 int64_t idcache_line_size; /* The minimum cache line size */ 1853 1854 /* 1855 * Find the values to export to userspace as AT_HWCAP and AT_HWCAP2. 1856 */ 1857 static void 1858 parse_cpu_features(void) 1859 { 1860 struct mrs_field_hwcap *hwcaps; 1861 struct mrs_field *fields; 1862 uint64_t min, reg; 1863 int i, j, k; 1864 1865 for (i = 0; i < nitems(user_regs); i++) { 1866 reg = CPU_DESC_FIELD(user_cpu_desc, i); 1867 fields = user_regs[i].fields; 1868 for (j = 0; fields[j].type != 0; j++) { 1869 hwcaps = fields[j].hwcaps; 1870 if (hwcaps == NULL) 1871 continue; 1872 1873 for (k = 0; hwcaps[k].hwcap != NULL; k++) { 1874 min = hwcaps[k].min; 1875 1876 /* 1877 * If the field is greater than the minimum 1878 * value we can set the hwcap; 1879 */ 1880 if (mrs_field_cmp(reg, min, fields[j].shift, 1881 4, fields[j].sign) >= 0) { 1882 *hwcaps[k].hwcap |= hwcaps[k].hwcap_val; 1883 } 1884 } 1885 } 1886 } 1887 } 1888 1889 static void 1890 identify_cpu_sysinit(void *dummy __unused) 1891 { 1892 int cpu; 1893 bool dic, idc; 1894 1895 dic = (allow_dic != 0); 1896 idc = (allow_idc != 0); 1897 1898 CPU_FOREACH(cpu) { 1899 check_cpu_regs(cpu); 1900 if (cpu != 0) 1901 update_special_regs(cpu); 1902 1903 if (CTR_DIC_VAL(cpu_desc[cpu].ctr) == 0) 1904 dic = false; 1905 if (CTR_IDC_VAL(cpu_desc[cpu].ctr) == 0) 1906 idc = false; 1907 } 1908 1909 /* Find the values to export to userspace as AT_HWCAP and AT_HWCAP2 */ 1910 parse_cpu_features(); 1911 1912 #ifdef COMPAT_FREEBSD32 1913 /* Set the default caps and any that need to check multiple fields */ 1914 elf32_hwcap |= parse_cpu_features_hwcap32(); 1915 #endif 1916 1917 if (dic && idc) { 1918 arm64_icache_sync_range = &arm64_dic_idc_icache_sync_range; 1919 if (bootverbose) 1920 printf("Enabling DIC & IDC ICache sync\n"); 1921 } else if (idc) { 1922 arm64_icache_sync_range = &arm64_idc_aliasing_icache_sync_range; 1923 if (bootverbose) 1924 printf("Enabling IDC ICache sync\n"); 1925 } 1926 1927 if ((elf_hwcap & HWCAP_ATOMICS) != 0) { 1928 lse_supported = true; 1929 if (bootverbose) 1930 printf("Enabling LSE atomics in the kernel\n"); 1931 } 1932 #ifdef LSE_ATOMICS 1933 if (!lse_supported) 1934 panic("CPU does not support LSE atomic instructions"); 1935 #endif 1936 1937 install_undef_handler(true, user_mrs_handler); 1938 } 1939 SYSINIT(identify_cpu, SI_SUB_CPU, SI_ORDER_MIDDLE, identify_cpu_sysinit, NULL); 1940 1941 static void 1942 cpu_features_sysinit(void *dummy __unused) 1943 { 1944 struct sbuf sb; 1945 u_int cpu; 1946 1947 CPU_FOREACH(cpu) 1948 print_cpu_features(cpu); 1949 1950 /* Fill in cpu_model for the hw.model sysctl */ 1951 sbuf_new(&sb, cpu_model, sizeof(cpu_model), SBUF_FIXEDLEN); 1952 print_cpu_midr(&sb, 0); 1953 1954 sbuf_finish(&sb); 1955 sbuf_delete(&sb); 1956 } 1957 /* Log features before APs are released and start printing to the dmesg. */ 1958 SYSINIT(cpu_features, SI_SUB_SMP - 1, SI_ORDER_ANY, cpu_features_sysinit, NULL); 1959 1960 #ifdef COMPAT_FREEBSD32 1961 static u_long 1962 parse_cpu_features_hwcap32(void) 1963 { 1964 u_long hwcap = HWCAP32_DEFAULT; 1965 1966 if ((MVFR1_SIMDLS_VAL(user_cpu_desc.mvfr1) >= 1967 MVFR1_SIMDLS_IMPL) && 1968 (MVFR1_SIMDInt_VAL(user_cpu_desc.mvfr1) >= 1969 MVFR1_SIMDInt_IMPL) && 1970 (MVFR1_SIMDSP_VAL(user_cpu_desc.mvfr1) >= 1971 MVFR1_SIMDSP_IMPL)) 1972 hwcap |= HWCAP32_NEON; 1973 1974 return (hwcap); 1975 } 1976 #endif /* COMPAT_FREEBSD32 */ 1977 1978 static void 1979 print_ctr_fields(struct sbuf *sb, uint64_t reg, void *arg) 1980 { 1981 1982 sbuf_printf(sb, "%u byte D-cacheline,", CTR_DLINE_SIZE(reg)); 1983 sbuf_printf(sb, "%u byte I-cacheline,", CTR_ILINE_SIZE(reg)); 1984 reg &= ~(CTR_DLINE_MASK | CTR_ILINE_MASK); 1985 1986 switch(CTR_L1IP_VAL(reg)) { 1987 case CTR_L1IP_VPIPT: 1988 sbuf_printf(sb, "VPIPT"); 1989 break; 1990 case CTR_L1IP_AIVIVT: 1991 sbuf_printf(sb, "AIVIVT"); 1992 break; 1993 case CTR_L1IP_VIPT: 1994 sbuf_printf(sb, "VIPT"); 1995 break; 1996 case CTR_L1IP_PIPT: 1997 sbuf_printf(sb, "PIPT"); 1998 break; 1999 } 2000 sbuf_printf(sb, " ICache,"); 2001 reg &= ~CTR_L1IP_MASK; 2002 2003 sbuf_printf(sb, "%d byte ERG,", CTR_ERG_SIZE(reg)); 2004 sbuf_printf(sb, "%d byte CWG", CTR_CWG_SIZE(reg)); 2005 reg &= ~(CTR_ERG_MASK | CTR_CWG_MASK); 2006 2007 if (CTR_IDC_VAL(reg) != 0) 2008 sbuf_printf(sb, ",IDC"); 2009 if (CTR_DIC_VAL(reg) != 0) 2010 sbuf_printf(sb, ",DIC"); 2011 reg &= ~(CTR_IDC_MASK | CTR_DIC_MASK); 2012 reg &= ~CTR_RES1; 2013 2014 if (reg != 0) 2015 sbuf_printf(sb, ",%lx", reg); 2016 } 2017 2018 static void 2019 print_register(struct sbuf *sb, const char *reg_name, uint64_t reg, 2020 void (*print_fields)(struct sbuf *, uint64_t, void *), void *arg) 2021 { 2022 2023 sbuf_printf(sb, "%29s = <", reg_name); 2024 2025 print_fields(sb, reg, arg); 2026 2027 sbuf_finish(sb); 2028 printf("%s>\n", sbuf_data(sb)); 2029 sbuf_clear(sb); 2030 } 2031 2032 static void 2033 print_id_fields(struct sbuf *sb, uint64_t reg, void *arg) 2034 { 2035 struct mrs_field *fields = arg; 2036 struct mrs_field_value *fv; 2037 int field, i, j, printed; 2038 2039 #define SEP_STR ((printed++) == 0) ? "" : "," 2040 printed = 0; 2041 for (i = 0; fields[i].type != 0; i++) { 2042 fv = fields[i].values; 2043 2044 /* TODO: Handle with an unknown message */ 2045 if (fv == NULL) 2046 continue; 2047 2048 field = (reg & fields[i].mask) >> fields[i].shift; 2049 for (j = 0; fv[j].desc != NULL; j++) { 2050 if ((fv[j].value >> fields[i].shift) != field) 2051 continue; 2052 2053 if (fv[j].desc[0] != '\0') 2054 sbuf_printf(sb, "%s%s", SEP_STR, fv[j].desc); 2055 break; 2056 } 2057 if (fv[j].desc == NULL) 2058 sbuf_printf(sb, "%sUnknown %s(%x)", SEP_STR, 2059 fields[i].name, field); 2060 2061 reg &= ~(0xful << fields[i].shift); 2062 } 2063 2064 if (reg != 0) 2065 sbuf_printf(sb, "%s%#lx", SEP_STR, reg); 2066 #undef SEP_STR 2067 } 2068 2069 static void 2070 print_id_register(struct sbuf *sb, const char *reg_name, uint64_t reg, 2071 struct mrs_field *fields) 2072 { 2073 2074 print_register(sb, reg_name, reg, print_id_fields, fields); 2075 } 2076 2077 static void 2078 print_cpu_midr(struct sbuf *sb, u_int cpu) 2079 { 2080 const struct cpu_parts *cpu_partsp; 2081 const char *cpu_impl_name; 2082 const char *cpu_part_name; 2083 u_int midr; 2084 u_int impl_id; 2085 u_int part_id; 2086 2087 midr = pcpu_find(cpu)->pc_midr; 2088 2089 cpu_impl_name = NULL; 2090 cpu_partsp = NULL; 2091 impl_id = CPU_IMPL(midr); 2092 for (int i = 0; cpu_implementers[i].impl_name != NULL; i++) { 2093 if (impl_id == cpu_implementers[i].impl_id) { 2094 cpu_impl_name = cpu_implementers[i].impl_name; 2095 cpu_partsp = cpu_implementers[i].cpu_parts; 2096 break; 2097 } 2098 } 2099 /* Unknown implementer, so unknown part */ 2100 if (cpu_impl_name == NULL) { 2101 sbuf_printf(sb, "Unknown Implementer (midr: %08x)", midr); 2102 return; 2103 } 2104 2105 KASSERT(cpu_partsp != NULL, ("%s: No parts table for implementer %s", 2106 __func__, cpu_impl_name)); 2107 2108 cpu_part_name = NULL; 2109 part_id = CPU_PART(midr); 2110 for (int i = 0; cpu_partsp[i].part_name != NULL; i++) { 2111 if (part_id == cpu_partsp[i].part_id) { 2112 cpu_part_name = cpu_partsp[i].part_name; 2113 break; 2114 } 2115 } 2116 /* Known Implementer, Unknown part */ 2117 if (cpu_part_name == NULL) { 2118 sbuf_printf(sb, "%s Unknown CPU r%dp%d (midr: %08x)", 2119 cpu_impl_name, CPU_VAR(midr), CPU_REV(midr), midr); 2120 return; 2121 } 2122 2123 sbuf_printf(sb, "%s %s r%dp%d", cpu_impl_name, 2124 cpu_part_name, CPU_VAR(midr), CPU_REV(midr)); 2125 } 2126 2127 static void 2128 print_cpu_cache(u_int cpu, struct sbuf *sb, uint64_t ccs, bool icache, 2129 bool unified) 2130 { 2131 size_t cache_size; 2132 size_t line_size; 2133 2134 /* LineSize is Log2(S) - 4. */ 2135 line_size = 1 << ((ccs & CCSIDR_LineSize_MASK) + 4); 2136 /* 2137 * Calculate cache size (sets * ways * line size). There are different 2138 * formats depending on the FEAT_CCIDX bit in ID_AA64MMFR2 feature 2139 * register. 2140 */ 2141 if ((cpu_desc[cpu].id_aa64mmfr2 & ID_AA64MMFR2_CCIDX_64)) 2142 cache_size = (CCSIDR_NSETS_64(ccs) + 1) * 2143 (CCSIDR_ASSOC_64(ccs) + 1); 2144 else 2145 cache_size = (CCSIDR_NSETS(ccs) + 1) * (CCSIDR_ASSOC(ccs) + 1); 2146 2147 cache_size *= line_size; 2148 sbuf_printf(sb, "%zuKB (%s)", cache_size / 1024, 2149 icache ? "instruction" : unified ? "unified" : "data"); 2150 } 2151 2152 static void 2153 print_cpu_caches(struct sbuf *sb, u_int cpu) 2154 { 2155 /* Print out each cache combination */ 2156 uint64_t clidr; 2157 int i = 1; 2158 clidr = cpu_desc[cpu].clidr; 2159 2160 for (i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) { 2161 int j = 0; 2162 int ctype_m = (clidr & CLIDR_CTYPE_MASK); 2163 2164 sbuf_printf(sb, " L%d cache: ", i + 1); 2165 if ((clidr & CLIDR_CTYPE_IO)) { 2166 print_cpu_cache(cpu, sb, cpu_desc[cpu].ccsidr[i][j++], 2167 true, false); 2168 /* If there's more, add to the line. */ 2169 if ((ctype_m & ~CLIDR_CTYPE_IO) != 0) 2170 sbuf_printf(sb, ", "); 2171 } 2172 if ((ctype_m & ~CLIDR_CTYPE_IO) != 0) { 2173 print_cpu_cache(cpu, sb, cpu_desc[cpu].ccsidr[i][j], 2174 false, (clidr & CLIDR_CTYPE_UNIFIED)); 2175 } 2176 sbuf_printf(sb, "\n"); 2177 2178 } 2179 sbuf_finish(sb); 2180 printf("%s", sbuf_data(sb)); 2181 } 2182 2183 static void 2184 print_cpu_features(u_int cpu) 2185 { 2186 struct sbuf *sb; 2187 2188 sb = sbuf_new_auto(); 2189 sbuf_printf(sb, "CPU%3u: ", cpu); 2190 print_cpu_midr(sb, cpu); 2191 2192 sbuf_cat(sb, " affinity:"); 2193 switch(cpu_aff_levels) { 2194 default: 2195 case 4: 2196 sbuf_printf(sb, " %2d", CPU_AFF3(cpu_desc[cpu].mpidr)); 2197 /* FALLTHROUGH */ 2198 case 3: 2199 sbuf_printf(sb, " %2d", CPU_AFF2(cpu_desc[cpu].mpidr)); 2200 /* FALLTHROUGH */ 2201 case 2: 2202 sbuf_printf(sb, " %2d", CPU_AFF1(cpu_desc[cpu].mpidr)); 2203 /* FALLTHROUGH */ 2204 case 1: 2205 case 0: /* On UP this will be zero */ 2206 sbuf_printf(sb, " %2d", CPU_AFF0(cpu_desc[cpu].mpidr)); 2207 break; 2208 } 2209 sbuf_finish(sb); 2210 printf("%s\n", sbuf_data(sb)); 2211 sbuf_clear(sb); 2212 2213 /* 2214 * There is a hardware errata where, if one CPU is performing a TLB 2215 * invalidation while another is performing a store-exclusive the 2216 * store-exclusive may return the wrong status. A workaround seems 2217 * to be to use an IPI to invalidate on each CPU, however given the 2218 * limited number of affected units (pass 1.1 is the evaluation 2219 * hardware revision), and the lack of information from Cavium 2220 * this has not been implemented. 2221 * 2222 * At the time of writing this the only information is from: 2223 * https://lkml.org/lkml/2016/8/4/722 2224 */ 2225 /* 2226 * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 on its own also 2227 * triggers on pass 2.0+. 2228 */ 2229 if (cpu == 0 && CPU_VAR(PCPU_GET(midr)) == 0 && 2230 CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1) 2231 printf("WARNING: ThunderX Pass 1.1 detected.\nThis has known " 2232 "hardware bugs that may cause the incorrect operation of " 2233 "atomic operations.\n"); 2234 2235 /* Cache Type Register */ 2236 if (cpu == 0 || (cpu_print_regs & PRINT_CTR_EL0) != 0) { 2237 print_register(sb, "Cache Type", 2238 cpu_desc[cpu].ctr, print_ctr_fields, NULL); 2239 } 2240 2241 /* AArch64 Instruction Set Attribute Register 0 */ 2242 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR0) != 0) 2243 print_id_register(sb, "Instruction Set Attributes 0", 2244 cpu_desc[cpu].id_aa64isar0, id_aa64isar0_fields); 2245 2246 /* AArch64 Instruction Set Attribute Register 1 */ 2247 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR1) != 0) 2248 print_id_register(sb, "Instruction Set Attributes 1", 2249 cpu_desc[cpu].id_aa64isar1, id_aa64isar1_fields); 2250 2251 /* AArch64 Instruction Set Attribute Register 2 */ 2252 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR2) != 0) 2253 print_id_register(sb, "Instruction Set Attributes 2", 2254 cpu_desc[cpu].id_aa64isar2, id_aa64isar2_fields); 2255 2256 /* AArch64 Processor Feature Register 0 */ 2257 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR0) != 0) 2258 print_id_register(sb, "Processor Features 0", 2259 cpu_desc[cpu].id_aa64pfr0, id_aa64pfr0_fields); 2260 2261 /* AArch64 Processor Feature Register 1 */ 2262 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR1) != 0) 2263 print_id_register(sb, "Processor Features 1", 2264 cpu_desc[cpu].id_aa64pfr1, id_aa64pfr1_fields); 2265 2266 /* AArch64 Memory Model Feature Register 0 */ 2267 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR0) != 0) 2268 print_id_register(sb, "Memory Model Features 0", 2269 cpu_desc[cpu].id_aa64mmfr0, id_aa64mmfr0_fields); 2270 2271 /* AArch64 Memory Model Feature Register 1 */ 2272 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR1) != 0) 2273 print_id_register(sb, "Memory Model Features 1", 2274 cpu_desc[cpu].id_aa64mmfr1, id_aa64mmfr1_fields); 2275 2276 /* AArch64 Memory Model Feature Register 2 */ 2277 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR2) != 0) 2278 print_id_register(sb, "Memory Model Features 2", 2279 cpu_desc[cpu].id_aa64mmfr2, id_aa64mmfr2_fields); 2280 2281 /* AArch64 Debug Feature Register 0 */ 2282 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_DFR0) != 0) 2283 print_id_register(sb, "Debug Features 0", 2284 cpu_desc[cpu].id_aa64dfr0, id_aa64dfr0_fields); 2285 2286 /* AArch64 Memory Model Feature Register 1 */ 2287 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_DFR1) != 0) 2288 print_id_register(sb, "Debug Features 1", 2289 cpu_desc[cpu].id_aa64dfr1, id_aa64dfr1_fields); 2290 2291 /* AArch64 Auxiliary Feature Register 0 */ 2292 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_AFR0) != 0) 2293 print_id_register(sb, "Auxiliary Features 0", 2294 cpu_desc[cpu].id_aa64afr0, id_aa64afr0_fields); 2295 2296 /* AArch64 Auxiliary Feature Register 1 */ 2297 if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_AFR1) != 0) 2298 print_id_register(sb, "Auxiliary Features 1", 2299 cpu_desc[cpu].id_aa64afr1, id_aa64afr1_fields); 2300 2301 /* AArch64 SVE Feature Register 0 */ 2302 /* We check the cpu == 0 case when setting PRINT_ID_AA64_ZFR0 */ 2303 if ((cpu_print_regs & PRINT_ID_AA64_ZFR0) != 0) 2304 print_id_register(sb, "SVE Features 0", 2305 cpu_desc[cpu].id_aa64zfr0, id_aa64zfr0_fields); 2306 2307 #ifdef COMPAT_FREEBSD32 2308 /* AArch32 Instruction Set Attribute Register 5 */ 2309 if (cpu == 0 || (cpu_print_regs & PRINT_ID_ISAR5) != 0) 2310 print_id_register(sb, "AArch32 Instruction Set Attributes 5", 2311 cpu_desc[cpu].id_isar5, id_isar5_fields); 2312 2313 /* AArch32 Media and VFP Feature Register 0 */ 2314 if (cpu == 0 || (cpu_print_regs & PRINT_MVFR0) != 0) 2315 print_id_register(sb, "AArch32 Media and VFP Features 0", 2316 cpu_desc[cpu].mvfr0, mvfr0_fields); 2317 2318 /* AArch32 Media and VFP Feature Register 1 */ 2319 if (cpu == 0 || (cpu_print_regs & PRINT_MVFR1) != 0) 2320 print_id_register(sb, "AArch32 Media and VFP Features 1", 2321 cpu_desc[cpu].mvfr1, mvfr1_fields); 2322 #endif 2323 if (bootverbose) 2324 print_cpu_caches(sb, cpu); 2325 2326 sbuf_delete(sb); 2327 sb = NULL; 2328 #undef SEP_STR 2329 } 2330 2331 void 2332 identify_cache(uint64_t ctr) 2333 { 2334 2335 /* Identify the L1 cache type */ 2336 switch (CTR_L1IP_VAL(ctr)) { 2337 case CTR_L1IP_PIPT: 2338 break; 2339 case CTR_L1IP_VPIPT: 2340 icache_vmid = true; 2341 break; 2342 default: 2343 case CTR_L1IP_VIPT: 2344 icache_aliasing = true; 2345 break; 2346 } 2347 2348 if (dcache_line_size == 0) { 2349 KASSERT(icache_line_size == 0, ("%s: i-cacheline size set: %ld", 2350 __func__, icache_line_size)); 2351 2352 /* Get the D cache line size */ 2353 dcache_line_size = CTR_DLINE_SIZE(ctr); 2354 /* And the same for the I cache */ 2355 icache_line_size = CTR_ILINE_SIZE(ctr); 2356 2357 idcache_line_size = MIN(dcache_line_size, icache_line_size); 2358 } 2359 2360 if (dcache_line_size != CTR_DLINE_SIZE(ctr)) { 2361 printf("WARNING: D-cacheline size mismatch %ld != %d\n", 2362 dcache_line_size, CTR_DLINE_SIZE(ctr)); 2363 } 2364 2365 if (icache_line_size != CTR_ILINE_SIZE(ctr)) { 2366 printf("WARNING: I-cacheline size mismatch %ld != %d\n", 2367 icache_line_size, CTR_ILINE_SIZE(ctr)); 2368 } 2369 } 2370 2371 void 2372 identify_cpu(u_int cpu) 2373 { 2374 uint64_t clidr; 2375 2376 /* Save affinity for current CPU */ 2377 cpu_desc[cpu].mpidr = get_mpidr(); 2378 CPU_AFFINITY(cpu) = cpu_desc[cpu].mpidr & CPU_AFF_MASK; 2379 2380 cpu_desc[cpu].ctr = READ_SPECIALREG(ctr_el0); 2381 cpu_desc[cpu].id_aa64dfr0 = READ_SPECIALREG(id_aa64dfr0_el1); 2382 cpu_desc[cpu].id_aa64dfr1 = READ_SPECIALREG(id_aa64dfr1_el1); 2383 cpu_desc[cpu].id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1); 2384 cpu_desc[cpu].id_aa64isar1 = READ_SPECIALREG(id_aa64isar1_el1); 2385 cpu_desc[cpu].id_aa64isar2 = READ_SPECIALREG(id_aa64isar2_el1); 2386 cpu_desc[cpu].id_aa64mmfr0 = READ_SPECIALREG(id_aa64mmfr0_el1); 2387 cpu_desc[cpu].id_aa64mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1); 2388 cpu_desc[cpu].id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1); 2389 cpu_desc[cpu].id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1); 2390 cpu_desc[cpu].id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1); 2391 2392 /* 2393 * ID_AA64ZFR0_EL1 is only valid when at least one of: 2394 * - ID_AA64PFR0_EL1.SVE is non-zero 2395 * - ID_AA64PFR1_EL1.SME is non-zero 2396 * In other cases it is zero, but still safe to read 2397 */ 2398 cpu_desc[cpu].have_sve = 2399 (ID_AA64PFR0_SVE_VAL(cpu_desc[cpu].id_aa64pfr0) != 0); 2400 cpu_desc[cpu].id_aa64zfr0 = READ_SPECIALREG(ID_AA64ZFR0_EL1_REG); 2401 2402 cpu_desc[cpu].clidr = READ_SPECIALREG(clidr_el1); 2403 2404 clidr = cpu_desc[cpu].clidr; 2405 2406 for (int i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) { 2407 int j = 0; 2408 if ((clidr & CLIDR_CTYPE_IO)) { 2409 WRITE_SPECIALREG(csselr_el1, 2410 CSSELR_Level(i) | CSSELR_InD); 2411 cpu_desc[cpu].ccsidr[i][j++] = 2412 READ_SPECIALREG(ccsidr_el1); 2413 } 2414 if ((clidr & ~CLIDR_CTYPE_IO) == 0) 2415 continue; 2416 WRITE_SPECIALREG(csselr_el1, CSSELR_Level(i)); 2417 cpu_desc[cpu].ccsidr[i][j] = READ_SPECIALREG(ccsidr_el1); 2418 } 2419 2420 #ifdef COMPAT_FREEBSD32 2421 /* Only read aarch32 SRs if EL0-32 is available */ 2422 if (ID_AA64PFR0_EL0_VAL(cpu_desc[cpu].id_aa64pfr0) == 2423 ID_AA64PFR0_EL0_64_32) { 2424 cpu_desc[cpu].id_isar5 = READ_SPECIALREG(id_isar5_el1); 2425 cpu_desc[cpu].mvfr0 = READ_SPECIALREG(mvfr0_el1); 2426 cpu_desc[cpu].mvfr1 = READ_SPECIALREG(mvfr1_el1); 2427 } 2428 #endif 2429 } 2430 2431 static void 2432 check_cpu_regs(u_int cpu) 2433 { 2434 2435 switch (cpu_aff_levels) { 2436 case 0: 2437 if (CPU_AFF0(cpu_desc[cpu].mpidr) != 2438 CPU_AFF0(cpu_desc[0].mpidr)) 2439 cpu_aff_levels = 1; 2440 /* FALLTHROUGH */ 2441 case 1: 2442 if (CPU_AFF1(cpu_desc[cpu].mpidr) != 2443 CPU_AFF1(cpu_desc[0].mpidr)) 2444 cpu_aff_levels = 2; 2445 /* FALLTHROUGH */ 2446 case 2: 2447 if (CPU_AFF2(cpu_desc[cpu].mpidr) != 2448 CPU_AFF2(cpu_desc[0].mpidr)) 2449 cpu_aff_levels = 3; 2450 /* FALLTHROUGH */ 2451 case 3: 2452 if (CPU_AFF3(cpu_desc[cpu].mpidr) != 2453 CPU_AFF3(cpu_desc[0].mpidr)) 2454 cpu_aff_levels = 4; 2455 break; 2456 } 2457 2458 if (cpu_desc[cpu].id_aa64afr0 != cpu_desc[0].id_aa64afr0) 2459 cpu_print_regs |= PRINT_ID_AA64_AFR0; 2460 if (cpu_desc[cpu].id_aa64afr1 != cpu_desc[0].id_aa64afr1) 2461 cpu_print_regs |= PRINT_ID_AA64_AFR1; 2462 2463 if (cpu_desc[cpu].id_aa64dfr0 != cpu_desc[0].id_aa64dfr0) 2464 cpu_print_regs |= PRINT_ID_AA64_DFR0; 2465 if (cpu_desc[cpu].id_aa64dfr1 != cpu_desc[0].id_aa64dfr1) 2466 cpu_print_regs |= PRINT_ID_AA64_DFR1; 2467 2468 if (cpu_desc[cpu].id_aa64isar0 != cpu_desc[0].id_aa64isar0) 2469 cpu_print_regs |= PRINT_ID_AA64_ISAR0; 2470 if (cpu_desc[cpu].id_aa64isar1 != cpu_desc[0].id_aa64isar1) 2471 cpu_print_regs |= PRINT_ID_AA64_ISAR1; 2472 if (cpu_desc[cpu].id_aa64isar2 != cpu_desc[0].id_aa64isar2) 2473 cpu_print_regs |= PRINT_ID_AA64_ISAR2; 2474 2475 if (cpu_desc[cpu].id_aa64mmfr0 != cpu_desc[0].id_aa64mmfr0) 2476 cpu_print_regs |= PRINT_ID_AA64_MMFR0; 2477 if (cpu_desc[cpu].id_aa64mmfr1 != cpu_desc[0].id_aa64mmfr1) 2478 cpu_print_regs |= PRINT_ID_AA64_MMFR1; 2479 if (cpu_desc[cpu].id_aa64mmfr2 != cpu_desc[0].id_aa64mmfr2) 2480 cpu_print_regs |= PRINT_ID_AA64_MMFR2; 2481 2482 if (cpu_desc[cpu].id_aa64pfr0 != cpu_desc[0].id_aa64pfr0) 2483 cpu_print_regs |= PRINT_ID_AA64_PFR0; 2484 if (cpu_desc[cpu].id_aa64pfr1 != cpu_desc[0].id_aa64pfr1) 2485 cpu_print_regs |= PRINT_ID_AA64_PFR1; 2486 2487 /* Only print if ID_AA64ZFR0_EL1 is valid */ 2488 if (cpu_desc[cpu].have_sve) { 2489 /* Print if the value changed */ 2490 if (cpu_desc[cpu].id_aa64zfr0 != cpu_desc[0].id_aa64zfr0) { 2491 cpu_print_regs |= PRINT_ID_AA64_ZFR0; 2492 /* Print if it didn't, but the previous CPU was invalid */ 2493 } else if (cpu > 0 && !cpu_desc[cpu - 1].have_sve) { 2494 cpu_print_regs |= PRINT_ID_AA64_ZFR0; 2495 } 2496 } 2497 2498 if (cpu_desc[cpu].ctr != cpu_desc[0].ctr) { 2499 /* 2500 * If the cache type register is different we may 2501 * have a different l1 cache type. 2502 */ 2503 identify_cache(cpu_desc[cpu].ctr); 2504 cpu_print_regs |= PRINT_CTR_EL0; 2505 } 2506 2507 #ifdef COMPAT_FREEBSD32 2508 if (cpu_desc[cpu].id_isar5 != cpu_desc[0].id_isar5) 2509 cpu_print_regs |= PRINT_ID_ISAR5; 2510 if (cpu_desc[cpu].mvfr0 != cpu_desc[0].mvfr0) 2511 cpu_print_regs |= PRINT_MVFR0; 2512 if (cpu_desc[cpu].mvfr1 != cpu_desc[0].mvfr1) 2513 cpu_print_regs |= PRINT_MVFR1; 2514 #endif 2515 } 2516