1/*- 2 * Copyright (c) 2012-2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#include "assym.inc" 30#include "opt_kstack_pages.h" 31#include <sys/syscall.h> 32#include <machine/asm.h> 33#include <machine/armreg.h> 34#include <machine/hypervisor.h> 35#include <machine/param.h> 36#include <machine/pte.h> 37#include <machine/vm.h> 38#include <machine/vmparam.h> 39 40#define VIRT_BITS 48 41#define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT) 42 43 .globl kernbase 44 .set kernbase, KERNBASE 45 46/* 47 * We assume: 48 * MMU on with an identity map, or off 49 * D-Cache: off 50 * I-Cache: on or off 51 * We are loaded at a 2MiB aligned address 52 */ 53 54ENTRY(_start) 55 /* Drop to EL1 */ 56 bl drop_to_el1 57 58 /* 59 * Disable the MMU. We may have entered the kernel with it on and 60 * will need to update the tables later. If this has been set up 61 * with anything other than a VA == PA map then this will fail, 62 * but in this case the code to find where we are running from 63 * would have also failed. 64 */ 65 dsb sy 66 mrs x2, sctlr_el1 67 bic x2, x2, SCTLR_M 68 msr sctlr_el1, x2 69 isb 70 71 /* Set the context id */ 72 msr contextidr_el1, xzr 73 74 /* Get the virt -> phys offset */ 75 bl get_virt_delta 76 77 /* 78 * At this point: 79 * x29 = PA - VA 80 * x28 = Our physical load address 81 */ 82 83 /* Create the page tables */ 84 bl create_pagetables 85 86 /* 87 * At this point: 88 * x27 = TTBR0 table 89 * x26 = Kernel L1 table 90 * x24 = TTBR1 table 91 */ 92 93 /* Enable the mmu */ 94 bl start_mmu 95 96 /* Load the new ttbr0 pagetable */ 97 adrp x27, pagetable_l0_ttbr0 98 add x27, x27, :lo12:pagetable_l0_ttbr0 99 100 /* Jump to the virtual address space */ 101 ldr x15, .Lvirtdone 102 br x15 103 104virtdone: 105 /* Set up the stack */ 106 adrp x25, initstack_end 107 add x25, x25, :lo12:initstack_end 108 mov sp, x25 109 sub sp, sp, #PCB_SIZE 110 111 /* Zero the BSS */ 112 ldr x15, .Lbss 113 ldr x14, .Lend 1141: 115 str xzr, [x15], #8 116 cmp x15, x14 117 b.lo 1b 118 119 /* Backup the module pointer */ 120 mov x1, x0 121 122 /* Make the page table base a virtual address */ 123 sub x26, x26, x29 124 sub x24, x24, x29 125 126 sub sp, sp, #BOOTPARAMS_SIZE 127 mov x0, sp 128 129 /* Degate the delda so it is VA -> PA */ 130 neg x29, x29 131 132 str x1, [x0, #BP_MODULEP] 133 str x26, [x0, #BP_KERN_L1PT] 134 str x29, [x0, #BP_KERN_DELTA] 135 adrp x25, initstack 136 add x25, x25, :lo12:initstack 137 str x25, [x0, #BP_KERN_STACK] 138 str x24, [x0, #BP_KERN_L0PT] 139 str x27, [x0, #BP_KERN_TTBR0] 140 str x23, [x0, #BP_BOOT_EL] 141 142 /* trace back starts here */ 143 mov fp, #0 144 /* Branch to C code */ 145 bl initarm 146 /* We are done with the boot params */ 147 add sp, sp, #BOOTPARAMS_SIZE 148 bl mi_startup 149 150 /* We should not get here */ 151 brk 0 152 153 .align 3 154.Lvirtdone: 155 .quad virtdone 156.Lbss: 157 .quad __bss_start 158.Lend: 159 .quad __bss_end 160END(_start) 161 162#ifdef SMP 163/* 164 * mpentry(unsigned long) 165 * 166 * Called by a core when it is being brought online. 167 * The data in x0 is passed straight to init_secondary. 168 */ 169ENTRY(mpentry) 170 /* Disable interrupts */ 171 msr daifset, #2 172 173 /* Drop to EL1 */ 174 bl drop_to_el1 175 176 /* Set the context id */ 177 msr contextidr_el1, xzr 178 179 /* Load the kernel page table */ 180 adrp x24, pagetable_l0_ttbr1 181 add x24, x24, :lo12:pagetable_l0_ttbr1 182 /* Load the identity page table */ 183 adrp x27, pagetable_l0_ttbr0_boostrap 184 add x27, x27, :lo12:pagetable_l0_ttbr0_boostrap 185 186 /* Enable the mmu */ 187 bl start_mmu 188 189 /* Load the new ttbr0 pagetable */ 190 adrp x27, pagetable_l0_ttbr0 191 add x27, x27, :lo12:pagetable_l0_ttbr0 192 193 /* Jump to the virtual address space */ 194 ldr x15, =mp_virtdone 195 br x15 196 197mp_virtdone: 198 /* Start using the AP boot stack */ 199 ldr x4, =bootstack 200 ldr x4, [x4] 201 mov sp, x4 202 203 /* Load the kernel ttbr0 pagetable */ 204 msr ttbr0_el1, x27 205 isb 206 207 /* Invalidate the TLB */ 208 tlbi vmalle1 209 dsb sy 210 isb 211 212 b init_secondary 213END(mpentry) 214#endif 215 216/* 217 * If we are started in EL2, configure the required hypervisor 218 * registers and drop to EL1. 219 */ 220LENTRY(drop_to_el1) 221 mrs x23, CurrentEL 222 lsr x23, x23, #2 223 cmp x23, #0x2 224 b.eq 1f 225 ret 2261: 227 /* Configure the Hypervisor */ 228 mov x2, #(HCR_RW) 229 msr hcr_el2, x2 230 231 /* Load the Virtualization Process ID Register */ 232 mrs x2, midr_el1 233 msr vpidr_el2, x2 234 235 /* Load the Virtualization Multiprocess ID Register */ 236 mrs x2, mpidr_el1 237 msr vmpidr_el2, x2 238 239 /* Set the bits that need to be 1 in sctlr_el1 */ 240 ldr x2, .Lsctlr_res1 241 msr sctlr_el1, x2 242 243 /* Don't trap to EL2 for exceptions */ 244 mov x2, #CPTR_RES1 245 msr cptr_el2, x2 246 247 /* Don't trap to EL2 for CP15 traps */ 248 msr hstr_el2, xzr 249 250 /* Enable access to the physical timers at EL1 */ 251 mrs x2, cnthctl_el2 252 orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) 253 msr cnthctl_el2, x2 254 255 /* Set the counter offset to a known value */ 256 msr cntvoff_el2, xzr 257 258 /* Hypervisor trap functions */ 259 adrp x2, hyp_vectors 260 add x2, x2, :lo12:hyp_vectors 261 msr vbar_el2, x2 262 263 mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h) 264 msr spsr_el2, x2 265 266 /* Configure GICv3 CPU interface */ 267 mrs x2, id_aa64pfr0_el1 268 /* Extract GIC bits from the register */ 269 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS 270 /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */ 271 cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT) 272 b.ne 2f 273 274 mrs x2, icc_sre_el2 275 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */ 276 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */ 277 msr icc_sre_el2, x2 2782: 279 280 /* Set the address to return to our return address */ 281 msr elr_el2, x30 282 isb 283 284 eret 285 286 .align 3 287.Lsctlr_res1: 288 .quad SCTLR_RES1 289LEND(drop_to_el1) 290 291#define VECT_EMPTY \ 292 .align 7; \ 293 1: b 1b 294 295 .align 11 296hyp_vectors: 297 VECT_EMPTY /* Synchronous EL2t */ 298 VECT_EMPTY /* IRQ EL2t */ 299 VECT_EMPTY /* FIQ EL2t */ 300 VECT_EMPTY /* Error EL2t */ 301 302 VECT_EMPTY /* Synchronous EL2h */ 303 VECT_EMPTY /* IRQ EL2h */ 304 VECT_EMPTY /* FIQ EL2h */ 305 VECT_EMPTY /* Error EL2h */ 306 307 VECT_EMPTY /* Synchronous 64-bit EL1 */ 308 VECT_EMPTY /* IRQ 64-bit EL1 */ 309 VECT_EMPTY /* FIQ 64-bit EL1 */ 310 VECT_EMPTY /* Error 64-bit EL1 */ 311 312 VECT_EMPTY /* Synchronous 32-bit EL1 */ 313 VECT_EMPTY /* IRQ 32-bit EL1 */ 314 VECT_EMPTY /* FIQ 32-bit EL1 */ 315 VECT_EMPTY /* Error 32-bit EL1 */ 316 317/* 318 * Get the delta between the physical address we were loaded to and the 319 * virtual address we expect to run from. This is used when building the 320 * initial page table. 321 */ 322LENTRY(get_virt_delta) 323 /* Load the physical address of virt_map */ 324 adrp x29, virt_map 325 add x29, x29, :lo12:virt_map 326 /* Load the virtual address of virt_map stored in virt_map */ 327 ldr x28, [x29] 328 /* Find PA - VA as PA' = VA' - VA + PA = VA' + (PA - VA) = VA' + x29 */ 329 sub x29, x29, x28 330 /* Find the load address for the kernel */ 331 mov x28, #(KERNBASE) 332 add x28, x28, x29 333 ret 334 335 .align 3 336virt_map: 337 .quad virt_map 338LEND(get_virt_delta) 339 340/* 341 * This builds the page tables containing the identity map, and the kernel 342 * virtual map. 343 * 344 * It relys on: 345 * We were loaded to an address that is on a 2MiB boundary 346 * All the memory must not cross a 1GiB boundaty 347 * x28 contains the physical address we were loaded from 348 * 349 * TODO: This is out of date. 350 * There are at least 5 pages before that address for the page tables 351 * The pages used are: 352 * - The Kernel L2 table 353 * - The Kernel L1 table 354 * - The Kernel L0 table (TTBR1) 355 * - The identity (PA = VA) L1 table 356 * - The identity (PA = VA) L0 table (TTBR0) 357 * - The DMAP L1 tables 358 */ 359LENTRY(create_pagetables) 360 /* Save the Link register */ 361 mov x5, x30 362 363 /* Clean the page table */ 364 adrp x6, pagetable 365 add x6, x6, :lo12:pagetable 366 mov x26, x6 367 adrp x27, pagetable_end 368 add x27, x27, :lo12:pagetable_end 3691: 370 stp xzr, xzr, [x6], #16 371 stp xzr, xzr, [x6], #16 372 stp xzr, xzr, [x6], #16 373 stp xzr, xzr, [x6], #16 374 cmp x6, x27 375 b.lo 1b 376 377 /* 378 * Build the TTBR1 maps. 379 */ 380 381 /* Find the size of the kernel */ 382 mov x6, #(KERNBASE) 383 384#if defined(LINUX_BOOT_ABI) 385 /* X19 is used as 'map FDT data' flag */ 386 mov x19, xzr 387 388 /* No modules or FDT pointer ? */ 389 cbz x0, booti_no_fdt 390 391 /* 392 * Test if x0 points to modules descriptor(virtual address) or 393 * to FDT (physical address) 394 */ 395 cmp x0, x6 /* x6 is #(KERNBASE) */ 396 b.lo booti_fdt 397#endif 398 399 /* Booted with modules pointer */ 400 /* Find modulep - begin */ 401 sub x8, x0, x6 402 /* Add two 2MiB pages for the module data and round up */ 403 ldr x7, =(3 * L2_SIZE - 1) 404 add x8, x8, x7 405 b common 406 407#if defined(LINUX_BOOT_ABI) 408booti_fdt: 409 /* Booted by U-Boot booti with FDT data */ 410 /* Set 'map FDT data' flag */ 411 mov x19, #1 412 413booti_no_fdt: 414 /* Booted by U-Boot booti without FTD data */ 415 /* Find the end - begin */ 416 ldr x7, .Lend 417 sub x8, x7, x6 418 419 /* 420 * Add one 2MiB page for copy of FDT data (maximum FDT size), 421 * one for metadata and round up 422 */ 423 ldr x7, =(3 * L2_SIZE - 1) 424 add x8, x8, x7 425#endif 426 427common: 428 /* Get the number of l2 pages to allocate, rounded down */ 429 lsr x10, x8, #(L2_SHIFT) 430 431 /* Create the kernel space L2 table */ 432 mov x6, x26 433 mov x7, #(ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 434 mov x8, #(KERNBASE & L2_BLOCK_MASK) 435 mov x9, x28 436 bl build_l2_block_pagetable 437 438 /* Move to the l1 table */ 439 add x26, x26, #PAGE_SIZE 440 441 /* Link the l1 -> l2 table */ 442 mov x9, x6 443 mov x6, x26 444 bl link_l1_pagetable 445 446 /* Move to the l0 table */ 447 add x24, x26, #PAGE_SIZE 448 449 /* Link the l0 -> l1 table */ 450 mov x9, x6 451 mov x6, x24 452 mov x10, #1 453 bl link_l0_pagetable 454 455 /* Link the DMAP tables */ 456 ldr x8, =DMAP_MIN_ADDRESS 457 adrp x9, pagetable_dmap 458 add x9, x9, :lo12:pagetable_dmap 459 mov x10, #DMAP_TABLES 460 bl link_l0_pagetable 461 462 /* 463 * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG. 464 * They are only needed early on, so the VA = PA map is uncached. 465 */ 466 add x27, x24, #PAGE_SIZE 467 468 mov x6, x27 /* The initial page table */ 469 470 /* Create the VA = PA map */ 471 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 472 adrp x16, _start 473 and x16, x16, #(~L2_OFFSET) 474 mov x9, x16 /* PA start */ 475 mov x8, x16 /* VA start (== PA start) */ 476 mov x10, #1 477 bl build_l2_block_pagetable 478 479#if defined(SOCDEV_PA) 480 /* Create a table for the UART */ 481 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE)) 482 add x16, x16, #(L2_SIZE) /* VA start */ 483 mov x8, x16 484 485 /* Store the socdev virtual address */ 486 add x17, x8, #(SOCDEV_PA & L2_OFFSET) 487 adrp x9, socdev_va 488 str x17, [x9, :lo12:socdev_va] 489 490 mov x9, #(SOCDEV_PA & ~L2_OFFSET) /* PA start */ 491 mov x10, #1 492 bl build_l2_block_pagetable 493#endif 494 495#if defined(LINUX_BOOT_ABI) 496 /* Map FDT data ? */ 497 cbz x19, 1f 498 499 /* Create the mapping for FDT data (2 MiB max) */ 500 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 501 add x16, x16, #(L2_SIZE) /* VA start */ 502 mov x8, x16 503 mov x9, x0 /* PA start */ 504 /* Update the module pointer to point at the allocated memory */ 505 and x0, x0, #(L2_OFFSET) /* Keep the lower bits */ 506 add x0, x0, x8 /* Add the aligned virtual address */ 507 508 mov x10, #1 509 bl build_l2_block_pagetable 510 5111: 512#endif 513 514 /* Move to the l1 table */ 515 add x27, x27, #PAGE_SIZE 516 517 /* Link the l1 -> l2 table */ 518 mov x9, x6 519 mov x6, x27 520 bl link_l1_pagetable 521 522 /* Move to the l0 table */ 523 add x27, x27, #PAGE_SIZE 524 525 /* Link the l0 -> l1 table */ 526 mov x9, x6 527 mov x6, x27 528 mov x10, #1 529 bl link_l0_pagetable 530 531 /* Restore the Link register */ 532 mov x30, x5 533 ret 534LEND(create_pagetables) 535 536/* 537 * Builds an L0 -> L1 table descriptor 538 * 539 * x6 = L0 table 540 * x8 = Virtual Address 541 * x9 = L1 PA (trashed) 542 * x10 = Entry count (trashed) 543 * x11, x12 and x13 are trashed 544 */ 545LENTRY(link_l0_pagetable) 546 /* 547 * Link an L0 -> L1 table entry. 548 */ 549 /* Find the table index */ 550 lsr x11, x8, #L0_SHIFT 551 and x11, x11, #L0_ADDR_MASK 552 553 /* Build the L0 block entry */ 554 mov x12, #L0_TABLE 555 556 /* Only use the output address bits */ 557 lsr x9, x9, #PAGE_SHIFT 5581: orr x13, x12, x9, lsl #PAGE_SHIFT 559 560 /* Store the entry */ 561 str x13, [x6, x11, lsl #3] 562 563 sub x10, x10, #1 564 add x11, x11, #1 565 add x9, x9, #1 566 cbnz x10, 1b 567 568 ret 569LEND(link_l0_pagetable) 570 571/* 572 * Builds an L1 -> L2 table descriptor 573 * 574 * x6 = L1 table 575 * x8 = Virtual Address 576 * x9 = L2 PA (trashed) 577 * x11, x12 and x13 are trashed 578 */ 579LENTRY(link_l1_pagetable) 580 /* 581 * Link an L1 -> L2 table entry. 582 */ 583 /* Find the table index */ 584 lsr x11, x8, #L1_SHIFT 585 and x11, x11, #Ln_ADDR_MASK 586 587 /* Build the L1 block entry */ 588 mov x12, #L1_TABLE 589 590 /* Only use the output address bits */ 591 lsr x9, x9, #PAGE_SHIFT 592 orr x13, x12, x9, lsl #PAGE_SHIFT 593 594 /* Store the entry */ 595 str x13, [x6, x11, lsl #3] 596 597 ret 598LEND(link_l1_pagetable) 599 600/* 601 * Builds count 2 MiB page table entry 602 * x6 = L2 table 603 * x7 = Block attributes 604 * x8 = VA start 605 * x9 = PA start (trashed) 606 * x10 = Entry count (trashed) 607 * x11, x12 and x13 are trashed 608 */ 609LENTRY(build_l2_block_pagetable) 610 /* 611 * Build the L2 table entry. 612 */ 613 /* Find the table index */ 614 lsr x11, x8, #L2_SHIFT 615 and x11, x11, #Ln_ADDR_MASK 616 617 /* Build the L2 block entry */ 618 orr x12, x7, #L2_BLOCK 619 orr x12, x12, #(ATTR_DEFAULT) 620 orr x12, x12, #(ATTR_S1_UXN) 621 622 /* Only use the output address bits */ 623 lsr x9, x9, #L2_SHIFT 624 625 /* Set the physical address for this virtual address */ 6261: orr x13, x12, x9, lsl #L2_SHIFT 627 628 /* Store the entry */ 629 str x13, [x6, x11, lsl #3] 630 631 sub x10, x10, #1 632 add x11, x11, #1 633 add x9, x9, #1 634 cbnz x10, 1b 635 636 ret 637LEND(build_l2_block_pagetable) 638 639LENTRY(start_mmu) 640 dsb sy 641 642 /* Load the exception vectors */ 643 ldr x2, =exception_vectors 644 msr vbar_el1, x2 645 646 /* Load ttbr0 and ttbr1 */ 647 msr ttbr0_el1, x27 648 msr ttbr1_el1, x24 649 isb 650 651 /* Clear the Monitor Debug System control register */ 652 msr mdscr_el1, xzr 653 654 /* Invalidate the TLB */ 655 tlbi vmalle1is 656 dsb ish 657 isb 658 659 ldr x2, mair 660 msr mair_el1, x2 661 662 /* 663 * Setup TCR according to the PARange and ASIDBits fields 664 * from ID_AA64MMFR0_EL1 and the HAFDBS field from the 665 * ID_AA64MMFR1_EL1. More precisely, set TCR_EL1.AS 666 * to 1 only if the ASIDBits field equals 0b0010. 667 */ 668 ldr x2, tcr 669 mrs x3, id_aa64mmfr0_el1 670 671 /* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */ 672 bfi x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH) 673 and x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK) 674 675 /* Check if the HW supports 16 bit ASIDS */ 676 cmp x3, #(ID_AA64MMFR0_ASIDBits_16) 677 /* If so x3 == 1, else x3 == 0 */ 678 cset x3, eq 679 /* Set TCR.AS with x3 */ 680 bfi x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH) 681 682 /* 683 * Check if the HW supports access flag and dirty state updates, 684 * and set TCR_EL1.HA and TCR_EL1.HD accordingly. 685 */ 686 mrs x3, id_aa64mmfr1_el1 687 and x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK) 688 cmp x3, #1 689 b.ne 1f 690 orr x2, x2, #(TCR_HA) 691 b 2f 6921: 693 cmp x3, #2 694 b.ne 2f 695 orr x2, x2, #(TCR_HA | TCR_HD) 6962: 697 msr tcr_el1, x2 698 699 /* 700 * Setup SCTLR. 701 */ 702 ldr x2, sctlr_set 703 ldr x3, sctlr_clear 704 mrs x1, sctlr_el1 705 bic x1, x1, x3 /* Clear the required bits */ 706 orr x1, x1, x2 /* Set the required bits */ 707 msr sctlr_el1, x1 708 isb 709 710 ret 711 712 .align 3 713mair: 714 .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE_nGnRnE) | \ 715 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \ 716 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \ 717 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) | \ 718 MAIR_ATTR(MAIR_DEVICE_nGnRE, VM_MEMATTR_DEVICE_nGnRE) 719tcr: 720 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | \ 721 TCR_CACHE_ATTRS | TCR_SMP_ATTRS) 722sctlr_set: 723 /* Bits to set */ 724 .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ 725 SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ 726 SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \ 727 SCTLR_M | SCTLR_CP15BEN) 728sctlr_clear: 729 /* Bits to clear */ 730 .quad (SCTLR_EE | SCTLR_EOE | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \ 731 SCTLR_ITD | SCTLR_A) 732LEND(start_mmu) 733 734ENTRY(abort) 735 b abort 736END(abort) 737 738 .section .init_pagetable, "aw", %nobits 739 .align PAGE_SHIFT 740 /* 741 * 6 initial tables (in the following order): 742 * L2 for kernel (High addresses) 743 * L1 for kernel 744 * L0 for kernel 745 * L1 bootstrap for user (Low addresses) 746 * L0 bootstrap for user 747 * L0 for user 748 */ 749pagetable: 750 .space PAGE_SIZE 751pagetable_l1_ttbr1: 752 .space PAGE_SIZE 753pagetable_l0_ttbr1: 754 .space PAGE_SIZE 755pagetable_l2_ttbr0_bootstrap: 756 .space PAGE_SIZE 757pagetable_l1_ttbr0_bootstrap: 758 .space PAGE_SIZE 759pagetable_l0_ttbr0_boostrap: 760 .space PAGE_SIZE 761pagetable_l0_ttbr0: 762 .space PAGE_SIZE 763 764 .globl pagetable_dmap 765pagetable_dmap: 766 .space PAGE_SIZE * DMAP_TABLES 767pagetable_end: 768 769el2_pagetable: 770 .space PAGE_SIZE 771 772 .align 4 773initstack: 774 .space (PAGE_SIZE * KSTACK_PAGES) 775initstack_end: 776 777 778ENTRY(sigcode) 779 mov x0, sp 780 add x0, x0, #SF_UC 781 7821: 783 mov x8, #SYS_sigreturn 784 svc 0 785 786 /* sigreturn failed, exit */ 787 mov x8, #SYS_exit 788 svc 0 789 790 b 1b 791END(sigcode) 792 /* This may be copied to the stack, keep it 16-byte aligned */ 793 .align 3 794esigcode: 795 796 .data 797 .align 3 798 .global szsigcode 799szsigcode: 800 .quad esigcode - sigcode 801 802EENTRY(aarch32_sigcode) 803 .word 0xe1a0000d // mov r0, sp 804 .word 0xe2800040 // add r0, r0, #SIGF_UC 805 .word 0xe59f700c // ldr r7, [pc, #12] 806 .word 0xef000000 // swi #0 807 .word 0xe59f7008 // ldr r7, [pc, #8] 808 .word 0xef000000 // swi #0 809 .word 0xeafffffa // b . - 16 810EEND(aarch32_sigcode) 811 .word SYS_sigreturn 812 .word SYS_exit 813 .align 3 814aarch32_esigcode: 815 .data 816 .global sz_aarch32_sigcode 817sz_aarch32_sigcode: 818 .quad aarch32_esigcode - aarch32_sigcode 819