1 /*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2003 Peter Wemm 9 * All rights reserved. 10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 11 * All rights reserved. 12 * Copyright (c) 2014 Andrew Turner 13 * All rights reserved. 14 * Copyright (c) 2014-2016 The FreeBSD Foundation 15 * All rights reserved. 16 * 17 * This code is derived from software contributed to Berkeley by 18 * the Systems Programming Group of the University of Utah Computer 19 * Science Department and William Jolitz of UUNET Technologies Inc. 20 * 21 * This software was developed by Andrew Turner under sponsorship from 22 * the FreeBSD Foundation. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by the University of 35 * California, Berkeley and its contributors. 36 * 4. Neither the name of the University nor the names of its contributors 37 * may be used to endorse or promote products derived from this software 38 * without specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 /*- 53 * Copyright (c) 2003 Networks Associates Technology, Inc. 54 * All rights reserved. 55 * 56 * This software was developed for the FreeBSD Project by Jake Burkholder, 57 * Safeport Network Services, and Network Associates Laboratories, the 58 * Security Research Division of Network Associates, Inc. under 59 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 60 * CHATS research program. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions 64 * are met: 65 * 1. Redistributions of source code must retain the above copyright 66 * notice, this list of conditions and the following disclaimer. 67 * 2. Redistributions in binary form must reproduce the above copyright 68 * notice, this list of conditions and the following disclaimer in the 69 * documentation and/or other materials provided with the distribution. 70 * 71 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 72 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 74 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 77 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 78 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 79 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 80 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 81 * SUCH DAMAGE. 82 */ 83 84 #include <sys/cdefs.h> 85 /* 86 * Manages physical address maps. 87 * 88 * Since the information managed by this module is 89 * also stored by the logical address mapping module, 90 * this module may throw away valid virtual-to-physical 91 * mappings at almost any time. However, invalidations 92 * of virtual-to-physical mappings must be done as 93 * requested. 94 * 95 * In order to cope with hardware architectures which 96 * make virtual-to-physical map invalidates expensive, 97 * this module may delay invalidate or reduced protection 98 * operations until such time as they are actually 99 * necessary. This module is given full information as 100 * to which processors are currently using which maps, 101 * and to when physical maps must be made correct. 102 */ 103 104 #include "opt_vm.h" 105 106 #include <sys/param.h> 107 #include <sys/asan.h> 108 #include <sys/bitstring.h> 109 #include <sys/bus.h> 110 #include <sys/systm.h> 111 #include <sys/kernel.h> 112 #include <sys/ktr.h> 113 #include <sys/limits.h> 114 #include <sys/lock.h> 115 #include <sys/malloc.h> 116 #include <sys/mman.h> 117 #include <sys/msan.h> 118 #include <sys/msgbuf.h> 119 #include <sys/mutex.h> 120 #include <sys/physmem.h> 121 #include <sys/proc.h> 122 #include <sys/rwlock.h> 123 #include <sys/sbuf.h> 124 #include <sys/sx.h> 125 #include <sys/vmem.h> 126 #include <sys/vmmeter.h> 127 #include <sys/sched.h> 128 #include <sys/sysctl.h> 129 #include <sys/_unrhdr.h> 130 #include <sys/smp.h> 131 132 #include <vm/vm.h> 133 #include <vm/vm_param.h> 134 #include <vm/vm_kern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_map.h> 137 #include <vm/vm_object.h> 138 #include <vm/vm_extern.h> 139 #include <vm/vm_pageout.h> 140 #include <vm/vm_pager.h> 141 #include <vm/vm_phys.h> 142 #include <vm/vm_radix.h> 143 #include <vm/vm_reserv.h> 144 #include <vm/vm_dumpset.h> 145 #include <vm/uma.h> 146 147 #include <machine/asan.h> 148 #include <machine/machdep.h> 149 #include <machine/md_var.h> 150 #include <machine/pcb.h> 151 152 #ifdef NUMA 153 #define PMAP_MEMDOM MAXMEMDOM 154 #else 155 #define PMAP_MEMDOM 1 156 #endif 157 158 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1) 159 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2) 160 161 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t))) 162 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t))) 163 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t))) 164 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t))) 165 166 #define NUL0E L0_ENTRIES 167 #define NUL1E (NUL0E * NL1PG) 168 #define NUL2E (NUL1E * NL2PG) 169 170 #ifdef PV_STATS 171 #define PV_STAT(x) do { x ; } while (0) 172 #define __pvused 173 #else 174 #define PV_STAT(x) do { } while (0) 175 #define __pvused __unused 176 #endif 177 178 #define pmap_l0_pindex(v) (NUL2E + NUL1E + ((v) >> L0_SHIFT)) 179 #define pmap_l1_pindex(v) (NUL2E + ((v) >> L1_SHIFT)) 180 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT) 181 182 #ifdef __ARM_FEATURE_BTI_DEFAULT 183 #define ATTR_KERN_GP ATTR_S1_GP 184 #else 185 #define ATTR_KERN_GP 0 186 #endif 187 #define PMAP_SAN_PTE_BITS (ATTR_DEFAULT | ATTR_S1_XN | ATTR_KERN_GP | \ 188 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | ATTR_S1_AP(ATTR_S1_AP_RW)) 189 190 struct pmap_large_md_page { 191 struct rwlock pv_lock; 192 struct md_page pv_page; 193 /* Pad to a power of 2, see pmap_init_pv_table(). */ 194 int pv_pad[2]; 195 }; 196 197 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large; 198 #define pv_dummy pv_dummy_large.pv_page 199 __read_mostly static struct pmap_large_md_page *pv_table; 200 201 static struct pmap_large_md_page * 202 _pa_to_pmdp(vm_paddr_t pa) 203 { 204 struct vm_phys_seg *seg; 205 206 if ((seg = vm_phys_paddr_to_seg(pa)) != NULL) 207 return ((struct pmap_large_md_page *)seg->md_first + 208 pmap_l2_pindex(pa) - pmap_l2_pindex(seg->start)); 209 return (NULL); 210 } 211 212 static struct pmap_large_md_page * 213 pa_to_pmdp(vm_paddr_t pa) 214 { 215 struct pmap_large_md_page *pvd; 216 217 pvd = _pa_to_pmdp(pa); 218 if (pvd == NULL) 219 panic("pa 0x%jx not within vm_phys_segs", (uintmax_t)pa); 220 return (pvd); 221 } 222 223 static struct pmap_large_md_page * 224 page_to_pmdp(vm_page_t m) 225 { 226 struct vm_phys_seg *seg; 227 228 seg = &vm_phys_segs[m->segind]; 229 return ((struct pmap_large_md_page *)seg->md_first + 230 pmap_l2_pindex(VM_PAGE_TO_PHYS(m)) - pmap_l2_pindex(seg->start)); 231 } 232 233 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page)) 234 #define page_to_pvh(m) (&(page_to_pmdp(m)->pv_page)) 235 236 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \ 237 struct pmap_large_md_page *_pvd; \ 238 struct rwlock *_lock; \ 239 _pvd = _pa_to_pmdp(pa); \ 240 if (__predict_false(_pvd == NULL)) \ 241 _lock = &pv_dummy_large.pv_lock; \ 242 else \ 243 _lock = &(_pvd->pv_lock); \ 244 _lock; \ 245 }) 246 247 static struct rwlock * 248 VM_PAGE_TO_PV_LIST_LOCK(vm_page_t m) 249 { 250 if ((m->flags & PG_FICTITIOUS) == 0) 251 return (&page_to_pmdp(m)->pv_lock); 252 else 253 return (&pv_dummy_large.pv_lock); 254 } 255 256 #define CHANGE_PV_LIST_LOCK(lockp, new_lock) do { \ 257 struct rwlock **_lockp = (lockp); \ 258 struct rwlock *_new_lock = (new_lock); \ 259 \ 260 if (_new_lock != *_lockp) { \ 261 if (*_lockp != NULL) \ 262 rw_wunlock(*_lockp); \ 263 *_lockp = _new_lock; \ 264 rw_wlock(*_lockp); \ 265 } \ 266 } while (0) 267 268 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) \ 269 CHANGE_PV_LIST_LOCK(lockp, PHYS_TO_PV_LIST_LOCK(pa)) 270 271 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \ 272 CHANGE_PV_LIST_LOCK(lockp, VM_PAGE_TO_PV_LIST_LOCK(m)) 273 274 #define RELEASE_PV_LIST_LOCK(lockp) do { \ 275 struct rwlock **_lockp = (lockp); \ 276 \ 277 if (*_lockp != NULL) { \ 278 rw_wunlock(*_lockp); \ 279 *_lockp = NULL; \ 280 } \ 281 } while (0) 282 283 /* 284 * The presence of this flag indicates that the mapping is writeable. 285 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise 286 * it is dirty. This flag may only be set on managed mappings. 287 * 288 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it 289 * as a software managed bit. 290 */ 291 #define ATTR_SW_DBM ATTR_DBM 292 293 struct pmap kernel_pmap_store; 294 295 /* Used for mapping ACPI memory before VM is initialized */ 296 #define PMAP_PREINIT_MAPPING_COUNT 32 297 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE) 298 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */ 299 static int vm_initialized = 0; /* No need to use pre-init maps when set */ 300 301 /* 302 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer. 303 * Always map entire L2 block for simplicity. 304 * VA of L2 block = preinit_map_va + i * L2_SIZE 305 */ 306 static struct pmap_preinit_mapping { 307 vm_paddr_t pa; 308 vm_offset_t va; 309 vm_size_t size; 310 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT]; 311 312 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 313 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 314 vm_offset_t kernel_vm_end = 0; 315 316 /* 317 * Data for the pv entry allocation mechanism. 318 */ 319 #ifdef NUMA 320 static __inline int 321 pc_to_domain(struct pv_chunk *pc) 322 { 323 return (vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc))); 324 } 325 #else 326 static __inline int 327 pc_to_domain(struct pv_chunk *pc __unused) 328 { 329 return (0); 330 } 331 #endif 332 333 struct pv_chunks_list { 334 struct mtx pvc_lock; 335 TAILQ_HEAD(pch, pv_chunk) pvc_list; 336 int active_reclaims; 337 } __aligned(CACHE_LINE_SIZE); 338 339 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM]; 340 341 vm_paddr_t dmap_phys_base; /* The start of the dmap region */ 342 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */ 343 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */ 344 345 extern pt_entry_t pagetable_l0_ttbr1[]; 346 347 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 348 static vm_paddr_t physmap[PHYSMAP_SIZE]; 349 static u_int physmap_idx; 350 351 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 352 "VM/pmap parameters"); 353 354 #if PAGE_SIZE == PAGE_SIZE_4K 355 #define L1_BLOCKS_SUPPORTED 1 356 #else 357 /* TODO: Make this dynamic when we support FEAT_LPA2 (TCR_EL1.DS == 1) */ 358 #define L1_BLOCKS_SUPPORTED 0 359 #endif 360 361 #define PMAP_ASSERT_L1_BLOCKS_SUPPORTED MPASS(L1_BLOCKS_SUPPORTED) 362 363 /* 364 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs 365 * that it has currently allocated to a pmap, a cursor ("asid_next") to 366 * optimize its search for a free ASID in the bit vector, and an epoch number 367 * ("asid_epoch") to indicate when it has reclaimed all previously allocated 368 * ASIDs that are not currently active on a processor. 369 * 370 * The current epoch number is always in the range [0, INT_MAX). Negative 371 * numbers and INT_MAX are reserved for special cases that are described 372 * below. 373 */ 374 struct asid_set { 375 int asid_bits; 376 bitstr_t *asid_set; 377 int asid_set_size; 378 int asid_next; 379 int asid_epoch; 380 struct mtx asid_set_mutex; 381 }; 382 383 static struct asid_set asids; 384 static struct asid_set vmids; 385 386 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 387 "ASID allocator"); 388 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asids.asid_bits, 0, 389 "The number of bits in an ASID"); 390 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asids.asid_next, 0, 391 "The last allocated ASID plus one"); 392 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asids.asid_epoch, 0, 393 "The current epoch number"); 394 395 static SYSCTL_NODE(_vm_pmap, OID_AUTO, vmid, CTLFLAG_RD, 0, "VMID allocator"); 396 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, bits, CTLFLAG_RD, &vmids.asid_bits, 0, 397 "The number of bits in an VMID"); 398 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, next, CTLFLAG_RD, &vmids.asid_next, 0, 399 "The last allocated VMID plus one"); 400 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, epoch, CTLFLAG_RD, &vmids.asid_epoch, 0, 401 "The current epoch number"); 402 403 void (*pmap_clean_stage2_tlbi)(void); 404 void (*pmap_invalidate_vpipt_icache)(void); 405 void (*pmap_stage2_invalidate_range)(uint64_t, vm_offset_t, vm_offset_t, bool); 406 void (*pmap_stage2_invalidate_all)(uint64_t); 407 408 /* 409 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved 410 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for 411 * dynamically allocated ASIDs have a non-negative epoch number. 412 * 413 * An invalid ASID is represented by -1. 414 * 415 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN), 416 * which indicates that an ASID should never be allocated to the pmap, and 417 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be 418 * allocated when the pmap is next activated. 419 */ 420 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \ 421 ((u_long)(epoch) << 32))) 422 #define COOKIE_TO_ASID(cookie) ((int)(cookie)) 423 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32)) 424 425 #define TLBI_VA_SHIFT 12 426 #define TLBI_VA_MASK ((1ul << 44) - 1) 427 #define TLBI_VA(addr) (((addr) >> TLBI_VA_SHIFT) & TLBI_VA_MASK) 428 #define TLBI_VA_L3_INCR (L3_SIZE >> TLBI_VA_SHIFT) 429 430 static int __read_frequently superpages_enabled = 1; 431 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled, 432 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0, 433 "Are large page mappings enabled?"); 434 435 /* 436 * Internal flags for pmap_enter()'s helper functions. 437 */ 438 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */ 439 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */ 440 441 TAILQ_HEAD(pv_chunklist, pv_chunk); 442 443 static void free_pv_chunk(struct pv_chunk *pc); 444 static void free_pv_chunk_batch(struct pv_chunklist *batch); 445 static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 446 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp); 447 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp); 448 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 449 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 450 vm_offset_t va); 451 452 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte); 453 static bool pmap_activate_int(pmap_t pmap); 454 static void pmap_alloc_asid(pmap_t pmap); 455 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size, 456 vm_prot_t prot, int mode, bool skip_unmapped); 457 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va); 458 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, 459 vm_offset_t va, struct rwlock **lockp); 460 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va); 461 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 462 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp); 463 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, 464 u_int flags, vm_page_t m, struct rwlock **lockp); 465 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, 466 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp); 467 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva, 468 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp); 469 static void pmap_reset_asid_set(pmap_t pmap); 470 static bool pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 471 vm_page_t m, struct rwlock **lockp); 472 473 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, 474 struct rwlock **lockp); 475 476 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, 477 struct spglist *free); 478 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *); 479 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va); 480 481 static pt_entry_t pmap_pte_bti(pmap_t pmap, vm_offset_t va); 482 483 /* 484 * These load the old table data and store the new value. 485 * They need to be atomic as the System MMU may write to the table at 486 * the same time as the CPU. 487 */ 488 #define pmap_clear(table) atomic_store_64(table, 0) 489 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits) 490 #define pmap_load(table) (*table) 491 #define pmap_load_clear(table) atomic_swap_64(table, 0) 492 #define pmap_load_store(table, entry) atomic_swap_64(table, entry) 493 #define pmap_set_bits(table, bits) atomic_set_64(table, bits) 494 #define pmap_store(table, entry) atomic_store_64(table, entry) 495 496 /********************/ 497 /* Inline functions */ 498 /********************/ 499 500 static __inline void 501 pagecopy(void *s, void *d) 502 { 503 504 memcpy(d, s, PAGE_SIZE); 505 } 506 507 static __inline pd_entry_t * 508 pmap_l0(pmap_t pmap, vm_offset_t va) 509 { 510 511 return (&pmap->pm_l0[pmap_l0_index(va)]); 512 } 513 514 static __inline pd_entry_t * 515 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va) 516 { 517 pd_entry_t *l1; 518 519 l1 = (pd_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(pmap_load(l0))); 520 return (&l1[pmap_l1_index(va)]); 521 } 522 523 static __inline pd_entry_t * 524 pmap_l1(pmap_t pmap, vm_offset_t va) 525 { 526 pd_entry_t *l0; 527 528 l0 = pmap_l0(pmap, va); 529 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE) 530 return (NULL); 531 532 return (pmap_l0_to_l1(l0, va)); 533 } 534 535 static __inline pd_entry_t * 536 pmap_l1_to_l2(pd_entry_t *l1p, vm_offset_t va) 537 { 538 pd_entry_t l1, *l2p; 539 540 l1 = pmap_load(l1p); 541 542 KASSERT(ADDR_IS_CANONICAL(va), 543 ("%s: Address not in canonical form: %lx", __func__, va)); 544 /* 545 * The valid bit may be clear if pmap_update_entry() is concurrently 546 * modifying the entry, so for KVA only the entry type may be checked. 547 */ 548 KASSERT(ADDR_IS_KERNEL(va) || (l1 & ATTR_DESCR_VALID) != 0, 549 ("%s: L1 entry %#lx for %#lx is invalid", __func__, l1, va)); 550 KASSERT((l1 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE, 551 ("%s: L1 entry %#lx for %#lx is a leaf", __func__, l1, va)); 552 l2p = (pd_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(l1)); 553 return (&l2p[pmap_l2_index(va)]); 554 } 555 556 static __inline pd_entry_t * 557 pmap_l2(pmap_t pmap, vm_offset_t va) 558 { 559 pd_entry_t *l1; 560 561 l1 = pmap_l1(pmap, va); 562 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE) 563 return (NULL); 564 565 return (pmap_l1_to_l2(l1, va)); 566 } 567 568 static __inline pt_entry_t * 569 pmap_l2_to_l3(pd_entry_t *l2p, vm_offset_t va) 570 { 571 pd_entry_t l2; 572 pt_entry_t *l3p; 573 574 l2 = pmap_load(l2p); 575 576 KASSERT(ADDR_IS_CANONICAL(va), 577 ("%s: Address not in canonical form: %lx", __func__, va)); 578 /* 579 * The valid bit may be clear if pmap_update_entry() is concurrently 580 * modifying the entry, so for KVA only the entry type may be checked. 581 */ 582 KASSERT(ADDR_IS_KERNEL(va) || (l2 & ATTR_DESCR_VALID) != 0, 583 ("%s: L2 entry %#lx for %#lx is invalid", __func__, l2, va)); 584 KASSERT((l2 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE, 585 ("%s: L2 entry %#lx for %#lx is a leaf", __func__, l2, va)); 586 l3p = (pt_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(l2)); 587 return (&l3p[pmap_l3_index(va)]); 588 } 589 590 /* 591 * Returns the lowest valid pde for a given virtual address. 592 * The next level may or may not point to a valid page or block. 593 */ 594 static __inline pd_entry_t * 595 pmap_pde(pmap_t pmap, vm_offset_t va, int *level) 596 { 597 pd_entry_t *l0, *l1, *l2, desc; 598 599 l0 = pmap_l0(pmap, va); 600 desc = pmap_load(l0) & ATTR_DESCR_MASK; 601 if (desc != L0_TABLE) { 602 *level = -1; 603 return (NULL); 604 } 605 606 l1 = pmap_l0_to_l1(l0, va); 607 desc = pmap_load(l1) & ATTR_DESCR_MASK; 608 if (desc != L1_TABLE) { 609 *level = 0; 610 return (l0); 611 } 612 613 l2 = pmap_l1_to_l2(l1, va); 614 desc = pmap_load(l2) & ATTR_DESCR_MASK; 615 if (desc != L2_TABLE) { 616 *level = 1; 617 return (l1); 618 } 619 620 *level = 2; 621 return (l2); 622 } 623 624 /* 625 * Returns the lowest valid pte block or table entry for a given virtual 626 * address. If there are no valid entries return NULL and set the level to 627 * the first invalid level. 628 */ 629 static __inline pt_entry_t * 630 pmap_pte(pmap_t pmap, vm_offset_t va, int *level) 631 { 632 pd_entry_t *l1, *l2, desc; 633 pt_entry_t *l3; 634 635 l1 = pmap_l1(pmap, va); 636 if (l1 == NULL) { 637 *level = 0; 638 return (NULL); 639 } 640 desc = pmap_load(l1) & ATTR_DESCR_MASK; 641 if (desc == L1_BLOCK) { 642 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 643 *level = 1; 644 return (l1); 645 } 646 647 if (desc != L1_TABLE) { 648 *level = 1; 649 return (NULL); 650 } 651 652 l2 = pmap_l1_to_l2(l1, va); 653 desc = pmap_load(l2) & ATTR_DESCR_MASK; 654 if (desc == L2_BLOCK) { 655 *level = 2; 656 return (l2); 657 } 658 659 if (desc != L2_TABLE) { 660 *level = 2; 661 return (NULL); 662 } 663 664 *level = 3; 665 l3 = pmap_l2_to_l3(l2, va); 666 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE) 667 return (NULL); 668 669 return (l3); 670 } 671 672 /* 673 * If the given pmap has an L{1,2}_BLOCK or L3_PAGE entry at the specified 674 * level that maps the specified virtual address, then a pointer to that entry 675 * is returned. Otherwise, NULL is returned, unless INVARIANTS are enabled 676 * and a diagnostic message is provided, in which case this function panics. 677 */ 678 static __always_inline pt_entry_t * 679 pmap_pte_exists(pmap_t pmap, vm_offset_t va, int level, const char *diag) 680 { 681 pd_entry_t *l0p, *l1p, *l2p; 682 pt_entry_t desc, *l3p; 683 int walk_level __diagused; 684 685 KASSERT(level >= 0 && level < 4, 686 ("%s: %s passed an out-of-range level (%d)", __func__, diag, 687 level)); 688 l0p = pmap_l0(pmap, va); 689 desc = pmap_load(l0p) & ATTR_DESCR_MASK; 690 if (desc == L0_TABLE && level > 0) { 691 l1p = pmap_l0_to_l1(l0p, va); 692 desc = pmap_load(l1p) & ATTR_DESCR_MASK; 693 if (desc == L1_BLOCK && level == 1) { 694 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 695 return (l1p); 696 } 697 if (desc == L1_TABLE && level > 1) { 698 l2p = pmap_l1_to_l2(l1p, va); 699 desc = pmap_load(l2p) & ATTR_DESCR_MASK; 700 if (desc == L2_BLOCK && level == 2) 701 return (l2p); 702 else if (desc == L2_TABLE && level > 2) { 703 l3p = pmap_l2_to_l3(l2p, va); 704 desc = pmap_load(l3p) & ATTR_DESCR_MASK; 705 if (desc == L3_PAGE && level == 3) 706 return (l3p); 707 else 708 walk_level = 3; 709 } else 710 walk_level = 2; 711 } else 712 walk_level = 1; 713 } else 714 walk_level = 0; 715 KASSERT(diag == NULL, 716 ("%s: va %#lx not mapped at level %d, desc %ld at level %d", 717 diag, va, level, desc, walk_level)); 718 return (NULL); 719 } 720 721 bool 722 pmap_ps_enabled(pmap_t pmap) 723 { 724 /* 725 * Promotion requires a hypervisor call when the kernel is running 726 * in EL1. To stop this disable superpage support on non-stage 1 727 * pmaps for now. 728 */ 729 if (pmap->pm_stage != PM_STAGE1) 730 return (false); 731 732 #ifdef KMSAN 733 /* 734 * The break-before-make in pmap_update_entry() results in a situation 735 * where a CPU may call into the KMSAN runtime while the entry is 736 * invalid. If the entry is used to map the current thread structure, 737 * then the runtime will attempt to access unmapped memory. Avoid this 738 * by simply disabling superpage promotion for the kernel map. 739 */ 740 if (pmap == kernel_pmap) 741 return (false); 742 #endif 743 744 return (superpages_enabled != 0); 745 } 746 747 bool 748 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1, 749 pd_entry_t **l2, pt_entry_t **l3) 750 { 751 pd_entry_t *l0p, *l1p, *l2p; 752 753 if (pmap->pm_l0 == NULL) 754 return (false); 755 756 l0p = pmap_l0(pmap, va); 757 *l0 = l0p; 758 759 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE) 760 return (false); 761 762 l1p = pmap_l0_to_l1(l0p, va); 763 *l1 = l1p; 764 765 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) { 766 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 767 *l2 = NULL; 768 *l3 = NULL; 769 return (true); 770 } 771 772 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE) 773 return (false); 774 775 l2p = pmap_l1_to_l2(l1p, va); 776 *l2 = l2p; 777 778 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) { 779 *l3 = NULL; 780 return (true); 781 } 782 783 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE) 784 return (false); 785 786 *l3 = pmap_l2_to_l3(l2p, va); 787 788 return (true); 789 } 790 791 static __inline int 792 pmap_l3_valid(pt_entry_t l3) 793 { 794 795 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE); 796 } 797 798 CTASSERT(L1_BLOCK == L2_BLOCK); 799 800 static pt_entry_t 801 pmap_pte_memattr(pmap_t pmap, vm_memattr_t memattr) 802 { 803 pt_entry_t val; 804 805 if (pmap->pm_stage == PM_STAGE1) { 806 val = ATTR_S1_IDX(memattr); 807 if (memattr == VM_MEMATTR_DEVICE) 808 val |= ATTR_S1_XN; 809 return (val); 810 } 811 812 val = 0; 813 814 switch (memattr) { 815 case VM_MEMATTR_DEVICE: 816 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_DEVICE_nGnRnE) | 817 ATTR_S2_XN(ATTR_S2_XN_ALL)); 818 case VM_MEMATTR_UNCACHEABLE: 819 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_NC)); 820 case VM_MEMATTR_WRITE_BACK: 821 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WB)); 822 case VM_MEMATTR_WRITE_THROUGH: 823 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WT)); 824 default: 825 panic("%s: invalid memory attribute %x", __func__, memattr); 826 } 827 } 828 829 static pt_entry_t 830 pmap_pte_prot(pmap_t pmap, vm_prot_t prot) 831 { 832 pt_entry_t val; 833 834 val = 0; 835 if (pmap->pm_stage == PM_STAGE1) { 836 if ((prot & VM_PROT_EXECUTE) == 0) 837 val |= ATTR_S1_XN; 838 if ((prot & VM_PROT_WRITE) == 0) 839 val |= ATTR_S1_AP(ATTR_S1_AP_RO); 840 } else { 841 if ((prot & VM_PROT_WRITE) != 0) 842 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE); 843 if ((prot & VM_PROT_READ) != 0) 844 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_READ); 845 if ((prot & VM_PROT_EXECUTE) == 0) 846 val |= ATTR_S2_XN(ATTR_S2_XN_ALL); 847 } 848 849 return (val); 850 } 851 852 /* 853 * Checks if the PTE is dirty. 854 */ 855 static inline int 856 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte) 857 { 858 859 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte)); 860 861 if (pmap->pm_stage == PM_STAGE1) { 862 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0, 863 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte)); 864 865 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == 866 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM)); 867 } 868 869 return ((pte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) == 870 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)); 871 } 872 873 static __inline void 874 pmap_resident_count_inc(pmap_t pmap, int count) 875 { 876 877 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 878 pmap->pm_stats.resident_count += count; 879 } 880 881 static __inline void 882 pmap_resident_count_dec(pmap_t pmap, int count) 883 { 884 885 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 886 KASSERT(pmap->pm_stats.resident_count >= count, 887 ("pmap %p resident count underflow %ld %d", pmap, 888 pmap->pm_stats.resident_count, count)); 889 pmap->pm_stats.resident_count -= count; 890 } 891 892 static vm_paddr_t 893 pmap_early_vtophys(vm_offset_t va) 894 { 895 vm_paddr_t pa_page; 896 897 pa_page = arm64_address_translate_s1e1r(va) & PAR_PA_MASK; 898 return (pa_page | (va & PAR_LOW_MASK)); 899 } 900 901 /* State of the bootstrapped DMAP page tables */ 902 struct pmap_bootstrap_state { 903 pt_entry_t *l1; 904 pt_entry_t *l2; 905 pt_entry_t *l3; 906 vm_offset_t freemempos; 907 vm_offset_t va; 908 vm_paddr_t pa; 909 pt_entry_t table_attrs; 910 u_int l0_slot; 911 u_int l1_slot; 912 u_int l2_slot; 913 bool dmap_valid; 914 }; 915 916 /* The bootstrap state */ 917 static struct pmap_bootstrap_state bs_state = { 918 .l1 = NULL, 919 .l2 = NULL, 920 .l3 = NULL, 921 .table_attrs = TATTR_PXN_TABLE, 922 .l0_slot = L0_ENTRIES, 923 .l1_slot = Ln_ENTRIES, 924 .l2_slot = Ln_ENTRIES, 925 .dmap_valid = false, 926 }; 927 928 static void 929 pmap_bootstrap_l0_table(struct pmap_bootstrap_state *state) 930 { 931 vm_paddr_t l1_pa; 932 pd_entry_t l0e; 933 u_int l0_slot; 934 935 /* Link the level 0 table to a level 1 table */ 936 l0_slot = pmap_l0_index(state->va); 937 if (l0_slot != state->l0_slot) { 938 /* 939 * Make sure we move from a low address to high address 940 * before the DMAP region is ready. This ensures we never 941 * modify an existing mapping until we can map from a 942 * physical address to a virtual address. 943 */ 944 MPASS(state->l0_slot < l0_slot || 945 state->l0_slot == L0_ENTRIES || 946 state->dmap_valid); 947 948 /* Reset lower levels */ 949 state->l2 = NULL; 950 state->l3 = NULL; 951 state->l1_slot = Ln_ENTRIES; 952 state->l2_slot = Ln_ENTRIES; 953 954 /* Check the existing L0 entry */ 955 state->l0_slot = l0_slot; 956 if (state->dmap_valid) { 957 l0e = pagetable_l0_ttbr1[l0_slot]; 958 if ((l0e & ATTR_DESCR_VALID) != 0) { 959 MPASS((l0e & ATTR_DESCR_MASK) == L0_TABLE); 960 l1_pa = PTE_TO_PHYS(l0e); 961 state->l1 = (pt_entry_t *)PHYS_TO_DMAP(l1_pa); 962 return; 963 } 964 } 965 966 /* Create a new L0 table entry */ 967 state->l1 = (pt_entry_t *)state->freemempos; 968 memset(state->l1, 0, PAGE_SIZE); 969 state->freemempos += PAGE_SIZE; 970 971 l1_pa = pmap_early_vtophys((vm_offset_t)state->l1); 972 MPASS((l1_pa & Ln_TABLE_MASK) == 0); 973 MPASS(pagetable_l0_ttbr1[l0_slot] == 0); 974 pmap_store(&pagetable_l0_ttbr1[l0_slot], PHYS_TO_PTE(l1_pa) | 975 TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0 | L0_TABLE); 976 } 977 KASSERT(state->l1 != NULL, ("%s: NULL l1", __func__)); 978 } 979 980 static void 981 pmap_bootstrap_l1_table(struct pmap_bootstrap_state *state) 982 { 983 vm_paddr_t l2_pa; 984 pd_entry_t l1e; 985 u_int l1_slot; 986 987 /* Make sure there is a valid L0 -> L1 table */ 988 pmap_bootstrap_l0_table(state); 989 990 /* Link the level 1 table to a level 2 table */ 991 l1_slot = pmap_l1_index(state->va); 992 if (l1_slot != state->l1_slot) { 993 /* See pmap_bootstrap_l0_table for a description */ 994 MPASS(state->l1_slot < l1_slot || 995 state->l1_slot == Ln_ENTRIES || 996 state->dmap_valid); 997 998 /* Reset lower levels */ 999 state->l3 = NULL; 1000 state->l2_slot = Ln_ENTRIES; 1001 1002 /* Check the existing L1 entry */ 1003 state->l1_slot = l1_slot; 1004 if (state->dmap_valid) { 1005 l1e = state->l1[l1_slot]; 1006 if ((l1e & ATTR_DESCR_VALID) != 0) { 1007 MPASS((l1e & ATTR_DESCR_MASK) == L1_TABLE); 1008 l2_pa = PTE_TO_PHYS(l1e); 1009 state->l2 = (pt_entry_t *)PHYS_TO_DMAP(l2_pa); 1010 return; 1011 } 1012 } 1013 1014 /* Create a new L1 table entry */ 1015 state->l2 = (pt_entry_t *)state->freemempos; 1016 memset(state->l2, 0, PAGE_SIZE); 1017 state->freemempos += PAGE_SIZE; 1018 1019 l2_pa = pmap_early_vtophys((vm_offset_t)state->l2); 1020 MPASS((l2_pa & Ln_TABLE_MASK) == 0); 1021 MPASS(state->l1[l1_slot] == 0); 1022 pmap_store(&state->l1[l1_slot], PHYS_TO_PTE(l2_pa) | 1023 state->table_attrs | L1_TABLE); 1024 } 1025 KASSERT(state->l2 != NULL, ("%s: NULL l2", __func__)); 1026 } 1027 1028 static void 1029 pmap_bootstrap_l2_table(struct pmap_bootstrap_state *state) 1030 { 1031 vm_paddr_t l3_pa; 1032 pd_entry_t l2e; 1033 u_int l2_slot; 1034 1035 /* Make sure there is a valid L1 -> L2 table */ 1036 pmap_bootstrap_l1_table(state); 1037 1038 /* Link the level 2 table to a level 3 table */ 1039 l2_slot = pmap_l2_index(state->va); 1040 if (l2_slot != state->l2_slot) { 1041 /* See pmap_bootstrap_l0_table for a description */ 1042 MPASS(state->l2_slot < l2_slot || 1043 state->l2_slot == Ln_ENTRIES || 1044 state->dmap_valid); 1045 1046 /* Check the existing L2 entry */ 1047 state->l2_slot = l2_slot; 1048 if (state->dmap_valid) { 1049 l2e = state->l2[l2_slot]; 1050 if ((l2e & ATTR_DESCR_VALID) != 0) { 1051 MPASS((l2e & ATTR_DESCR_MASK) == L2_TABLE); 1052 l3_pa = PTE_TO_PHYS(l2e); 1053 state->l3 = (pt_entry_t *)PHYS_TO_DMAP(l3_pa); 1054 return; 1055 } 1056 } 1057 1058 /* Create a new L2 table entry */ 1059 state->l3 = (pt_entry_t *)state->freemempos; 1060 memset(state->l3, 0, PAGE_SIZE); 1061 state->freemempos += PAGE_SIZE; 1062 1063 l3_pa = pmap_early_vtophys((vm_offset_t)state->l3); 1064 MPASS((l3_pa & Ln_TABLE_MASK) == 0); 1065 MPASS(state->l2[l2_slot] == 0); 1066 pmap_store(&state->l2[l2_slot], PHYS_TO_PTE(l3_pa) | 1067 state->table_attrs | L2_TABLE); 1068 } 1069 KASSERT(state->l3 != NULL, ("%s: NULL l3", __func__)); 1070 } 1071 1072 static void 1073 pmap_bootstrap_l2_block(struct pmap_bootstrap_state *state, int i) 1074 { 1075 u_int l2_slot; 1076 bool first; 1077 1078 if ((physmap[i + 1] - state->pa) < L2_SIZE) 1079 return; 1080 1081 /* Make sure there is a valid L1 table */ 1082 pmap_bootstrap_l1_table(state); 1083 1084 MPASS((state->va & L2_OFFSET) == 0); 1085 for (first = true; 1086 state->va < DMAP_MAX_ADDRESS && 1087 (physmap[i + 1] - state->pa) >= L2_SIZE; 1088 state->va += L2_SIZE, state->pa += L2_SIZE) { 1089 /* 1090 * Stop if we are about to walk off the end of what the 1091 * current L1 slot can address. 1092 */ 1093 if (!first && (state->pa & L1_OFFSET) == 0) 1094 break; 1095 1096 first = false; 1097 l2_slot = pmap_l2_index(state->va); 1098 MPASS((state->pa & L2_OFFSET) == 0); 1099 MPASS(state->l2[l2_slot] == 0); 1100 pmap_store(&state->l2[l2_slot], PHYS_TO_PTE(state->pa) | 1101 ATTR_DEFAULT | ATTR_S1_XN | ATTR_KERN_GP | 1102 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK); 1103 } 1104 MPASS(state->va == (state->pa - dmap_phys_base + DMAP_MIN_ADDRESS)); 1105 } 1106 1107 static void 1108 pmap_bootstrap_l3_page(struct pmap_bootstrap_state *state, int i) 1109 { 1110 u_int l3_slot; 1111 bool first; 1112 1113 if ((physmap[i + 1] - state->pa) < L3_SIZE) 1114 return; 1115 1116 /* Make sure there is a valid L2 table */ 1117 pmap_bootstrap_l2_table(state); 1118 1119 MPASS((state->va & L3_OFFSET) == 0); 1120 for (first = true; 1121 state->va < DMAP_MAX_ADDRESS && 1122 (physmap[i + 1] - state->pa) >= L3_SIZE; 1123 state->va += L3_SIZE, state->pa += L3_SIZE) { 1124 /* 1125 * Stop if we are about to walk off the end of what the 1126 * current L2 slot can address. 1127 */ 1128 if (!first && (state->pa & L2_OFFSET) == 0) 1129 break; 1130 1131 first = false; 1132 l3_slot = pmap_l3_index(state->va); 1133 MPASS((state->pa & L3_OFFSET) == 0); 1134 MPASS(state->l3[l3_slot] == 0); 1135 pmap_store(&state->l3[l3_slot], PHYS_TO_PTE(state->pa) | 1136 ATTR_DEFAULT | ATTR_S1_XN | ATTR_KERN_GP | 1137 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L3_PAGE); 1138 } 1139 MPASS(state->va == (state->pa - dmap_phys_base + DMAP_MIN_ADDRESS)); 1140 } 1141 1142 static void 1143 pmap_bootstrap_dmap(vm_paddr_t min_pa) 1144 { 1145 int i; 1146 1147 dmap_phys_base = min_pa & ~L1_OFFSET; 1148 dmap_phys_max = 0; 1149 dmap_max_addr = 0; 1150 1151 for (i = 0; i < (physmap_idx * 2); i += 2) { 1152 bs_state.pa = physmap[i] & ~L3_OFFSET; 1153 bs_state.va = bs_state.pa - dmap_phys_base + DMAP_MIN_ADDRESS; 1154 1155 /* Create L3 mappings at the start of the region */ 1156 if ((bs_state.pa & L2_OFFSET) != 0) 1157 pmap_bootstrap_l3_page(&bs_state, i); 1158 MPASS(bs_state.pa <= physmap[i + 1]); 1159 1160 if (L1_BLOCKS_SUPPORTED) { 1161 /* Create L2 mappings at the start of the region */ 1162 if ((bs_state.pa & L1_OFFSET) != 0) 1163 pmap_bootstrap_l2_block(&bs_state, i); 1164 MPASS(bs_state.pa <= physmap[i + 1]); 1165 1166 /* Create the main L1 block mappings */ 1167 for (; bs_state.va < DMAP_MAX_ADDRESS && 1168 (physmap[i + 1] - bs_state.pa) >= L1_SIZE; 1169 bs_state.va += L1_SIZE, bs_state.pa += L1_SIZE) { 1170 /* Make sure there is a valid L1 table */ 1171 pmap_bootstrap_l0_table(&bs_state); 1172 MPASS((bs_state.pa & L1_OFFSET) == 0); 1173 pmap_store( 1174 &bs_state.l1[pmap_l1_index(bs_state.va)], 1175 PHYS_TO_PTE(bs_state.pa) | ATTR_DEFAULT | 1176 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | 1177 ATTR_S1_XN | ATTR_KERN_GP | L1_BLOCK); 1178 } 1179 MPASS(bs_state.pa <= physmap[i + 1]); 1180 1181 /* Create L2 mappings at the end of the region */ 1182 pmap_bootstrap_l2_block(&bs_state, i); 1183 } else { 1184 while (bs_state.va < DMAP_MAX_ADDRESS && 1185 (physmap[i + 1] - bs_state.pa) >= L2_SIZE) { 1186 pmap_bootstrap_l2_block(&bs_state, i); 1187 } 1188 } 1189 MPASS(bs_state.pa <= physmap[i + 1]); 1190 1191 /* Create L3 mappings at the end of the region */ 1192 pmap_bootstrap_l3_page(&bs_state, i); 1193 MPASS(bs_state.pa == physmap[i + 1]); 1194 1195 if (bs_state.pa > dmap_phys_max) { 1196 dmap_phys_max = bs_state.pa; 1197 dmap_max_addr = bs_state.va; 1198 } 1199 } 1200 1201 cpu_tlb_flushID(); 1202 } 1203 1204 static void 1205 pmap_bootstrap_l2(vm_offset_t va) 1206 { 1207 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address")); 1208 1209 /* Leave bs_state.pa as it's only needed to bootstrap blocks and pages*/ 1210 bs_state.va = va; 1211 1212 for (; bs_state.va < VM_MAX_KERNEL_ADDRESS; bs_state.va += L1_SIZE) 1213 pmap_bootstrap_l1_table(&bs_state); 1214 } 1215 1216 static void 1217 pmap_bootstrap_l3(vm_offset_t va) 1218 { 1219 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address")); 1220 1221 /* Leave bs_state.pa as it's only needed to bootstrap blocks and pages*/ 1222 bs_state.va = va; 1223 1224 for (; bs_state.va < VM_MAX_KERNEL_ADDRESS; bs_state.va += L2_SIZE) 1225 pmap_bootstrap_l2_table(&bs_state); 1226 } 1227 1228 /* 1229 * Bootstrap the system enough to run with virtual memory. 1230 */ 1231 void 1232 pmap_bootstrap(vm_size_t kernlen) 1233 { 1234 vm_offset_t dpcpu, msgbufpv; 1235 vm_paddr_t start_pa, pa, min_pa; 1236 int i; 1237 1238 /* Verify that the ASID is set through TTBR0. */ 1239 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0, 1240 ("pmap_bootstrap: TCR_EL1.A1 != 0")); 1241 1242 /* Set this early so we can use the pagetable walking functions */ 1243 kernel_pmap_store.pm_l0 = pagetable_l0_ttbr1; 1244 PMAP_LOCK_INIT(kernel_pmap); 1245 kernel_pmap->pm_l0_paddr = 1246 pmap_early_vtophys((vm_offset_t)kernel_pmap_store.pm_l0); 1247 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 1248 vm_radix_init(&kernel_pmap->pm_root); 1249 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN); 1250 kernel_pmap->pm_stage = PM_STAGE1; 1251 kernel_pmap->pm_levels = 4; 1252 kernel_pmap->pm_ttbr = kernel_pmap->pm_l0_paddr; 1253 kernel_pmap->pm_asid_set = &asids; 1254 1255 /* Assume the address we were loaded to is a valid physical address */ 1256 min_pa = pmap_early_vtophys(KERNBASE); 1257 1258 physmap_idx = physmem_avail(physmap, nitems(physmap)); 1259 physmap_idx /= 2; 1260 1261 /* 1262 * Find the minimum physical address. physmap is sorted, 1263 * but may contain empty ranges. 1264 */ 1265 for (i = 0; i < physmap_idx * 2; i += 2) { 1266 if (physmap[i] == physmap[i + 1]) 1267 continue; 1268 if (physmap[i] <= min_pa) 1269 min_pa = physmap[i]; 1270 } 1271 1272 bs_state.freemempos = KERNBASE + kernlen; 1273 bs_state.freemempos = roundup2(bs_state.freemempos, PAGE_SIZE); 1274 1275 /* Create a direct map region early so we can use it for pa -> va */ 1276 pmap_bootstrap_dmap(min_pa); 1277 bs_state.dmap_valid = true; 1278 /* 1279 * We only use PXN when we know nothing will be executed from it, e.g. 1280 * the DMAP region. 1281 */ 1282 bs_state.table_attrs &= ~TATTR_PXN_TABLE; 1283 1284 start_pa = pa = pmap_early_vtophys(KERNBASE); 1285 1286 /* 1287 * Create the l2 tables up to VM_MAX_KERNEL_ADDRESS. We assume that the 1288 * loader allocated the first and only l2 page table page used to map 1289 * the kernel, preloaded files and module metadata. 1290 */ 1291 pmap_bootstrap_l2(KERNBASE + L1_SIZE); 1292 /* And the l3 tables for the early devmap */ 1293 pmap_bootstrap_l3(VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE)); 1294 1295 cpu_tlb_flushID(); 1296 1297 #define alloc_pages(var, np) \ 1298 (var) = bs_state.freemempos; \ 1299 bs_state.freemempos += (np * PAGE_SIZE); \ 1300 memset((char *)(var), 0, ((np) * PAGE_SIZE)); 1301 1302 /* Allocate dynamic per-cpu area. */ 1303 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 1304 dpcpu_init((void *)dpcpu, 0); 1305 1306 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */ 1307 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 1308 msgbufp = (void *)msgbufpv; 1309 1310 /* Reserve some VA space for early BIOS/ACPI mapping */ 1311 preinit_map_va = roundup2(bs_state.freemempos, L2_SIZE); 1312 1313 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE; 1314 virtual_avail = roundup2(virtual_avail, L1_SIZE); 1315 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE); 1316 kernel_vm_end = virtual_avail; 1317 1318 pa = pmap_early_vtophys(bs_state.freemempos); 1319 1320 physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC); 1321 1322 cpu_tlb_flushID(); 1323 } 1324 1325 #if defined(KASAN) || defined(KMSAN) 1326 static void 1327 pmap_bootstrap_allocate_san_l2(vm_paddr_t start_pa, vm_paddr_t end_pa, 1328 vm_offset_t *vap, vm_offset_t eva) 1329 { 1330 vm_paddr_t pa; 1331 vm_offset_t va; 1332 pd_entry_t *l2; 1333 1334 va = *vap; 1335 pa = rounddown2(end_pa - L2_SIZE, L2_SIZE); 1336 for (; pa >= start_pa && va < eva; va += L2_SIZE, pa -= L2_SIZE) { 1337 l2 = pmap_l2(kernel_pmap, va); 1338 1339 /* 1340 * KASAN stack checking results in us having already allocated 1341 * part of our shadow map, so we can just skip those segments. 1342 */ 1343 if ((pmap_load(l2) & ATTR_DESCR_VALID) != 0) { 1344 pa += L2_SIZE; 1345 continue; 1346 } 1347 1348 bzero((void *)PHYS_TO_DMAP(pa), L2_SIZE); 1349 physmem_exclude_region(pa, L2_SIZE, EXFLAG_NOALLOC); 1350 pmap_store(l2, PHYS_TO_PTE(pa) | PMAP_SAN_PTE_BITS | L2_BLOCK); 1351 } 1352 *vap = va; 1353 } 1354 1355 /* 1356 * Finish constructing the initial shadow map: 1357 * - Count how many pages from KERNBASE to virtual_avail (scaled for 1358 * shadow map) 1359 * - Map that entire range using L2 superpages. 1360 */ 1361 static void 1362 pmap_bootstrap_san1(vm_offset_t va, int scale) 1363 { 1364 vm_offset_t eva; 1365 vm_paddr_t kernstart; 1366 int i; 1367 1368 kernstart = pmap_early_vtophys(KERNBASE); 1369 1370 /* 1371 * Rebuild physmap one more time, we may have excluded more regions from 1372 * allocation since pmap_bootstrap(). 1373 */ 1374 bzero(physmap, sizeof(physmap)); 1375 physmap_idx = physmem_avail(physmap, nitems(physmap)); 1376 physmap_idx /= 2; 1377 1378 eva = va + (virtual_avail - VM_MIN_KERNEL_ADDRESS) / scale; 1379 1380 /* 1381 * Find a slot in the physmap large enough for what we needed. We try to put 1382 * the shadow map as high up as we can to avoid depleting the lower 4GB in case 1383 * it's needed for, e.g., an xhci controller that can only do 32-bit DMA. 1384 */ 1385 for (i = (physmap_idx * 2) - 2; i >= 0; i -= 2) { 1386 vm_paddr_t plow, phigh; 1387 1388 /* L2 mappings must be backed by memory that is L2-aligned */ 1389 plow = roundup2(physmap[i], L2_SIZE); 1390 phigh = physmap[i + 1]; 1391 if (plow >= phigh) 1392 continue; 1393 if (kernstart >= plow && kernstart < phigh) 1394 phigh = kernstart; 1395 if (phigh - plow >= L2_SIZE) { 1396 pmap_bootstrap_allocate_san_l2(plow, phigh, &va, eva); 1397 if (va >= eva) 1398 break; 1399 } 1400 } 1401 if (i < 0) 1402 panic("Could not find phys region for shadow map"); 1403 1404 /* 1405 * Done. We should now have a valid shadow address mapped for all KVA 1406 * that has been mapped so far, i.e., KERNBASE to virtual_avail. Thus, 1407 * shadow accesses by the sanitizer runtime will succeed for this range. 1408 * When the kernel virtual address range is later expanded, as will 1409 * happen in vm_mem_init(), the shadow map will be grown as well. This 1410 * is handled by pmap_san_enter(). 1411 */ 1412 } 1413 1414 void 1415 pmap_bootstrap_san(void) 1416 { 1417 #ifdef KASAN 1418 pmap_bootstrap_san1(KASAN_MIN_ADDRESS, KASAN_SHADOW_SCALE); 1419 #else 1420 static uint8_t kmsan_shad_ptp[PAGE_SIZE * 2] __aligned(PAGE_SIZE); 1421 static uint8_t kmsan_orig_ptp[PAGE_SIZE * 2] __aligned(PAGE_SIZE); 1422 pd_entry_t *l0, *l1; 1423 1424 if (virtual_avail - VM_MIN_KERNEL_ADDRESS > L1_SIZE) 1425 panic("initial kernel map is too large"); 1426 1427 l0 = pmap_l0(kernel_pmap, KMSAN_SHAD_MIN_ADDRESS); 1428 pmap_store(l0, L0_TABLE | PHYS_TO_PTE( 1429 pmap_early_vtophys((vm_offset_t)kmsan_shad_ptp))); 1430 l1 = pmap_l0_to_l1(l0, KMSAN_SHAD_MIN_ADDRESS); 1431 pmap_store(l1, L1_TABLE | PHYS_TO_PTE( 1432 pmap_early_vtophys((vm_offset_t)kmsan_shad_ptp + PAGE_SIZE))); 1433 pmap_bootstrap_san1(KMSAN_SHAD_MIN_ADDRESS, 1); 1434 1435 l0 = pmap_l0(kernel_pmap, KMSAN_ORIG_MIN_ADDRESS); 1436 pmap_store(l0, L0_TABLE | PHYS_TO_PTE( 1437 pmap_early_vtophys((vm_offset_t)kmsan_orig_ptp))); 1438 l1 = pmap_l0_to_l1(l0, KMSAN_ORIG_MIN_ADDRESS); 1439 pmap_store(l1, L1_TABLE | PHYS_TO_PTE( 1440 pmap_early_vtophys((vm_offset_t)kmsan_orig_ptp + PAGE_SIZE))); 1441 pmap_bootstrap_san1(KMSAN_ORIG_MIN_ADDRESS, 1); 1442 #endif 1443 } 1444 #endif 1445 1446 /* 1447 * Initialize a vm_page's machine-dependent fields. 1448 */ 1449 void 1450 pmap_page_init(vm_page_t m) 1451 { 1452 1453 TAILQ_INIT(&m->md.pv_list); 1454 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK; 1455 } 1456 1457 static void 1458 pmap_init_asids(struct asid_set *set, int bits) 1459 { 1460 int i; 1461 1462 set->asid_bits = bits; 1463 1464 /* 1465 * We may be too early in the overall initialization process to use 1466 * bit_alloc(). 1467 */ 1468 set->asid_set_size = 1 << set->asid_bits; 1469 set->asid_set = kmem_malloc(bitstr_size(set->asid_set_size), 1470 M_WAITOK | M_ZERO); 1471 for (i = 0; i < ASID_FIRST_AVAILABLE; i++) 1472 bit_set(set->asid_set, i); 1473 set->asid_next = ASID_FIRST_AVAILABLE; 1474 mtx_init(&set->asid_set_mutex, "asid set", NULL, MTX_SPIN); 1475 } 1476 1477 static void 1478 pmap_init_pv_table(void) 1479 { 1480 struct vm_phys_seg *seg, *next_seg; 1481 struct pmap_large_md_page *pvd; 1482 vm_size_t s; 1483 int domain, i, j, pages; 1484 1485 /* 1486 * We strongly depend on the size being a power of two, so the assert 1487 * is overzealous. However, should the struct be resized to a 1488 * different power of two, the code below needs to be revisited. 1489 */ 1490 CTASSERT((sizeof(*pvd) == 64)); 1491 1492 /* 1493 * Calculate the size of the array. 1494 */ 1495 s = 0; 1496 for (i = 0; i < vm_phys_nsegs; i++) { 1497 seg = &vm_phys_segs[i]; 1498 pages = pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1499 pmap_l2_pindex(seg->start); 1500 s += round_page(pages * sizeof(*pvd)); 1501 } 1502 pv_table = (struct pmap_large_md_page *)kva_alloc(s); 1503 if (pv_table == NULL) 1504 panic("%s: kva_alloc failed\n", __func__); 1505 1506 /* 1507 * Iterate physical segments to allocate domain-local memory for PV 1508 * list headers. 1509 */ 1510 pvd = pv_table; 1511 for (i = 0; i < vm_phys_nsegs; i++) { 1512 seg = &vm_phys_segs[i]; 1513 pages = pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1514 pmap_l2_pindex(seg->start); 1515 domain = seg->domain; 1516 1517 s = round_page(pages * sizeof(*pvd)); 1518 1519 for (j = 0; j < s; j += PAGE_SIZE) { 1520 vm_page_t m = vm_page_alloc_noobj_domain(domain, 1521 VM_ALLOC_ZERO); 1522 if (m == NULL) 1523 panic("failed to allocate PV table page"); 1524 pmap_qenter((vm_offset_t)pvd + j, &m, 1); 1525 } 1526 1527 for (j = 0; j < s / sizeof(*pvd); j++) { 1528 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW); 1529 TAILQ_INIT(&pvd->pv_page.pv_list); 1530 pvd++; 1531 } 1532 } 1533 pvd = &pv_dummy_large; 1534 memset(pvd, 0, sizeof(*pvd)); 1535 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW); 1536 TAILQ_INIT(&pvd->pv_page.pv_list); 1537 1538 /* 1539 * Set pointers from vm_phys_segs to pv_table. 1540 */ 1541 for (i = 0, pvd = pv_table; i < vm_phys_nsegs; i++) { 1542 seg = &vm_phys_segs[i]; 1543 seg->md_first = pvd; 1544 pvd += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1545 pmap_l2_pindex(seg->start); 1546 1547 /* 1548 * If there is a following segment, and the final 1549 * superpage of this segment and the initial superpage 1550 * of the next segment are the same then adjust the 1551 * pv_table entry for that next segment down by one so 1552 * that the pv_table entries will be shared. 1553 */ 1554 if (i + 1 < vm_phys_nsegs) { 1555 next_seg = &vm_phys_segs[i + 1]; 1556 if (pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1 == 1557 pmap_l2_pindex(next_seg->start)) { 1558 pvd--; 1559 } 1560 } 1561 } 1562 } 1563 1564 /* 1565 * Initialize the pmap module. 1566 * Called by vm_init, to initialize any structures that the pmap 1567 * system needs to map virtual memory. 1568 */ 1569 void 1570 pmap_init(void) 1571 { 1572 uint64_t mmfr1; 1573 int i, vmid_bits; 1574 1575 /* 1576 * Are large page mappings enabled? 1577 */ 1578 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled); 1579 if (superpages_enabled) { 1580 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 1581 ("pmap_init: can't assign to pagesizes[1]")); 1582 pagesizes[1] = L2_SIZE; 1583 if (L1_BLOCKS_SUPPORTED) { 1584 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0, 1585 ("pmap_init: can't assign to pagesizes[2]")); 1586 pagesizes[2] = L1_SIZE; 1587 } 1588 } 1589 1590 /* 1591 * Initialize the ASID allocator. 1592 */ 1593 pmap_init_asids(&asids, 1594 (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8); 1595 1596 if (has_hyp()) { 1597 mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1); 1598 vmid_bits = 8; 1599 1600 if (ID_AA64MMFR1_VMIDBits_VAL(mmfr1) == 1601 ID_AA64MMFR1_VMIDBits_16) 1602 vmid_bits = 16; 1603 pmap_init_asids(&vmids, vmid_bits); 1604 } 1605 1606 /* 1607 * Initialize pv chunk lists. 1608 */ 1609 for (i = 0; i < PMAP_MEMDOM; i++) { 1610 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, 1611 MTX_DEF); 1612 TAILQ_INIT(&pv_chunks[i].pvc_list); 1613 } 1614 pmap_init_pv_table(); 1615 1616 vm_initialized = 1; 1617 } 1618 1619 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 1620 "2MB page mapping counters"); 1621 1622 static u_long pmap_l2_demotions; 1623 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD, 1624 &pmap_l2_demotions, 0, "2MB page demotions"); 1625 1626 static u_long pmap_l2_mappings; 1627 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD, 1628 &pmap_l2_mappings, 0, "2MB page mappings"); 1629 1630 static u_long pmap_l2_p_failures; 1631 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD, 1632 &pmap_l2_p_failures, 0, "2MB page promotion failures"); 1633 1634 static u_long pmap_l2_promotions; 1635 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD, 1636 &pmap_l2_promotions, 0, "2MB page promotions"); 1637 1638 /* 1639 * If the given value for "final_only" is false, then any cached intermediate- 1640 * level entries, i.e., L{0,1,2}_TABLE entries, are invalidated in addition to 1641 * any cached final-level entry, i.e., either an L{1,2}_BLOCK or L3_PAGE entry. 1642 * Otherwise, just the cached final-level entry is invalidated. 1643 */ 1644 static __inline void 1645 pmap_s1_invalidate_kernel(uint64_t r, bool final_only) 1646 { 1647 if (final_only) 1648 __asm __volatile("tlbi vaale1is, %0" : : "r" (r)); 1649 else 1650 __asm __volatile("tlbi vaae1is, %0" : : "r" (r)); 1651 } 1652 1653 static __inline void 1654 pmap_s1_invalidate_user(uint64_t r, bool final_only) 1655 { 1656 if (final_only) 1657 __asm __volatile("tlbi vale1is, %0" : : "r" (r)); 1658 else 1659 __asm __volatile("tlbi vae1is, %0" : : "r" (r)); 1660 } 1661 1662 /* 1663 * Invalidates any cached final- and optionally intermediate-level TLB entries 1664 * for the specified virtual address in the given virtual address space. 1665 */ 1666 static __inline void 1667 pmap_s1_invalidate_page(pmap_t pmap, vm_offset_t va, bool final_only) 1668 { 1669 uint64_t r; 1670 1671 PMAP_ASSERT_STAGE1(pmap); 1672 1673 dsb(ishst); 1674 r = TLBI_VA(va); 1675 if (pmap == kernel_pmap) { 1676 pmap_s1_invalidate_kernel(r, final_only); 1677 } else { 1678 r |= ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)); 1679 pmap_s1_invalidate_user(r, final_only); 1680 } 1681 dsb(ish); 1682 isb(); 1683 } 1684 1685 static __inline void 1686 pmap_s2_invalidate_page(pmap_t pmap, vm_offset_t va, bool final_only) 1687 { 1688 PMAP_ASSERT_STAGE2(pmap); 1689 MPASS(pmap_stage2_invalidate_range != NULL); 1690 pmap_stage2_invalidate_range(pmap_to_ttbr0(pmap), va, va + PAGE_SIZE, 1691 final_only); 1692 } 1693 1694 static __inline void 1695 pmap_invalidate_page(pmap_t pmap, vm_offset_t va, bool final_only) 1696 { 1697 if (pmap->pm_stage == PM_STAGE1) 1698 pmap_s1_invalidate_page(pmap, va, final_only); 1699 else 1700 pmap_s2_invalidate_page(pmap, va, final_only); 1701 } 1702 1703 /* 1704 * Invalidates any cached final- and optionally intermediate-level TLB entries 1705 * for the specified virtual address range in the given virtual address space. 1706 */ 1707 static __inline void 1708 pmap_s1_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1709 bool final_only) 1710 { 1711 uint64_t end, r, start; 1712 1713 PMAP_ASSERT_STAGE1(pmap); 1714 1715 dsb(ishst); 1716 if (pmap == kernel_pmap) { 1717 start = TLBI_VA(sva); 1718 end = TLBI_VA(eva); 1719 for (r = start; r < end; r += TLBI_VA_L3_INCR) 1720 pmap_s1_invalidate_kernel(r, final_only); 1721 } else { 1722 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)); 1723 start |= TLBI_VA(sva); 1724 end |= TLBI_VA(eva); 1725 for (r = start; r < end; r += TLBI_VA_L3_INCR) 1726 pmap_s1_invalidate_user(r, final_only); 1727 } 1728 dsb(ish); 1729 isb(); 1730 } 1731 1732 static __inline void 1733 pmap_s2_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1734 bool final_only) 1735 { 1736 PMAP_ASSERT_STAGE2(pmap); 1737 MPASS(pmap_stage2_invalidate_range != NULL); 1738 pmap_stage2_invalidate_range(pmap_to_ttbr0(pmap), sva, eva, final_only); 1739 } 1740 1741 static __inline void 1742 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1743 bool final_only) 1744 { 1745 if (pmap->pm_stage == PM_STAGE1) 1746 pmap_s1_invalidate_range(pmap, sva, eva, final_only); 1747 else 1748 pmap_s2_invalidate_range(pmap, sva, eva, final_only); 1749 } 1750 1751 /* 1752 * Invalidates all cached intermediate- and final-level TLB entries for the 1753 * given virtual address space. 1754 */ 1755 static __inline void 1756 pmap_s1_invalidate_all(pmap_t pmap) 1757 { 1758 uint64_t r; 1759 1760 PMAP_ASSERT_STAGE1(pmap); 1761 1762 dsb(ishst); 1763 if (pmap == kernel_pmap) { 1764 __asm __volatile("tlbi vmalle1is"); 1765 } else { 1766 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)); 1767 __asm __volatile("tlbi aside1is, %0" : : "r" (r)); 1768 } 1769 dsb(ish); 1770 isb(); 1771 } 1772 1773 static __inline void 1774 pmap_s2_invalidate_all(pmap_t pmap) 1775 { 1776 PMAP_ASSERT_STAGE2(pmap); 1777 MPASS(pmap_stage2_invalidate_all != NULL); 1778 pmap_stage2_invalidate_all(pmap_to_ttbr0(pmap)); 1779 } 1780 1781 static __inline void 1782 pmap_invalidate_all(pmap_t pmap) 1783 { 1784 if (pmap->pm_stage == PM_STAGE1) 1785 pmap_s1_invalidate_all(pmap); 1786 else 1787 pmap_s2_invalidate_all(pmap); 1788 } 1789 1790 /* 1791 * Routine: pmap_extract 1792 * Function: 1793 * Extract the physical page address associated 1794 * with the given map/virtual_address pair. 1795 */ 1796 vm_paddr_t 1797 pmap_extract(pmap_t pmap, vm_offset_t va) 1798 { 1799 pt_entry_t *pte, tpte; 1800 vm_paddr_t pa; 1801 int lvl; 1802 1803 pa = 0; 1804 PMAP_LOCK(pmap); 1805 /* 1806 * Find the block or page map for this virtual address. pmap_pte 1807 * will return either a valid block/page entry, or NULL. 1808 */ 1809 pte = pmap_pte(pmap, va, &lvl); 1810 if (pte != NULL) { 1811 tpte = pmap_load(pte); 1812 pa = PTE_TO_PHYS(tpte); 1813 switch(lvl) { 1814 case 1: 1815 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 1816 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK, 1817 ("pmap_extract: Invalid L1 pte found: %lx", 1818 tpte & ATTR_DESCR_MASK)); 1819 pa |= (va & L1_OFFSET); 1820 break; 1821 case 2: 1822 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK, 1823 ("pmap_extract: Invalid L2 pte found: %lx", 1824 tpte & ATTR_DESCR_MASK)); 1825 pa |= (va & L2_OFFSET); 1826 break; 1827 case 3: 1828 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE, 1829 ("pmap_extract: Invalid L3 pte found: %lx", 1830 tpte & ATTR_DESCR_MASK)); 1831 pa |= (va & L3_OFFSET); 1832 break; 1833 } 1834 } 1835 PMAP_UNLOCK(pmap); 1836 return (pa); 1837 } 1838 1839 /* 1840 * Routine: pmap_extract_and_hold 1841 * Function: 1842 * Atomically extract and hold the physical page 1843 * with the given pmap and virtual address pair 1844 * if that mapping permits the given protection. 1845 */ 1846 vm_page_t 1847 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1848 { 1849 pt_entry_t *pte, tpte; 1850 vm_offset_t off; 1851 vm_page_t m; 1852 int lvl; 1853 bool use; 1854 1855 m = NULL; 1856 PMAP_LOCK(pmap); 1857 pte = pmap_pte(pmap, va, &lvl); 1858 if (pte != NULL) { 1859 tpte = pmap_load(pte); 1860 1861 KASSERT(lvl > 0 && lvl <= 3, 1862 ("pmap_extract_and_hold: Invalid level %d", lvl)); 1863 /* 1864 * Check that the pte is either a L3 page, or a L1 or L2 block 1865 * entry. We can assume L1_BLOCK == L2_BLOCK. 1866 */ 1867 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) || 1868 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK), 1869 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl, 1870 tpte & ATTR_DESCR_MASK)); 1871 1872 use = false; 1873 if ((prot & VM_PROT_WRITE) == 0) 1874 use = true; 1875 else if (pmap->pm_stage == PM_STAGE1 && 1876 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)) 1877 use = true; 1878 else if (pmap->pm_stage == PM_STAGE2 && 1879 ((tpte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) == 1880 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE))) 1881 use = true; 1882 1883 if (use) { 1884 switch (lvl) { 1885 case 1: 1886 off = va & L1_OFFSET; 1887 break; 1888 case 2: 1889 off = va & L2_OFFSET; 1890 break; 1891 case 3: 1892 default: 1893 off = 0; 1894 } 1895 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tpte) | off); 1896 if (m != NULL && !vm_page_wire_mapped(m)) 1897 m = NULL; 1898 } 1899 } 1900 PMAP_UNLOCK(pmap); 1901 return (m); 1902 } 1903 1904 /* 1905 * Walks the page tables to translate a kernel virtual address to a 1906 * physical address. Returns true if the kva is valid and stores the 1907 * physical address in pa if it is not NULL. 1908 * 1909 * See the comment above data_abort() for the rationale for specifying 1910 * NO_PERTHREAD_SSP here. 1911 */ 1912 bool NO_PERTHREAD_SSP 1913 pmap_klookup(vm_offset_t va, vm_paddr_t *pa) 1914 { 1915 pt_entry_t *pte, tpte; 1916 register_t intr; 1917 uint64_t par; 1918 1919 /* 1920 * Disable interrupts so we don't get interrupted between asking 1921 * for address translation, and getting the result back. 1922 */ 1923 intr = intr_disable(); 1924 par = arm64_address_translate_s1e1r(va); 1925 intr_restore(intr); 1926 1927 if (PAR_SUCCESS(par)) { 1928 if (pa != NULL) 1929 *pa = (par & PAR_PA_MASK) | (va & PAR_LOW_MASK); 1930 return (true); 1931 } 1932 1933 /* 1934 * Fall back to walking the page table. The address translation 1935 * instruction may fail when the page is in a break-before-make 1936 * sequence. As we only clear the valid bit in said sequence we 1937 * can walk the page table to find the physical address. 1938 */ 1939 1940 pte = pmap_l1(kernel_pmap, va); 1941 if (pte == NULL) 1942 return (false); 1943 1944 /* 1945 * A concurrent pmap_update_entry() will clear the entry's valid bit 1946 * but leave the rest of the entry unchanged. Therefore, we treat a 1947 * non-zero entry as being valid, and we ignore the valid bit when 1948 * determining whether the entry maps a block, page, or table. 1949 */ 1950 tpte = pmap_load(pte); 1951 if (tpte == 0) 1952 return (false); 1953 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) { 1954 if (pa != NULL) 1955 *pa = PTE_TO_PHYS(tpte) | (va & L1_OFFSET); 1956 return (true); 1957 } 1958 pte = pmap_l1_to_l2(&tpte, va); 1959 tpte = pmap_load(pte); 1960 if (tpte == 0) 1961 return (false); 1962 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) { 1963 if (pa != NULL) 1964 *pa = PTE_TO_PHYS(tpte) | (va & L2_OFFSET); 1965 return (true); 1966 } 1967 pte = pmap_l2_to_l3(&tpte, va); 1968 tpte = pmap_load(pte); 1969 if (tpte == 0) 1970 return (false); 1971 if (pa != NULL) 1972 *pa = PTE_TO_PHYS(tpte) | (va & L3_OFFSET); 1973 return (true); 1974 } 1975 1976 /* 1977 * Routine: pmap_kextract 1978 * Function: 1979 * Extract the physical page address associated with the given kernel 1980 * virtual address. 1981 */ 1982 vm_paddr_t 1983 pmap_kextract(vm_offset_t va) 1984 { 1985 vm_paddr_t pa; 1986 1987 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) 1988 return (DMAP_TO_PHYS(va)); 1989 1990 if (pmap_klookup(va, &pa) == false) 1991 return (0); 1992 return (pa); 1993 } 1994 1995 /*************************************************** 1996 * Low level mapping routines..... 1997 ***************************************************/ 1998 1999 void 2000 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode) 2001 { 2002 pd_entry_t *pde; 2003 pt_entry_t attr, old_l3e, *pte; 2004 vm_offset_t va; 2005 int lvl; 2006 2007 KASSERT((pa & L3_OFFSET) == 0, 2008 ("pmap_kenter: Invalid physical address")); 2009 KASSERT((sva & L3_OFFSET) == 0, 2010 ("pmap_kenter: Invalid virtual address")); 2011 KASSERT((size & PAGE_MASK) == 0, 2012 ("pmap_kenter: Mapping is not page-sized")); 2013 2014 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN | 2015 ATTR_KERN_GP | ATTR_S1_IDX(mode) | L3_PAGE; 2016 old_l3e = 0; 2017 va = sva; 2018 while (size != 0) { 2019 pde = pmap_pde(kernel_pmap, va, &lvl); 2020 KASSERT(pde != NULL, 2021 ("pmap_kenter: Invalid page entry, va: 0x%lx", va)); 2022 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl)); 2023 2024 pte = pmap_l2_to_l3(pde, va); 2025 old_l3e |= pmap_load_store(pte, PHYS_TO_PTE(pa) | attr); 2026 2027 va += PAGE_SIZE; 2028 pa += PAGE_SIZE; 2029 size -= PAGE_SIZE; 2030 } 2031 if ((old_l3e & ATTR_DESCR_VALID) != 0) 2032 pmap_s1_invalidate_range(kernel_pmap, sva, va, true); 2033 else { 2034 /* 2035 * Because the old entries were invalid and the new mappings 2036 * are not executable, an isb is not required. 2037 */ 2038 dsb(ishst); 2039 } 2040 } 2041 2042 void 2043 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa) 2044 { 2045 2046 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE); 2047 } 2048 2049 /* 2050 * Remove a page from the kernel pagetables. 2051 */ 2052 void 2053 pmap_kremove(vm_offset_t va) 2054 { 2055 pt_entry_t *pte; 2056 2057 pte = pmap_pte_exists(kernel_pmap, va, 3, __func__); 2058 pmap_clear(pte); 2059 pmap_s1_invalidate_page(kernel_pmap, va, true); 2060 } 2061 2062 /* 2063 * Remove the specified range of mappings from the kernel address space. 2064 * 2065 * Should only be applied to mappings that were created by pmap_kenter() or 2066 * pmap_kenter_device(). Nothing about this function is actually specific 2067 * to device mappings. 2068 */ 2069 void 2070 pmap_kremove_device(vm_offset_t sva, vm_size_t size) 2071 { 2072 pt_entry_t *pte; 2073 vm_offset_t va; 2074 2075 KASSERT((sva & L3_OFFSET) == 0, 2076 ("pmap_kremove_device: Invalid virtual address")); 2077 KASSERT((size & PAGE_MASK) == 0, 2078 ("pmap_kremove_device: Mapping is not page-sized")); 2079 2080 va = sva; 2081 while (size != 0) { 2082 pte = pmap_pte_exists(kernel_pmap, va, 3, __func__); 2083 pmap_clear(pte); 2084 2085 va += PAGE_SIZE; 2086 size -= PAGE_SIZE; 2087 } 2088 pmap_s1_invalidate_range(kernel_pmap, sva, va, true); 2089 } 2090 2091 /* 2092 * Used to map a range of physical addresses into kernel 2093 * virtual address space. 2094 * 2095 * The value passed in '*virt' is a suggested virtual address for 2096 * the mapping. Architectures which can support a direct-mapped 2097 * physical to virtual region can return the appropriate address 2098 * within that region, leaving '*virt' unchanged. Other 2099 * architectures should map the pages starting at '*virt' and 2100 * update '*virt' with the first usable address after the mapped 2101 * region. 2102 */ 2103 vm_offset_t 2104 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 2105 { 2106 return PHYS_TO_DMAP(start); 2107 } 2108 2109 /* 2110 * Add a list of wired pages to the kva 2111 * this routine is only used for temporary 2112 * kernel mappings that do not need to have 2113 * page modification or references recorded. 2114 * Note that old mappings are simply written 2115 * over. The page *must* be wired. 2116 * Note: SMP coherent. Uses a ranged shootdown IPI. 2117 */ 2118 void 2119 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 2120 { 2121 pd_entry_t *pde; 2122 pt_entry_t attr, old_l3e, pa, *pte; 2123 vm_offset_t va; 2124 vm_page_t m; 2125 int i, lvl; 2126 2127 old_l3e = 0; 2128 va = sva; 2129 for (i = 0; i < count; i++) { 2130 pde = pmap_pde(kernel_pmap, va, &lvl); 2131 KASSERT(pde != NULL, 2132 ("pmap_qenter: Invalid page entry, va: 0x%lx", va)); 2133 KASSERT(lvl == 2, 2134 ("pmap_qenter: Invalid level %d", lvl)); 2135 2136 m = ma[i]; 2137 pa = VM_PAGE_TO_PHYS(m); 2138 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN | 2139 ATTR_KERN_GP | ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE; 2140 pte = pmap_l2_to_l3(pde, va); 2141 old_l3e |= pmap_load_store(pte, PHYS_TO_PTE(pa) | attr); 2142 2143 va += L3_SIZE; 2144 } 2145 if ((old_l3e & ATTR_DESCR_VALID) != 0) 2146 pmap_s1_invalidate_range(kernel_pmap, sva, va, true); 2147 else { 2148 /* 2149 * Because the old entries were invalid and the new mappings 2150 * are not executable, an isb is not required. 2151 */ 2152 dsb(ishst); 2153 } 2154 } 2155 2156 /* 2157 * This routine tears out page mappings from the 2158 * kernel -- it is meant only for temporary mappings. 2159 */ 2160 void 2161 pmap_qremove(vm_offset_t sva, int count) 2162 { 2163 pt_entry_t *pte; 2164 vm_offset_t va; 2165 2166 KASSERT(ADDR_IS_CANONICAL(sva), 2167 ("%s: Address not in canonical form: %lx", __func__, sva)); 2168 KASSERT(ADDR_IS_KERNEL(sva), ("usermode va %lx", sva)); 2169 2170 va = sva; 2171 while (count-- > 0) { 2172 pte = pmap_pte_exists(kernel_pmap, va, 3, NULL); 2173 if (pte != NULL) { 2174 pmap_clear(pte); 2175 } 2176 2177 va += PAGE_SIZE; 2178 } 2179 pmap_s1_invalidate_range(kernel_pmap, sva, va, true); 2180 } 2181 2182 /*************************************************** 2183 * Page table page management routines..... 2184 ***************************************************/ 2185 /* 2186 * Schedule the specified unused page table page to be freed. Specifically, 2187 * add the page to the specified list of pages that will be released to the 2188 * physical memory manager after the TLB has been updated. 2189 */ 2190 static __inline void 2191 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free, bool set_PG_ZERO) 2192 { 2193 2194 if (set_PG_ZERO) 2195 m->flags |= PG_ZERO; 2196 else 2197 m->flags &= ~PG_ZERO; 2198 SLIST_INSERT_HEAD(free, m, plinks.s.ss); 2199 } 2200 2201 /* 2202 * Decrements a page table page's reference count, which is used to record the 2203 * number of valid page table entries within the page. If the reference count 2204 * drops to zero, then the page table page is unmapped. Returns true if the 2205 * page table page was unmapped and false otherwise. 2206 */ 2207 static inline bool 2208 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free) 2209 { 2210 2211 --m->ref_count; 2212 if (m->ref_count == 0) { 2213 _pmap_unwire_l3(pmap, va, m, free); 2214 return (true); 2215 } else 2216 return (false); 2217 } 2218 2219 static void 2220 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free) 2221 { 2222 2223 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2224 /* 2225 * unmap the page table page 2226 */ 2227 if (m->pindex >= (NUL2E + NUL1E)) { 2228 /* l1 page */ 2229 pd_entry_t *l0; 2230 2231 l0 = pmap_l0(pmap, va); 2232 pmap_clear(l0); 2233 } else if (m->pindex >= NUL2E) { 2234 /* l2 page */ 2235 pd_entry_t *l1; 2236 2237 l1 = pmap_l1(pmap, va); 2238 pmap_clear(l1); 2239 } else { 2240 /* l3 page */ 2241 pd_entry_t *l2; 2242 2243 l2 = pmap_l2(pmap, va); 2244 pmap_clear(l2); 2245 } 2246 pmap_resident_count_dec(pmap, 1); 2247 if (m->pindex < NUL2E) { 2248 /* We just released an l3, unhold the matching l2 */ 2249 pd_entry_t *l1, tl1; 2250 vm_page_t l2pg; 2251 2252 l1 = pmap_l1(pmap, va); 2253 tl1 = pmap_load(l1); 2254 l2pg = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tl1)); 2255 pmap_unwire_l3(pmap, va, l2pg, free); 2256 } else if (m->pindex < (NUL2E + NUL1E)) { 2257 /* We just released an l2, unhold the matching l1 */ 2258 pd_entry_t *l0, tl0; 2259 vm_page_t l1pg; 2260 2261 l0 = pmap_l0(pmap, va); 2262 tl0 = pmap_load(l0); 2263 l1pg = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tl0)); 2264 pmap_unwire_l3(pmap, va, l1pg, free); 2265 } 2266 pmap_invalidate_page(pmap, va, false); 2267 2268 /* 2269 * Put page on a list so that it is released after 2270 * *ALL* TLB shootdown is done 2271 */ 2272 pmap_add_delayed_free_list(m, free, true); 2273 } 2274 2275 /* 2276 * After removing a page table entry, this routine is used to 2277 * conditionally free the page, and manage the reference count. 2278 */ 2279 static int 2280 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde, 2281 struct spglist *free) 2282 { 2283 vm_page_t mpte; 2284 2285 KASSERT(ADDR_IS_CANONICAL(va), 2286 ("%s: Address not in canonical form: %lx", __func__, va)); 2287 if (ADDR_IS_KERNEL(va)) 2288 return (0); 2289 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0")); 2290 mpte = PHYS_TO_VM_PAGE(PTE_TO_PHYS(ptepde)); 2291 return (pmap_unwire_l3(pmap, va, mpte, free)); 2292 } 2293 2294 /* 2295 * Release a page table page reference after a failed attempt to create a 2296 * mapping. 2297 */ 2298 static void 2299 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte) 2300 { 2301 struct spglist free; 2302 2303 SLIST_INIT(&free); 2304 if (pmap_unwire_l3(pmap, va, mpte, &free)) 2305 vm_page_free_pages_toq(&free, true); 2306 } 2307 2308 void 2309 pmap_pinit0(pmap_t pmap) 2310 { 2311 2312 PMAP_LOCK_INIT(pmap); 2313 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 2314 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1); 2315 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr); 2316 TAILQ_INIT(&pmap->pm_pvchunk); 2317 vm_radix_init(&pmap->pm_root); 2318 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN); 2319 pmap->pm_stage = PM_STAGE1; 2320 pmap->pm_levels = 4; 2321 pmap->pm_ttbr = pmap->pm_l0_paddr; 2322 pmap->pm_asid_set = &asids; 2323 2324 PCPU_SET(curpmap, pmap); 2325 } 2326 2327 int 2328 pmap_pinit_stage(pmap_t pmap, enum pmap_stage stage, int levels) 2329 { 2330 vm_page_t m; 2331 2332 /* 2333 * allocate the l0 page 2334 */ 2335 m = vm_page_alloc_noobj(VM_ALLOC_WAITOK | VM_ALLOC_WIRED | 2336 VM_ALLOC_ZERO); 2337 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(m); 2338 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr); 2339 2340 TAILQ_INIT(&pmap->pm_pvchunk); 2341 vm_radix_init(&pmap->pm_root); 2342 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 2343 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX); 2344 2345 MPASS(levels == 3 || levels == 4); 2346 pmap->pm_levels = levels; 2347 pmap->pm_stage = stage; 2348 switch (stage) { 2349 case PM_STAGE1: 2350 pmap->pm_asid_set = &asids; 2351 break; 2352 case PM_STAGE2: 2353 pmap->pm_asid_set = &vmids; 2354 break; 2355 default: 2356 panic("%s: Invalid pmap type %d", __func__, stage); 2357 break; 2358 } 2359 2360 /* XXX Temporarily disable deferred ASID allocation. */ 2361 pmap_alloc_asid(pmap); 2362 2363 /* 2364 * Allocate the level 1 entry to use as the root. This will increase 2365 * the refcount on the level 1 page so it won't be removed until 2366 * pmap_release() is called. 2367 */ 2368 if (pmap->pm_levels == 3) { 2369 PMAP_LOCK(pmap); 2370 m = _pmap_alloc_l3(pmap, NUL2E + NUL1E, NULL); 2371 PMAP_UNLOCK(pmap); 2372 } 2373 pmap->pm_ttbr = VM_PAGE_TO_PHYS(m); 2374 2375 return (1); 2376 } 2377 2378 int 2379 pmap_pinit(pmap_t pmap) 2380 { 2381 2382 return (pmap_pinit_stage(pmap, PM_STAGE1, 4)); 2383 } 2384 2385 /* 2386 * This routine is called if the desired page table page does not exist. 2387 * 2388 * If page table page allocation fails, this routine may sleep before 2389 * returning NULL. It sleeps only if a lock pointer was given. 2390 * 2391 * Note: If a page allocation fails at page table level two or three, 2392 * one or two pages may be held during the wait, only to be released 2393 * afterwards. This conservative approach is easily argued to avoid 2394 * race conditions. 2395 */ 2396 static vm_page_t 2397 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp) 2398 { 2399 vm_page_t m, l1pg, l2pg; 2400 2401 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2402 2403 /* 2404 * Allocate a page table page. 2405 */ 2406 if ((m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 2407 if (lockp != NULL) { 2408 RELEASE_PV_LIST_LOCK(lockp); 2409 PMAP_UNLOCK(pmap); 2410 vm_wait(NULL); 2411 PMAP_LOCK(pmap); 2412 } 2413 2414 /* 2415 * Indicate the need to retry. While waiting, the page table 2416 * page may have been allocated. 2417 */ 2418 return (NULL); 2419 } 2420 m->pindex = ptepindex; 2421 2422 /* 2423 * Because of AArch64's weak memory consistency model, we must have a 2424 * barrier here to ensure that the stores for zeroing "m", whether by 2425 * pmap_zero_page() or an earlier function, are visible before adding 2426 * "m" to the page table. Otherwise, a page table walk by another 2427 * processor's MMU could see the mapping to "m" and a stale, non-zero 2428 * PTE within "m". 2429 */ 2430 dmb(ishst); 2431 2432 /* 2433 * Map the pagetable page into the process address space, if 2434 * it isn't already there. 2435 */ 2436 2437 if (ptepindex >= (NUL2E + NUL1E)) { 2438 pd_entry_t *l0p, l0e; 2439 vm_pindex_t l0index; 2440 2441 l0index = ptepindex - (NUL2E + NUL1E); 2442 l0p = &pmap->pm_l0[l0index]; 2443 KASSERT((pmap_load(l0p) & ATTR_DESCR_VALID) == 0, 2444 ("%s: L0 entry %#lx is valid", __func__, pmap_load(l0p))); 2445 l0e = PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) | L0_TABLE; 2446 2447 /* 2448 * Mark all kernel memory as not accessible from userspace 2449 * and userspace memory as not executable from the kernel. 2450 * This has been done for the bootstrap L0 entries in 2451 * locore.S. 2452 */ 2453 if (pmap == kernel_pmap) 2454 l0e |= TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0; 2455 else 2456 l0e |= TATTR_PXN_TABLE; 2457 pmap_store(l0p, l0e); 2458 } else if (ptepindex >= NUL2E) { 2459 vm_pindex_t l0index, l1index; 2460 pd_entry_t *l0, *l1; 2461 pd_entry_t tl0; 2462 2463 l1index = ptepindex - NUL2E; 2464 l0index = l1index >> Ln_ENTRIES_SHIFT; 2465 2466 l0 = &pmap->pm_l0[l0index]; 2467 tl0 = pmap_load(l0); 2468 if (tl0 == 0) { 2469 /* recurse for allocating page dir */ 2470 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index, 2471 lockp) == NULL) { 2472 vm_page_unwire_noq(m); 2473 vm_page_free_zero(m); 2474 return (NULL); 2475 } 2476 } else { 2477 l1pg = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tl0)); 2478 l1pg->ref_count++; 2479 } 2480 2481 l1 = (pd_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(pmap_load(l0))); 2482 l1 = &l1[ptepindex & Ln_ADDR_MASK]; 2483 KASSERT((pmap_load(l1) & ATTR_DESCR_VALID) == 0, 2484 ("%s: L1 entry %#lx is valid", __func__, pmap_load(l1))); 2485 pmap_store(l1, PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) | L1_TABLE); 2486 } else { 2487 vm_pindex_t l0index, l1index; 2488 pd_entry_t *l0, *l1, *l2; 2489 pd_entry_t tl0, tl1; 2490 2491 l1index = ptepindex >> Ln_ENTRIES_SHIFT; 2492 l0index = l1index >> Ln_ENTRIES_SHIFT; 2493 2494 l0 = &pmap->pm_l0[l0index]; 2495 tl0 = pmap_load(l0); 2496 if (tl0 == 0) { 2497 /* recurse for allocating page dir */ 2498 if (_pmap_alloc_l3(pmap, NUL2E + l1index, 2499 lockp) == NULL) { 2500 vm_page_unwire_noq(m); 2501 vm_page_free_zero(m); 2502 return (NULL); 2503 } 2504 tl0 = pmap_load(l0); 2505 l1 = (pd_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(tl0)); 2506 l1 = &l1[l1index & Ln_ADDR_MASK]; 2507 } else { 2508 l1 = (pd_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(tl0)); 2509 l1 = &l1[l1index & Ln_ADDR_MASK]; 2510 tl1 = pmap_load(l1); 2511 if (tl1 == 0) { 2512 /* recurse for allocating page dir */ 2513 if (_pmap_alloc_l3(pmap, NUL2E + l1index, 2514 lockp) == NULL) { 2515 vm_page_unwire_noq(m); 2516 vm_page_free_zero(m); 2517 return (NULL); 2518 } 2519 } else { 2520 l2pg = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tl1)); 2521 l2pg->ref_count++; 2522 } 2523 } 2524 2525 l2 = (pd_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(pmap_load(l1))); 2526 l2 = &l2[ptepindex & Ln_ADDR_MASK]; 2527 KASSERT((pmap_load(l2) & ATTR_DESCR_VALID) == 0, 2528 ("%s: L2 entry %#lx is valid", __func__, pmap_load(l2))); 2529 pmap_store(l2, PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) | L2_TABLE); 2530 } 2531 2532 pmap_resident_count_inc(pmap, 1); 2533 2534 return (m); 2535 } 2536 2537 static pd_entry_t * 2538 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp, 2539 struct rwlock **lockp) 2540 { 2541 pd_entry_t *l1, *l2; 2542 vm_page_t l2pg; 2543 vm_pindex_t l2pindex; 2544 2545 KASSERT(ADDR_IS_CANONICAL(va), 2546 ("%s: Address not in canonical form: %lx", __func__, va)); 2547 2548 retry: 2549 l1 = pmap_l1(pmap, va); 2550 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) { 2551 l2 = pmap_l1_to_l2(l1, va); 2552 if (!ADDR_IS_KERNEL(va)) { 2553 /* Add a reference to the L2 page. */ 2554 l2pg = PHYS_TO_VM_PAGE(PTE_TO_PHYS(pmap_load(l1))); 2555 l2pg->ref_count++; 2556 } else 2557 l2pg = NULL; 2558 } else if (!ADDR_IS_KERNEL(va)) { 2559 /* Allocate a L2 page. */ 2560 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT; 2561 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp); 2562 if (l2pg == NULL) { 2563 if (lockp != NULL) 2564 goto retry; 2565 else 2566 return (NULL); 2567 } 2568 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg)); 2569 l2 = &l2[pmap_l2_index(va)]; 2570 } else 2571 panic("pmap_alloc_l2: missing page table page for va %#lx", 2572 va); 2573 *l2pgp = l2pg; 2574 return (l2); 2575 } 2576 2577 static vm_page_t 2578 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp) 2579 { 2580 vm_pindex_t ptepindex; 2581 pd_entry_t *pde, tpde; 2582 #ifdef INVARIANTS 2583 pt_entry_t *pte; 2584 #endif 2585 vm_page_t m; 2586 int lvl; 2587 2588 /* 2589 * Calculate pagetable page index 2590 */ 2591 ptepindex = pmap_l2_pindex(va); 2592 retry: 2593 /* 2594 * Get the page directory entry 2595 */ 2596 pde = pmap_pde(pmap, va, &lvl); 2597 2598 /* 2599 * If the page table page is mapped, we just increment the hold count, 2600 * and activate it. If we get a level 2 pde it will point to a level 3 2601 * table. 2602 */ 2603 switch (lvl) { 2604 case -1: 2605 break; 2606 case 0: 2607 #ifdef INVARIANTS 2608 pte = pmap_l0_to_l1(pde, va); 2609 KASSERT(pmap_load(pte) == 0, 2610 ("pmap_alloc_l3: TODO: l0 superpages")); 2611 #endif 2612 break; 2613 case 1: 2614 #ifdef INVARIANTS 2615 pte = pmap_l1_to_l2(pde, va); 2616 KASSERT(pmap_load(pte) == 0, 2617 ("pmap_alloc_l3: TODO: l1 superpages")); 2618 #endif 2619 break; 2620 case 2: 2621 tpde = pmap_load(pde); 2622 if (tpde != 0) { 2623 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tpde)); 2624 m->ref_count++; 2625 return (m); 2626 } 2627 break; 2628 default: 2629 panic("pmap_alloc_l3: Invalid level %d", lvl); 2630 } 2631 2632 /* 2633 * Here if the pte page isn't mapped, or if it has been deallocated. 2634 */ 2635 m = _pmap_alloc_l3(pmap, ptepindex, lockp); 2636 if (m == NULL && lockp != NULL) 2637 goto retry; 2638 2639 return (m); 2640 } 2641 2642 /*************************************************** 2643 * Pmap allocation/deallocation routines. 2644 ***************************************************/ 2645 2646 /* 2647 * Release any resources held by the given physical map. 2648 * Called when a pmap initialized by pmap_pinit is being released. 2649 * Should only be called if the map contains no valid mappings. 2650 */ 2651 void 2652 pmap_release(pmap_t pmap) 2653 { 2654 bool rv __diagused; 2655 struct spglist free; 2656 struct asid_set *set; 2657 vm_page_t m; 2658 int asid; 2659 2660 if (pmap->pm_levels != 4) { 2661 PMAP_ASSERT_STAGE2(pmap); 2662 KASSERT(pmap->pm_stats.resident_count == 1, 2663 ("pmap_release: pmap resident count %ld != 0", 2664 pmap->pm_stats.resident_count)); 2665 KASSERT((pmap->pm_l0[0] & ATTR_DESCR_VALID) == ATTR_DESCR_VALID, 2666 ("pmap_release: Invalid l0 entry: %lx", pmap->pm_l0[0])); 2667 2668 SLIST_INIT(&free); 2669 m = PHYS_TO_VM_PAGE(pmap->pm_ttbr); 2670 PMAP_LOCK(pmap); 2671 rv = pmap_unwire_l3(pmap, 0, m, &free); 2672 PMAP_UNLOCK(pmap); 2673 MPASS(rv == true); 2674 vm_page_free_pages_toq(&free, true); 2675 } 2676 2677 KASSERT(pmap->pm_stats.resident_count == 0, 2678 ("pmap_release: pmap resident count %ld != 0", 2679 pmap->pm_stats.resident_count)); 2680 KASSERT(vm_radix_is_empty(&pmap->pm_root), 2681 ("pmap_release: pmap has reserved page table page(s)")); 2682 2683 set = pmap->pm_asid_set; 2684 KASSERT(set != NULL, ("%s: NULL asid set", __func__)); 2685 2686 /* 2687 * Allow the ASID to be reused. In stage 2 VMIDs we don't invalidate 2688 * the entries when removing them so rely on a later tlb invalidation. 2689 * this will happen when updating the VMID generation. Because of this 2690 * we don't reuse VMIDs within a generation. 2691 */ 2692 if (pmap->pm_stage == PM_STAGE1) { 2693 mtx_lock_spin(&set->asid_set_mutex); 2694 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) { 2695 asid = COOKIE_TO_ASID(pmap->pm_cookie); 2696 KASSERT(asid >= ASID_FIRST_AVAILABLE && 2697 asid < set->asid_set_size, 2698 ("pmap_release: pmap cookie has out-of-range asid")); 2699 bit_clear(set->asid_set, asid); 2700 } 2701 mtx_unlock_spin(&set->asid_set_mutex); 2702 } 2703 2704 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr); 2705 vm_page_unwire_noq(m); 2706 vm_page_free_zero(m); 2707 } 2708 2709 static int 2710 kvm_size(SYSCTL_HANDLER_ARGS) 2711 { 2712 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS; 2713 2714 return sysctl_handle_long(oidp, &ksize, 0, req); 2715 } 2716 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE, 2717 0, 0, kvm_size, "LU", 2718 "Size of KVM"); 2719 2720 static int 2721 kvm_free(SYSCTL_HANDLER_ARGS) 2722 { 2723 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 2724 2725 return sysctl_handle_long(oidp, &kfree, 0, req); 2726 } 2727 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE, 2728 0, 0, kvm_free, "LU", 2729 "Amount of KVM free"); 2730 2731 /* 2732 * grow the number of kernel page table entries, if needed 2733 */ 2734 void 2735 pmap_growkernel(vm_offset_t addr) 2736 { 2737 vm_paddr_t paddr; 2738 vm_page_t nkpg; 2739 pd_entry_t *l0, *l1, *l2; 2740 2741 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 2742 2743 addr = roundup2(addr, L2_SIZE); 2744 if (addr - 1 >= vm_map_max(kernel_map)) 2745 addr = vm_map_max(kernel_map); 2746 if (kernel_vm_end < addr) { 2747 kasan_shadow_map(kernel_vm_end, addr - kernel_vm_end); 2748 kmsan_shadow_map(kernel_vm_end, addr - kernel_vm_end); 2749 } 2750 while (kernel_vm_end < addr) { 2751 l0 = pmap_l0(kernel_pmap, kernel_vm_end); 2752 KASSERT(pmap_load(l0) != 0, 2753 ("pmap_growkernel: No level 0 kernel entry")); 2754 2755 l1 = pmap_l0_to_l1(l0, kernel_vm_end); 2756 if (pmap_load(l1) == 0) { 2757 /* We need a new PDP entry */ 2758 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | 2759 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 2760 if (nkpg == NULL) 2761 panic("pmap_growkernel: no memory to grow kernel"); 2762 nkpg->pindex = kernel_vm_end >> L1_SHIFT; 2763 /* See the dmb() in _pmap_alloc_l3(). */ 2764 dmb(ishst); 2765 paddr = VM_PAGE_TO_PHYS(nkpg); 2766 pmap_store(l1, PHYS_TO_PTE(paddr) | L1_TABLE); 2767 continue; /* try again */ 2768 } 2769 l2 = pmap_l1_to_l2(l1, kernel_vm_end); 2770 if (pmap_load(l2) != 0) { 2771 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET; 2772 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) { 2773 kernel_vm_end = vm_map_max(kernel_map); 2774 break; 2775 } 2776 continue; 2777 } 2778 2779 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED | 2780 VM_ALLOC_ZERO); 2781 if (nkpg == NULL) 2782 panic("pmap_growkernel: no memory to grow kernel"); 2783 nkpg->pindex = kernel_vm_end >> L2_SHIFT; 2784 /* See the dmb() in _pmap_alloc_l3(). */ 2785 dmb(ishst); 2786 paddr = VM_PAGE_TO_PHYS(nkpg); 2787 pmap_store(l2, PHYS_TO_PTE(paddr) | L2_TABLE); 2788 2789 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET; 2790 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) { 2791 kernel_vm_end = vm_map_max(kernel_map); 2792 break; 2793 } 2794 } 2795 } 2796 2797 /*************************************************** 2798 * page management routines. 2799 ***************************************************/ 2800 2801 static const uint64_t pc_freemask[_NPCM] = { 2802 [0 ... _NPCM - 2] = PC_FREEN, 2803 [_NPCM - 1] = PC_FREEL 2804 }; 2805 2806 #ifdef PV_STATS 2807 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 2808 2809 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 2810 "Current number of pv entry chunks"); 2811 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 2812 "Current number of pv entry chunks allocated"); 2813 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 2814 "Current number of pv entry chunks frees"); 2815 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 2816 "Number of times tried to get a chunk page but failed."); 2817 2818 static long pv_entry_frees, pv_entry_allocs, pv_entry_count; 2819 static int pv_entry_spare; 2820 2821 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 2822 "Current number of pv entry frees"); 2823 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 2824 "Current number of pv entry allocs"); 2825 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 2826 "Current number of pv entries"); 2827 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 2828 "Current number of spare pv entries"); 2829 #endif 2830 2831 /* 2832 * We are in a serious low memory condition. Resort to 2833 * drastic measures to free some pages so we can allocate 2834 * another pv entry chunk. 2835 * 2836 * Returns NULL if PV entries were reclaimed from the specified pmap. 2837 * 2838 * We do not, however, unmap 2mpages because subsequent accesses will 2839 * allocate per-page pv entries until repromotion occurs, thereby 2840 * exacerbating the shortage of free pv entries. 2841 */ 2842 static vm_page_t 2843 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain) 2844 { 2845 struct pv_chunks_list *pvc; 2846 struct pv_chunk *pc, *pc_marker, *pc_marker_end; 2847 struct pv_chunk_header pc_marker_b, pc_marker_end_b; 2848 struct md_page *pvh; 2849 pd_entry_t *pde; 2850 pmap_t next_pmap, pmap; 2851 pt_entry_t *pte, tpte; 2852 pv_entry_t pv; 2853 vm_offset_t va; 2854 vm_page_t m, m_pc; 2855 struct spglist free; 2856 uint64_t inuse; 2857 int bit, field, freed, lvl; 2858 2859 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 2860 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL")); 2861 2862 pmap = NULL; 2863 m_pc = NULL; 2864 SLIST_INIT(&free); 2865 bzero(&pc_marker_b, sizeof(pc_marker_b)); 2866 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b)); 2867 pc_marker = (struct pv_chunk *)&pc_marker_b; 2868 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b; 2869 2870 pvc = &pv_chunks[domain]; 2871 mtx_lock(&pvc->pvc_lock); 2872 pvc->active_reclaims++; 2873 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru); 2874 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru); 2875 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end && 2876 SLIST_EMPTY(&free)) { 2877 next_pmap = pc->pc_pmap; 2878 if (next_pmap == NULL) { 2879 /* 2880 * The next chunk is a marker. However, it is 2881 * not our marker, so active_reclaims must be 2882 * > 1. Consequently, the next_chunk code 2883 * will not rotate the pv_chunks list. 2884 */ 2885 goto next_chunk; 2886 } 2887 mtx_unlock(&pvc->pvc_lock); 2888 2889 /* 2890 * A pv_chunk can only be removed from the pc_lru list 2891 * when both pvc->pvc_lock is owned and the 2892 * corresponding pmap is locked. 2893 */ 2894 if (pmap != next_pmap) { 2895 if (pmap != NULL && pmap != locked_pmap) 2896 PMAP_UNLOCK(pmap); 2897 pmap = next_pmap; 2898 /* Avoid deadlock and lock recursion. */ 2899 if (pmap > locked_pmap) { 2900 RELEASE_PV_LIST_LOCK(lockp); 2901 PMAP_LOCK(pmap); 2902 mtx_lock(&pvc->pvc_lock); 2903 continue; 2904 } else if (pmap != locked_pmap) { 2905 if (PMAP_TRYLOCK(pmap)) { 2906 mtx_lock(&pvc->pvc_lock); 2907 continue; 2908 } else { 2909 pmap = NULL; /* pmap is not locked */ 2910 mtx_lock(&pvc->pvc_lock); 2911 pc = TAILQ_NEXT(pc_marker, pc_lru); 2912 if (pc == NULL || 2913 pc->pc_pmap != next_pmap) 2914 continue; 2915 goto next_chunk; 2916 } 2917 } 2918 } 2919 2920 /* 2921 * Destroy every non-wired, 4 KB page mapping in the chunk. 2922 */ 2923 freed = 0; 2924 for (field = 0; field < _NPCM; field++) { 2925 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2926 inuse != 0; inuse &= ~(1UL << bit)) { 2927 bit = ffsl(inuse) - 1; 2928 pv = &pc->pc_pventry[field * 64 + bit]; 2929 va = pv->pv_va; 2930 pde = pmap_pde(pmap, va, &lvl); 2931 if (lvl != 2) 2932 continue; 2933 pte = pmap_l2_to_l3(pde, va); 2934 tpte = pmap_load(pte); 2935 if ((tpte & ATTR_SW_WIRED) != 0) 2936 continue; 2937 tpte = pmap_load_clear(pte); 2938 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tpte)); 2939 if (pmap_pte_dirty(pmap, tpte)) 2940 vm_page_dirty(m); 2941 if ((tpte & ATTR_AF) != 0) { 2942 pmap_s1_invalidate_page(pmap, va, true); 2943 vm_page_aflag_set(m, PGA_REFERENCED); 2944 } 2945 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 2946 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2947 m->md.pv_gen++; 2948 if (TAILQ_EMPTY(&m->md.pv_list) && 2949 (m->flags & PG_FICTITIOUS) == 0) { 2950 pvh = page_to_pvh(m); 2951 if (TAILQ_EMPTY(&pvh->pv_list)) { 2952 vm_page_aflag_clear(m, 2953 PGA_WRITEABLE); 2954 } 2955 } 2956 pc->pc_map[field] |= 1UL << bit; 2957 pmap_unuse_pt(pmap, va, pmap_load(pde), &free); 2958 freed++; 2959 } 2960 } 2961 if (freed == 0) { 2962 mtx_lock(&pvc->pvc_lock); 2963 goto next_chunk; 2964 } 2965 /* Every freed mapping is for a 4 KB page. */ 2966 pmap_resident_count_dec(pmap, freed); 2967 PV_STAT(atomic_add_long(&pv_entry_frees, freed)); 2968 PV_STAT(atomic_add_int(&pv_entry_spare, freed)); 2969 PV_STAT(atomic_subtract_long(&pv_entry_count, freed)); 2970 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2971 if (pc_is_free(pc)) { 2972 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV)); 2973 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1)); 2974 PV_STAT(atomic_add_int(&pc_chunk_frees, 1)); 2975 /* Entire chunk is free; return it. */ 2976 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc)); 2977 dump_drop_page(m_pc->phys_addr); 2978 mtx_lock(&pvc->pvc_lock); 2979 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru); 2980 break; 2981 } 2982 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2983 mtx_lock(&pvc->pvc_lock); 2984 /* One freed pv entry in locked_pmap is sufficient. */ 2985 if (pmap == locked_pmap) 2986 break; 2987 2988 next_chunk: 2989 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru); 2990 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru); 2991 if (pvc->active_reclaims == 1 && pmap != NULL) { 2992 /* 2993 * Rotate the pv chunks list so that we do not 2994 * scan the same pv chunks that could not be 2995 * freed (because they contained a wired 2996 * and/or superpage mapping) on every 2997 * invocation of reclaim_pv_chunk(). 2998 */ 2999 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker){ 3000 MPASS(pc->pc_pmap != NULL); 3001 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru); 3002 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru); 3003 } 3004 } 3005 } 3006 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru); 3007 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru); 3008 pvc->active_reclaims--; 3009 mtx_unlock(&pvc->pvc_lock); 3010 if (pmap != NULL && pmap != locked_pmap) 3011 PMAP_UNLOCK(pmap); 3012 if (m_pc == NULL && !SLIST_EMPTY(&free)) { 3013 m_pc = SLIST_FIRST(&free); 3014 SLIST_REMOVE_HEAD(&free, plinks.s.ss); 3015 /* Recycle a freed page table page. */ 3016 m_pc->ref_count = 1; 3017 } 3018 vm_page_free_pages_toq(&free, true); 3019 return (m_pc); 3020 } 3021 3022 static vm_page_t 3023 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp) 3024 { 3025 vm_page_t m; 3026 int i, domain; 3027 3028 domain = PCPU_GET(domain); 3029 for (i = 0; i < vm_ndomains; i++) { 3030 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain); 3031 if (m != NULL) 3032 break; 3033 domain = (domain + 1) % vm_ndomains; 3034 } 3035 3036 return (m); 3037 } 3038 3039 /* 3040 * free the pv_entry back to the free list 3041 */ 3042 static void 3043 free_pv_entry(pmap_t pmap, pv_entry_t pv) 3044 { 3045 struct pv_chunk *pc; 3046 int idx, field, bit; 3047 3048 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3049 PV_STAT(atomic_add_long(&pv_entry_frees, 1)); 3050 PV_STAT(atomic_add_int(&pv_entry_spare, 1)); 3051 PV_STAT(atomic_subtract_long(&pv_entry_count, 1)); 3052 pc = pv_to_chunk(pv); 3053 idx = pv - &pc->pc_pventry[0]; 3054 field = idx / 64; 3055 bit = idx % 64; 3056 pc->pc_map[field] |= 1ul << bit; 3057 if (!pc_is_free(pc)) { 3058 /* 98% of the time, pc is already at the head of the list. */ 3059 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) { 3060 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3061 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 3062 } 3063 return; 3064 } 3065 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3066 free_pv_chunk(pc); 3067 } 3068 3069 static void 3070 free_pv_chunk_dequeued(struct pv_chunk *pc) 3071 { 3072 vm_page_t m; 3073 3074 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV)); 3075 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1)); 3076 PV_STAT(atomic_add_int(&pc_chunk_frees, 1)); 3077 /* entire chunk is free, return it */ 3078 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc)); 3079 dump_drop_page(m->phys_addr); 3080 vm_page_unwire_noq(m); 3081 vm_page_free(m); 3082 } 3083 3084 static void 3085 free_pv_chunk(struct pv_chunk *pc) 3086 { 3087 struct pv_chunks_list *pvc; 3088 3089 pvc = &pv_chunks[pc_to_domain(pc)]; 3090 mtx_lock(&pvc->pvc_lock); 3091 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru); 3092 mtx_unlock(&pvc->pvc_lock); 3093 free_pv_chunk_dequeued(pc); 3094 } 3095 3096 static void 3097 free_pv_chunk_batch(struct pv_chunklist *batch) 3098 { 3099 struct pv_chunks_list *pvc; 3100 struct pv_chunk *pc, *npc; 3101 int i; 3102 3103 for (i = 0; i < vm_ndomains; i++) { 3104 if (TAILQ_EMPTY(&batch[i])) 3105 continue; 3106 pvc = &pv_chunks[i]; 3107 mtx_lock(&pvc->pvc_lock); 3108 TAILQ_FOREACH(pc, &batch[i], pc_list) { 3109 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru); 3110 } 3111 mtx_unlock(&pvc->pvc_lock); 3112 } 3113 3114 for (i = 0; i < vm_ndomains; i++) { 3115 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) { 3116 free_pv_chunk_dequeued(pc); 3117 } 3118 } 3119 } 3120 3121 /* 3122 * Returns a new PV entry, allocating a new PV chunk from the system when 3123 * needed. If this PV chunk allocation fails and a PV list lock pointer was 3124 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is 3125 * returned. 3126 * 3127 * The given PV list lock may be released. 3128 */ 3129 static pv_entry_t 3130 get_pv_entry(pmap_t pmap, struct rwlock **lockp) 3131 { 3132 struct pv_chunks_list *pvc; 3133 int bit, field; 3134 pv_entry_t pv; 3135 struct pv_chunk *pc; 3136 vm_page_t m; 3137 3138 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3139 PV_STAT(atomic_add_long(&pv_entry_allocs, 1)); 3140 retry: 3141 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 3142 if (pc != NULL) { 3143 for (field = 0; field < _NPCM; field++) { 3144 if (pc->pc_map[field]) { 3145 bit = ffsl(pc->pc_map[field]) - 1; 3146 break; 3147 } 3148 } 3149 if (field < _NPCM) { 3150 pv = &pc->pc_pventry[field * 64 + bit]; 3151 pc->pc_map[field] &= ~(1ul << bit); 3152 /* If this was the last item, move it to tail */ 3153 if (pc_is_full(pc)) { 3154 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3155 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, 3156 pc_list); 3157 } 3158 PV_STAT(atomic_add_long(&pv_entry_count, 1)); 3159 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1)); 3160 return (pv); 3161 } 3162 } 3163 /* No free items, allocate another chunk */ 3164 m = vm_page_alloc_noobj(VM_ALLOC_WIRED); 3165 if (m == NULL) { 3166 if (lockp == NULL) { 3167 PV_STAT(pc_chunk_tryfail++); 3168 return (NULL); 3169 } 3170 m = reclaim_pv_chunk(pmap, lockp); 3171 if (m == NULL) 3172 goto retry; 3173 } 3174 PV_STAT(atomic_add_int(&pc_chunk_count, 1)); 3175 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1)); 3176 dump_add_page(m->phys_addr); 3177 pc = (void *)PHYS_TO_DMAP(m->phys_addr); 3178 pc->pc_pmap = pmap; 3179 memcpy(pc->pc_map, pc_freemask, sizeof(pc_freemask)); 3180 pc->pc_map[0] &= ~1ul; /* preallocated bit 0 */ 3181 pvc = &pv_chunks[vm_page_domain(m)]; 3182 mtx_lock(&pvc->pvc_lock); 3183 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru); 3184 mtx_unlock(&pvc->pvc_lock); 3185 pv = &pc->pc_pventry[0]; 3186 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 3187 PV_STAT(atomic_add_long(&pv_entry_count, 1)); 3188 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1)); 3189 return (pv); 3190 } 3191 3192 /* 3193 * Ensure that the number of spare PV entries in the specified pmap meets or 3194 * exceeds the given count, "needed". 3195 * 3196 * The given PV list lock may be released. 3197 */ 3198 static void 3199 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp) 3200 { 3201 struct pv_chunks_list *pvc; 3202 struct pch new_tail[PMAP_MEMDOM]; 3203 struct pv_chunk *pc; 3204 vm_page_t m; 3205 int avail, free, i; 3206 bool reclaimed; 3207 3208 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3209 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL")); 3210 3211 /* 3212 * Newly allocated PV chunks must be stored in a private list until 3213 * the required number of PV chunks have been allocated. Otherwise, 3214 * reclaim_pv_chunk() could recycle one of these chunks. In 3215 * contrast, these chunks must be added to the pmap upon allocation. 3216 */ 3217 for (i = 0; i < PMAP_MEMDOM; i++) 3218 TAILQ_INIT(&new_tail[i]); 3219 retry: 3220 avail = 0; 3221 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) { 3222 bit_count((bitstr_t *)pc->pc_map, 0, 3223 sizeof(pc->pc_map) * NBBY, &free); 3224 if (free == 0) 3225 break; 3226 avail += free; 3227 if (avail >= needed) 3228 break; 3229 } 3230 for (reclaimed = false; avail < needed; avail += _NPCPV) { 3231 m = vm_page_alloc_noobj(VM_ALLOC_WIRED); 3232 if (m == NULL) { 3233 m = reclaim_pv_chunk(pmap, lockp); 3234 if (m == NULL) 3235 goto retry; 3236 reclaimed = true; 3237 } 3238 PV_STAT(atomic_add_int(&pc_chunk_count, 1)); 3239 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1)); 3240 dump_add_page(m->phys_addr); 3241 pc = (void *)PHYS_TO_DMAP(m->phys_addr); 3242 pc->pc_pmap = pmap; 3243 memcpy(pc->pc_map, pc_freemask, sizeof(pc_freemask)); 3244 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 3245 TAILQ_INSERT_TAIL(&new_tail[vm_page_domain(m)], pc, pc_lru); 3246 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV)); 3247 3248 /* 3249 * The reclaim might have freed a chunk from the current pmap. 3250 * If that chunk contained available entries, we need to 3251 * re-count the number of available entries. 3252 */ 3253 if (reclaimed) 3254 goto retry; 3255 } 3256 for (i = 0; i < vm_ndomains; i++) { 3257 if (TAILQ_EMPTY(&new_tail[i])) 3258 continue; 3259 pvc = &pv_chunks[i]; 3260 mtx_lock(&pvc->pvc_lock); 3261 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru); 3262 mtx_unlock(&pvc->pvc_lock); 3263 } 3264 } 3265 3266 /* 3267 * First find and then remove the pv entry for the specified pmap and virtual 3268 * address from the specified pv list. Returns the pv entry if found and NULL 3269 * otherwise. This operation can be performed on pv lists for either 4KB or 3270 * 2MB page mappings. 3271 */ 3272 static __inline pv_entry_t 3273 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 3274 { 3275 pv_entry_t pv; 3276 3277 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 3278 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 3279 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 3280 pvh->pv_gen++; 3281 break; 3282 } 3283 } 3284 return (pv); 3285 } 3286 3287 /* 3288 * After demotion from a 2MB page mapping to 512 4KB page mappings, 3289 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv 3290 * entries for each of the 4KB page mappings. 3291 */ 3292 static void 3293 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 3294 struct rwlock **lockp) 3295 { 3296 struct md_page *pvh; 3297 struct pv_chunk *pc; 3298 pv_entry_t pv; 3299 vm_offset_t va_last; 3300 vm_page_t m; 3301 int bit, field; 3302 3303 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3304 KASSERT((va & L2_OFFSET) == 0, 3305 ("pmap_pv_demote_l2: va is not 2mpage aligned")); 3306 KASSERT((pa & L2_OFFSET) == 0, 3307 ("pmap_pv_demote_l2: pa is not 2mpage aligned")); 3308 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 3309 3310 /* 3311 * Transfer the 2mpage's pv entry for this mapping to the first 3312 * page's pv list. Once this transfer begins, the pv list lock 3313 * must not be released until the last pv entry is reinstantiated. 3314 */ 3315 pvh = pa_to_pvh(pa); 3316 pv = pmap_pvh_remove(pvh, pmap, va); 3317 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found")); 3318 m = PHYS_TO_VM_PAGE(pa); 3319 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3320 m->md.pv_gen++; 3321 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */ 3322 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1)); 3323 va_last = va + L2_SIZE - PAGE_SIZE; 3324 for (;;) { 3325 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 3326 KASSERT(!pc_is_full(pc), ("pmap_pv_demote_l2: missing spare")); 3327 for (field = 0; field < _NPCM; field++) { 3328 while (pc->pc_map[field]) { 3329 bit = ffsl(pc->pc_map[field]) - 1; 3330 pc->pc_map[field] &= ~(1ul << bit); 3331 pv = &pc->pc_pventry[field * 64 + bit]; 3332 va += PAGE_SIZE; 3333 pv->pv_va = va; 3334 m++; 3335 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3336 ("pmap_pv_demote_l2: page %p is not managed", m)); 3337 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3338 m->md.pv_gen++; 3339 if (va == va_last) 3340 goto out; 3341 } 3342 } 3343 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3344 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 3345 } 3346 out: 3347 if (pc_is_full(pc)) { 3348 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3349 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 3350 } 3351 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1)); 3352 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1)); 3353 } 3354 3355 /* 3356 * First find and then destroy the pv entry for the specified pmap and virtual 3357 * address. This operation can be performed on pv lists for either 4KB or 2MB 3358 * page mappings. 3359 */ 3360 static void 3361 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 3362 { 3363 pv_entry_t pv; 3364 3365 pv = pmap_pvh_remove(pvh, pmap, va); 3366 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 3367 free_pv_entry(pmap, pv); 3368 } 3369 3370 /* 3371 * Conditionally create the PV entry for a 4KB page mapping if the required 3372 * memory can be allocated without resorting to reclamation. 3373 */ 3374 static bool 3375 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m, 3376 struct rwlock **lockp) 3377 { 3378 pv_entry_t pv; 3379 3380 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3381 /* Pass NULL instead of the lock pointer to disable reclamation. */ 3382 if ((pv = get_pv_entry(pmap, NULL)) != NULL) { 3383 pv->pv_va = va; 3384 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 3385 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3386 m->md.pv_gen++; 3387 return (true); 3388 } else 3389 return (false); 3390 } 3391 3392 /* 3393 * Create the PV entry for a 2MB page mapping. Always returns true unless the 3394 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns 3395 * false if the PV entry cannot be allocated without resorting to reclamation. 3396 */ 3397 static bool 3398 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags, 3399 struct rwlock **lockp) 3400 { 3401 struct md_page *pvh; 3402 pv_entry_t pv; 3403 vm_paddr_t pa; 3404 3405 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3406 /* Pass NULL instead of the lock pointer to disable reclamation. */ 3407 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ? 3408 NULL : lockp)) == NULL) 3409 return (false); 3410 pv->pv_va = va; 3411 pa = PTE_TO_PHYS(l2e); 3412 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 3413 pvh = pa_to_pvh(pa); 3414 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 3415 pvh->pv_gen++; 3416 return (true); 3417 } 3418 3419 static void 3420 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va) 3421 { 3422 pt_entry_t newl2, oldl2 __diagused; 3423 vm_page_t ml3; 3424 vm_paddr_t ml3pa; 3425 3426 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va)); 3427 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap)); 3428 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3429 3430 ml3 = pmap_remove_pt_page(pmap, va); 3431 if (ml3 == NULL) 3432 panic("pmap_remove_kernel_l2: Missing pt page"); 3433 3434 ml3pa = VM_PAGE_TO_PHYS(ml3); 3435 newl2 = PHYS_TO_PTE(ml3pa) | L2_TABLE; 3436 3437 /* 3438 * If this page table page was unmapped by a promotion, then it 3439 * contains valid mappings. Zero it to invalidate those mappings. 3440 */ 3441 if (vm_page_any_valid(ml3)) 3442 pagezero((void *)PHYS_TO_DMAP(ml3pa)); 3443 3444 /* 3445 * Demote the mapping. The caller must have already invalidated the 3446 * mapping (i.e., the "break" in break-before-make). 3447 */ 3448 oldl2 = pmap_load_store(l2, newl2); 3449 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx", 3450 __func__, l2, oldl2)); 3451 } 3452 3453 /* 3454 * pmap_remove_l2: Do the things to unmap a level 2 superpage. 3455 */ 3456 static int 3457 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, 3458 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp) 3459 { 3460 struct md_page *pvh; 3461 pt_entry_t old_l2; 3462 vm_page_t m, ml3, mt; 3463 3464 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3465 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned")); 3466 old_l2 = pmap_load_clear(l2); 3467 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK, 3468 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2)); 3469 3470 /* 3471 * Since a promotion must break the 4KB page mappings before making 3472 * the 2MB page mapping, a pmap_s1_invalidate_page() suffices. 3473 */ 3474 pmap_s1_invalidate_page(pmap, sva, true); 3475 3476 if (old_l2 & ATTR_SW_WIRED) 3477 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE; 3478 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE); 3479 if (old_l2 & ATTR_SW_MANAGED) { 3480 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(old_l2)); 3481 pvh = page_to_pvh(m); 3482 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 3483 pmap_pvh_free(pvh, pmap, sva); 3484 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) { 3485 if (pmap_pte_dirty(pmap, old_l2)) 3486 vm_page_dirty(mt); 3487 if (old_l2 & ATTR_AF) 3488 vm_page_aflag_set(mt, PGA_REFERENCED); 3489 if (TAILQ_EMPTY(&mt->md.pv_list) && 3490 TAILQ_EMPTY(&pvh->pv_list)) 3491 vm_page_aflag_clear(mt, PGA_WRITEABLE); 3492 } 3493 } 3494 if (pmap == kernel_pmap) { 3495 pmap_remove_kernel_l2(pmap, l2, sva); 3496 } else { 3497 ml3 = pmap_remove_pt_page(pmap, sva); 3498 if (ml3 != NULL) { 3499 KASSERT(vm_page_any_valid(ml3), 3500 ("pmap_remove_l2: l3 page not promoted")); 3501 pmap_resident_count_dec(pmap, 1); 3502 KASSERT(ml3->ref_count == NL3PG, 3503 ("pmap_remove_l2: l3 page ref count error")); 3504 ml3->ref_count = 0; 3505 pmap_add_delayed_free_list(ml3, free, false); 3506 } 3507 } 3508 return (pmap_unuse_pt(pmap, sva, l1e, free)); 3509 } 3510 3511 /* 3512 * pmap_remove_l3: do the things to unmap a page in a process 3513 */ 3514 static int 3515 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va, 3516 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp) 3517 { 3518 struct md_page *pvh; 3519 pt_entry_t old_l3; 3520 vm_page_t m; 3521 3522 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3523 old_l3 = pmap_load_clear(l3); 3524 pmap_s1_invalidate_page(pmap, va, true); 3525 if (old_l3 & ATTR_SW_WIRED) 3526 pmap->pm_stats.wired_count -= 1; 3527 pmap_resident_count_dec(pmap, 1); 3528 if (old_l3 & ATTR_SW_MANAGED) { 3529 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(old_l3)); 3530 if (pmap_pte_dirty(pmap, old_l3)) 3531 vm_page_dirty(m); 3532 if (old_l3 & ATTR_AF) 3533 vm_page_aflag_set(m, PGA_REFERENCED); 3534 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 3535 pmap_pvh_free(&m->md, pmap, va); 3536 if (TAILQ_EMPTY(&m->md.pv_list) && 3537 (m->flags & PG_FICTITIOUS) == 0) { 3538 pvh = page_to_pvh(m); 3539 if (TAILQ_EMPTY(&pvh->pv_list)) 3540 vm_page_aflag_clear(m, PGA_WRITEABLE); 3541 } 3542 } 3543 return (pmap_unuse_pt(pmap, va, l2e, free)); 3544 } 3545 3546 /* 3547 * Remove the specified range of addresses from the L3 page table that is 3548 * identified by the given L2 entry. 3549 */ 3550 static void 3551 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva, 3552 vm_offset_t eva, struct spglist *free, struct rwlock **lockp) 3553 { 3554 struct md_page *pvh; 3555 struct rwlock *new_lock; 3556 pt_entry_t *l3, old_l3; 3557 vm_offset_t va; 3558 vm_page_t l3pg, m; 3559 3560 KASSERT(ADDR_IS_CANONICAL(sva), 3561 ("%s: Start address not in canonical form: %lx", __func__, sva)); 3562 KASSERT(ADDR_IS_CANONICAL(eva) || eva == VM_MAX_USER_ADDRESS, 3563 ("%s: End address not in canonical form: %lx", __func__, eva)); 3564 3565 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3566 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE), 3567 ("pmap_remove_l3_range: range crosses an L3 page table boundary")); 3568 l3pg = !ADDR_IS_KERNEL(sva) ? PHYS_TO_VM_PAGE(PTE_TO_PHYS(l2e)) : NULL; 3569 va = eva; 3570 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) { 3571 if (!pmap_l3_valid(pmap_load(l3))) { 3572 if (va != eva) { 3573 pmap_invalidate_range(pmap, va, sva, true); 3574 va = eva; 3575 } 3576 continue; 3577 } 3578 old_l3 = pmap_load_clear(l3); 3579 if ((old_l3 & ATTR_SW_WIRED) != 0) 3580 pmap->pm_stats.wired_count--; 3581 pmap_resident_count_dec(pmap, 1); 3582 if ((old_l3 & ATTR_SW_MANAGED) != 0) { 3583 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(old_l3)); 3584 if (pmap_pte_dirty(pmap, old_l3)) 3585 vm_page_dirty(m); 3586 if ((old_l3 & ATTR_AF) != 0) 3587 vm_page_aflag_set(m, PGA_REFERENCED); 3588 new_lock = VM_PAGE_TO_PV_LIST_LOCK(m); 3589 if (new_lock != *lockp) { 3590 if (*lockp != NULL) { 3591 /* 3592 * Pending TLB invalidations must be 3593 * performed before the PV list lock is 3594 * released. Otherwise, a concurrent 3595 * pmap_remove_all() on a physical page 3596 * could return while a stale TLB entry 3597 * still provides access to that page. 3598 */ 3599 if (va != eva) { 3600 pmap_invalidate_range(pmap, va, 3601 sva, true); 3602 va = eva; 3603 } 3604 rw_wunlock(*lockp); 3605 } 3606 *lockp = new_lock; 3607 rw_wlock(*lockp); 3608 } 3609 pmap_pvh_free(&m->md, pmap, sva); 3610 if (TAILQ_EMPTY(&m->md.pv_list) && 3611 (m->flags & PG_FICTITIOUS) == 0) { 3612 pvh = page_to_pvh(m); 3613 if (TAILQ_EMPTY(&pvh->pv_list)) 3614 vm_page_aflag_clear(m, PGA_WRITEABLE); 3615 } 3616 } 3617 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) { 3618 /* 3619 * _pmap_unwire_l3() has already invalidated the TLB 3620 * entries at all levels for "sva". So, we need not 3621 * perform "sva += L3_SIZE;" here. Moreover, we need 3622 * not perform "va = sva;" if "sva" is at the start 3623 * of a new valid range consisting of a single page. 3624 */ 3625 break; 3626 } 3627 if (va == eva) 3628 va = sva; 3629 } 3630 if (va != eva) 3631 pmap_invalidate_range(pmap, va, sva, true); 3632 } 3633 3634 /* 3635 * Remove the given range of addresses from the specified map. 3636 * 3637 * It is assumed that the start and end are properly 3638 * rounded to the page size. 3639 */ 3640 void 3641 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3642 { 3643 struct rwlock *lock; 3644 vm_offset_t va_next; 3645 pd_entry_t *l0, *l1, *l2; 3646 pt_entry_t l3_paddr; 3647 struct spglist free; 3648 3649 /* 3650 * Perform an unsynchronized read. This is, however, safe. 3651 */ 3652 if (pmap->pm_stats.resident_count == 0) 3653 return; 3654 3655 SLIST_INIT(&free); 3656 3657 PMAP_LOCK(pmap); 3658 3659 lock = NULL; 3660 for (; sva < eva; sva = va_next) { 3661 if (pmap->pm_stats.resident_count == 0) 3662 break; 3663 3664 l0 = pmap_l0(pmap, sva); 3665 if (pmap_load(l0) == 0) { 3666 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 3667 if (va_next < sva) 3668 va_next = eva; 3669 continue; 3670 } 3671 3672 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 3673 if (va_next < sva) 3674 va_next = eva; 3675 l1 = pmap_l0_to_l1(l0, sva); 3676 if (pmap_load(l1) == 0) 3677 continue; 3678 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) { 3679 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 3680 KASSERT(va_next <= eva, 3681 ("partial update of non-transparent 1G page " 3682 "l1 %#lx sva %#lx eva %#lx va_next %#lx", 3683 pmap_load(l1), sva, eva, va_next)); 3684 MPASS(pmap != kernel_pmap); 3685 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0); 3686 pmap_clear(l1); 3687 pmap_s1_invalidate_page(pmap, sva, true); 3688 pmap_resident_count_dec(pmap, L1_SIZE / PAGE_SIZE); 3689 pmap_unuse_pt(pmap, sva, pmap_load(l0), &free); 3690 continue; 3691 } 3692 3693 /* 3694 * Calculate index for next page table. 3695 */ 3696 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 3697 if (va_next < sva) 3698 va_next = eva; 3699 3700 l2 = pmap_l1_to_l2(l1, sva); 3701 if (l2 == NULL) 3702 continue; 3703 3704 l3_paddr = pmap_load(l2); 3705 3706 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) { 3707 if (sva + L2_SIZE == va_next && eva >= va_next) { 3708 pmap_remove_l2(pmap, l2, sva, pmap_load(l1), 3709 &free, &lock); 3710 continue; 3711 } else if (pmap_demote_l2_locked(pmap, l2, sva, 3712 &lock) == NULL) 3713 continue; 3714 l3_paddr = pmap_load(l2); 3715 } 3716 3717 /* 3718 * Weed out invalid mappings. 3719 */ 3720 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE) 3721 continue; 3722 3723 /* 3724 * Limit our scan to either the end of the va represented 3725 * by the current page table page, or to the end of the 3726 * range being removed. 3727 */ 3728 if (va_next > eva) 3729 va_next = eva; 3730 3731 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free, 3732 &lock); 3733 } 3734 if (lock != NULL) 3735 rw_wunlock(lock); 3736 PMAP_UNLOCK(pmap); 3737 vm_page_free_pages_toq(&free, true); 3738 } 3739 3740 /* 3741 * Remove the given range of addresses as part of a logical unmap 3742 * operation. This has the effect of calling pmap_remove(), but 3743 * also clears any metadata that should persist for the lifetime 3744 * of a logical mapping. 3745 */ 3746 void 3747 pmap_map_delete(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3748 { 3749 pmap_remove(pmap, sva, eva); 3750 } 3751 3752 /* 3753 * Routine: pmap_remove_all 3754 * Function: 3755 * Removes this physical page from 3756 * all physical maps in which it resides. 3757 * Reflects back modify bits to the pager. 3758 * 3759 * Notes: 3760 * Original versions of this routine were very 3761 * inefficient because they iteratively called 3762 * pmap_remove (slow...) 3763 */ 3764 3765 void 3766 pmap_remove_all(vm_page_t m) 3767 { 3768 struct md_page *pvh; 3769 pv_entry_t pv; 3770 pmap_t pmap; 3771 struct rwlock *lock; 3772 pd_entry_t *pde, tpde; 3773 pt_entry_t *pte, tpte; 3774 vm_offset_t va; 3775 struct spglist free; 3776 int lvl, pvh_gen, md_gen; 3777 3778 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3779 ("pmap_remove_all: page %p is not managed", m)); 3780 SLIST_INIT(&free); 3781 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 3782 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m); 3783 rw_wlock(lock); 3784 retry: 3785 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 3786 pmap = PV_PMAP(pv); 3787 if (!PMAP_TRYLOCK(pmap)) { 3788 pvh_gen = pvh->pv_gen; 3789 rw_wunlock(lock); 3790 PMAP_LOCK(pmap); 3791 rw_wlock(lock); 3792 if (pvh_gen != pvh->pv_gen) { 3793 PMAP_UNLOCK(pmap); 3794 goto retry; 3795 } 3796 } 3797 va = pv->pv_va; 3798 pte = pmap_pte_exists(pmap, va, 2, __func__); 3799 pmap_demote_l2_locked(pmap, pte, va, &lock); 3800 PMAP_UNLOCK(pmap); 3801 } 3802 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3803 pmap = PV_PMAP(pv); 3804 if (!PMAP_TRYLOCK(pmap)) { 3805 pvh_gen = pvh->pv_gen; 3806 md_gen = m->md.pv_gen; 3807 rw_wunlock(lock); 3808 PMAP_LOCK(pmap); 3809 rw_wlock(lock); 3810 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 3811 PMAP_UNLOCK(pmap); 3812 goto retry; 3813 } 3814 } 3815 pmap_resident_count_dec(pmap, 1); 3816 3817 pde = pmap_pde(pmap, pv->pv_va, &lvl); 3818 KASSERT(pde != NULL, 3819 ("pmap_remove_all: no page directory entry found")); 3820 KASSERT(lvl == 2, 3821 ("pmap_remove_all: invalid pde level %d", lvl)); 3822 tpde = pmap_load(pde); 3823 3824 pte = pmap_l2_to_l3(pde, pv->pv_va); 3825 tpte = pmap_load_clear(pte); 3826 if (tpte & ATTR_SW_WIRED) 3827 pmap->pm_stats.wired_count--; 3828 if ((tpte & ATTR_AF) != 0) { 3829 pmap_invalidate_page(pmap, pv->pv_va, true); 3830 vm_page_aflag_set(m, PGA_REFERENCED); 3831 } 3832 3833 /* 3834 * Update the vm_page_t clean and reference bits. 3835 */ 3836 if (pmap_pte_dirty(pmap, tpte)) 3837 vm_page_dirty(m); 3838 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free); 3839 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3840 m->md.pv_gen++; 3841 free_pv_entry(pmap, pv); 3842 PMAP_UNLOCK(pmap); 3843 } 3844 vm_page_aflag_clear(m, PGA_WRITEABLE); 3845 rw_wunlock(lock); 3846 vm_page_free_pages_toq(&free, true); 3847 } 3848 3849 /* 3850 * Masks and sets bits in a level 2 page table entries in the specified pmap 3851 */ 3852 static void 3853 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask, 3854 pt_entry_t nbits) 3855 { 3856 pd_entry_t old_l2; 3857 vm_page_t m, mt; 3858 3859 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3860 PMAP_ASSERT_STAGE1(pmap); 3861 KASSERT((sva & L2_OFFSET) == 0, 3862 ("pmap_protect_l2: sva is not 2mpage aligned")); 3863 old_l2 = pmap_load(l2); 3864 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK, 3865 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2)); 3866 3867 /* 3868 * Return if the L2 entry already has the desired access restrictions 3869 * in place. 3870 */ 3871 if ((old_l2 & mask) == nbits) 3872 return; 3873 3874 while (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits)) 3875 cpu_spinwait(); 3876 3877 /* 3878 * When a dirty read/write superpage mapping is write protected, 3879 * update the dirty field of each of the superpage's constituent 4KB 3880 * pages. 3881 */ 3882 if ((old_l2 & ATTR_SW_MANAGED) != 0 && 3883 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 && 3884 pmap_pte_dirty(pmap, old_l2)) { 3885 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(old_l2)); 3886 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) 3887 vm_page_dirty(mt); 3888 } 3889 3890 /* 3891 * Since a promotion must break the 4KB page mappings before making 3892 * the 2MB page mapping, a pmap_s1_invalidate_page() suffices. 3893 */ 3894 pmap_s1_invalidate_page(pmap, sva, true); 3895 } 3896 3897 /* 3898 * Masks and sets bits in last level page table entries in the specified 3899 * pmap and range 3900 */ 3901 static void 3902 pmap_mask_set_locked(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, pt_entry_t mask, 3903 pt_entry_t nbits, bool invalidate) 3904 { 3905 vm_offset_t va, va_next; 3906 pd_entry_t *l0, *l1, *l2; 3907 pt_entry_t *l3p, l3; 3908 3909 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3910 for (; sva < eva; sva = va_next) { 3911 l0 = pmap_l0(pmap, sva); 3912 if (pmap_load(l0) == 0) { 3913 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 3914 if (va_next < sva) 3915 va_next = eva; 3916 continue; 3917 } 3918 3919 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 3920 if (va_next < sva) 3921 va_next = eva; 3922 l1 = pmap_l0_to_l1(l0, sva); 3923 if (pmap_load(l1) == 0) 3924 continue; 3925 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) { 3926 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 3927 KASSERT(va_next <= eva, 3928 ("partial update of non-transparent 1G page " 3929 "l1 %#lx sva %#lx eva %#lx va_next %#lx", 3930 pmap_load(l1), sva, eva, va_next)); 3931 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0); 3932 if ((pmap_load(l1) & mask) != nbits) { 3933 pmap_store(l1, (pmap_load(l1) & ~mask) | nbits); 3934 if (invalidate) 3935 pmap_s1_invalidate_page(pmap, sva, true); 3936 } 3937 continue; 3938 } 3939 3940 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 3941 if (va_next < sva) 3942 va_next = eva; 3943 3944 l2 = pmap_l1_to_l2(l1, sva); 3945 if (pmap_load(l2) == 0) 3946 continue; 3947 3948 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) { 3949 if (sva + L2_SIZE == va_next && eva >= va_next) { 3950 pmap_protect_l2(pmap, l2, sva, mask, nbits); 3951 continue; 3952 } else if (pmap_demote_l2(pmap, l2, sva) == NULL) 3953 continue; 3954 } 3955 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE, 3956 ("pmap_protect: Invalid L2 entry after demotion")); 3957 3958 if (va_next > eva) 3959 va_next = eva; 3960 3961 va = va_next; 3962 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++, 3963 sva += L3_SIZE) { 3964 l3 = pmap_load(l3p); 3965 3966 /* 3967 * Go to the next L3 entry if the current one is 3968 * invalid or already has the desired access 3969 * restrictions in place. (The latter case occurs 3970 * frequently. For example, in a "buildworld" 3971 * workload, almost 1 out of 4 L3 entries already 3972 * have the desired restrictions.) 3973 */ 3974 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) { 3975 if (va != va_next) { 3976 if (invalidate) 3977 pmap_s1_invalidate_range(pmap, 3978 va, sva, true); 3979 va = va_next; 3980 } 3981 continue; 3982 } 3983 3984 while (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | 3985 nbits)) 3986 cpu_spinwait(); 3987 3988 /* 3989 * When a dirty read/write mapping is write protected, 3990 * update the page's dirty field. 3991 */ 3992 if ((l3 & ATTR_SW_MANAGED) != 0 && 3993 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 && 3994 pmap_pte_dirty(pmap, l3)) 3995 vm_page_dirty(PHYS_TO_VM_PAGE(PTE_TO_PHYS(l3))); 3996 3997 if (va == va_next) 3998 va = sva; 3999 } 4000 if (va != va_next && invalidate) 4001 pmap_s1_invalidate_range(pmap, va, sva, true); 4002 } 4003 } 4004 4005 static void 4006 pmap_mask_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, pt_entry_t mask, 4007 pt_entry_t nbits, bool invalidate) 4008 { 4009 PMAP_LOCK(pmap); 4010 pmap_mask_set_locked(pmap, sva, eva, mask, nbits, invalidate); 4011 PMAP_UNLOCK(pmap); 4012 } 4013 4014 /* 4015 * Set the physical protection on the 4016 * specified range of this map as requested. 4017 */ 4018 void 4019 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 4020 { 4021 pt_entry_t mask, nbits; 4022 4023 PMAP_ASSERT_STAGE1(pmap); 4024 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot)); 4025 if (prot == VM_PROT_NONE) { 4026 pmap_remove(pmap, sva, eva); 4027 return; 4028 } 4029 4030 mask = nbits = 0; 4031 if ((prot & VM_PROT_WRITE) == 0) { 4032 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM; 4033 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO); 4034 } 4035 if ((prot & VM_PROT_EXECUTE) == 0) { 4036 mask |= ATTR_S1_XN; 4037 nbits |= ATTR_S1_XN; 4038 } 4039 if (pmap == kernel_pmap) { 4040 mask |= ATTR_KERN_GP; 4041 nbits |= ATTR_KERN_GP; 4042 } 4043 if (mask == 0) 4044 return; 4045 4046 pmap_mask_set(pmap, sva, eva, mask, nbits, true); 4047 } 4048 4049 void 4050 pmap_disable_promotion(vm_offset_t sva, vm_size_t size) 4051 { 4052 4053 MPASS((sva & L3_OFFSET) == 0); 4054 MPASS(((sva + size) & L3_OFFSET) == 0); 4055 4056 pmap_mask_set(kernel_pmap, sva, sva + size, ATTR_SW_NO_PROMOTE, 4057 ATTR_SW_NO_PROMOTE, false); 4058 } 4059 4060 /* 4061 * Inserts the specified page table page into the specified pmap's collection 4062 * of idle page table pages. Each of a pmap's page table pages is responsible 4063 * for mapping a distinct range of virtual addresses. The pmap's collection is 4064 * ordered by this virtual address range. 4065 * 4066 * If "promoted" is false, then the page table page "mpte" must be zero filled; 4067 * "mpte"'s valid field will be set to 0. 4068 * 4069 * If "promoted" is true and "all_l3e_AF_set" is false, then "mpte" must 4070 * contain valid mappings with identical attributes except for ATTR_AF; 4071 * "mpte"'s valid field will be set to 1. 4072 * 4073 * If "promoted" and "all_l3e_AF_set" are both true, then "mpte" must contain 4074 * valid mappings with identical attributes including ATTR_AF; "mpte"'s valid 4075 * field will be set to VM_PAGE_BITS_ALL. 4076 */ 4077 static __inline int 4078 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted, 4079 bool all_l3e_AF_set) 4080 { 4081 4082 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4083 KASSERT(promoted || !all_l3e_AF_set, 4084 ("a zero-filled PTP can't have ATTR_AF set in every PTE")); 4085 mpte->valid = promoted ? (all_l3e_AF_set ? VM_PAGE_BITS_ALL : 1) : 0; 4086 return (vm_radix_insert(&pmap->pm_root, mpte)); 4087 } 4088 4089 /* 4090 * Removes the page table page mapping the specified virtual address from the 4091 * specified pmap's collection of idle page table pages, and returns it. 4092 * Otherwise, returns NULL if there is no page table page corresponding to the 4093 * specified virtual address. 4094 */ 4095 static __inline vm_page_t 4096 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va) 4097 { 4098 4099 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4100 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va))); 4101 } 4102 4103 /* 4104 * Performs a break-before-make update of a pmap entry. This is needed when 4105 * either promoting or demoting pages to ensure the TLB doesn't get into an 4106 * inconsistent state. 4107 */ 4108 static void 4109 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte, 4110 vm_offset_t va, vm_size_t size) 4111 { 4112 register_t intr; 4113 4114 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4115 4116 if ((newpte & ATTR_SW_NO_PROMOTE) != 0) 4117 panic("%s: Updating non-promote pte", __func__); 4118 4119 /* 4120 * Ensure we don't get switched out with the page table in an 4121 * inconsistent state. We also need to ensure no interrupts fire 4122 * as they may make use of an address we are about to invalidate. 4123 */ 4124 intr = intr_disable(); 4125 4126 /* 4127 * Clear the old mapping's valid bit, but leave the rest of the entry 4128 * unchanged, so that a lockless, concurrent pmap_kextract() can still 4129 * lookup the physical address. 4130 */ 4131 pmap_clear_bits(pte, ATTR_DESCR_VALID); 4132 4133 /* 4134 * When promoting, the L{1,2}_TABLE entry that is being replaced might 4135 * be cached, so we invalidate intermediate entries as well as final 4136 * entries. 4137 */ 4138 pmap_s1_invalidate_range(pmap, va, va + size, false); 4139 4140 /* Create the new mapping */ 4141 pmap_store(pte, newpte); 4142 dsb(ishst); 4143 4144 intr_restore(intr); 4145 } 4146 4147 #if VM_NRESERVLEVEL > 0 4148 /* 4149 * After promotion from 512 4KB page mappings to a single 2MB page mapping, 4150 * replace the many pv entries for the 4KB page mappings by a single pv entry 4151 * for the 2MB page mapping. 4152 */ 4153 static void 4154 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 4155 struct rwlock **lockp) 4156 { 4157 struct md_page *pvh; 4158 pv_entry_t pv; 4159 vm_offset_t va_last; 4160 vm_page_t m; 4161 4162 KASSERT((pa & L2_OFFSET) == 0, 4163 ("pmap_pv_promote_l2: pa is not 2mpage aligned")); 4164 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 4165 4166 /* 4167 * Transfer the first page's pv entry for this mapping to the 2mpage's 4168 * pv list. Aside from avoiding the cost of a call to get_pv_entry(), 4169 * a transfer avoids the possibility that get_pv_entry() calls 4170 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the 4171 * mappings that is being promoted. 4172 */ 4173 m = PHYS_TO_VM_PAGE(pa); 4174 va = va & ~L2_OFFSET; 4175 pv = pmap_pvh_remove(&m->md, pmap, va); 4176 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found")); 4177 pvh = page_to_pvh(m); 4178 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 4179 pvh->pv_gen++; 4180 /* Free the remaining NPTEPG - 1 pv entries. */ 4181 va_last = va + L2_SIZE - PAGE_SIZE; 4182 do { 4183 m++; 4184 va += PAGE_SIZE; 4185 pmap_pvh_free(&m->md, pmap, va); 4186 } while (va < va_last); 4187 } 4188 4189 /* 4190 * Tries to promote the 512, contiguous 4KB page mappings that are within a 4191 * single level 2 table entry to a single 2MB page mapping. For promotion 4192 * to occur, two conditions must be met: (1) the 4KB page mappings must map 4193 * aligned, contiguous physical memory and (2) the 4KB page mappings must have 4194 * identical characteristics. 4195 */ 4196 static bool 4197 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va, vm_page_t mpte, 4198 struct rwlock **lockp) 4199 { 4200 pt_entry_t all_l3e_AF, *firstl3, *l3, newl2, oldl3, pa; 4201 4202 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4203 4204 /* 4205 * Currently, this function only supports promotion on stage 1 pmaps 4206 * because it tests stage 1 specific fields and performs a break- 4207 * before-make sequence that is incorrect for stage 2 pmaps. 4208 */ 4209 if (pmap->pm_stage != PM_STAGE1 || !pmap_ps_enabled(pmap)) 4210 return (false); 4211 4212 /* 4213 * Examine the first L3E in the specified PTP. Abort if this L3E is 4214 * ineligible for promotion... 4215 */ 4216 firstl3 = (pt_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(pmap_load(l2))); 4217 newl2 = pmap_load(firstl3); 4218 if ((newl2 & ATTR_SW_NO_PROMOTE) != 0) 4219 return (false); 4220 /* ... is not the first physical page within an L2 block */ 4221 if ((PTE_TO_PHYS(newl2) & L2_OFFSET) != 0 || 4222 ((newl2 & ATTR_DESCR_MASK) != L3_PAGE)) { /* ... or is invalid */ 4223 atomic_add_long(&pmap_l2_p_failures, 1); 4224 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx" 4225 " in pmap %p", va, pmap); 4226 return (false); 4227 } 4228 4229 /* 4230 * Both here and in the below "for" loop, to allow for repromotion 4231 * after MADV_FREE, conditionally write protect a clean L3E before 4232 * possibly aborting the promotion due to other L3E attributes. Why? 4233 * Suppose that MADV_FREE is applied to a part of a superpage, the 4234 * address range [S, E). pmap_advise() will demote the superpage 4235 * mapping, destroy the 4KB page mapping at the end of [S, E), and 4236 * set AP_RO and clear AF in the L3Es for the rest of [S, E). Later, 4237 * imagine that the memory in [S, E) is recycled, but the last 4KB 4238 * page in [S, E) is not the last to be rewritten, or simply accessed. 4239 * In other words, there is still a 4KB page in [S, E), call it P, 4240 * that is writeable but AP_RO is set and AF is clear in P's L3E. 4241 * Unless we write protect P before aborting the promotion, if and 4242 * when P is finally rewritten, there won't be a page fault to trigger 4243 * repromotion. 4244 */ 4245 setl2: 4246 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == 4247 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) { 4248 /* 4249 * When the mapping is clean, i.e., ATTR_S1_AP_RO is set, 4250 * ATTR_SW_DBM can be cleared without a TLB invalidation. 4251 */ 4252 if (!atomic_fcmpset_64(firstl3, &newl2, newl2 & ~ATTR_SW_DBM)) 4253 goto setl2; 4254 newl2 &= ~ATTR_SW_DBM; 4255 CTR2(KTR_PMAP, "pmap_promote_l2: protect for va %#lx" 4256 " in pmap %p", va & ~L2_OFFSET, pmap); 4257 } 4258 4259 /* 4260 * Examine each of the other L3Es in the specified PTP. Abort if this 4261 * L3E maps an unexpected 4KB physical page or does not have identical 4262 * characteristics to the first L3E. If ATTR_AF is not set in every 4263 * PTE, then request that the PTP be refilled on demotion. 4264 */ 4265 all_l3e_AF = newl2 & ATTR_AF; 4266 pa = (PTE_TO_PHYS(newl2) | (newl2 & ATTR_DESCR_MASK)) 4267 + L2_SIZE - PAGE_SIZE; 4268 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) { 4269 oldl3 = pmap_load(l3); 4270 if ((PTE_TO_PHYS(oldl3) | (oldl3 & ATTR_DESCR_MASK)) != pa) { 4271 atomic_add_long(&pmap_l2_p_failures, 1); 4272 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx" 4273 " in pmap %p", va, pmap); 4274 return (false); 4275 } 4276 setl3: 4277 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == 4278 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) { 4279 /* 4280 * When the mapping is clean, i.e., ATTR_S1_AP_RO is 4281 * set, ATTR_SW_DBM can be cleared without a TLB 4282 * invalidation. 4283 */ 4284 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 & 4285 ~ATTR_SW_DBM)) 4286 goto setl3; 4287 oldl3 &= ~ATTR_SW_DBM; 4288 } 4289 if ((oldl3 & (ATTR_MASK & ~ATTR_AF)) != (newl2 & (ATTR_MASK & 4290 ~ATTR_AF))) { 4291 atomic_add_long(&pmap_l2_p_failures, 1); 4292 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx" 4293 " in pmap %p", va, pmap); 4294 return (false); 4295 } 4296 all_l3e_AF &= oldl3; 4297 pa -= PAGE_SIZE; 4298 } 4299 4300 /* 4301 * Unless all PTEs have ATTR_AF set, clear it from the superpage 4302 * mapping, so that promotions triggered by speculative mappings, 4303 * such as pmap_enter_quick(), don't automatically mark the 4304 * underlying pages as referenced. 4305 */ 4306 newl2 &= ~ATTR_AF | all_l3e_AF; 4307 4308 /* 4309 * Save the page table page in its current state until the L2 4310 * mapping the superpage is demoted by pmap_demote_l2() or 4311 * destroyed by pmap_remove_l3(). 4312 */ 4313 if (mpte == NULL) 4314 mpte = PHYS_TO_VM_PAGE(PTE_TO_PHYS(pmap_load(l2))); 4315 KASSERT(mpte >= vm_page_array && 4316 mpte < &vm_page_array[vm_page_array_size], 4317 ("pmap_promote_l2: page table page is out of range")); 4318 KASSERT(mpte->pindex == pmap_l2_pindex(va), 4319 ("pmap_promote_l2: page table page's pindex is wrong")); 4320 if (pmap_insert_pt_page(pmap, mpte, true, all_l3e_AF != 0)) { 4321 atomic_add_long(&pmap_l2_p_failures, 1); 4322 CTR2(KTR_PMAP, 4323 "pmap_promote_l2: failure for va %#lx in pmap %p", va, 4324 pmap); 4325 return (false); 4326 } 4327 4328 if ((newl2 & ATTR_SW_MANAGED) != 0) 4329 pmap_pv_promote_l2(pmap, va, PTE_TO_PHYS(newl2), lockp); 4330 4331 newl2 &= ~ATTR_DESCR_MASK; 4332 newl2 |= L2_BLOCK; 4333 4334 pmap_update_entry(pmap, l2, newl2, va & ~L2_OFFSET, L2_SIZE); 4335 4336 atomic_add_long(&pmap_l2_promotions, 1); 4337 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va, 4338 pmap); 4339 return (true); 4340 } 4341 #endif /* VM_NRESERVLEVEL > 0 */ 4342 4343 static int 4344 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags, 4345 int psind) 4346 { 4347 pd_entry_t *l0p, *l1p, *l2p, origpte; 4348 vm_page_t mp; 4349 4350 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4351 KASSERT(psind > 0 && psind < MAXPAGESIZES, 4352 ("psind %d unexpected", psind)); 4353 KASSERT((PTE_TO_PHYS(newpte) & (pagesizes[psind] - 1)) == 0, 4354 ("unaligned phys address %#lx newpte %#lx psind %d", 4355 PTE_TO_PHYS(newpte), newpte, psind)); 4356 4357 restart: 4358 if (psind == 2) { 4359 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 4360 4361 l0p = pmap_l0(pmap, va); 4362 if ((pmap_load(l0p) & ATTR_DESCR_VALID) == 0) { 4363 mp = _pmap_alloc_l3(pmap, pmap_l0_pindex(va), NULL); 4364 if (mp == NULL) { 4365 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 4366 return (KERN_RESOURCE_SHORTAGE); 4367 PMAP_UNLOCK(pmap); 4368 vm_wait(NULL); 4369 PMAP_LOCK(pmap); 4370 goto restart; 4371 } 4372 l1p = pmap_l0_to_l1(l0p, va); 4373 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va)); 4374 origpte = pmap_load(l1p); 4375 } else { 4376 l1p = pmap_l0_to_l1(l0p, va); 4377 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va)); 4378 origpte = pmap_load(l1p); 4379 if ((origpte & ATTR_DESCR_VALID) == 0) { 4380 mp = PHYS_TO_VM_PAGE( 4381 PTE_TO_PHYS(pmap_load(l0p))); 4382 mp->ref_count++; 4383 } 4384 } 4385 KASSERT((PTE_TO_PHYS(origpte) == PTE_TO_PHYS(newpte) && 4386 (origpte & ATTR_DESCR_MASK) == L1_BLOCK) || 4387 (origpte & ATTR_DESCR_VALID) == 0, 4388 ("va %#lx changing 1G phys page l1 %#lx newpte %#lx", 4389 va, origpte, newpte)); 4390 pmap_store(l1p, newpte); 4391 } else /* (psind == 1) */ { 4392 l2p = pmap_l2(pmap, va); 4393 if (l2p == NULL) { 4394 mp = _pmap_alloc_l3(pmap, pmap_l1_pindex(va), NULL); 4395 if (mp == NULL) { 4396 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 4397 return (KERN_RESOURCE_SHORTAGE); 4398 PMAP_UNLOCK(pmap); 4399 vm_wait(NULL); 4400 PMAP_LOCK(pmap); 4401 goto restart; 4402 } 4403 l2p = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp)); 4404 l2p = &l2p[pmap_l2_index(va)]; 4405 origpte = pmap_load(l2p); 4406 } else { 4407 l1p = pmap_l1(pmap, va); 4408 origpte = pmap_load(l2p); 4409 if ((origpte & ATTR_DESCR_VALID) == 0) { 4410 mp = PHYS_TO_VM_PAGE( 4411 PTE_TO_PHYS(pmap_load(l1p))); 4412 mp->ref_count++; 4413 } 4414 } 4415 KASSERT((origpte & ATTR_DESCR_VALID) == 0 || 4416 ((origpte & ATTR_DESCR_MASK) == L2_BLOCK && 4417 PTE_TO_PHYS(origpte) == PTE_TO_PHYS(newpte)), 4418 ("va %#lx changing 2M phys page l2 %#lx newpte %#lx", 4419 va, origpte, newpte)); 4420 pmap_store(l2p, newpte); 4421 } 4422 dsb(ishst); 4423 4424 if ((origpte & ATTR_DESCR_VALID) == 0) 4425 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE); 4426 if ((newpte & ATTR_SW_WIRED) != 0 && (origpte & ATTR_SW_WIRED) == 0) 4427 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE; 4428 else if ((newpte & ATTR_SW_WIRED) == 0 && 4429 (origpte & ATTR_SW_WIRED) != 0) 4430 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE; 4431 4432 return (KERN_SUCCESS); 4433 } 4434 4435 /* 4436 * Insert the given physical page (p) at 4437 * the specified virtual address (v) in the 4438 * target physical map with the protection requested. 4439 * 4440 * If specified, the page will be wired down, meaning 4441 * that the related pte can not be reclaimed. 4442 * 4443 * NB: This is the only routine which MAY NOT lazy-evaluate 4444 * or lose information. That is, this routine must actually 4445 * insert this page into the given map NOW. 4446 */ 4447 int 4448 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 4449 u_int flags, int8_t psind) 4450 { 4451 struct rwlock *lock; 4452 pd_entry_t *pde; 4453 pt_entry_t new_l3, orig_l3; 4454 pt_entry_t *l2, *l3; 4455 pv_entry_t pv; 4456 vm_paddr_t opa, pa; 4457 vm_page_t mpte, om; 4458 bool nosleep; 4459 int lvl, rv; 4460 4461 KASSERT(ADDR_IS_CANONICAL(va), 4462 ("%s: Address not in canonical form: %lx", __func__, va)); 4463 4464 va = trunc_page(va); 4465 if ((m->oflags & VPO_UNMANAGED) == 0) 4466 VM_PAGE_OBJECT_BUSY_ASSERT(m); 4467 pa = VM_PAGE_TO_PHYS(m); 4468 new_l3 = (pt_entry_t)(PHYS_TO_PTE(pa) | ATTR_DEFAULT | L3_PAGE); 4469 new_l3 |= pmap_pte_memattr(pmap, m->md.pv_memattr); 4470 new_l3 |= pmap_pte_prot(pmap, prot); 4471 if ((flags & PMAP_ENTER_WIRED) != 0) 4472 new_l3 |= ATTR_SW_WIRED; 4473 if (pmap->pm_stage == PM_STAGE1) { 4474 if (!ADDR_IS_KERNEL(va)) 4475 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN; 4476 else 4477 new_l3 |= ATTR_S1_UXN; 4478 if (pmap != kernel_pmap) 4479 new_l3 |= ATTR_S1_nG; 4480 } else { 4481 /* 4482 * Clear the access flag on executable mappings, this will be 4483 * set later when the page is accessed. The fault handler is 4484 * required to invalidate the I-cache. 4485 * 4486 * TODO: Switch to the valid flag to allow hardware management 4487 * of the access flag. Much of the pmap code assumes the 4488 * valid flag is set and fails to destroy the old page tables 4489 * correctly if it is clear. 4490 */ 4491 if (prot & VM_PROT_EXECUTE) 4492 new_l3 &= ~ATTR_AF; 4493 } 4494 if ((m->oflags & VPO_UNMANAGED) == 0) { 4495 new_l3 |= ATTR_SW_MANAGED; 4496 if ((prot & VM_PROT_WRITE) != 0) { 4497 new_l3 |= ATTR_SW_DBM; 4498 if ((flags & VM_PROT_WRITE) == 0) { 4499 if (pmap->pm_stage == PM_STAGE1) 4500 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO); 4501 else 4502 new_l3 &= 4503 ~ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE); 4504 } 4505 } 4506 } 4507 4508 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa); 4509 4510 lock = NULL; 4511 PMAP_LOCK(pmap); 4512 /* Wait until we lock the pmap to protect the bti rangeset */ 4513 new_l3 |= pmap_pte_bti(pmap, va); 4514 4515 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) { 4516 KASSERT((m->oflags & VPO_UNMANAGED) != 0, 4517 ("managed largepage va %#lx flags %#x", va, flags)); 4518 new_l3 &= ~L3_PAGE; 4519 if (psind == 2) { 4520 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 4521 new_l3 |= L1_BLOCK; 4522 } else /* (psind == 1) */ 4523 new_l3 |= L2_BLOCK; 4524 rv = pmap_enter_largepage(pmap, va, new_l3, flags, psind); 4525 goto out; 4526 } 4527 if (psind == 1) { 4528 /* Assert the required virtual and physical alignment. */ 4529 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned")); 4530 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind")); 4531 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK, 4532 flags, m, &lock); 4533 goto out; 4534 } 4535 mpte = NULL; 4536 4537 /* 4538 * In the case that a page table page is not 4539 * resident, we are creating it here. 4540 */ 4541 retry: 4542 pde = pmap_pde(pmap, va, &lvl); 4543 if (pde != NULL && lvl == 2) { 4544 l3 = pmap_l2_to_l3(pde, va); 4545 if (!ADDR_IS_KERNEL(va) && mpte == NULL) { 4546 mpte = PHYS_TO_VM_PAGE(PTE_TO_PHYS(pmap_load(pde))); 4547 mpte->ref_count++; 4548 } 4549 goto havel3; 4550 } else if (pde != NULL && lvl == 1) { 4551 l2 = pmap_l1_to_l2(pde, va); 4552 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK && 4553 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) { 4554 l3 = &l3[pmap_l3_index(va)]; 4555 if (!ADDR_IS_KERNEL(va)) { 4556 mpte = PHYS_TO_VM_PAGE( 4557 PTE_TO_PHYS(pmap_load(l2))); 4558 mpte->ref_count++; 4559 } 4560 goto havel3; 4561 } 4562 /* We need to allocate an L3 table. */ 4563 } 4564 if (!ADDR_IS_KERNEL(va)) { 4565 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0; 4566 4567 /* 4568 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order 4569 * to handle the possibility that a superpage mapping for "va" 4570 * was created while we slept. 4571 */ 4572 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va), 4573 nosleep ? NULL : &lock); 4574 if (mpte == NULL && nosleep) { 4575 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL"); 4576 rv = KERN_RESOURCE_SHORTAGE; 4577 goto out; 4578 } 4579 goto retry; 4580 } else 4581 panic("pmap_enter: missing L3 table for kernel va %#lx", va); 4582 4583 havel3: 4584 orig_l3 = pmap_load(l3); 4585 opa = PTE_TO_PHYS(orig_l3); 4586 pv = NULL; 4587 4588 /* 4589 * Is the specified virtual address already mapped? 4590 */ 4591 if (pmap_l3_valid(orig_l3)) { 4592 /* 4593 * Wiring change, just update stats. We don't worry about 4594 * wiring PT pages as they remain resident as long as there 4595 * are valid mappings in them. Hence, if a user page is wired, 4596 * the PT page will be also. 4597 */ 4598 if ((flags & PMAP_ENTER_WIRED) != 0 && 4599 (orig_l3 & ATTR_SW_WIRED) == 0) 4600 pmap->pm_stats.wired_count++; 4601 else if ((flags & PMAP_ENTER_WIRED) == 0 && 4602 (orig_l3 & ATTR_SW_WIRED) != 0) 4603 pmap->pm_stats.wired_count--; 4604 4605 /* 4606 * Remove the extra PT page reference. 4607 */ 4608 if (mpte != NULL) { 4609 mpte->ref_count--; 4610 KASSERT(mpte->ref_count > 0, 4611 ("pmap_enter: missing reference to page table page," 4612 " va: 0x%lx", va)); 4613 } 4614 4615 /* 4616 * Has the physical page changed? 4617 */ 4618 if (opa == pa) { 4619 /* 4620 * No, might be a protection or wiring change. 4621 */ 4622 if ((orig_l3 & ATTR_SW_MANAGED) != 0 && 4623 (new_l3 & ATTR_SW_DBM) != 0) 4624 vm_page_aflag_set(m, PGA_WRITEABLE); 4625 goto validate; 4626 } 4627 4628 /* 4629 * The physical page has changed. Temporarily invalidate 4630 * the mapping. 4631 */ 4632 orig_l3 = pmap_load_clear(l3); 4633 KASSERT(PTE_TO_PHYS(orig_l3) == opa, 4634 ("pmap_enter: unexpected pa update for %#lx", va)); 4635 if ((orig_l3 & ATTR_SW_MANAGED) != 0) { 4636 om = PHYS_TO_VM_PAGE(opa); 4637 4638 /* 4639 * The pmap lock is sufficient to synchronize with 4640 * concurrent calls to pmap_page_test_mappings() and 4641 * pmap_ts_referenced(). 4642 */ 4643 if (pmap_pte_dirty(pmap, orig_l3)) 4644 vm_page_dirty(om); 4645 if ((orig_l3 & ATTR_AF) != 0) { 4646 pmap_invalidate_page(pmap, va, true); 4647 vm_page_aflag_set(om, PGA_REFERENCED); 4648 } 4649 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, om); 4650 pv = pmap_pvh_remove(&om->md, pmap, va); 4651 if ((m->oflags & VPO_UNMANAGED) != 0) 4652 free_pv_entry(pmap, pv); 4653 if ((om->a.flags & PGA_WRITEABLE) != 0 && 4654 TAILQ_EMPTY(&om->md.pv_list) && 4655 ((om->flags & PG_FICTITIOUS) != 0 || 4656 TAILQ_EMPTY(&page_to_pvh(om)->pv_list))) 4657 vm_page_aflag_clear(om, PGA_WRITEABLE); 4658 } else { 4659 KASSERT((orig_l3 & ATTR_AF) != 0, 4660 ("pmap_enter: unmanaged mapping lacks ATTR_AF")); 4661 pmap_invalidate_page(pmap, va, true); 4662 } 4663 orig_l3 = 0; 4664 } else { 4665 /* 4666 * Increment the counters. 4667 */ 4668 if ((new_l3 & ATTR_SW_WIRED) != 0) 4669 pmap->pm_stats.wired_count++; 4670 pmap_resident_count_inc(pmap, 1); 4671 } 4672 /* 4673 * Enter on the PV list if part of our managed memory. 4674 */ 4675 if ((m->oflags & VPO_UNMANAGED) == 0) { 4676 if (pv == NULL) { 4677 pv = get_pv_entry(pmap, &lock); 4678 pv->pv_va = va; 4679 } 4680 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m); 4681 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 4682 m->md.pv_gen++; 4683 if ((new_l3 & ATTR_SW_DBM) != 0) 4684 vm_page_aflag_set(m, PGA_WRITEABLE); 4685 } 4686 4687 validate: 4688 if (pmap->pm_stage == PM_STAGE1) { 4689 /* 4690 * Sync icache if exec permission and attribute 4691 * VM_MEMATTR_WRITE_BACK is set. Do it now, before the mapping 4692 * is stored and made valid for hardware table walk. If done 4693 * later, then other can access this page before caches are 4694 * properly synced. Don't do it for kernel memory which is 4695 * mapped with exec permission even if the memory isn't going 4696 * to hold executable code. The only time when icache sync is 4697 * needed is after kernel module is loaded and the relocation 4698 * info is processed. And it's done in elf_cpu_load_file(). 4699 */ 4700 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap && 4701 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK && 4702 (opa != pa || (orig_l3 & ATTR_S1_XN))) { 4703 PMAP_ASSERT_STAGE1(pmap); 4704 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE); 4705 } 4706 } else { 4707 cpu_dcache_wb_range(PHYS_TO_DMAP(pa), PAGE_SIZE); 4708 } 4709 4710 /* 4711 * Update the L3 entry 4712 */ 4713 if (pmap_l3_valid(orig_l3)) { 4714 KASSERT(opa == pa, ("pmap_enter: invalid update")); 4715 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) { 4716 /* same PA, different attributes */ 4717 orig_l3 = pmap_load_store(l3, new_l3); 4718 pmap_invalidate_page(pmap, va, true); 4719 if ((orig_l3 & ATTR_SW_MANAGED) != 0 && 4720 pmap_pte_dirty(pmap, orig_l3)) 4721 vm_page_dirty(m); 4722 } else { 4723 /* 4724 * orig_l3 == new_l3 4725 * This can happens if multiple threads simultaneously 4726 * access not yet mapped page. This bad for performance 4727 * since this can cause full demotion-NOP-promotion 4728 * cycle. 4729 * Another possible reasons are: 4730 * - VM and pmap memory layout are diverged 4731 * - tlb flush is missing somewhere and CPU doesn't see 4732 * actual mapping. 4733 */ 4734 CTR4(KTR_PMAP, "%s: already mapped page - " 4735 "pmap %p va 0x%#lx pte 0x%lx", 4736 __func__, pmap, va, new_l3); 4737 } 4738 } else { 4739 /* New mapping */ 4740 pmap_store(l3, new_l3); 4741 dsb(ishst); 4742 } 4743 4744 #if VM_NRESERVLEVEL > 0 4745 /* 4746 * If both the page table page and the reservation are fully 4747 * populated, then attempt promotion. 4748 */ 4749 if ((mpte == NULL || mpte->ref_count == NL3PG) && 4750 (m->flags & PG_FICTITIOUS) == 0 && 4751 vm_reserv_level_iffullpop(m) == 0) 4752 (void)pmap_promote_l2(pmap, pde, va, mpte, &lock); 4753 #endif 4754 4755 rv = KERN_SUCCESS; 4756 out: 4757 if (lock != NULL) 4758 rw_wunlock(lock); 4759 PMAP_UNLOCK(pmap); 4760 return (rv); 4761 } 4762 4763 /* 4764 * Tries to create a read- and/or execute-only 2MB page mapping. Returns 4765 * KERN_SUCCESS if the mapping was created. Otherwise, returns an error 4766 * value. See pmap_enter_l2() for the possible error values when "no sleep", 4767 * "no replace", and "no reclaim" are specified. 4768 */ 4769 static int 4770 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 4771 struct rwlock **lockp) 4772 { 4773 pd_entry_t new_l2; 4774 4775 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4776 PMAP_ASSERT_STAGE1(pmap); 4777 KASSERT(ADDR_IS_CANONICAL(va), 4778 ("%s: Address not in canonical form: %lx", __func__, va)); 4779 4780 new_l2 = (pd_entry_t)(PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) | ATTR_DEFAULT | 4781 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) | 4782 L2_BLOCK); 4783 new_l2 |= pmap_pte_bti(pmap, va); 4784 if ((m->oflags & VPO_UNMANAGED) == 0) { 4785 new_l2 |= ATTR_SW_MANAGED; 4786 new_l2 &= ~ATTR_AF; 4787 } 4788 if ((prot & VM_PROT_EXECUTE) == 0 || 4789 m->md.pv_memattr == VM_MEMATTR_DEVICE) 4790 new_l2 |= ATTR_S1_XN; 4791 if (!ADDR_IS_KERNEL(va)) 4792 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN; 4793 else 4794 new_l2 |= ATTR_S1_UXN; 4795 if (pmap != kernel_pmap) 4796 new_l2 |= ATTR_S1_nG; 4797 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP | 4798 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, m, lockp)); 4799 } 4800 4801 /* 4802 * Returns true if every page table entry in the specified page table is 4803 * zero. 4804 */ 4805 static bool 4806 pmap_every_pte_zero(vm_paddr_t pa) 4807 { 4808 pt_entry_t *pt_end, *pte; 4809 4810 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned")); 4811 pte = (pt_entry_t *)PHYS_TO_DMAP(pa); 4812 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) { 4813 if (*pte != 0) 4814 return (false); 4815 } 4816 return (true); 4817 } 4818 4819 /* 4820 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if 4821 * the mapping was created, and one of KERN_FAILURE, KERN_NO_SPACE, or 4822 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if 4823 * PMAP_ENTER_NOREPLACE was specified and a 4KB page mapping already exists 4824 * within the 2MB virtual address range starting at the specified virtual 4825 * address. Returns KERN_NO_SPACE if PMAP_ENTER_NOREPLACE was specified and a 4826 * 2MB page mapping already exists at the specified virtual address. Returns 4827 * KERN_RESOURCE_SHORTAGE if either (1) PMAP_ENTER_NOSLEEP was specified and a 4828 * page table page allocation failed or (2) PMAP_ENTER_NORECLAIM was specified 4829 * and a PV entry allocation failed. 4830 */ 4831 static int 4832 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags, 4833 vm_page_t m, struct rwlock **lockp) 4834 { 4835 struct spglist free; 4836 pd_entry_t *l2, old_l2; 4837 vm_page_t l2pg, mt; 4838 vm_page_t uwptpg; 4839 4840 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4841 KASSERT(ADDR_IS_CANONICAL(va), 4842 ("%s: Address not in canonical form: %lx", __func__, va)); 4843 4844 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags & 4845 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) { 4846 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p", 4847 va, pmap); 4848 return (KERN_RESOURCE_SHORTAGE); 4849 } 4850 4851 /* 4852 * If there are existing mappings, either abort or remove them. 4853 */ 4854 if ((old_l2 = pmap_load(l2)) != 0) { 4855 KASSERT(l2pg == NULL || l2pg->ref_count > 1, 4856 ("pmap_enter_l2: l2pg's ref count is too low")); 4857 if ((flags & PMAP_ENTER_NOREPLACE) != 0) { 4858 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK) { 4859 if (l2pg != NULL) 4860 l2pg->ref_count--; 4861 CTR2(KTR_PMAP, 4862 "pmap_enter_l2: no space for va %#lx" 4863 " in pmap %p", va, pmap); 4864 return (KERN_NO_SPACE); 4865 } else if (!ADDR_IS_KERNEL(va) || 4866 !pmap_every_pte_zero(PTE_TO_PHYS(old_l2))) { 4867 if (l2pg != NULL) 4868 l2pg->ref_count--; 4869 CTR2(KTR_PMAP, 4870 "pmap_enter_l2: failure for va %#lx" 4871 " in pmap %p", va, pmap); 4872 return (KERN_FAILURE); 4873 } 4874 } 4875 SLIST_INIT(&free); 4876 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK) 4877 (void)pmap_remove_l2(pmap, l2, va, 4878 pmap_load(pmap_l1(pmap, va)), &free, lockp); 4879 else 4880 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE, 4881 &free, lockp); 4882 if (!ADDR_IS_KERNEL(va)) { 4883 vm_page_free_pages_toq(&free, true); 4884 KASSERT(pmap_load(l2) == 0, 4885 ("pmap_enter_l2: non-zero L2 entry %p", l2)); 4886 } else { 4887 KASSERT(SLIST_EMPTY(&free), 4888 ("pmap_enter_l2: freed kernel page table page")); 4889 4890 /* 4891 * Both pmap_remove_l2() and pmap_remove_l3_range() 4892 * will leave the kernel page table page zero filled. 4893 * Nonetheless, the TLB could have an intermediate 4894 * entry for the kernel page table page, so request 4895 * an invalidation at all levels after clearing 4896 * the L2_TABLE entry. 4897 */ 4898 mt = PHYS_TO_VM_PAGE(PTE_TO_PHYS(pmap_load(l2))); 4899 if (pmap_insert_pt_page(pmap, mt, false, false)) 4900 panic("pmap_enter_l2: trie insert failed"); 4901 pmap_clear(l2); 4902 pmap_s1_invalidate_page(pmap, va, false); 4903 } 4904 } 4905 4906 /* 4907 * Allocate leaf ptpage for wired userspace pages. 4908 */ 4909 uwptpg = NULL; 4910 if ((new_l2 & ATTR_SW_WIRED) != 0 && pmap != kernel_pmap) { 4911 uwptpg = vm_page_alloc_noobj(VM_ALLOC_WIRED); 4912 if (uwptpg == NULL) { 4913 return (KERN_RESOURCE_SHORTAGE); 4914 } 4915 uwptpg->pindex = pmap_l2_pindex(va); 4916 if (pmap_insert_pt_page(pmap, uwptpg, true, false)) { 4917 vm_page_unwire_noq(uwptpg); 4918 vm_page_free(uwptpg); 4919 return (KERN_RESOURCE_SHORTAGE); 4920 } 4921 pmap_resident_count_inc(pmap, 1); 4922 uwptpg->ref_count = NL3PG; 4923 } 4924 if ((new_l2 & ATTR_SW_MANAGED) != 0) { 4925 /* 4926 * Abort this mapping if its PV entry could not be created. 4927 */ 4928 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) { 4929 if (l2pg != NULL) 4930 pmap_abort_ptp(pmap, va, l2pg); 4931 if (uwptpg != NULL) { 4932 mt = pmap_remove_pt_page(pmap, va); 4933 KASSERT(mt == uwptpg, 4934 ("removed pt page %p, expected %p", mt, 4935 uwptpg)); 4936 pmap_resident_count_dec(pmap, 1); 4937 uwptpg->ref_count = 1; 4938 vm_page_unwire_noq(uwptpg); 4939 vm_page_free(uwptpg); 4940 } 4941 CTR2(KTR_PMAP, 4942 "pmap_enter_l2: failure for va %#lx in pmap %p", 4943 va, pmap); 4944 return (KERN_RESOURCE_SHORTAGE); 4945 } 4946 if ((new_l2 & ATTR_SW_DBM) != 0) 4947 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) 4948 vm_page_aflag_set(mt, PGA_WRITEABLE); 4949 } 4950 4951 /* 4952 * Increment counters. 4953 */ 4954 if ((new_l2 & ATTR_SW_WIRED) != 0) 4955 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE; 4956 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE; 4957 4958 /* 4959 * Conditionally sync the icache. See pmap_enter() for details. 4960 */ 4961 if ((new_l2 & ATTR_S1_XN) == 0 && (PTE_TO_PHYS(new_l2) != 4962 PTE_TO_PHYS(old_l2) || (old_l2 & ATTR_S1_XN) != 0) && 4963 pmap != kernel_pmap && m->md.pv_memattr == VM_MEMATTR_WRITE_BACK) { 4964 cpu_icache_sync_range(PHYS_TO_DMAP(PTE_TO_PHYS(new_l2)), 4965 L2_SIZE); 4966 } 4967 4968 /* 4969 * Map the superpage. 4970 */ 4971 pmap_store(l2, new_l2); 4972 dsb(ishst); 4973 4974 atomic_add_long(&pmap_l2_mappings, 1); 4975 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p", 4976 va, pmap); 4977 4978 return (KERN_SUCCESS); 4979 } 4980 4981 /* 4982 * Maps a sequence of resident pages belonging to the same object. 4983 * The sequence begins with the given page m_start. This page is 4984 * mapped at the given virtual address start. Each subsequent page is 4985 * mapped at a virtual address that is offset from start by the same 4986 * amount as the page is offset from m_start within the object. The 4987 * last page in the sequence is the page with the largest offset from 4988 * m_start that can be mapped at a virtual address less than the given 4989 * virtual address end. Not every virtual page between start and end 4990 * is mapped; only those for which a resident page exists with the 4991 * corresponding offset from m_start are mapped. 4992 */ 4993 void 4994 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 4995 vm_page_t m_start, vm_prot_t prot) 4996 { 4997 struct rwlock *lock; 4998 vm_offset_t va; 4999 vm_page_t m, mpte; 5000 vm_pindex_t diff, psize; 5001 int rv; 5002 5003 VM_OBJECT_ASSERT_LOCKED(m_start->object); 5004 5005 psize = atop(end - start); 5006 mpte = NULL; 5007 m = m_start; 5008 lock = NULL; 5009 PMAP_LOCK(pmap); 5010 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 5011 va = start + ptoa(diff); 5012 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end && 5013 m->psind == 1 && pmap_ps_enabled(pmap) && 5014 ((rv = pmap_enter_2mpage(pmap, va, m, prot, &lock)) == 5015 KERN_SUCCESS || rv == KERN_NO_SPACE)) 5016 m = &m[L2_SIZE / PAGE_SIZE - 1]; 5017 else 5018 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, 5019 &lock); 5020 m = TAILQ_NEXT(m, listq); 5021 } 5022 if (lock != NULL) 5023 rw_wunlock(lock); 5024 PMAP_UNLOCK(pmap); 5025 } 5026 5027 /* 5028 * this code makes some *MAJOR* assumptions: 5029 * 1. Current pmap & pmap exists. 5030 * 2. Not wired. 5031 * 3. Read access. 5032 * 4. No page table pages. 5033 * but is *MUCH* faster than pmap_enter... 5034 */ 5035 5036 void 5037 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 5038 { 5039 struct rwlock *lock; 5040 5041 lock = NULL; 5042 PMAP_LOCK(pmap); 5043 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock); 5044 if (lock != NULL) 5045 rw_wunlock(lock); 5046 PMAP_UNLOCK(pmap); 5047 } 5048 5049 static vm_page_t 5050 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 5051 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp) 5052 { 5053 pd_entry_t *pde; 5054 pt_entry_t *l1, *l2, *l3, l3_val; 5055 vm_paddr_t pa; 5056 int lvl; 5057 5058 KASSERT(!VA_IS_CLEANMAP(va) || 5059 (m->oflags & VPO_UNMANAGED) != 0, 5060 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 5061 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 5062 PMAP_ASSERT_STAGE1(pmap); 5063 KASSERT(ADDR_IS_CANONICAL(va), 5064 ("%s: Address not in canonical form: %lx", __func__, va)); 5065 l2 = NULL; 5066 5067 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va); 5068 /* 5069 * In the case that a page table page is not 5070 * resident, we are creating it here. 5071 */ 5072 if (!ADDR_IS_KERNEL(va)) { 5073 vm_pindex_t l2pindex; 5074 5075 /* 5076 * Calculate pagetable page index 5077 */ 5078 l2pindex = pmap_l2_pindex(va); 5079 if (mpte && (mpte->pindex == l2pindex)) { 5080 mpte->ref_count++; 5081 } else { 5082 /* 5083 * If the page table page is mapped, we just increment 5084 * the hold count, and activate it. Otherwise, we 5085 * attempt to allocate a page table page, passing NULL 5086 * instead of the PV list lock pointer because we don't 5087 * intend to sleep. If this attempt fails, we don't 5088 * retry. Instead, we give up. 5089 */ 5090 l1 = pmap_l1(pmap, va); 5091 if (l1 != NULL && pmap_load(l1) != 0) { 5092 if ((pmap_load(l1) & ATTR_DESCR_MASK) == 5093 L1_BLOCK) 5094 return (NULL); 5095 l2 = pmap_l1_to_l2(l1, va); 5096 if (pmap_load(l2) != 0) { 5097 if ((pmap_load(l2) & ATTR_DESCR_MASK) == 5098 L2_BLOCK) 5099 return (NULL); 5100 mpte = PHYS_TO_VM_PAGE( 5101 PTE_TO_PHYS(pmap_load(l2))); 5102 mpte->ref_count++; 5103 } else { 5104 mpte = _pmap_alloc_l3(pmap, l2pindex, 5105 NULL); 5106 if (mpte == NULL) 5107 return (mpte); 5108 } 5109 } else { 5110 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL); 5111 if (mpte == NULL) 5112 return (mpte); 5113 } 5114 } 5115 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte)); 5116 l3 = &l3[pmap_l3_index(va)]; 5117 } else { 5118 mpte = NULL; 5119 pde = pmap_pde(kernel_pmap, va, &lvl); 5120 KASSERT(pde != NULL, 5121 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx", 5122 va)); 5123 KASSERT(lvl == 2, 5124 ("pmap_enter_quick_locked: Invalid level %d", lvl)); 5125 l3 = pmap_l2_to_l3(pde, va); 5126 } 5127 5128 /* 5129 * Abort if a mapping already exists. 5130 */ 5131 if (pmap_load(l3) != 0) { 5132 if (mpte != NULL) 5133 mpte->ref_count--; 5134 return (NULL); 5135 } 5136 5137 /* 5138 * Enter on the PV list if part of our managed memory. 5139 */ 5140 if ((m->oflags & VPO_UNMANAGED) == 0 && 5141 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) { 5142 if (mpte != NULL) 5143 pmap_abort_ptp(pmap, va, mpte); 5144 return (NULL); 5145 } 5146 5147 /* 5148 * Increment counters 5149 */ 5150 pmap_resident_count_inc(pmap, 1); 5151 5152 pa = VM_PAGE_TO_PHYS(m); 5153 l3_val = PHYS_TO_PTE(pa) | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) | 5154 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE; 5155 l3_val |= pmap_pte_bti(pmap, va); 5156 if ((prot & VM_PROT_EXECUTE) == 0 || 5157 m->md.pv_memattr == VM_MEMATTR_DEVICE) 5158 l3_val |= ATTR_S1_XN; 5159 if (!ADDR_IS_KERNEL(va)) 5160 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN; 5161 else 5162 l3_val |= ATTR_S1_UXN; 5163 if (pmap != kernel_pmap) 5164 l3_val |= ATTR_S1_nG; 5165 5166 /* 5167 * Now validate mapping with RO protection 5168 */ 5169 if ((m->oflags & VPO_UNMANAGED) == 0) { 5170 l3_val |= ATTR_SW_MANAGED; 5171 l3_val &= ~ATTR_AF; 5172 } 5173 5174 /* Sync icache before the mapping is stored to PTE */ 5175 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap && 5176 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK) 5177 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE); 5178 5179 pmap_store(l3, l3_val); 5180 dsb(ishst); 5181 5182 #if VM_NRESERVLEVEL > 0 5183 /* 5184 * If both the PTP and the reservation are fully populated, then 5185 * attempt promotion. 5186 */ 5187 if ((mpte == NULL || mpte->ref_count == NL3PG) && 5188 (m->flags & PG_FICTITIOUS) == 0 && 5189 vm_reserv_level_iffullpop(m) == 0) { 5190 if (l2 == NULL) 5191 l2 = pmap_pde(pmap, va, &lvl); 5192 5193 /* 5194 * If promotion succeeds, then the next call to this function 5195 * should not be given the unmapped PTP as a hint. 5196 */ 5197 if (pmap_promote_l2(pmap, l2, va, mpte, lockp)) 5198 mpte = NULL; 5199 } 5200 #endif 5201 5202 return (mpte); 5203 } 5204 5205 /* 5206 * This code maps large physical mmap regions into the 5207 * processor address space. Note that some shortcuts 5208 * are taken, but the code works. 5209 */ 5210 void 5211 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 5212 vm_pindex_t pindex, vm_size_t size) 5213 { 5214 5215 VM_OBJECT_ASSERT_WLOCKED(object); 5216 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 5217 ("pmap_object_init_pt: non-device object")); 5218 } 5219 5220 /* 5221 * Clear the wired attribute from the mappings for the specified range of 5222 * addresses in the given pmap. Every valid mapping within that range 5223 * must have the wired attribute set. In contrast, invalid mappings 5224 * cannot have the wired attribute set, so they are ignored. 5225 * 5226 * The wired attribute of the page table entry is not a hardware feature, 5227 * so there is no need to invalidate any TLB entries. 5228 */ 5229 void 5230 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 5231 { 5232 vm_offset_t va_next; 5233 pd_entry_t *l0, *l1, *l2; 5234 pt_entry_t *l3; 5235 5236 PMAP_LOCK(pmap); 5237 for (; sva < eva; sva = va_next) { 5238 l0 = pmap_l0(pmap, sva); 5239 if (pmap_load(l0) == 0) { 5240 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 5241 if (va_next < sva) 5242 va_next = eva; 5243 continue; 5244 } 5245 5246 l1 = pmap_l0_to_l1(l0, sva); 5247 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 5248 if (va_next < sva) 5249 va_next = eva; 5250 if (pmap_load(l1) == 0) 5251 continue; 5252 5253 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) { 5254 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 5255 KASSERT(va_next <= eva, 5256 ("partial update of non-transparent 1G page " 5257 "l1 %#lx sva %#lx eva %#lx va_next %#lx", 5258 pmap_load(l1), sva, eva, va_next)); 5259 MPASS(pmap != kernel_pmap); 5260 MPASS((pmap_load(l1) & (ATTR_SW_MANAGED | 5261 ATTR_SW_WIRED)) == ATTR_SW_WIRED); 5262 pmap_clear_bits(l1, ATTR_SW_WIRED); 5263 pmap->pm_stats.wired_count -= L1_SIZE / PAGE_SIZE; 5264 continue; 5265 } 5266 5267 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 5268 if (va_next < sva) 5269 va_next = eva; 5270 5271 l2 = pmap_l1_to_l2(l1, sva); 5272 if (pmap_load(l2) == 0) 5273 continue; 5274 5275 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) { 5276 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0) 5277 panic("pmap_unwire: l2 %#jx is missing " 5278 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2)); 5279 5280 /* 5281 * Are we unwiring the entire large page? If not, 5282 * demote the mapping and fall through. 5283 */ 5284 if (sva + L2_SIZE == va_next && eva >= va_next) { 5285 pmap_clear_bits(l2, ATTR_SW_WIRED); 5286 pmap->pm_stats.wired_count -= L2_SIZE / 5287 PAGE_SIZE; 5288 continue; 5289 } else if (pmap_demote_l2(pmap, l2, sva) == NULL) 5290 panic("pmap_unwire: demotion failed"); 5291 } 5292 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE, 5293 ("pmap_unwire: Invalid l2 entry after demotion")); 5294 5295 if (va_next > eva) 5296 va_next = eva; 5297 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++, 5298 sva += L3_SIZE) { 5299 if (pmap_load(l3) == 0) 5300 continue; 5301 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0) 5302 panic("pmap_unwire: l3 %#jx is missing " 5303 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3)); 5304 5305 /* 5306 * ATTR_SW_WIRED must be cleared atomically. Although 5307 * the pmap lock synchronizes access to ATTR_SW_WIRED, 5308 * the System MMU may write to the entry concurrently. 5309 */ 5310 pmap_clear_bits(l3, ATTR_SW_WIRED); 5311 pmap->pm_stats.wired_count--; 5312 } 5313 } 5314 PMAP_UNLOCK(pmap); 5315 } 5316 5317 /* 5318 * Copy the range specified by src_addr/len 5319 * from the source map to the range dst_addr/len 5320 * in the destination map. 5321 * 5322 * This routine is only advisory and need not do anything. 5323 * 5324 * Because the executable mappings created by this routine are copied, 5325 * it should not have to flush the instruction cache. 5326 */ 5327 void 5328 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 5329 vm_offset_t src_addr) 5330 { 5331 struct rwlock *lock; 5332 pd_entry_t *l0, *l1, *l2, srcptepaddr; 5333 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte; 5334 vm_offset_t addr, end_addr, va_next; 5335 vm_page_t dst_m, dstmpte, srcmpte; 5336 5337 PMAP_ASSERT_STAGE1(dst_pmap); 5338 PMAP_ASSERT_STAGE1(src_pmap); 5339 5340 if (dst_addr != src_addr) 5341 return; 5342 end_addr = src_addr + len; 5343 lock = NULL; 5344 if (dst_pmap < src_pmap) { 5345 PMAP_LOCK(dst_pmap); 5346 PMAP_LOCK(src_pmap); 5347 } else { 5348 PMAP_LOCK(src_pmap); 5349 PMAP_LOCK(dst_pmap); 5350 } 5351 for (addr = src_addr; addr < end_addr; addr = va_next) { 5352 l0 = pmap_l0(src_pmap, addr); 5353 if (pmap_load(l0) == 0) { 5354 va_next = (addr + L0_SIZE) & ~L0_OFFSET; 5355 if (va_next < addr) 5356 va_next = end_addr; 5357 continue; 5358 } 5359 5360 va_next = (addr + L1_SIZE) & ~L1_OFFSET; 5361 if (va_next < addr) 5362 va_next = end_addr; 5363 l1 = pmap_l0_to_l1(l0, addr); 5364 if (pmap_load(l1) == 0) 5365 continue; 5366 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) { 5367 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 5368 KASSERT(va_next <= end_addr, 5369 ("partial update of non-transparent 1G page " 5370 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx", 5371 pmap_load(l1), addr, end_addr, va_next)); 5372 srcptepaddr = pmap_load(l1); 5373 l1 = pmap_l1(dst_pmap, addr); 5374 if (l1 == NULL) { 5375 if (_pmap_alloc_l3(dst_pmap, 5376 pmap_l0_pindex(addr), NULL) == NULL) 5377 break; 5378 l1 = pmap_l1(dst_pmap, addr); 5379 } else { 5380 l0 = pmap_l0(dst_pmap, addr); 5381 dst_m = PHYS_TO_VM_PAGE( 5382 PTE_TO_PHYS(pmap_load(l0))); 5383 dst_m->ref_count++; 5384 } 5385 KASSERT(pmap_load(l1) == 0, 5386 ("1G mapping present in dst pmap " 5387 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx", 5388 pmap_load(l1), addr, end_addr, va_next)); 5389 pmap_store(l1, srcptepaddr & ~ATTR_SW_WIRED); 5390 pmap_resident_count_inc(dst_pmap, L1_SIZE / PAGE_SIZE); 5391 continue; 5392 } 5393 5394 va_next = (addr + L2_SIZE) & ~L2_OFFSET; 5395 if (va_next < addr) 5396 va_next = end_addr; 5397 l2 = pmap_l1_to_l2(l1, addr); 5398 srcptepaddr = pmap_load(l2); 5399 if (srcptepaddr == 0) 5400 continue; 5401 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) { 5402 /* 5403 * We can only virtual copy whole superpages. 5404 */ 5405 if ((addr & L2_OFFSET) != 0 || 5406 addr + L2_SIZE > end_addr) 5407 continue; 5408 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_m, NULL); 5409 if (l2 == NULL) 5410 break; 5411 if (pmap_load(l2) == 0 && 5412 ((srcptepaddr & ATTR_SW_MANAGED) == 0 || 5413 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr, 5414 PMAP_ENTER_NORECLAIM, &lock))) { 5415 /* 5416 * We leave the dirty bit unchanged because 5417 * managed read/write superpage mappings are 5418 * required to be dirty. However, managed 5419 * superpage mappings are not required to 5420 * have their accessed bit set, so we clear 5421 * it because we don't know if this mapping 5422 * will be used. 5423 */ 5424 srcptepaddr &= ~ATTR_SW_WIRED; 5425 if ((srcptepaddr & ATTR_SW_MANAGED) != 0) 5426 srcptepaddr &= ~ATTR_AF; 5427 pmap_store(l2, srcptepaddr); 5428 pmap_resident_count_inc(dst_pmap, L2_SIZE / 5429 PAGE_SIZE); 5430 atomic_add_long(&pmap_l2_mappings, 1); 5431 } else 5432 pmap_abort_ptp(dst_pmap, addr, dst_m); 5433 continue; 5434 } 5435 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE, 5436 ("pmap_copy: invalid L2 entry")); 5437 srcmpte = PHYS_TO_VM_PAGE(PTE_TO_PHYS(srcptepaddr)); 5438 KASSERT(srcmpte->ref_count > 0, 5439 ("pmap_copy: source page table page is unused")); 5440 if (va_next > end_addr) 5441 va_next = end_addr; 5442 src_pte = (pt_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(srcptepaddr)); 5443 src_pte = &src_pte[pmap_l3_index(addr)]; 5444 dstmpte = NULL; 5445 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) { 5446 ptetemp = pmap_load(src_pte); 5447 5448 /* 5449 * We only virtual copy managed pages. 5450 */ 5451 if ((ptetemp & ATTR_SW_MANAGED) == 0) 5452 continue; 5453 5454 if (dstmpte != NULL) { 5455 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr), 5456 ("dstmpte pindex/addr mismatch")); 5457 dstmpte->ref_count++; 5458 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr, 5459 NULL)) == NULL) 5460 goto out; 5461 dst_pte = (pt_entry_t *) 5462 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte)); 5463 dst_pte = &dst_pte[pmap_l3_index(addr)]; 5464 if (pmap_load(dst_pte) == 0 && 5465 pmap_try_insert_pv_entry(dst_pmap, addr, 5466 PHYS_TO_VM_PAGE(PTE_TO_PHYS(ptetemp)), &lock)) { 5467 /* 5468 * Clear the wired, modified, and accessed 5469 * (referenced) bits during the copy. 5470 */ 5471 mask = ATTR_AF | ATTR_SW_WIRED; 5472 nbits = 0; 5473 if ((ptetemp & ATTR_SW_DBM) != 0) 5474 nbits |= ATTR_S1_AP_RW_BIT; 5475 pmap_store(dst_pte, (ptetemp & ~mask) | nbits); 5476 pmap_resident_count_inc(dst_pmap, 1); 5477 } else { 5478 pmap_abort_ptp(dst_pmap, addr, dstmpte); 5479 goto out; 5480 } 5481 /* Have we copied all of the valid mappings? */ 5482 if (dstmpte->ref_count >= srcmpte->ref_count) 5483 break; 5484 } 5485 } 5486 out: 5487 /* 5488 * XXX This barrier may not be needed because the destination pmap is 5489 * not active. 5490 */ 5491 dsb(ishst); 5492 5493 if (lock != NULL) 5494 rw_wunlock(lock); 5495 PMAP_UNLOCK(src_pmap); 5496 PMAP_UNLOCK(dst_pmap); 5497 } 5498 5499 /* 5500 * pmap_zero_page zeros the specified hardware page by mapping 5501 * the page into KVM and using bzero to clear its contents. 5502 */ 5503 void 5504 pmap_zero_page(vm_page_t m) 5505 { 5506 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 5507 5508 pagezero((void *)va); 5509 } 5510 5511 /* 5512 * pmap_zero_page_area zeros the specified hardware page by mapping 5513 * the page into KVM and using bzero to clear its contents. 5514 * 5515 * off and size may not cover an area beyond a single hardware page. 5516 */ 5517 void 5518 pmap_zero_page_area(vm_page_t m, int off, int size) 5519 { 5520 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 5521 5522 if (off == 0 && size == PAGE_SIZE) 5523 pagezero((void *)va); 5524 else 5525 bzero((char *)va + off, size); 5526 } 5527 5528 /* 5529 * pmap_copy_page copies the specified (machine independent) 5530 * page by mapping the page into virtual memory and using 5531 * bcopy to copy the page, one machine dependent page at a 5532 * time. 5533 */ 5534 void 5535 pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 5536 { 5537 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc)); 5538 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst)); 5539 5540 pagecopy((void *)src, (void *)dst); 5541 } 5542 5543 int unmapped_buf_allowed = 1; 5544 5545 void 5546 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 5547 vm_offset_t b_offset, int xfersize) 5548 { 5549 void *a_cp, *b_cp; 5550 vm_page_t m_a, m_b; 5551 vm_paddr_t p_a, p_b; 5552 vm_offset_t a_pg_offset, b_pg_offset; 5553 int cnt; 5554 5555 while (xfersize > 0) { 5556 a_pg_offset = a_offset & PAGE_MASK; 5557 m_a = ma[a_offset >> PAGE_SHIFT]; 5558 p_a = m_a->phys_addr; 5559 b_pg_offset = b_offset & PAGE_MASK; 5560 m_b = mb[b_offset >> PAGE_SHIFT]; 5561 p_b = m_b->phys_addr; 5562 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 5563 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 5564 if (__predict_false(!PHYS_IN_DMAP(p_a))) { 5565 panic("!DMAP a %lx", p_a); 5566 } else { 5567 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset; 5568 } 5569 if (__predict_false(!PHYS_IN_DMAP(p_b))) { 5570 panic("!DMAP b %lx", p_b); 5571 } else { 5572 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset; 5573 } 5574 bcopy(a_cp, b_cp, cnt); 5575 a_offset += cnt; 5576 b_offset += cnt; 5577 xfersize -= cnt; 5578 } 5579 } 5580 5581 vm_offset_t 5582 pmap_quick_enter_page(vm_page_t m) 5583 { 5584 5585 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m))); 5586 } 5587 5588 void 5589 pmap_quick_remove_page(vm_offset_t addr) 5590 { 5591 } 5592 5593 /* 5594 * Returns true if the pmap's pv is one of the first 5595 * 16 pvs linked to from this page. This count may 5596 * be changed upwards or downwards in the future; it 5597 * is only necessary that true be returned for a small 5598 * subset of pmaps for proper page aging. 5599 */ 5600 bool 5601 pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 5602 { 5603 struct md_page *pvh; 5604 struct rwlock *lock; 5605 pv_entry_t pv; 5606 int loops = 0; 5607 bool rv; 5608 5609 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5610 ("pmap_page_exists_quick: page %p is not managed", m)); 5611 rv = false; 5612 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5613 rw_rlock(lock); 5614 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5615 if (PV_PMAP(pv) == pmap) { 5616 rv = true; 5617 break; 5618 } 5619 loops++; 5620 if (loops >= 16) 5621 break; 5622 } 5623 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) { 5624 pvh = page_to_pvh(m); 5625 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 5626 if (PV_PMAP(pv) == pmap) { 5627 rv = true; 5628 break; 5629 } 5630 loops++; 5631 if (loops >= 16) 5632 break; 5633 } 5634 } 5635 rw_runlock(lock); 5636 return (rv); 5637 } 5638 5639 /* 5640 * pmap_page_wired_mappings: 5641 * 5642 * Return the number of managed mappings to the given physical page 5643 * that are wired. 5644 */ 5645 int 5646 pmap_page_wired_mappings(vm_page_t m) 5647 { 5648 struct rwlock *lock; 5649 struct md_page *pvh; 5650 pmap_t pmap; 5651 pt_entry_t *pte; 5652 pv_entry_t pv; 5653 int count, md_gen, pvh_gen; 5654 5655 if ((m->oflags & VPO_UNMANAGED) != 0) 5656 return (0); 5657 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5658 rw_rlock(lock); 5659 restart: 5660 count = 0; 5661 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5662 pmap = PV_PMAP(pv); 5663 if (!PMAP_TRYLOCK(pmap)) { 5664 md_gen = m->md.pv_gen; 5665 rw_runlock(lock); 5666 PMAP_LOCK(pmap); 5667 rw_rlock(lock); 5668 if (md_gen != m->md.pv_gen) { 5669 PMAP_UNLOCK(pmap); 5670 goto restart; 5671 } 5672 } 5673 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__); 5674 if ((pmap_load(pte) & ATTR_SW_WIRED) != 0) 5675 count++; 5676 PMAP_UNLOCK(pmap); 5677 } 5678 if ((m->flags & PG_FICTITIOUS) == 0) { 5679 pvh = page_to_pvh(m); 5680 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 5681 pmap = PV_PMAP(pv); 5682 if (!PMAP_TRYLOCK(pmap)) { 5683 md_gen = m->md.pv_gen; 5684 pvh_gen = pvh->pv_gen; 5685 rw_runlock(lock); 5686 PMAP_LOCK(pmap); 5687 rw_rlock(lock); 5688 if (md_gen != m->md.pv_gen || 5689 pvh_gen != pvh->pv_gen) { 5690 PMAP_UNLOCK(pmap); 5691 goto restart; 5692 } 5693 } 5694 pte = pmap_pte_exists(pmap, pv->pv_va, 2, __func__); 5695 if ((pmap_load(pte) & ATTR_SW_WIRED) != 0) 5696 count++; 5697 PMAP_UNLOCK(pmap); 5698 } 5699 } 5700 rw_runlock(lock); 5701 return (count); 5702 } 5703 5704 /* 5705 * Returns true if the given page is mapped individually or as part of 5706 * a 2mpage. Otherwise, returns false. 5707 */ 5708 bool 5709 pmap_page_is_mapped(vm_page_t m) 5710 { 5711 struct rwlock *lock; 5712 bool rv; 5713 5714 if ((m->oflags & VPO_UNMANAGED) != 0) 5715 return (false); 5716 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5717 rw_rlock(lock); 5718 rv = !TAILQ_EMPTY(&m->md.pv_list) || 5719 ((m->flags & PG_FICTITIOUS) == 0 && 5720 !TAILQ_EMPTY(&page_to_pvh(m)->pv_list)); 5721 rw_runlock(lock); 5722 return (rv); 5723 } 5724 5725 /* 5726 * Destroy all managed, non-wired mappings in the given user-space 5727 * pmap. This pmap cannot be active on any processor besides the 5728 * caller. 5729 * 5730 * This function cannot be applied to the kernel pmap. Moreover, it 5731 * is not intended for general use. It is only to be used during 5732 * process termination. Consequently, it can be implemented in ways 5733 * that make it faster than pmap_remove(). First, it can more quickly 5734 * destroy mappings by iterating over the pmap's collection of PV 5735 * entries, rather than searching the page table. Second, it doesn't 5736 * have to test and clear the page table entries atomically, because 5737 * no processor is currently accessing the user address space. In 5738 * particular, a page table entry's dirty bit won't change state once 5739 * this function starts. 5740 */ 5741 void 5742 pmap_remove_pages(pmap_t pmap) 5743 { 5744 pd_entry_t *pde; 5745 pt_entry_t *pte, tpte; 5746 struct spglist free; 5747 struct pv_chunklist free_chunks[PMAP_MEMDOM]; 5748 vm_page_t m, ml3, mt; 5749 pv_entry_t pv; 5750 struct md_page *pvh; 5751 struct pv_chunk *pc, *npc; 5752 struct rwlock *lock; 5753 int64_t bit; 5754 uint64_t inuse, bitmask; 5755 int allfree, field, i, idx, lvl; 5756 int freed __pvused; 5757 vm_paddr_t pa; 5758 5759 lock = NULL; 5760 5761 for (i = 0; i < PMAP_MEMDOM; i++) 5762 TAILQ_INIT(&free_chunks[i]); 5763 SLIST_INIT(&free); 5764 PMAP_LOCK(pmap); 5765 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 5766 allfree = 1; 5767 freed = 0; 5768 for (field = 0; field < _NPCM; field++) { 5769 inuse = ~pc->pc_map[field] & pc_freemask[field]; 5770 while (inuse != 0) { 5771 bit = ffsl(inuse) - 1; 5772 bitmask = 1UL << bit; 5773 idx = field * 64 + bit; 5774 pv = &pc->pc_pventry[idx]; 5775 inuse &= ~bitmask; 5776 5777 pde = pmap_pde(pmap, pv->pv_va, &lvl); 5778 KASSERT(pde != NULL, 5779 ("Attempting to remove an unmapped page")); 5780 5781 switch(lvl) { 5782 case 1: 5783 pte = pmap_l1_to_l2(pde, pv->pv_va); 5784 tpte = pmap_load(pte); 5785 KASSERT((tpte & ATTR_DESCR_MASK) == 5786 L2_BLOCK, 5787 ("Attempting to remove an invalid " 5788 "block: %lx", tpte)); 5789 break; 5790 case 2: 5791 pte = pmap_l2_to_l3(pde, pv->pv_va); 5792 tpte = pmap_load(pte); 5793 KASSERT((tpte & ATTR_DESCR_MASK) == 5794 L3_PAGE, 5795 ("Attempting to remove an invalid " 5796 "page: %lx", tpte)); 5797 break; 5798 default: 5799 panic( 5800 "Invalid page directory level: %d", 5801 lvl); 5802 } 5803 5804 /* 5805 * We cannot remove wired pages from a process' mapping at this time 5806 */ 5807 if (tpte & ATTR_SW_WIRED) { 5808 allfree = 0; 5809 continue; 5810 } 5811 5812 /* Mark free */ 5813 pc->pc_map[field] |= bitmask; 5814 5815 /* 5816 * Because this pmap is not active on other 5817 * processors, the dirty bit cannot have 5818 * changed state since we last loaded pte. 5819 */ 5820 pmap_clear(pte); 5821 5822 pa = PTE_TO_PHYS(tpte); 5823 5824 m = PHYS_TO_VM_PAGE(pa); 5825 KASSERT(m->phys_addr == pa, 5826 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 5827 m, (uintmax_t)m->phys_addr, 5828 (uintmax_t)tpte)); 5829 5830 KASSERT((m->flags & PG_FICTITIOUS) != 0 || 5831 m < &vm_page_array[vm_page_array_size], 5832 ("pmap_remove_pages: bad pte %#jx", 5833 (uintmax_t)tpte)); 5834 5835 /* 5836 * Update the vm_page_t clean/reference bits. 5837 */ 5838 if (pmap_pte_dirty(pmap, tpte)) { 5839 switch (lvl) { 5840 case 1: 5841 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) 5842 vm_page_dirty(mt); 5843 break; 5844 case 2: 5845 vm_page_dirty(m); 5846 break; 5847 } 5848 } 5849 5850 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m); 5851 5852 switch (lvl) { 5853 case 1: 5854 pmap_resident_count_dec(pmap, 5855 L2_SIZE / PAGE_SIZE); 5856 pvh = page_to_pvh(m); 5857 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next); 5858 pvh->pv_gen++; 5859 if (TAILQ_EMPTY(&pvh->pv_list)) { 5860 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) 5861 if ((mt->a.flags & PGA_WRITEABLE) != 0 && 5862 TAILQ_EMPTY(&mt->md.pv_list)) 5863 vm_page_aflag_clear(mt, PGA_WRITEABLE); 5864 } 5865 ml3 = pmap_remove_pt_page(pmap, 5866 pv->pv_va); 5867 if (ml3 != NULL) { 5868 KASSERT(vm_page_any_valid(ml3), 5869 ("pmap_remove_pages: l3 page not promoted")); 5870 pmap_resident_count_dec(pmap,1); 5871 KASSERT(ml3->ref_count == NL3PG, 5872 ("pmap_remove_pages: l3 page ref count error")); 5873 ml3->ref_count = 0; 5874 pmap_add_delayed_free_list(ml3, 5875 &free, false); 5876 } 5877 break; 5878 case 2: 5879 pmap_resident_count_dec(pmap, 1); 5880 TAILQ_REMOVE(&m->md.pv_list, pv, 5881 pv_next); 5882 m->md.pv_gen++; 5883 if ((m->a.flags & PGA_WRITEABLE) != 0 && 5884 TAILQ_EMPTY(&m->md.pv_list) && 5885 (m->flags & PG_FICTITIOUS) == 0) { 5886 pvh = page_to_pvh(m); 5887 if (TAILQ_EMPTY(&pvh->pv_list)) 5888 vm_page_aflag_clear(m, 5889 PGA_WRITEABLE); 5890 } 5891 break; 5892 } 5893 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde), 5894 &free); 5895 freed++; 5896 } 5897 } 5898 PV_STAT(atomic_add_long(&pv_entry_frees, freed)); 5899 PV_STAT(atomic_add_int(&pv_entry_spare, freed)); 5900 PV_STAT(atomic_subtract_long(&pv_entry_count, freed)); 5901 if (allfree) { 5902 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 5903 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, 5904 pc_list); 5905 } 5906 } 5907 if (lock != NULL) 5908 rw_wunlock(lock); 5909 pmap_invalidate_all(pmap); 5910 free_pv_chunk_batch(free_chunks); 5911 PMAP_UNLOCK(pmap); 5912 vm_page_free_pages_toq(&free, true); 5913 } 5914 5915 /* 5916 * This is used to check if a page has been accessed or modified. 5917 */ 5918 static bool 5919 pmap_page_test_mappings(vm_page_t m, bool accessed, bool modified) 5920 { 5921 struct rwlock *lock; 5922 pv_entry_t pv; 5923 struct md_page *pvh; 5924 pt_entry_t *pte, mask, value; 5925 pmap_t pmap; 5926 int md_gen, pvh_gen; 5927 bool rv; 5928 5929 rv = false; 5930 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5931 rw_rlock(lock); 5932 restart: 5933 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5934 pmap = PV_PMAP(pv); 5935 PMAP_ASSERT_STAGE1(pmap); 5936 if (!PMAP_TRYLOCK(pmap)) { 5937 md_gen = m->md.pv_gen; 5938 rw_runlock(lock); 5939 PMAP_LOCK(pmap); 5940 rw_rlock(lock); 5941 if (md_gen != m->md.pv_gen) { 5942 PMAP_UNLOCK(pmap); 5943 goto restart; 5944 } 5945 } 5946 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__); 5947 mask = 0; 5948 value = 0; 5949 if (modified) { 5950 mask |= ATTR_S1_AP_RW_BIT; 5951 value |= ATTR_S1_AP(ATTR_S1_AP_RW); 5952 } 5953 if (accessed) { 5954 mask |= ATTR_AF | ATTR_DESCR_MASK; 5955 value |= ATTR_AF | L3_PAGE; 5956 } 5957 rv = (pmap_load(pte) & mask) == value; 5958 PMAP_UNLOCK(pmap); 5959 if (rv) 5960 goto out; 5961 } 5962 if ((m->flags & PG_FICTITIOUS) == 0) { 5963 pvh = page_to_pvh(m); 5964 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 5965 pmap = PV_PMAP(pv); 5966 PMAP_ASSERT_STAGE1(pmap); 5967 if (!PMAP_TRYLOCK(pmap)) { 5968 md_gen = m->md.pv_gen; 5969 pvh_gen = pvh->pv_gen; 5970 rw_runlock(lock); 5971 PMAP_LOCK(pmap); 5972 rw_rlock(lock); 5973 if (md_gen != m->md.pv_gen || 5974 pvh_gen != pvh->pv_gen) { 5975 PMAP_UNLOCK(pmap); 5976 goto restart; 5977 } 5978 } 5979 pte = pmap_pte_exists(pmap, pv->pv_va, 2, __func__); 5980 mask = 0; 5981 value = 0; 5982 if (modified) { 5983 mask |= ATTR_S1_AP_RW_BIT; 5984 value |= ATTR_S1_AP(ATTR_S1_AP_RW); 5985 } 5986 if (accessed) { 5987 mask |= ATTR_AF | ATTR_DESCR_MASK; 5988 value |= ATTR_AF | L2_BLOCK; 5989 } 5990 rv = (pmap_load(pte) & mask) == value; 5991 PMAP_UNLOCK(pmap); 5992 if (rv) 5993 goto out; 5994 } 5995 } 5996 out: 5997 rw_runlock(lock); 5998 return (rv); 5999 } 6000 6001 /* 6002 * pmap_is_modified: 6003 * 6004 * Return whether or not the specified physical page was modified 6005 * in any physical maps. 6006 */ 6007 bool 6008 pmap_is_modified(vm_page_t m) 6009 { 6010 6011 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 6012 ("pmap_is_modified: page %p is not managed", m)); 6013 6014 /* 6015 * If the page is not busied then this check is racy. 6016 */ 6017 if (!pmap_page_is_write_mapped(m)) 6018 return (false); 6019 return (pmap_page_test_mappings(m, false, true)); 6020 } 6021 6022 /* 6023 * pmap_is_prefaultable: 6024 * 6025 * Return whether or not the specified virtual address is eligible 6026 * for prefault. 6027 */ 6028 bool 6029 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 6030 { 6031 pd_entry_t *pde; 6032 pt_entry_t *pte; 6033 bool rv; 6034 int lvl; 6035 6036 /* 6037 * Return true if and only if the L3 entry for the specified virtual 6038 * address is allocated but invalid. 6039 */ 6040 rv = false; 6041 PMAP_LOCK(pmap); 6042 pde = pmap_pde(pmap, addr, &lvl); 6043 if (pde != NULL && lvl == 2) { 6044 pte = pmap_l2_to_l3(pde, addr); 6045 rv = pmap_load(pte) == 0; 6046 } 6047 PMAP_UNLOCK(pmap); 6048 return (rv); 6049 } 6050 6051 /* 6052 * pmap_is_referenced: 6053 * 6054 * Return whether or not the specified physical page was referenced 6055 * in any physical maps. 6056 */ 6057 bool 6058 pmap_is_referenced(vm_page_t m) 6059 { 6060 6061 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 6062 ("pmap_is_referenced: page %p is not managed", m)); 6063 return (pmap_page_test_mappings(m, true, false)); 6064 } 6065 6066 /* 6067 * Clear the write and modified bits in each of the given page's mappings. 6068 */ 6069 void 6070 pmap_remove_write(vm_page_t m) 6071 { 6072 struct md_page *pvh; 6073 pmap_t pmap; 6074 struct rwlock *lock; 6075 pv_entry_t next_pv, pv; 6076 pt_entry_t oldpte, *pte, set, clear, mask, val; 6077 vm_offset_t va; 6078 int md_gen, pvh_gen; 6079 6080 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 6081 ("pmap_remove_write: page %p is not managed", m)); 6082 vm_page_assert_busied(m); 6083 6084 if (!pmap_page_is_write_mapped(m)) 6085 return; 6086 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 6087 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m); 6088 rw_wlock(lock); 6089 retry: 6090 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 6091 pmap = PV_PMAP(pv); 6092 PMAP_ASSERT_STAGE1(pmap); 6093 if (!PMAP_TRYLOCK(pmap)) { 6094 pvh_gen = pvh->pv_gen; 6095 rw_wunlock(lock); 6096 PMAP_LOCK(pmap); 6097 rw_wlock(lock); 6098 if (pvh_gen != pvh->pv_gen) { 6099 PMAP_UNLOCK(pmap); 6100 goto retry; 6101 } 6102 } 6103 va = pv->pv_va; 6104 pte = pmap_pte_exists(pmap, va, 2, __func__); 6105 if ((pmap_load(pte) & ATTR_SW_DBM) != 0) 6106 (void)pmap_demote_l2_locked(pmap, pte, va, &lock); 6107 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 6108 ("inconsistent pv lock %p %p for page %p", 6109 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 6110 PMAP_UNLOCK(pmap); 6111 } 6112 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 6113 pmap = PV_PMAP(pv); 6114 if (!PMAP_TRYLOCK(pmap)) { 6115 pvh_gen = pvh->pv_gen; 6116 md_gen = m->md.pv_gen; 6117 rw_wunlock(lock); 6118 PMAP_LOCK(pmap); 6119 rw_wlock(lock); 6120 if (pvh_gen != pvh->pv_gen || 6121 md_gen != m->md.pv_gen) { 6122 PMAP_UNLOCK(pmap); 6123 goto retry; 6124 } 6125 } 6126 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__); 6127 oldpte = pmap_load(pte); 6128 if ((oldpte & ATTR_SW_DBM) != 0) { 6129 if (pmap->pm_stage == PM_STAGE1) { 6130 set = ATTR_S1_AP_RW_BIT; 6131 clear = 0; 6132 mask = ATTR_S1_AP_RW_BIT; 6133 val = ATTR_S1_AP(ATTR_S1_AP_RW); 6134 } else { 6135 set = 0; 6136 clear = ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE); 6137 mask = ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE); 6138 val = ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE); 6139 } 6140 clear |= ATTR_SW_DBM; 6141 while (!atomic_fcmpset_64(pte, &oldpte, 6142 (oldpte | set) & ~clear)) 6143 cpu_spinwait(); 6144 6145 if ((oldpte & mask) == val) 6146 vm_page_dirty(m); 6147 pmap_invalidate_page(pmap, pv->pv_va, true); 6148 } 6149 PMAP_UNLOCK(pmap); 6150 } 6151 rw_wunlock(lock); 6152 vm_page_aflag_clear(m, PGA_WRITEABLE); 6153 } 6154 6155 /* 6156 * pmap_ts_referenced: 6157 * 6158 * Return a count of reference bits for a page, clearing those bits. 6159 * It is not necessary for every reference bit to be cleared, but it 6160 * is necessary that 0 only be returned when there are truly no 6161 * reference bits set. 6162 * 6163 * As an optimization, update the page's dirty field if a modified bit is 6164 * found while counting reference bits. This opportunistic update can be 6165 * performed at low cost and can eliminate the need for some future calls 6166 * to pmap_is_modified(). However, since this function stops after 6167 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 6168 * dirty pages. Those dirty pages will only be detected by a future call 6169 * to pmap_is_modified(). 6170 */ 6171 int 6172 pmap_ts_referenced(vm_page_t m) 6173 { 6174 struct md_page *pvh; 6175 pv_entry_t pv, pvf; 6176 pmap_t pmap; 6177 struct rwlock *lock; 6178 pt_entry_t *pte, tpte; 6179 vm_offset_t va; 6180 vm_paddr_t pa; 6181 int cleared, md_gen, not_cleared, pvh_gen; 6182 struct spglist free; 6183 6184 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 6185 ("pmap_ts_referenced: page %p is not managed", m)); 6186 SLIST_INIT(&free); 6187 cleared = 0; 6188 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m); 6189 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 6190 rw_wlock(lock); 6191 retry: 6192 not_cleared = 0; 6193 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL) 6194 goto small_mappings; 6195 pv = pvf; 6196 do { 6197 if (pvf == NULL) 6198 pvf = pv; 6199 pmap = PV_PMAP(pv); 6200 if (!PMAP_TRYLOCK(pmap)) { 6201 pvh_gen = pvh->pv_gen; 6202 rw_wunlock(lock); 6203 PMAP_LOCK(pmap); 6204 rw_wlock(lock); 6205 if (pvh_gen != pvh->pv_gen) { 6206 PMAP_UNLOCK(pmap); 6207 goto retry; 6208 } 6209 } 6210 va = pv->pv_va; 6211 pte = pmap_pte_exists(pmap, va, 2, __func__); 6212 tpte = pmap_load(pte); 6213 if (pmap_pte_dirty(pmap, tpte)) { 6214 /* 6215 * Although "tpte" is mapping a 2MB page, because 6216 * this function is called at a 4KB page granularity, 6217 * we only update the 4KB page under test. 6218 */ 6219 vm_page_dirty(m); 6220 } 6221 if ((tpte & ATTR_AF) != 0) { 6222 pa = VM_PAGE_TO_PHYS(m); 6223 6224 /* 6225 * Since this reference bit is shared by 512 4KB pages, 6226 * it should not be cleared every time it is tested. 6227 * Apply a simple "hash" function on the physical page 6228 * number, the virtual superpage number, and the pmap 6229 * address to select one 4KB page out of the 512 on 6230 * which testing the reference bit will result in 6231 * clearing that reference bit. This function is 6232 * designed to avoid the selection of the same 4KB page 6233 * for every 2MB page mapping. 6234 * 6235 * On demotion, a mapping that hasn't been referenced 6236 * is simply destroyed. To avoid the possibility of a 6237 * subsequent page fault on a demoted wired mapping, 6238 * always leave its reference bit set. Moreover, 6239 * since the superpage is wired, the current state of 6240 * its reference bit won't affect page replacement. 6241 */ 6242 if ((((pa >> PAGE_SHIFT) ^ (va >> L2_SHIFT) ^ 6243 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 && 6244 (tpte & ATTR_SW_WIRED) == 0) { 6245 pmap_clear_bits(pte, ATTR_AF); 6246 pmap_invalidate_page(pmap, va, true); 6247 cleared++; 6248 } else 6249 not_cleared++; 6250 } 6251 PMAP_UNLOCK(pmap); 6252 /* Rotate the PV list if it has more than one entry. */ 6253 if (TAILQ_NEXT(pv, pv_next) != NULL) { 6254 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 6255 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 6256 pvh->pv_gen++; 6257 } 6258 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX) 6259 goto out; 6260 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf); 6261 small_mappings: 6262 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL) 6263 goto out; 6264 pv = pvf; 6265 do { 6266 if (pvf == NULL) 6267 pvf = pv; 6268 pmap = PV_PMAP(pv); 6269 if (!PMAP_TRYLOCK(pmap)) { 6270 pvh_gen = pvh->pv_gen; 6271 md_gen = m->md.pv_gen; 6272 rw_wunlock(lock); 6273 PMAP_LOCK(pmap); 6274 rw_wlock(lock); 6275 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 6276 PMAP_UNLOCK(pmap); 6277 goto retry; 6278 } 6279 } 6280 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__); 6281 tpte = pmap_load(pte); 6282 if (pmap_pte_dirty(pmap, tpte)) 6283 vm_page_dirty(m); 6284 if ((tpte & ATTR_AF) != 0) { 6285 if ((tpte & ATTR_SW_WIRED) == 0) { 6286 pmap_clear_bits(pte, ATTR_AF); 6287 pmap_invalidate_page(pmap, pv->pv_va, true); 6288 cleared++; 6289 } else 6290 not_cleared++; 6291 } 6292 PMAP_UNLOCK(pmap); 6293 /* Rotate the PV list if it has more than one entry. */ 6294 if (TAILQ_NEXT(pv, pv_next) != NULL) { 6295 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 6296 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 6297 m->md.pv_gen++; 6298 } 6299 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared + 6300 not_cleared < PMAP_TS_REFERENCED_MAX); 6301 out: 6302 rw_wunlock(lock); 6303 vm_page_free_pages_toq(&free, true); 6304 return (cleared + not_cleared); 6305 } 6306 6307 /* 6308 * Apply the given advice to the specified range of addresses within the 6309 * given pmap. Depending on the advice, clear the referenced and/or 6310 * modified flags in each mapping and set the mapped page's dirty field. 6311 */ 6312 void 6313 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 6314 { 6315 struct rwlock *lock; 6316 vm_offset_t va, va_next; 6317 vm_page_t m; 6318 pd_entry_t *l0, *l1, *l2, oldl2; 6319 pt_entry_t *l3, oldl3; 6320 6321 PMAP_ASSERT_STAGE1(pmap); 6322 6323 if (advice != MADV_DONTNEED && advice != MADV_FREE) 6324 return; 6325 6326 PMAP_LOCK(pmap); 6327 for (; sva < eva; sva = va_next) { 6328 l0 = pmap_l0(pmap, sva); 6329 if (pmap_load(l0) == 0) { 6330 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 6331 if (va_next < sva) 6332 va_next = eva; 6333 continue; 6334 } 6335 6336 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 6337 if (va_next < sva) 6338 va_next = eva; 6339 l1 = pmap_l0_to_l1(l0, sva); 6340 if (pmap_load(l1) == 0) 6341 continue; 6342 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) { 6343 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 6344 continue; 6345 } 6346 6347 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 6348 if (va_next < sva) 6349 va_next = eva; 6350 l2 = pmap_l1_to_l2(l1, sva); 6351 oldl2 = pmap_load(l2); 6352 if (oldl2 == 0) 6353 continue; 6354 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) { 6355 if ((oldl2 & ATTR_SW_MANAGED) == 0) 6356 continue; 6357 lock = NULL; 6358 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) { 6359 if (lock != NULL) 6360 rw_wunlock(lock); 6361 6362 /* 6363 * The 2MB page mapping was destroyed. 6364 */ 6365 continue; 6366 } 6367 6368 /* 6369 * Unless the page mappings are wired, remove the 6370 * mapping to a single page so that a subsequent 6371 * access may repromote. Choosing the last page 6372 * within the address range [sva, min(va_next, eva)) 6373 * generally results in more repromotions. Since the 6374 * underlying page table page is fully populated, this 6375 * removal never frees a page table page. 6376 */ 6377 if ((oldl2 & ATTR_SW_WIRED) == 0) { 6378 va = eva; 6379 if (va > va_next) 6380 va = va_next; 6381 va -= PAGE_SIZE; 6382 KASSERT(va >= sva, 6383 ("pmap_advise: no address gap")); 6384 l3 = pmap_l2_to_l3(l2, va); 6385 KASSERT(pmap_load(l3) != 0, 6386 ("pmap_advise: invalid PTE")); 6387 pmap_remove_l3(pmap, l3, va, pmap_load(l2), 6388 NULL, &lock); 6389 } 6390 if (lock != NULL) 6391 rw_wunlock(lock); 6392 } 6393 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE, 6394 ("pmap_advise: invalid L2 entry after demotion")); 6395 if (va_next > eva) 6396 va_next = eva; 6397 va = va_next; 6398 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++, 6399 sva += L3_SIZE) { 6400 oldl3 = pmap_load(l3); 6401 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) != 6402 (ATTR_SW_MANAGED | L3_PAGE)) 6403 goto maybe_invlrng; 6404 else if (pmap_pte_dirty(pmap, oldl3)) { 6405 if (advice == MADV_DONTNEED) { 6406 /* 6407 * Future calls to pmap_is_modified() 6408 * can be avoided by making the page 6409 * dirty now. 6410 */ 6411 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(oldl3)); 6412 vm_page_dirty(m); 6413 } 6414 while (!atomic_fcmpset_long(l3, &oldl3, 6415 (oldl3 & ~ATTR_AF) | 6416 ATTR_S1_AP(ATTR_S1_AP_RO))) 6417 cpu_spinwait(); 6418 } else if ((oldl3 & ATTR_AF) != 0) 6419 pmap_clear_bits(l3, ATTR_AF); 6420 else 6421 goto maybe_invlrng; 6422 if (va == va_next) 6423 va = sva; 6424 continue; 6425 maybe_invlrng: 6426 if (va != va_next) { 6427 pmap_s1_invalidate_range(pmap, va, sva, true); 6428 va = va_next; 6429 } 6430 } 6431 if (va != va_next) 6432 pmap_s1_invalidate_range(pmap, va, sva, true); 6433 } 6434 PMAP_UNLOCK(pmap); 6435 } 6436 6437 /* 6438 * Clear the modify bits on the specified physical page. 6439 */ 6440 void 6441 pmap_clear_modify(vm_page_t m) 6442 { 6443 struct md_page *pvh; 6444 struct rwlock *lock; 6445 pmap_t pmap; 6446 pv_entry_t next_pv, pv; 6447 pd_entry_t *l2, oldl2; 6448 pt_entry_t *l3, oldl3; 6449 vm_offset_t va; 6450 int md_gen, pvh_gen; 6451 6452 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 6453 ("pmap_clear_modify: page %p is not managed", m)); 6454 vm_page_assert_busied(m); 6455 6456 if (!pmap_page_is_write_mapped(m)) 6457 return; 6458 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m); 6459 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 6460 rw_wlock(lock); 6461 restart: 6462 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 6463 pmap = PV_PMAP(pv); 6464 PMAP_ASSERT_STAGE1(pmap); 6465 if (!PMAP_TRYLOCK(pmap)) { 6466 pvh_gen = pvh->pv_gen; 6467 rw_wunlock(lock); 6468 PMAP_LOCK(pmap); 6469 rw_wlock(lock); 6470 if (pvh_gen != pvh->pv_gen) { 6471 PMAP_UNLOCK(pmap); 6472 goto restart; 6473 } 6474 } 6475 va = pv->pv_va; 6476 l2 = pmap_l2(pmap, va); 6477 oldl2 = pmap_load(l2); 6478 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */ 6479 if ((oldl2 & ATTR_SW_DBM) != 0 && 6480 pmap_demote_l2_locked(pmap, l2, va, &lock) && 6481 (oldl2 & ATTR_SW_WIRED) == 0) { 6482 /* 6483 * Write protect the mapping to a single page so that 6484 * a subsequent write access may repromote. 6485 */ 6486 va += VM_PAGE_TO_PHYS(m) - PTE_TO_PHYS(oldl2); 6487 l3 = pmap_l2_to_l3(l2, va); 6488 oldl3 = pmap_load(l3); 6489 while (!atomic_fcmpset_long(l3, &oldl3, 6490 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO))) 6491 cpu_spinwait(); 6492 vm_page_dirty(m); 6493 pmap_s1_invalidate_page(pmap, va, true); 6494 } 6495 PMAP_UNLOCK(pmap); 6496 } 6497 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 6498 pmap = PV_PMAP(pv); 6499 PMAP_ASSERT_STAGE1(pmap); 6500 if (!PMAP_TRYLOCK(pmap)) { 6501 md_gen = m->md.pv_gen; 6502 pvh_gen = pvh->pv_gen; 6503 rw_wunlock(lock); 6504 PMAP_LOCK(pmap); 6505 rw_wlock(lock); 6506 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 6507 PMAP_UNLOCK(pmap); 6508 goto restart; 6509 } 6510 } 6511 l2 = pmap_l2(pmap, pv->pv_va); 6512 l3 = pmap_l2_to_l3(l2, pv->pv_va); 6513 oldl3 = pmap_load(l3); 6514 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){ 6515 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO)); 6516 pmap_s1_invalidate_page(pmap, pv->pv_va, true); 6517 } 6518 PMAP_UNLOCK(pmap); 6519 } 6520 rw_wunlock(lock); 6521 } 6522 6523 void * 6524 pmap_mapbios(vm_paddr_t pa, vm_size_t size) 6525 { 6526 struct pmap_preinit_mapping *ppim; 6527 vm_offset_t va, offset; 6528 pd_entry_t old_l2e, *pde; 6529 pt_entry_t *l2; 6530 int i, lvl, l2_blocks, free_l2_count, start_idx; 6531 6532 if (!vm_initialized) { 6533 /* 6534 * No L3 ptables so map entire L2 blocks where start VA is: 6535 * preinit_map_va + start_idx * L2_SIZE 6536 * There may be duplicate mappings (multiple VA -> same PA) but 6537 * ARM64 dcache is always PIPT so that's acceptable. 6538 */ 6539 if (size == 0) 6540 return (NULL); 6541 6542 /* Calculate how many L2 blocks are needed for the mapping */ 6543 l2_blocks = (roundup2(pa + size, L2_SIZE) - 6544 rounddown2(pa, L2_SIZE)) >> L2_SHIFT; 6545 6546 offset = pa & L2_OFFSET; 6547 6548 if (preinit_map_va == 0) 6549 return (NULL); 6550 6551 /* Map 2MiB L2 blocks from reserved VA space */ 6552 6553 free_l2_count = 0; 6554 start_idx = -1; 6555 /* Find enough free contiguous VA space */ 6556 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 6557 ppim = pmap_preinit_mapping + i; 6558 if (free_l2_count > 0 && ppim->pa != 0) { 6559 /* Not enough space here */ 6560 free_l2_count = 0; 6561 start_idx = -1; 6562 continue; 6563 } 6564 6565 if (ppim->pa == 0) { 6566 /* Free L2 block */ 6567 if (start_idx == -1) 6568 start_idx = i; 6569 free_l2_count++; 6570 if (free_l2_count == l2_blocks) 6571 break; 6572 } 6573 } 6574 if (free_l2_count != l2_blocks) 6575 panic("%s: too many preinit mappings", __func__); 6576 6577 va = preinit_map_va + (start_idx * L2_SIZE); 6578 for (i = start_idx; i < start_idx + l2_blocks; i++) { 6579 /* Mark entries as allocated */ 6580 ppim = pmap_preinit_mapping + i; 6581 ppim->pa = pa; 6582 ppim->va = va + offset; 6583 ppim->size = size; 6584 } 6585 6586 /* Map L2 blocks */ 6587 pa = rounddown2(pa, L2_SIZE); 6588 old_l2e = 0; 6589 for (i = 0; i < l2_blocks; i++) { 6590 pde = pmap_pde(kernel_pmap, va, &lvl); 6591 KASSERT(pde != NULL, 6592 ("pmap_mapbios: Invalid page entry, va: 0x%lx", 6593 va)); 6594 KASSERT(lvl == 1, 6595 ("pmap_mapbios: Invalid level %d", lvl)); 6596 6597 /* Insert L2_BLOCK */ 6598 l2 = pmap_l1_to_l2(pde, va); 6599 old_l2e |= pmap_load_store(l2, 6600 PHYS_TO_PTE(pa) | ATTR_DEFAULT | ATTR_S1_XN | 6601 ATTR_KERN_GP | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | 6602 L2_BLOCK); 6603 6604 va += L2_SIZE; 6605 pa += L2_SIZE; 6606 } 6607 if ((old_l2e & ATTR_DESCR_VALID) != 0) 6608 pmap_s1_invalidate_all(kernel_pmap); 6609 else { 6610 /* 6611 * Because the old entries were invalid and the new 6612 * mappings are not executable, an isb is not required. 6613 */ 6614 dsb(ishst); 6615 } 6616 6617 va = preinit_map_va + (start_idx * L2_SIZE); 6618 6619 } else { 6620 /* kva_alloc may be used to map the pages */ 6621 offset = pa & PAGE_MASK; 6622 size = round_page(offset + size); 6623 6624 va = kva_alloc(size); 6625 if (va == 0) 6626 panic("%s: Couldn't allocate KVA", __func__); 6627 6628 pde = pmap_pde(kernel_pmap, va, &lvl); 6629 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl)); 6630 6631 /* L3 table is linked */ 6632 va = trunc_page(va); 6633 pa = trunc_page(pa); 6634 pmap_kenter(va, size, pa, memory_mapping_mode(pa)); 6635 } 6636 6637 return ((void *)(va + offset)); 6638 } 6639 6640 void 6641 pmap_unmapbios(void *p, vm_size_t size) 6642 { 6643 struct pmap_preinit_mapping *ppim; 6644 vm_offset_t offset, va, va_trunc; 6645 pd_entry_t *pde; 6646 pt_entry_t *l2; 6647 int i, lvl, l2_blocks, block; 6648 bool preinit_map; 6649 6650 va = (vm_offset_t)p; 6651 l2_blocks = 6652 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT; 6653 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size)); 6654 6655 /* Remove preinit mapping */ 6656 preinit_map = false; 6657 block = 0; 6658 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 6659 ppim = pmap_preinit_mapping + i; 6660 if (ppim->va == va) { 6661 KASSERT(ppim->size == size, 6662 ("pmap_unmapbios: size mismatch")); 6663 ppim->va = 0; 6664 ppim->pa = 0; 6665 ppim->size = 0; 6666 preinit_map = true; 6667 offset = block * L2_SIZE; 6668 va_trunc = rounddown2(va, L2_SIZE) + offset; 6669 6670 /* Remove L2_BLOCK */ 6671 pde = pmap_pde(kernel_pmap, va_trunc, &lvl); 6672 KASSERT(pde != NULL, 6673 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", 6674 va_trunc)); 6675 l2 = pmap_l1_to_l2(pde, va_trunc); 6676 pmap_clear(l2); 6677 6678 if (block == (l2_blocks - 1)) 6679 break; 6680 block++; 6681 } 6682 } 6683 if (preinit_map) { 6684 pmap_s1_invalidate_all(kernel_pmap); 6685 return; 6686 } 6687 6688 /* Unmap the pages reserved with kva_alloc. */ 6689 if (vm_initialized) { 6690 offset = va & PAGE_MASK; 6691 size = round_page(offset + size); 6692 va = trunc_page(va); 6693 6694 /* Unmap and invalidate the pages */ 6695 pmap_kremove_device(va, size); 6696 6697 kva_free(va, size); 6698 } 6699 } 6700 6701 /* 6702 * Sets the memory attribute for the specified page. 6703 */ 6704 void 6705 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 6706 { 6707 6708 m->md.pv_memattr = ma; 6709 6710 /* 6711 * If "m" is a normal page, update its direct mapping. This update 6712 * can be relied upon to perform any cache operations that are 6713 * required for data coherence. 6714 */ 6715 if ((m->flags & PG_FICTITIOUS) == 0 && 6716 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE, 6717 m->md.pv_memattr) != 0) 6718 panic("memory attribute change on the direct map failed"); 6719 } 6720 6721 /* 6722 * Changes the specified virtual address range's memory type to that given by 6723 * the parameter "mode". The specified virtual address range must be 6724 * completely contained within either the direct map or the kernel map. If 6725 * the virtual address range is contained within the kernel map, then the 6726 * memory type for each of the corresponding ranges of the direct map is also 6727 * changed. (The corresponding ranges of the direct map are those ranges that 6728 * map the same physical pages as the specified virtual address range.) These 6729 * changes to the direct map are necessary because Intel describes the 6730 * behavior of their processors as "undefined" if two or more mappings to the 6731 * same physical page have different memory types. 6732 * 6733 * Returns zero if the change completed successfully, and either EINVAL or 6734 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 6735 * of the virtual address range was not mapped, and ENOMEM is returned if 6736 * there was insufficient memory available to complete the change. In the 6737 * latter case, the memory type may have been changed on some part of the 6738 * virtual address range or the direct map. 6739 */ 6740 int 6741 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 6742 { 6743 int error; 6744 6745 PMAP_LOCK(kernel_pmap); 6746 error = pmap_change_props_locked(va, size, PROT_NONE, mode, false); 6747 PMAP_UNLOCK(kernel_pmap); 6748 return (error); 6749 } 6750 6751 /* 6752 * Changes the specified virtual address range's protections to those 6753 * specified by "prot". Like pmap_change_attr(), protections for aliases 6754 * in the direct map are updated as well. Protections on aliasing mappings may 6755 * be a subset of the requested protections; for example, mappings in the direct 6756 * map are never executable. 6757 */ 6758 int 6759 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot) 6760 { 6761 int error; 6762 6763 /* Only supported within the kernel map. */ 6764 if (va < VM_MIN_KERNEL_ADDRESS) 6765 return (EINVAL); 6766 6767 PMAP_LOCK(kernel_pmap); 6768 error = pmap_change_props_locked(va, size, prot, -1, false); 6769 PMAP_UNLOCK(kernel_pmap); 6770 return (error); 6771 } 6772 6773 static int 6774 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot, 6775 int mode, bool skip_unmapped) 6776 { 6777 vm_offset_t base, offset, tmpva; 6778 vm_size_t pte_size; 6779 vm_paddr_t pa; 6780 pt_entry_t pte, *ptep, *newpte; 6781 pt_entry_t bits, mask; 6782 int lvl, rv; 6783 6784 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED); 6785 base = trunc_page(va); 6786 offset = va & PAGE_MASK; 6787 size = round_page(offset + size); 6788 6789 if (!VIRT_IN_DMAP(base) && 6790 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS)) 6791 return (EINVAL); 6792 6793 bits = 0; 6794 mask = 0; 6795 if (mode != -1) { 6796 bits = ATTR_S1_IDX(mode); 6797 mask = ATTR_S1_IDX_MASK; 6798 if (mode == VM_MEMATTR_DEVICE) { 6799 mask |= ATTR_S1_XN; 6800 bits |= ATTR_S1_XN; 6801 } 6802 } 6803 if (prot != VM_PROT_NONE) { 6804 /* Don't mark the DMAP as executable. It never is on arm64. */ 6805 if (VIRT_IN_DMAP(base)) { 6806 prot &= ~VM_PROT_EXECUTE; 6807 /* 6808 * XXX Mark the DMAP as writable for now. We rely 6809 * on this in ddb & dtrace to insert breakpoint 6810 * instructions. 6811 */ 6812 prot |= VM_PROT_WRITE; 6813 } 6814 6815 if ((prot & VM_PROT_WRITE) == 0) { 6816 bits |= ATTR_S1_AP(ATTR_S1_AP_RO); 6817 } 6818 if ((prot & VM_PROT_EXECUTE) == 0) { 6819 bits |= ATTR_S1_PXN; 6820 } 6821 bits |= ATTR_S1_UXN; 6822 mask |= ATTR_S1_AP_MASK | ATTR_S1_XN; 6823 } 6824 6825 for (tmpva = base; tmpva < base + size; ) { 6826 ptep = pmap_pte(kernel_pmap, tmpva, &lvl); 6827 if (ptep == NULL && !skip_unmapped) { 6828 return (EINVAL); 6829 } else if ((ptep == NULL && skip_unmapped) || 6830 (pmap_load(ptep) & mask) == bits) { 6831 /* 6832 * We already have the correct attribute or there 6833 * is no memory mapped at this address and we are 6834 * skipping unmapped memory. 6835 */ 6836 switch (lvl) { 6837 default: 6838 panic("Invalid DMAP table level: %d\n", lvl); 6839 case 1: 6840 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE; 6841 break; 6842 case 2: 6843 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE; 6844 break; 6845 case 3: 6846 tmpva += PAGE_SIZE; 6847 break; 6848 } 6849 } else { 6850 /* We can't demote/promote this entry */ 6851 MPASS((pmap_load(ptep) & ATTR_SW_NO_PROMOTE) == 0); 6852 6853 /* 6854 * Split the entry to an level 3 table, then 6855 * set the new attribute. 6856 */ 6857 switch (lvl) { 6858 default: 6859 panic("Invalid DMAP table level: %d\n", lvl); 6860 case 1: 6861 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 6862 if ((tmpva & L1_OFFSET) == 0 && 6863 (base + size - tmpva) >= L1_SIZE) { 6864 pte_size = L1_SIZE; 6865 break; 6866 } 6867 newpte = pmap_demote_l1(kernel_pmap, ptep, 6868 tmpva & ~L1_OFFSET); 6869 if (newpte == NULL) 6870 return (EINVAL); 6871 ptep = pmap_l1_to_l2(ptep, tmpva); 6872 /* FALLTHROUGH */ 6873 case 2: 6874 if ((tmpva & L2_OFFSET) == 0 && 6875 (base + size - tmpva) >= L2_SIZE) { 6876 pte_size = L2_SIZE; 6877 break; 6878 } 6879 newpte = pmap_demote_l2(kernel_pmap, ptep, 6880 tmpva); 6881 if (newpte == NULL) 6882 return (EINVAL); 6883 ptep = pmap_l2_to_l3(ptep, tmpva); 6884 /* FALLTHROUGH */ 6885 case 3: 6886 pte_size = PAGE_SIZE; 6887 break; 6888 } 6889 6890 /* Update the entry */ 6891 pte = pmap_load(ptep); 6892 pte &= ~mask; 6893 pte |= bits; 6894 6895 pmap_update_entry(kernel_pmap, ptep, pte, tmpva, 6896 pte_size); 6897 6898 pa = PTE_TO_PHYS(pte); 6899 if (!VIRT_IN_DMAP(tmpva) && PHYS_IN_DMAP(pa)) { 6900 /* 6901 * Keep the DMAP memory in sync. 6902 */ 6903 rv = pmap_change_props_locked( 6904 PHYS_TO_DMAP(pa), pte_size, 6905 prot, mode, true); 6906 if (rv != 0) 6907 return (rv); 6908 } 6909 6910 /* 6911 * If moving to a non-cacheable entry flush 6912 * the cache. 6913 */ 6914 if (mode == VM_MEMATTR_UNCACHEABLE) 6915 cpu_dcache_wbinv_range(tmpva, pte_size); 6916 tmpva += pte_size; 6917 } 6918 } 6919 6920 return (0); 6921 } 6922 6923 /* 6924 * Create an L2 table to map all addresses within an L1 mapping. 6925 */ 6926 static pt_entry_t * 6927 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va) 6928 { 6929 pt_entry_t *l2, newl2, oldl1; 6930 vm_offset_t tmpl1; 6931 vm_paddr_t l2phys, phys; 6932 vm_page_t ml2; 6933 int i; 6934 6935 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 6936 oldl1 = pmap_load(l1); 6937 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 6938 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK, 6939 ("pmap_demote_l1: Demoting a non-block entry")); 6940 KASSERT((va & L1_OFFSET) == 0, 6941 ("pmap_demote_l1: Invalid virtual address %#lx", va)); 6942 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0, 6943 ("pmap_demote_l1: Level 1 table shouldn't be managed")); 6944 KASSERT((oldl1 & ATTR_SW_NO_PROMOTE) == 0, 6945 ("pmap_demote_l1: Demoting entry with no-demote flag set")); 6946 6947 tmpl1 = 0; 6948 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) { 6949 tmpl1 = kva_alloc(PAGE_SIZE); 6950 if (tmpl1 == 0) 6951 return (NULL); 6952 } 6953 6954 if ((ml2 = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED)) == 6955 NULL) { 6956 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx" 6957 " in pmap %p", va, pmap); 6958 l2 = NULL; 6959 goto fail; 6960 } 6961 6962 l2phys = VM_PAGE_TO_PHYS(ml2); 6963 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys); 6964 6965 /* Address the range points at */ 6966 phys = PTE_TO_PHYS(oldl1); 6967 /* The attributed from the old l1 table to be copied */ 6968 newl2 = oldl1 & ATTR_MASK; 6969 6970 /* Create the new entries */ 6971 for (i = 0; i < Ln_ENTRIES; i++) { 6972 l2[i] = newl2 | phys; 6973 phys += L2_SIZE; 6974 } 6975 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK), 6976 ("Invalid l2 page (%lx != %lx)", l2[0], 6977 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK)); 6978 6979 if (tmpl1 != 0) { 6980 pmap_kenter(tmpl1, PAGE_SIZE, 6981 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, 6982 VM_MEMATTR_WRITE_BACK); 6983 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK)); 6984 } 6985 6986 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE); 6987 6988 fail: 6989 if (tmpl1 != 0) { 6990 pmap_kremove(tmpl1); 6991 kva_free(tmpl1, PAGE_SIZE); 6992 } 6993 6994 return (l2); 6995 } 6996 6997 static void 6998 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3) 6999 { 7000 pt_entry_t *l3; 7001 7002 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) { 7003 *l3 = newl3; 7004 newl3 += L3_SIZE; 7005 } 7006 } 7007 7008 static void 7009 pmap_demote_l2_check(pt_entry_t *firstl3p __unused, pt_entry_t newl3e __unused) 7010 { 7011 #ifdef INVARIANTS 7012 #ifdef DIAGNOSTIC 7013 pt_entry_t *xl3p, *yl3p; 7014 7015 for (xl3p = firstl3p; xl3p < firstl3p + Ln_ENTRIES; 7016 xl3p++, newl3e += PAGE_SIZE) { 7017 if (PTE_TO_PHYS(pmap_load(xl3p)) != PTE_TO_PHYS(newl3e)) { 7018 printf("pmap_demote_l2: xl3e %zd and newl3e map " 7019 "different pages: found %#lx, expected %#lx\n", 7020 xl3p - firstl3p, pmap_load(xl3p), newl3e); 7021 printf("page table dump\n"); 7022 for (yl3p = firstl3p; yl3p < firstl3p + Ln_ENTRIES; 7023 yl3p++) { 7024 printf("%zd %#lx\n", yl3p - firstl3p, 7025 pmap_load(yl3p)); 7026 } 7027 panic("firstpte"); 7028 } 7029 } 7030 #else 7031 KASSERT(PTE_TO_PHYS(pmap_load(firstl3p)) == PTE_TO_PHYS(newl3e), 7032 ("pmap_demote_l2: firstl3 and newl3e map different physical" 7033 " addresses")); 7034 #endif 7035 #endif 7036 } 7037 7038 static void 7039 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2, 7040 struct rwlock **lockp) 7041 { 7042 struct spglist free; 7043 7044 SLIST_INIT(&free); 7045 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free, 7046 lockp); 7047 vm_page_free_pages_toq(&free, true); 7048 } 7049 7050 /* 7051 * Create an L3 table to map all addresses within an L2 mapping. 7052 */ 7053 static pt_entry_t * 7054 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va, 7055 struct rwlock **lockp) 7056 { 7057 pt_entry_t *l3, newl3, oldl2; 7058 vm_offset_t tmpl2; 7059 vm_paddr_t l3phys; 7060 vm_page_t ml3; 7061 7062 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 7063 PMAP_ASSERT_STAGE1(pmap); 7064 KASSERT(ADDR_IS_CANONICAL(va), 7065 ("%s: Address not in canonical form: %lx", __func__, va)); 7066 7067 l3 = NULL; 7068 oldl2 = pmap_load(l2); 7069 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK, 7070 ("pmap_demote_l2: Demoting a non-block entry")); 7071 KASSERT((oldl2 & ATTR_SW_NO_PROMOTE) == 0, 7072 ("pmap_demote_l2: Demoting entry with no-demote flag set")); 7073 va &= ~L2_OFFSET; 7074 7075 tmpl2 = 0; 7076 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) { 7077 tmpl2 = kva_alloc(PAGE_SIZE); 7078 if (tmpl2 == 0) 7079 return (NULL); 7080 } 7081 7082 /* 7083 * Invalidate the 2MB page mapping and return "failure" if the 7084 * mapping was never accessed. 7085 */ 7086 if ((oldl2 & ATTR_AF) == 0) { 7087 KASSERT((oldl2 & ATTR_SW_WIRED) == 0, 7088 ("pmap_demote_l2: a wired mapping is missing ATTR_AF")); 7089 pmap_demote_l2_abort(pmap, va, l2, lockp); 7090 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p", 7091 va, pmap); 7092 goto fail; 7093 } 7094 7095 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) { 7096 KASSERT((oldl2 & ATTR_SW_WIRED) == 0, 7097 ("pmap_demote_l2: page table page for a wired mapping" 7098 " is missing")); 7099 7100 /* 7101 * If the page table page is missing and the mapping 7102 * is for a kernel address, the mapping must belong to 7103 * either the direct map or the early kernel memory. 7104 * Page table pages are preallocated for every other 7105 * part of the kernel address space, so the direct map 7106 * region and early kernel memory are the only parts of the 7107 * kernel address space that must be handled here. 7108 */ 7109 KASSERT(!ADDR_IS_KERNEL(va) || VIRT_IN_DMAP(va) || 7110 (va >= VM_MIN_KERNEL_ADDRESS && va < kernel_vm_end), 7111 ("pmap_demote_l2: No saved mpte for va %#lx", va)); 7112 7113 /* 7114 * If the 2MB page mapping belongs to the direct map 7115 * region of the kernel's address space, then the page 7116 * allocation request specifies the highest possible 7117 * priority (VM_ALLOC_INTERRUPT). Otherwise, the 7118 * priority is normal. 7119 */ 7120 ml3 = vm_page_alloc_noobj( 7121 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : 0) | 7122 VM_ALLOC_WIRED); 7123 7124 /* 7125 * If the allocation of the new page table page fails, 7126 * invalidate the 2MB page mapping and return "failure". 7127 */ 7128 if (ml3 == NULL) { 7129 pmap_demote_l2_abort(pmap, va, l2, lockp); 7130 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx" 7131 " in pmap %p", va, pmap); 7132 goto fail; 7133 } 7134 ml3->pindex = pmap_l2_pindex(va); 7135 7136 if (!ADDR_IS_KERNEL(va)) { 7137 ml3->ref_count = NL3PG; 7138 pmap_resident_count_inc(pmap, 1); 7139 } 7140 } 7141 l3phys = VM_PAGE_TO_PHYS(ml3); 7142 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys); 7143 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE; 7144 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 7145 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM), 7146 ("pmap_demote_l2: L2 entry is writeable but not dirty")); 7147 7148 /* 7149 * If the PTP is not leftover from an earlier promotion or it does not 7150 * have ATTR_AF set in every L3E, then fill it. The new L3Es will all 7151 * have ATTR_AF set. 7152 * 7153 * When pmap_update_entry() clears the old L2 mapping, it (indirectly) 7154 * performs a dsb(). That dsb() ensures that the stores for filling 7155 * "l3" are visible before "l3" is added to the page table. 7156 */ 7157 if (!vm_page_all_valid(ml3)) 7158 pmap_fill_l3(l3, newl3); 7159 7160 pmap_demote_l2_check(l3, newl3); 7161 7162 /* 7163 * If the mapping has changed attributes, update the L3Es. 7164 */ 7165 if ((pmap_load(l3) & (ATTR_MASK & ~ATTR_AF)) != (newl3 & (ATTR_MASK & 7166 ~ATTR_AF))) 7167 pmap_fill_l3(l3, newl3); 7168 7169 /* 7170 * Map the temporary page so we don't lose access to the l2 table. 7171 */ 7172 if (tmpl2 != 0) { 7173 pmap_kenter(tmpl2, PAGE_SIZE, 7174 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, 7175 VM_MEMATTR_WRITE_BACK); 7176 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK)); 7177 } 7178 7179 /* 7180 * The spare PV entries must be reserved prior to demoting the 7181 * mapping, that is, prior to changing the PDE. Otherwise, the state 7182 * of the L2 and the PV lists will be inconsistent, which can result 7183 * in reclaim_pv_chunk() attempting to remove a PV entry from the 7184 * wrong PV list and pmap_pv_demote_l2() failing to find the expected 7185 * PV entry for the 2MB page mapping that is being demoted. 7186 */ 7187 if ((oldl2 & ATTR_SW_MANAGED) != 0) 7188 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp); 7189 7190 /* 7191 * Pass PAGE_SIZE so that a single TLB invalidation is performed on 7192 * the 2MB page mapping. 7193 */ 7194 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE); 7195 7196 /* 7197 * Demote the PV entry. 7198 */ 7199 if ((oldl2 & ATTR_SW_MANAGED) != 0) 7200 pmap_pv_demote_l2(pmap, va, PTE_TO_PHYS(oldl2), lockp); 7201 7202 atomic_add_long(&pmap_l2_demotions, 1); 7203 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx" 7204 " in pmap %p %lx", va, pmap, l3[0]); 7205 7206 fail: 7207 if (tmpl2 != 0) { 7208 pmap_kremove(tmpl2); 7209 kva_free(tmpl2, PAGE_SIZE); 7210 } 7211 7212 return (l3); 7213 7214 } 7215 7216 static pt_entry_t * 7217 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va) 7218 { 7219 struct rwlock *lock; 7220 pt_entry_t *l3; 7221 7222 lock = NULL; 7223 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock); 7224 if (lock != NULL) 7225 rw_wunlock(lock); 7226 return (l3); 7227 } 7228 7229 /* 7230 * Perform the pmap work for mincore(2). If the page is not both referenced and 7231 * modified by this pmap, returns its physical address so that the caller can 7232 * find other mappings. 7233 */ 7234 int 7235 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap) 7236 { 7237 pt_entry_t *pte, tpte; 7238 vm_paddr_t mask, pa; 7239 int lvl, val; 7240 bool managed; 7241 7242 PMAP_ASSERT_STAGE1(pmap); 7243 PMAP_LOCK(pmap); 7244 pte = pmap_pte(pmap, addr, &lvl); 7245 if (pte != NULL) { 7246 tpte = pmap_load(pte); 7247 7248 switch (lvl) { 7249 case 3: 7250 mask = L3_OFFSET; 7251 break; 7252 case 2: 7253 mask = L2_OFFSET; 7254 break; 7255 case 1: 7256 mask = L1_OFFSET; 7257 break; 7258 default: 7259 panic("pmap_mincore: invalid level %d", lvl); 7260 } 7261 7262 managed = (tpte & ATTR_SW_MANAGED) != 0; 7263 val = MINCORE_INCORE; 7264 if (lvl != 3) 7265 val |= MINCORE_PSIND(3 - lvl); 7266 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed && 7267 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW))) 7268 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 7269 if ((tpte & ATTR_AF) == ATTR_AF) 7270 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 7271 7272 pa = PTE_TO_PHYS(tpte) | (addr & mask); 7273 } else { 7274 managed = false; 7275 val = 0; 7276 } 7277 7278 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 7279 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) { 7280 *pap = pa; 7281 } 7282 PMAP_UNLOCK(pmap); 7283 return (val); 7284 } 7285 7286 /* 7287 * Garbage collect every ASID that is neither active on a processor nor 7288 * reserved. 7289 */ 7290 static void 7291 pmap_reset_asid_set(pmap_t pmap) 7292 { 7293 pmap_t curpmap; 7294 int asid, cpuid, epoch; 7295 struct asid_set *set; 7296 enum pmap_stage stage; 7297 7298 set = pmap->pm_asid_set; 7299 stage = pmap->pm_stage; 7300 7301 set = pmap->pm_asid_set; 7302 KASSERT(set != NULL, ("%s: NULL asid set", __func__)); 7303 mtx_assert(&set->asid_set_mutex, MA_OWNED); 7304 7305 /* 7306 * Ensure that the store to asid_epoch is globally visible before the 7307 * loads from pc_curpmap are performed. 7308 */ 7309 epoch = set->asid_epoch + 1; 7310 if (epoch == INT_MAX) 7311 epoch = 0; 7312 set->asid_epoch = epoch; 7313 dsb(ishst); 7314 if (stage == PM_STAGE1) { 7315 __asm __volatile("tlbi vmalle1is"); 7316 } else { 7317 KASSERT(pmap_clean_stage2_tlbi != NULL, 7318 ("%s: Unset stage 2 tlb invalidation callback\n", 7319 __func__)); 7320 pmap_clean_stage2_tlbi(); 7321 } 7322 dsb(ish); 7323 bit_nclear(set->asid_set, ASID_FIRST_AVAILABLE, 7324 set->asid_set_size - 1); 7325 CPU_FOREACH(cpuid) { 7326 if (cpuid == curcpu) 7327 continue; 7328 if (stage == PM_STAGE1) { 7329 curpmap = pcpu_find(cpuid)->pc_curpmap; 7330 PMAP_ASSERT_STAGE1(pmap); 7331 } else { 7332 curpmap = pcpu_find(cpuid)->pc_curvmpmap; 7333 if (curpmap == NULL) 7334 continue; 7335 PMAP_ASSERT_STAGE2(pmap); 7336 } 7337 KASSERT(curpmap->pm_asid_set == set, ("Incorrect set")); 7338 asid = COOKIE_TO_ASID(curpmap->pm_cookie); 7339 if (asid == -1) 7340 continue; 7341 bit_set(set->asid_set, asid); 7342 curpmap->pm_cookie = COOKIE_FROM(asid, epoch); 7343 } 7344 } 7345 7346 /* 7347 * Allocate a new ASID for the specified pmap. 7348 */ 7349 static void 7350 pmap_alloc_asid(pmap_t pmap) 7351 { 7352 struct asid_set *set; 7353 int new_asid; 7354 7355 set = pmap->pm_asid_set; 7356 KASSERT(set != NULL, ("%s: NULL asid set", __func__)); 7357 7358 mtx_lock_spin(&set->asid_set_mutex); 7359 7360 /* 7361 * While this processor was waiting to acquire the asid set mutex, 7362 * pmap_reset_asid_set() running on another processor might have 7363 * updated this pmap's cookie to the current epoch. In which case, we 7364 * don't need to allocate a new ASID. 7365 */ 7366 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) 7367 goto out; 7368 7369 bit_ffc_at(set->asid_set, set->asid_next, set->asid_set_size, 7370 &new_asid); 7371 if (new_asid == -1) { 7372 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE, 7373 set->asid_next, &new_asid); 7374 if (new_asid == -1) { 7375 pmap_reset_asid_set(pmap); 7376 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE, 7377 set->asid_set_size, &new_asid); 7378 KASSERT(new_asid != -1, ("ASID allocation failure")); 7379 } 7380 } 7381 bit_set(set->asid_set, new_asid); 7382 set->asid_next = new_asid + 1; 7383 pmap->pm_cookie = COOKIE_FROM(new_asid, set->asid_epoch); 7384 out: 7385 mtx_unlock_spin(&set->asid_set_mutex); 7386 } 7387 7388 static uint64_t __read_mostly ttbr_flags; 7389 7390 /* 7391 * Compute the value that should be stored in ttbr0 to activate the specified 7392 * pmap. This value may change from time to time. 7393 */ 7394 uint64_t 7395 pmap_to_ttbr0(pmap_t pmap) 7396 { 7397 uint64_t ttbr; 7398 7399 ttbr = pmap->pm_ttbr; 7400 ttbr |= ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)); 7401 ttbr |= ttbr_flags; 7402 7403 return (ttbr); 7404 } 7405 7406 static void 7407 pmap_set_cnp(void *arg) 7408 { 7409 uint64_t ttbr0, ttbr1; 7410 u_int cpuid; 7411 7412 cpuid = *(u_int *)arg; 7413 if (cpuid == curcpu) { 7414 /* 7415 * Set the flags while all CPUs are handling the 7416 * smp_rendezvous so will not call pmap_to_ttbr0. Any calls 7417 * to pmap_to_ttbr0 after this will have the CnP flag set. 7418 * The dsb after invalidating the TLB will act as a barrier 7419 * to ensure all CPUs can observe this change. 7420 */ 7421 ttbr_flags |= TTBR_CnP; 7422 } 7423 7424 ttbr0 = READ_SPECIALREG(ttbr0_el1); 7425 ttbr0 |= TTBR_CnP; 7426 7427 ttbr1 = READ_SPECIALREG(ttbr1_el1); 7428 ttbr1 |= TTBR_CnP; 7429 7430 /* Update ttbr{0,1}_el1 with the CnP flag */ 7431 WRITE_SPECIALREG(ttbr0_el1, ttbr0); 7432 WRITE_SPECIALREG(ttbr1_el1, ttbr1); 7433 isb(); 7434 __asm __volatile("tlbi vmalle1is"); 7435 dsb(ish); 7436 isb(); 7437 } 7438 7439 /* 7440 * Defer enabling CnP until we have read the ID registers to know if it's 7441 * supported on all CPUs. 7442 */ 7443 static void 7444 pmap_init_cnp(void *dummy __unused) 7445 { 7446 uint64_t reg; 7447 u_int cpuid; 7448 7449 if (!get_kernel_reg(ID_AA64MMFR2_EL1, ®)) 7450 return; 7451 7452 if (ID_AA64MMFR2_CnP_VAL(reg) != ID_AA64MMFR2_CnP_NONE) { 7453 if (bootverbose) 7454 printf("Enabling CnP\n"); 7455 cpuid = curcpu; 7456 smp_rendezvous(NULL, pmap_set_cnp, NULL, &cpuid); 7457 } 7458 7459 } 7460 SYSINIT(pmap_init_cnp, SI_SUB_SMP, SI_ORDER_ANY, pmap_init_cnp, NULL); 7461 7462 static bool 7463 pmap_activate_int(pmap_t pmap) 7464 { 7465 struct asid_set *set; 7466 int epoch; 7467 7468 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap")); 7469 KASSERT(pmap != kernel_pmap, ("kernel pmap activation")); 7470 7471 if ((pmap->pm_stage == PM_STAGE1 && pmap == PCPU_GET(curpmap)) || 7472 (pmap->pm_stage == PM_STAGE2 && pmap == PCPU_GET(curvmpmap))) { 7473 /* 7474 * Handle the possibility that the old thread was preempted 7475 * after an "ic" or "tlbi" instruction but before it performed 7476 * a "dsb" instruction. If the old thread migrates to a new 7477 * processor, its completion of a "dsb" instruction on that 7478 * new processor does not guarantee that the "ic" or "tlbi" 7479 * instructions performed on the old processor have completed. 7480 */ 7481 dsb(ish); 7482 return (false); 7483 } 7484 7485 set = pmap->pm_asid_set; 7486 KASSERT(set != NULL, ("%s: NULL asid set", __func__)); 7487 7488 /* 7489 * Ensure that the store to curpmap is globally visible before the 7490 * load from asid_epoch is performed. 7491 */ 7492 if (pmap->pm_stage == PM_STAGE1) 7493 PCPU_SET(curpmap, pmap); 7494 else 7495 PCPU_SET(curvmpmap, pmap); 7496 dsb(ish); 7497 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie); 7498 if (epoch >= 0 && epoch != set->asid_epoch) 7499 pmap_alloc_asid(pmap); 7500 7501 if (pmap->pm_stage == PM_STAGE1) { 7502 set_ttbr0(pmap_to_ttbr0(pmap)); 7503 if (PCPU_GET(bcast_tlbi_workaround) != 0) 7504 invalidate_local_icache(); 7505 } 7506 return (true); 7507 } 7508 7509 void 7510 pmap_activate_vm(pmap_t pmap) 7511 { 7512 7513 PMAP_ASSERT_STAGE2(pmap); 7514 7515 (void)pmap_activate_int(pmap); 7516 } 7517 7518 void 7519 pmap_activate(struct thread *td) 7520 { 7521 pmap_t pmap; 7522 7523 pmap = vmspace_pmap(td->td_proc->p_vmspace); 7524 PMAP_ASSERT_STAGE1(pmap); 7525 critical_enter(); 7526 (void)pmap_activate_int(pmap); 7527 critical_exit(); 7528 } 7529 7530 /* 7531 * Activate the thread we are switching to. 7532 * To simplify the assembly in cpu_throw return the new threads pcb. 7533 */ 7534 struct pcb * 7535 pmap_switch(struct thread *new) 7536 { 7537 pcpu_bp_harden bp_harden; 7538 struct pcb *pcb; 7539 7540 /* Store the new curthread */ 7541 PCPU_SET(curthread, new); 7542 7543 /* And the new pcb */ 7544 pcb = new->td_pcb; 7545 PCPU_SET(curpcb, pcb); 7546 7547 /* 7548 * TODO: We may need to flush the cache here if switching 7549 * to a user process. 7550 */ 7551 7552 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) { 7553 /* 7554 * Stop userspace from training the branch predictor against 7555 * other processes. This will call into a CPU specific 7556 * function that clears the branch predictor state. 7557 */ 7558 bp_harden = PCPU_GET(bp_harden); 7559 if (bp_harden != NULL) 7560 bp_harden(); 7561 } 7562 7563 return (pcb); 7564 } 7565 7566 void 7567 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz) 7568 { 7569 7570 PMAP_ASSERT_STAGE1(pmap); 7571 KASSERT(ADDR_IS_CANONICAL(va), 7572 ("%s: Address not in canonical form: %lx", __func__, va)); 7573 7574 if (ADDR_IS_KERNEL(va)) { 7575 cpu_icache_sync_range(va, sz); 7576 } else { 7577 u_int len, offset; 7578 vm_paddr_t pa; 7579 7580 /* Find the length of data in this page to flush */ 7581 offset = va & PAGE_MASK; 7582 len = imin(PAGE_SIZE - offset, sz); 7583 7584 while (sz != 0) { 7585 /* Extract the physical address & find it in the DMAP */ 7586 pa = pmap_extract(pmap, va); 7587 if (pa != 0) 7588 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len); 7589 7590 /* Move to the next page */ 7591 sz -= len; 7592 va += len; 7593 /* Set the length for the next iteration */ 7594 len = imin(PAGE_SIZE, sz); 7595 } 7596 } 7597 } 7598 7599 static int 7600 pmap_stage2_fault(pmap_t pmap, uint64_t esr, uint64_t far) 7601 { 7602 pd_entry_t *pdep; 7603 pt_entry_t *ptep, pte; 7604 int rv, lvl, dfsc; 7605 7606 PMAP_ASSERT_STAGE2(pmap); 7607 rv = KERN_FAILURE; 7608 7609 /* Data and insn aborts use same encoding for FSC field. */ 7610 dfsc = esr & ISS_DATA_DFSC_MASK; 7611 switch (dfsc) { 7612 case ISS_DATA_DFSC_TF_L0: 7613 case ISS_DATA_DFSC_TF_L1: 7614 case ISS_DATA_DFSC_TF_L2: 7615 case ISS_DATA_DFSC_TF_L3: 7616 PMAP_LOCK(pmap); 7617 pdep = pmap_pde(pmap, far, &lvl); 7618 if (pdep == NULL || lvl != (dfsc - ISS_DATA_DFSC_TF_L1)) { 7619 PMAP_UNLOCK(pmap); 7620 break; 7621 } 7622 7623 switch (lvl) { 7624 case 0: 7625 ptep = pmap_l0_to_l1(pdep, far); 7626 break; 7627 case 1: 7628 ptep = pmap_l1_to_l2(pdep, far); 7629 break; 7630 case 2: 7631 ptep = pmap_l2_to_l3(pdep, far); 7632 break; 7633 default: 7634 panic("%s: Invalid pde level %d", __func__,lvl); 7635 } 7636 goto fault_exec; 7637 7638 case ISS_DATA_DFSC_AFF_L1: 7639 case ISS_DATA_DFSC_AFF_L2: 7640 case ISS_DATA_DFSC_AFF_L3: 7641 PMAP_LOCK(pmap); 7642 ptep = pmap_pte(pmap, far, &lvl); 7643 fault_exec: 7644 if (ptep != NULL && (pte = pmap_load(ptep)) != 0) { 7645 if (icache_vmid) { 7646 pmap_invalidate_vpipt_icache(); 7647 } else { 7648 /* 7649 * If accessing an executable page invalidate 7650 * the I-cache so it will be valid when we 7651 * continue execution in the guest. The D-cache 7652 * is assumed to already be clean to the Point 7653 * of Coherency. 7654 */ 7655 if ((pte & ATTR_S2_XN_MASK) != 7656 ATTR_S2_XN(ATTR_S2_XN_NONE)) { 7657 invalidate_icache(); 7658 } 7659 } 7660 pmap_set_bits(ptep, ATTR_AF | ATTR_DESCR_VALID); 7661 rv = KERN_SUCCESS; 7662 } 7663 PMAP_UNLOCK(pmap); 7664 break; 7665 } 7666 7667 return (rv); 7668 } 7669 7670 int 7671 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far) 7672 { 7673 pt_entry_t pte, *ptep; 7674 register_t intr; 7675 uint64_t ec, par; 7676 int lvl, rv; 7677 7678 rv = KERN_FAILURE; 7679 7680 ec = ESR_ELx_EXCEPTION(esr); 7681 switch (ec) { 7682 case EXCP_INSN_ABORT_L: 7683 case EXCP_INSN_ABORT: 7684 case EXCP_DATA_ABORT_L: 7685 case EXCP_DATA_ABORT: 7686 break; 7687 default: 7688 return (rv); 7689 } 7690 7691 if (pmap->pm_stage == PM_STAGE2) 7692 return (pmap_stage2_fault(pmap, esr, far)); 7693 7694 /* Data and insn aborts use same encoding for FSC field. */ 7695 switch (esr & ISS_DATA_DFSC_MASK) { 7696 case ISS_DATA_DFSC_AFF_L1: 7697 case ISS_DATA_DFSC_AFF_L2: 7698 case ISS_DATA_DFSC_AFF_L3: 7699 PMAP_LOCK(pmap); 7700 ptep = pmap_pte(pmap, far, &lvl); 7701 if (ptep != NULL) { 7702 pmap_set_bits(ptep, ATTR_AF); 7703 rv = KERN_SUCCESS; 7704 /* 7705 * XXXMJ as an optimization we could mark the entry 7706 * dirty if this is a write fault. 7707 */ 7708 } 7709 PMAP_UNLOCK(pmap); 7710 break; 7711 case ISS_DATA_DFSC_PF_L1: 7712 case ISS_DATA_DFSC_PF_L2: 7713 case ISS_DATA_DFSC_PF_L3: 7714 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) || 7715 (esr & ISS_DATA_WnR) == 0) 7716 return (rv); 7717 PMAP_LOCK(pmap); 7718 ptep = pmap_pte(pmap, far, &lvl); 7719 if (ptep != NULL && 7720 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) { 7721 if ((pte & ATTR_S1_AP_RW_BIT) == 7722 ATTR_S1_AP(ATTR_S1_AP_RO)) { 7723 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT); 7724 pmap_s1_invalidate_page(pmap, far, true); 7725 } 7726 rv = KERN_SUCCESS; 7727 } 7728 PMAP_UNLOCK(pmap); 7729 break; 7730 case ISS_DATA_DFSC_TF_L0: 7731 case ISS_DATA_DFSC_TF_L1: 7732 case ISS_DATA_DFSC_TF_L2: 7733 case ISS_DATA_DFSC_TF_L3: 7734 /* 7735 * Retry the translation. A break-before-make sequence can 7736 * produce a transient fault. 7737 */ 7738 if (pmap == kernel_pmap) { 7739 /* 7740 * The translation fault may have occurred within a 7741 * critical section. Therefore, we must check the 7742 * address without acquiring the kernel pmap's lock. 7743 */ 7744 if (pmap_klookup(far, NULL)) 7745 rv = KERN_SUCCESS; 7746 } else { 7747 PMAP_LOCK(pmap); 7748 /* Ask the MMU to check the address. */ 7749 intr = intr_disable(); 7750 par = arm64_address_translate_s1e0r(far); 7751 intr_restore(intr); 7752 PMAP_UNLOCK(pmap); 7753 7754 /* 7755 * If the translation was successful, then we can 7756 * return success to the trap handler. 7757 */ 7758 if (PAR_SUCCESS(par)) 7759 rv = KERN_SUCCESS; 7760 } 7761 break; 7762 } 7763 7764 return (rv); 7765 } 7766 7767 /* 7768 * Increase the starting virtual address of the given mapping if a 7769 * different alignment might result in more superpage mappings. 7770 */ 7771 void 7772 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 7773 vm_offset_t *addr, vm_size_t size) 7774 { 7775 vm_offset_t superpage_offset; 7776 7777 if (size < L2_SIZE) 7778 return; 7779 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 7780 offset += ptoa(object->pg_color); 7781 superpage_offset = offset & L2_OFFSET; 7782 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE || 7783 (*addr & L2_OFFSET) == superpage_offset) 7784 return; 7785 if ((*addr & L2_OFFSET) < superpage_offset) 7786 *addr = (*addr & ~L2_OFFSET) + superpage_offset; 7787 else 7788 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset; 7789 } 7790 7791 /** 7792 * Get the kernel virtual address of a set of physical pages. If there are 7793 * physical addresses not covered by the DMAP perform a transient mapping 7794 * that will be removed when calling pmap_unmap_io_transient. 7795 * 7796 * \param page The pages the caller wishes to obtain the virtual 7797 * address on the kernel memory map. 7798 * \param vaddr On return contains the kernel virtual memory address 7799 * of the pages passed in the page parameter. 7800 * \param count Number of pages passed in. 7801 * \param can_fault true if the thread using the mapped pages can take 7802 * page faults, false otherwise. 7803 * 7804 * \returns true if the caller must call pmap_unmap_io_transient when 7805 * finished or false otherwise. 7806 * 7807 */ 7808 bool 7809 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count, 7810 bool can_fault) 7811 { 7812 vm_paddr_t paddr; 7813 bool needs_mapping; 7814 int error __diagused, i; 7815 7816 /* 7817 * Allocate any KVA space that we need, this is done in a separate 7818 * loop to prevent calling vmem_alloc while pinned. 7819 */ 7820 needs_mapping = false; 7821 for (i = 0; i < count; i++) { 7822 paddr = VM_PAGE_TO_PHYS(page[i]); 7823 if (__predict_false(!PHYS_IN_DMAP(paddr))) { 7824 error = vmem_alloc(kernel_arena, PAGE_SIZE, 7825 M_BESTFIT | M_WAITOK, &vaddr[i]); 7826 KASSERT(error == 0, ("vmem_alloc failed: %d", error)); 7827 needs_mapping = true; 7828 } else { 7829 vaddr[i] = PHYS_TO_DMAP(paddr); 7830 } 7831 } 7832 7833 /* Exit early if everything is covered by the DMAP */ 7834 if (!needs_mapping) 7835 return (false); 7836 7837 if (!can_fault) 7838 sched_pin(); 7839 for (i = 0; i < count; i++) { 7840 paddr = VM_PAGE_TO_PHYS(page[i]); 7841 if (!PHYS_IN_DMAP(paddr)) { 7842 panic( 7843 "pmap_map_io_transient: TODO: Map out of DMAP data"); 7844 } 7845 } 7846 7847 return (needs_mapping); 7848 } 7849 7850 void 7851 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count, 7852 bool can_fault) 7853 { 7854 vm_paddr_t paddr; 7855 int i; 7856 7857 if (!can_fault) 7858 sched_unpin(); 7859 for (i = 0; i < count; i++) { 7860 paddr = VM_PAGE_TO_PHYS(page[i]); 7861 if (!PHYS_IN_DMAP(paddr)) { 7862 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data"); 7863 } 7864 } 7865 } 7866 7867 bool 7868 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode) 7869 { 7870 7871 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH); 7872 } 7873 7874 static pt_entry_t 7875 pmap_pte_bti(pmap_t pmap, vm_offset_t va __diagused) 7876 { 7877 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 7878 MPASS(ADDR_IS_CANONICAL(va)); 7879 7880 if (pmap->pm_stage != PM_STAGE1) 7881 return (0); 7882 if (pmap == kernel_pmap) 7883 return (ATTR_KERN_GP); 7884 return (0); 7885 } 7886 7887 #if defined(KASAN) || defined(KMSAN) 7888 static pd_entry_t *pmap_san_early_l2; 7889 7890 #define SAN_BOOTSTRAP_L2_SIZE (1 * L2_SIZE) 7891 #define SAN_BOOTSTRAP_SIZE (2 * PAGE_SIZE) 7892 static vm_offset_t __nosanitizeaddress 7893 pmap_san_enter_bootstrap_alloc_l2(void) 7894 { 7895 static uint8_t bootstrap_data[SAN_BOOTSTRAP_L2_SIZE] __aligned(L2_SIZE); 7896 static size_t offset = 0; 7897 vm_offset_t addr; 7898 7899 if (offset + L2_SIZE > sizeof(bootstrap_data)) { 7900 panic("%s: out of memory for the bootstrap shadow map L2 entries", 7901 __func__); 7902 } 7903 7904 addr = (uintptr_t)&bootstrap_data[offset]; 7905 offset += L2_SIZE; 7906 return (addr); 7907 } 7908 7909 /* 7910 * SAN L1 + L2 pages, maybe L3 entries later? 7911 */ 7912 static vm_offset_t __nosanitizeaddress 7913 pmap_san_enter_bootstrap_alloc_pages(int npages) 7914 { 7915 static uint8_t bootstrap_data[SAN_BOOTSTRAP_SIZE] __aligned(PAGE_SIZE); 7916 static size_t offset = 0; 7917 vm_offset_t addr; 7918 7919 if (offset + (npages * PAGE_SIZE) > sizeof(bootstrap_data)) { 7920 panic("%s: out of memory for the bootstrap shadow map", 7921 __func__); 7922 } 7923 7924 addr = (uintptr_t)&bootstrap_data[offset]; 7925 offset += (npages * PAGE_SIZE); 7926 return (addr); 7927 } 7928 7929 static void __nosanitizeaddress 7930 pmap_san_enter_bootstrap(void) 7931 { 7932 vm_offset_t freemempos; 7933 7934 /* L1, L2 */ 7935 freemempos = pmap_san_enter_bootstrap_alloc_pages(2); 7936 bs_state.freemempos = freemempos; 7937 bs_state.va = KASAN_MIN_ADDRESS; 7938 pmap_bootstrap_l1_table(&bs_state); 7939 pmap_san_early_l2 = bs_state.l2; 7940 } 7941 7942 static vm_page_t 7943 pmap_san_enter_alloc_l3(void) 7944 { 7945 vm_page_t m; 7946 7947 m = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED | 7948 VM_ALLOC_ZERO); 7949 if (m == NULL) 7950 panic("%s: no memory to grow shadow map", __func__); 7951 return (m); 7952 } 7953 7954 static vm_page_t 7955 pmap_san_enter_alloc_l2(void) 7956 { 7957 return (vm_page_alloc_noobj_contig(VM_ALLOC_WIRED | VM_ALLOC_ZERO, 7958 Ln_ENTRIES, 0, ~0ul, L2_SIZE, 0, VM_MEMATTR_DEFAULT)); 7959 } 7960 7961 void __nosanitizeaddress __nosanitizememory 7962 pmap_san_enter(vm_offset_t va) 7963 { 7964 pd_entry_t *l1, *l2; 7965 pt_entry_t *l3; 7966 vm_page_t m; 7967 7968 if (virtual_avail == 0) { 7969 vm_offset_t block; 7970 int slot; 7971 bool first; 7972 7973 /* Temporary shadow map prior to pmap_bootstrap(). */ 7974 first = pmap_san_early_l2 == NULL; 7975 if (first) 7976 pmap_san_enter_bootstrap(); 7977 7978 l2 = pmap_san_early_l2; 7979 slot = pmap_l2_index(va); 7980 7981 if ((pmap_load(&l2[slot]) & ATTR_DESCR_VALID) == 0) { 7982 MPASS(first); 7983 block = pmap_san_enter_bootstrap_alloc_l2(); 7984 pmap_store(&l2[slot], 7985 PHYS_TO_PTE(pmap_early_vtophys(block)) | 7986 PMAP_SAN_PTE_BITS | L2_BLOCK); 7987 dmb(ishst); 7988 } 7989 7990 return; 7991 } 7992 7993 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 7994 l1 = pmap_l1(kernel_pmap, va); 7995 MPASS(l1 != NULL); 7996 if ((pmap_load(l1) & ATTR_DESCR_VALID) == 0) { 7997 m = pmap_san_enter_alloc_l3(); 7998 pmap_store(l1, PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) | L1_TABLE); 7999 } 8000 l2 = pmap_l1_to_l2(l1, va); 8001 if ((pmap_load(l2) & ATTR_DESCR_VALID) == 0) { 8002 m = pmap_san_enter_alloc_l2(); 8003 if (m != NULL) { 8004 pmap_store(l2, PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) | 8005 PMAP_SAN_PTE_BITS | L2_BLOCK); 8006 } else { 8007 m = pmap_san_enter_alloc_l3(); 8008 pmap_store(l2, PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) | 8009 L2_TABLE); 8010 } 8011 dmb(ishst); 8012 } 8013 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) 8014 return; 8015 l3 = pmap_l2_to_l3(l2, va); 8016 if ((pmap_load(l3) & ATTR_DESCR_VALID) != 0) 8017 return; 8018 m = pmap_san_enter_alloc_l3(); 8019 pmap_store(l3, PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) | 8020 PMAP_SAN_PTE_BITS | L3_PAGE); 8021 dmb(ishst); 8022 } 8023 #endif /* KASAN || KMSAN */ 8024 8025 /* 8026 * Track a range of the kernel's virtual address space that is contiguous 8027 * in various mapping attributes. 8028 */ 8029 struct pmap_kernel_map_range { 8030 vm_offset_t sva; 8031 pt_entry_t attrs; 8032 int l3pages; 8033 int l3contig; 8034 int l2blocks; 8035 int l1blocks; 8036 }; 8037 8038 static void 8039 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range, 8040 vm_offset_t eva) 8041 { 8042 const char *mode; 8043 int index; 8044 8045 if (eva <= range->sva) 8046 return; 8047 8048 index = range->attrs & ATTR_S1_IDX_MASK; 8049 switch (index) { 8050 case ATTR_S1_IDX(VM_MEMATTR_DEVICE_NP): 8051 mode = "DEV-NP"; 8052 break; 8053 case ATTR_S1_IDX(VM_MEMATTR_DEVICE): 8054 mode = "DEV"; 8055 break; 8056 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE): 8057 mode = "UC"; 8058 break; 8059 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK): 8060 mode = "WB"; 8061 break; 8062 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH): 8063 mode = "WT"; 8064 break; 8065 default: 8066 printf( 8067 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n", 8068 __func__, index, range->sva, eva); 8069 mode = "??"; 8070 break; 8071 } 8072 8073 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c%c %6s %d %d %d %d\n", 8074 range->sva, eva, 8075 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-', 8076 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x', 8077 (range->attrs & ATTR_S1_UXN) != 0 ? '-' : 'X', 8078 (range->attrs & ATTR_S1_AP(ATTR_S1_AP_USER)) != 0 ? 'u' : 's', 8079 (range->attrs & ATTR_S1_GP) != 0 ? 'g' : '-', 8080 mode, range->l1blocks, range->l2blocks, range->l3contig, 8081 range->l3pages); 8082 8083 /* Reset to sentinel value. */ 8084 range->sva = 0xfffffffffffffffful; 8085 } 8086 8087 /* 8088 * Determine whether the attributes specified by a page table entry match those 8089 * being tracked by the current range. 8090 */ 8091 static bool 8092 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs) 8093 { 8094 8095 return (range->attrs == attrs); 8096 } 8097 8098 static void 8099 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va, 8100 pt_entry_t attrs) 8101 { 8102 8103 memset(range, 0, sizeof(*range)); 8104 range->sva = va; 8105 range->attrs = attrs; 8106 } 8107 8108 /* Get the block/page attributes that correspond to the table attributes */ 8109 static pt_entry_t 8110 sysctl_kmaps_table_attrs(pd_entry_t table) 8111 { 8112 pt_entry_t attrs; 8113 8114 attrs = 0; 8115 if ((table & TATTR_UXN_TABLE) != 0) 8116 attrs |= ATTR_S1_UXN; 8117 if ((table & TATTR_PXN_TABLE) != 0) 8118 attrs |= ATTR_S1_PXN; 8119 if ((table & TATTR_AP_TABLE_RO) != 0) 8120 attrs |= ATTR_S1_AP(ATTR_S1_AP_RO); 8121 8122 return (attrs); 8123 } 8124 8125 /* Read the block/page attributes we care about */ 8126 static pt_entry_t 8127 sysctl_kmaps_block_attrs(pt_entry_t block) 8128 { 8129 return (block & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK | 8130 ATTR_S1_GP)); 8131 } 8132 8133 /* 8134 * Given a leaf PTE, derive the mapping's attributes. If they do not match 8135 * those of the current run, dump the address range and its attributes, and 8136 * begin a new run. 8137 */ 8138 static void 8139 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range, 8140 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e, 8141 pt_entry_t l3e) 8142 { 8143 pt_entry_t attrs; 8144 8145 attrs = sysctl_kmaps_table_attrs(l0e); 8146 8147 if ((l1e & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) { 8148 attrs |= sysctl_kmaps_block_attrs(l1e); 8149 goto done; 8150 } 8151 attrs |= sysctl_kmaps_table_attrs(l1e); 8152 8153 if ((l2e & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) { 8154 attrs |= sysctl_kmaps_block_attrs(l2e); 8155 goto done; 8156 } 8157 attrs |= sysctl_kmaps_table_attrs(l2e); 8158 attrs |= sysctl_kmaps_block_attrs(l3e); 8159 8160 done: 8161 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) { 8162 sysctl_kmaps_dump(sb, range, va); 8163 sysctl_kmaps_reinit(range, va, attrs); 8164 } 8165 } 8166 8167 static int 8168 sysctl_kmaps(SYSCTL_HANDLER_ARGS) 8169 { 8170 struct pmap_kernel_map_range range; 8171 struct sbuf sbuf, *sb; 8172 pd_entry_t l0e, *l1, l1e, *l2, l2e; 8173 pt_entry_t *l3, l3e; 8174 vm_offset_t sva; 8175 vm_paddr_t pa; 8176 int error, i, j, k, l; 8177 8178 error = sysctl_wire_old_buffer(req, 0); 8179 if (error != 0) 8180 return (error); 8181 sb = &sbuf; 8182 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req); 8183 8184 /* Sentinel value. */ 8185 range.sva = 0xfffffffffffffffful; 8186 8187 /* 8188 * Iterate over the kernel page tables without holding the kernel pmap 8189 * lock. Kernel page table pages are never freed, so at worst we will 8190 * observe inconsistencies in the output. 8191 */ 8192 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES; 8193 i++) { 8194 if (i == pmap_l0_index(DMAP_MIN_ADDRESS)) 8195 sbuf_printf(sb, "\nDirect map:\n"); 8196 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS)) 8197 sbuf_printf(sb, "\nKernel map:\n"); 8198 #ifdef KASAN 8199 else if (i == pmap_l0_index(KASAN_MIN_ADDRESS)) 8200 sbuf_printf(sb, "\nKASAN shadow map:\n"); 8201 #endif 8202 #ifdef KMSAN 8203 else if (i == pmap_l0_index(KMSAN_SHAD_MIN_ADDRESS)) 8204 sbuf_printf(sb, "\nKMSAN shadow map:\n"); 8205 else if (i == pmap_l0_index(KMSAN_ORIG_MIN_ADDRESS)) 8206 sbuf_printf(sb, "\nKMSAN origin map:\n"); 8207 #endif 8208 8209 l0e = kernel_pmap->pm_l0[i]; 8210 if ((l0e & ATTR_DESCR_VALID) == 0) { 8211 sysctl_kmaps_dump(sb, &range, sva); 8212 sva += L0_SIZE; 8213 continue; 8214 } 8215 pa = PTE_TO_PHYS(l0e); 8216 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa); 8217 8218 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) { 8219 l1e = l1[j]; 8220 if ((l1e & ATTR_DESCR_VALID) == 0) { 8221 sysctl_kmaps_dump(sb, &range, sva); 8222 sva += L1_SIZE; 8223 continue; 8224 } 8225 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) { 8226 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 8227 sysctl_kmaps_check(sb, &range, sva, l0e, l1e, 8228 0, 0); 8229 range.l1blocks++; 8230 sva += L1_SIZE; 8231 continue; 8232 } 8233 pa = PTE_TO_PHYS(l1e); 8234 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa); 8235 8236 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) { 8237 l2e = l2[k]; 8238 if ((l2e & ATTR_DESCR_VALID) == 0) { 8239 sysctl_kmaps_dump(sb, &range, sva); 8240 sva += L2_SIZE; 8241 continue; 8242 } 8243 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) { 8244 sysctl_kmaps_check(sb, &range, sva, 8245 l0e, l1e, l2e, 0); 8246 range.l2blocks++; 8247 sva += L2_SIZE; 8248 continue; 8249 } 8250 pa = PTE_TO_PHYS(l2e); 8251 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa); 8252 8253 for (l = pmap_l3_index(sva); l < Ln_ENTRIES; 8254 l++, sva += L3_SIZE) { 8255 l3e = l3[l]; 8256 if ((l3e & ATTR_DESCR_VALID) == 0) { 8257 sysctl_kmaps_dump(sb, &range, 8258 sva); 8259 continue; 8260 } 8261 sysctl_kmaps_check(sb, &range, sva, 8262 l0e, l1e, l2e, l3e); 8263 if ((l3e & ATTR_CONTIGUOUS) != 0) 8264 range.l3contig += l % 16 == 0 ? 8265 1 : 0; 8266 else 8267 range.l3pages++; 8268 } 8269 } 8270 } 8271 } 8272 8273 error = sbuf_finish(sb); 8274 sbuf_delete(sb); 8275 return (error); 8276 } 8277 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps, 8278 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP, 8279 NULL, 0, sysctl_kmaps, "A", 8280 "Dump kernel address layout"); 8281