1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * 4 * This software was developed by Semihalf under 5 * the sponsorship of the FreeBSD Foundation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_platform.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 #include <sys/endian.h> 44 45 #include <vm/vm.h> 46 47 #ifdef FDT 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 #include <dev/ofw/ofw_pci.h> 52 #endif 53 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pci_host_generic.h> 57 #include <dev/pci/pcib_private.h> 58 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <machine/smp.h> 62 #include <machine/intr.h> 63 64 #include <arm64/cavium/thunder_pcie_common.h> 65 #include <arm64/cavium/thunder_pcie_pem.h> 66 #include "pcib_if.h" 67 68 #define THUNDER_PEM_DEVICE_ID 0xa020 69 #define THUNDER_PEM_VENDOR_ID 0x177d 70 71 /* ThunderX specific defines */ 72 #define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24)) 73 #define PCIERC_CFG002 0x08 74 #define PCIERC_CFG006 0x18 75 #define PCIERC_CFG032 0x80 76 #define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF) 77 #define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3) 78 #define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF) 79 #define PEM_CFG_RD 0x30 80 #define PEM_CFG_LINK_MASK 0x3 81 #define PEM_CFG_LINK_RDY 0x3 82 #define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4) 83 #define SBNUM_OFFSET 0x8 84 #define SBNUM_MASK 0xFF 85 #define PEM_ON_REG 0x420 86 #define PEM_CTL_STATUS 0x0 87 #define PEM_LINK_ENABLE (1 << 4) 88 #define PEM_LINK_DLLA (1 << 29) 89 #define PEM_LINK_LT (1 << 27) 90 #define PEM_BUS_SHIFT (24) 91 #define PEM_SLOT_SHIFT (19) 92 #define PEM_FUNC_SHIFT (16) 93 #define SLIX_S2M_REGX_ACC 0x874001000000UL 94 #define SLIX_S2M_REGX_ACC_SIZE 0x1000 95 #define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL 96 #define SLI_BASE 0x880000000000UL 97 #define SLI_WINDOW_SPACING 0x004000000000UL 98 #define SLI_PCI_OFFSET 0x001000000000UL 99 #define SLI_NODE_SHIFT (44) 100 #define SLI_NODE_MASK (3) 101 #define SLI_GROUP_SHIFT (40) 102 #define SLI_ID_SHIFT (24) 103 #define SLI_ID_MASK (7) 104 #define SLI_PEMS_PER_GROUP (3) 105 #define SLI_GROUPS_PER_NODE (2) 106 #define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE) 107 #define SLI_ACC_REG_CNT (256) 108 109 /* 110 * Each PEM device creates its own bus with 111 * own address translation, so we can adjust bus addresses 112 * as we want. To support 32-bit cards let's assume 113 * PCI window assignment looks as following: 114 * 115 * 0x00000000 - 0x000FFFFF IO 116 * 0x00100000 - 0xFFFFFFFF Memory 117 */ 118 #define PCI_IO_BASE 0x00000000UL 119 #define PCI_IO_SIZE 0x00100000UL 120 #define PCI_MEMORY_BASE PCI_IO_SIZE 121 #define PCI_MEMORY_SIZE 0xFFF00000UL 122 123 #define RID_PEM_SPACE 1 124 125 static int thunder_pem_activate_resource(device_t, device_t, int, int, 126 struct resource *); 127 static int thunder_pem_adjust_resource(device_t, device_t, int, 128 struct resource *, rman_res_t, rman_res_t); 129 static struct resource * thunder_pem_alloc_resource(device_t, device_t, int, 130 int *, rman_res_t, rman_res_t, rman_res_t, u_int); 131 static int thunder_pem_alloc_msi(device_t, device_t, int, int, int *); 132 static int thunder_pem_release_msi(device_t, device_t, int, int *); 133 static int thunder_pem_alloc_msix(device_t, device_t, int *); 134 static int thunder_pem_release_msix(device_t, device_t, int); 135 static int thunder_pem_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 136 static int thunder_pem_get_id(device_t, device_t, enum pci_id_type, 137 uintptr_t *); 138 static int thunder_pem_attach(device_t); 139 static int thunder_pem_deactivate_resource(device_t, device_t, int, int, 140 struct resource *); 141 static bus_dma_tag_t thunder_pem_get_dma_tag(device_t, device_t); 142 static int thunder_pem_detach(device_t); 143 static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int); 144 static int thunder_pem_link_init(struct thunder_pem_softc *); 145 static int thunder_pem_maxslots(device_t); 146 static int thunder_pem_probe(device_t); 147 static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int, 148 int); 149 static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *); 150 static void thunder_pem_release_all(device_t); 151 static int thunder_pem_release_resource(device_t, device_t, int, int, 152 struct resource *); 153 static struct rman * thunder_pem_rman(struct thunder_pem_softc *, int); 154 static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *, 155 int, int); 156 static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int, 157 uint32_t, int); 158 static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t); 159 160 /* Global handlers for SLI interface */ 161 static bus_space_handle_t sli0_s2m_regx_base = 0; 162 static bus_space_handle_t sli1_s2m_regx_base = 0; 163 164 static device_method_t thunder_pem_methods[] = { 165 /* Device interface */ 166 DEVMETHOD(device_probe, thunder_pem_probe), 167 DEVMETHOD(device_attach, thunder_pem_attach), 168 DEVMETHOD(device_detach, thunder_pem_detach), 169 170 /* Bus interface */ 171 DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar), 172 DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar), 173 DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource), 174 DEVMETHOD(bus_release_resource, thunder_pem_release_resource), 175 DEVMETHOD(bus_adjust_resource, thunder_pem_adjust_resource), 176 DEVMETHOD(bus_activate_resource, thunder_pem_activate_resource), 177 DEVMETHOD(bus_deactivate_resource, thunder_pem_deactivate_resource), 178 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 179 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 180 181 DEVMETHOD(bus_get_dma_tag, thunder_pem_get_dma_tag), 182 183 /* pcib interface */ 184 DEVMETHOD(pcib_maxslots, thunder_pem_maxslots), 185 DEVMETHOD(pcib_read_config, thunder_pem_read_config), 186 DEVMETHOD(pcib_write_config, thunder_pem_write_config), 187 DEVMETHOD(pcib_alloc_msix, thunder_pem_alloc_msix), 188 DEVMETHOD(pcib_release_msix, thunder_pem_release_msix), 189 DEVMETHOD(pcib_alloc_msi, thunder_pem_alloc_msi), 190 DEVMETHOD(pcib_release_msi, thunder_pem_release_msi), 191 DEVMETHOD(pcib_map_msi, thunder_pem_map_msi), 192 DEVMETHOD(pcib_get_id, thunder_pem_get_id), 193 194 DEVMETHOD_END 195 }; 196 197 DEFINE_CLASS_0(pcib, thunder_pem_driver, thunder_pem_methods, 198 sizeof(struct thunder_pem_softc)); 199 200 extern struct bus_space memmap_bus; 201 202 DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, 0, 0); 203 MODULE_DEPEND(thunder_pem, pci, 1, 1, 1); 204 205 static int 206 thunder_pem_maxslots(device_t dev) 207 { 208 209 #if 0 210 /* max slots per bus acc. to standard */ 211 return (PCI_SLOTMAX); 212 #else 213 /* 214 * ARM64TODO Workaround - otherwise an em(4) interface appears to be 215 * present on every PCI function on the bus to which it is connected 216 */ 217 return (0); 218 #endif 219 } 220 221 static int 222 thunder_pem_read_ivar(device_t dev, device_t child, int index, 223 uintptr_t *result) 224 { 225 struct thunder_pem_softc *sc; 226 int secondary_bus = 0; 227 228 sc = device_get_softc(dev); 229 230 if (index == PCIB_IVAR_BUS) { 231 secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006); 232 *result = PCIERC_CFG006_SEC_BUS(secondary_bus); 233 return (0); 234 } 235 if (index == PCIB_IVAR_DOMAIN) { 236 *result = sc->id; 237 return (0); 238 } 239 240 return (ENOENT); 241 } 242 243 static int 244 thunder_pem_write_ivar(device_t dev, device_t child, int index, 245 uintptr_t value) 246 { 247 248 return (ENOENT); 249 } 250 251 static int 252 thunder_pem_activate_resource(device_t dev, device_t child, int type, int rid, 253 struct resource *r) 254 { 255 int err; 256 bus_addr_t paddr; 257 bus_size_t psize; 258 bus_space_handle_t vaddr; 259 struct thunder_pem_softc *sc; 260 261 if ((err = rman_activate_resource(r)) != 0) 262 return (err); 263 264 sc = device_get_softc(dev); 265 266 /* 267 * If this is a memory resource, map it into the kernel. 268 */ 269 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { 270 paddr = (bus_addr_t)rman_get_start(r); 271 psize = (bus_size_t)rman_get_size(r); 272 273 paddr = range_addr_pci_to_phys(sc->ranges, paddr); 274 275 err = bus_space_map(&memmap_bus, paddr, psize, 0, &vaddr); 276 if (err != 0) { 277 rman_deactivate_resource(r); 278 return (err); 279 } 280 rman_set_bustag(r, &memmap_bus); 281 rman_set_virtual(r, (void *)vaddr); 282 rman_set_bushandle(r, vaddr); 283 } 284 return (0); 285 } 286 287 /* 288 * This function is an exact copy of nexus_deactivate_resource() 289 * Keep it up-to-date with all changes in nexus. To be removed 290 * once bus-mapping interface is developed. 291 */ 292 static int 293 thunder_pem_deactivate_resource(device_t bus, device_t child, int type, int rid, 294 struct resource *r) 295 { 296 bus_size_t psize; 297 bus_space_handle_t vaddr; 298 299 psize = (bus_size_t)rman_get_size(r); 300 vaddr = rman_get_bushandle(r); 301 302 if (vaddr != 0) { 303 bus_space_unmap(&memmap_bus, vaddr, psize); 304 rman_set_virtual(r, NULL); 305 rman_set_bushandle(r, 0); 306 } 307 308 return (rman_deactivate_resource(r)); 309 } 310 311 static int 312 thunder_pem_adjust_resource(device_t dev, device_t child, int type, 313 struct resource *res, rman_res_t start, rman_res_t end) 314 { 315 struct thunder_pem_softc *sc; 316 struct rman *rm; 317 318 sc = device_get_softc(dev); 319 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 320 if (type == PCI_RES_BUS) 321 return (pci_domain_adjust_bus(sc->id, child, res, start, end)); 322 #endif 323 324 rm = thunder_pem_rman(sc, type); 325 if (rm == NULL) 326 return (bus_generic_adjust_resource(dev, child, type, res, 327 start, end)); 328 if (!rman_is_region_manager(res, rm)) 329 /* 330 * This means a child device has a memory or I/O 331 * resource not from you which shouldn't happen. 332 */ 333 return (EINVAL); 334 return (rman_adjust_resource(res, start, end)); 335 } 336 337 static bus_dma_tag_t 338 thunder_pem_get_dma_tag(device_t dev, device_t child) 339 { 340 struct thunder_pem_softc *sc; 341 342 sc = device_get_softc(dev); 343 return (sc->dmat); 344 } 345 346 static int 347 thunder_pem_alloc_msi(device_t pci, device_t child, int count, int maxcount, 348 int *irqs) 349 { 350 device_t bus; 351 352 bus = device_get_parent(pci); 353 return (PCIB_ALLOC_MSI(device_get_parent(bus), child, count, maxcount, 354 irqs)); 355 } 356 357 static int 358 thunder_pem_release_msi(device_t pci, device_t child, int count, int *irqs) 359 { 360 device_t bus; 361 362 bus = device_get_parent(pci); 363 return (PCIB_RELEASE_MSI(device_get_parent(bus), child, count, irqs)); 364 } 365 366 static int 367 thunder_pem_alloc_msix(device_t pci, device_t child, int *irq) 368 { 369 device_t bus; 370 371 bus = device_get_parent(pci); 372 return (PCIB_ALLOC_MSIX(device_get_parent(bus), child, irq)); 373 } 374 375 static int 376 thunder_pem_release_msix(device_t pci, device_t child, int irq) 377 { 378 device_t bus; 379 380 bus = device_get_parent(pci); 381 return (PCIB_RELEASE_MSIX(device_get_parent(bus), child, irq)); 382 } 383 384 static int 385 thunder_pem_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 386 uint32_t *data) 387 { 388 device_t bus; 389 390 bus = device_get_parent(pci); 391 return (PCIB_MAP_MSI(device_get_parent(bus), child, irq, addr, data)); 392 } 393 394 static int 395 thunder_pem_get_id(device_t pci, device_t child, enum pci_id_type type, 396 uintptr_t *id) 397 { 398 int bsf; 399 int pem; 400 401 if (type != PCI_ID_MSI) 402 return (pcib_get_id(pci, child, type, id)); 403 404 bsf = pci_get_rid(child); 405 406 /* PEM (PCIe MAC/root complex) number is equal to domain */ 407 pem = pci_get_domain(child); 408 409 /* 410 * Set appropriate device ID (passed by the HW along with 411 * the transaction to memory) for different root complex 412 * numbers using hard-coded domain portion for each group. 413 */ 414 if (pem < 3) 415 *id = (0x1 << PCI_RID_DOMAIN_SHIFT) | bsf; 416 else if (pem < 6) 417 *id = (0x3 << PCI_RID_DOMAIN_SHIFT) | bsf; 418 else if (pem < 9) 419 *id = (0x9 << PCI_RID_DOMAIN_SHIFT) | bsf; 420 else if (pem < 12) 421 *id = (0xB << PCI_RID_DOMAIN_SHIFT) | bsf; 422 else 423 return (ENXIO); 424 425 return (0); 426 } 427 428 static int 429 thunder_pem_identify(device_t dev) 430 { 431 struct thunder_pem_softc *sc; 432 rman_res_t start; 433 434 sc = device_get_softc(dev); 435 start = rman_get_start(sc->reg); 436 437 /* Calculate PEM designations from its address */ 438 sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK; 439 sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) + 440 (SLI_PEMS_PER_NODE * sc->node); 441 sc->sli = sc->id % SLI_PEMS_PER_GROUP; 442 sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE; 443 sc->sli_window_base = SLI_BASE | 444 (((uint64_t)sc->node) << SLI_NODE_SHIFT) | 445 ((uint64_t)sc->sli_group << SLI_GROUP_SHIFT); 446 sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli; 447 448 return (0); 449 } 450 451 static void 452 thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc, 453 int sli_group, int slix) 454 { 455 uint64_t regval; 456 bus_space_handle_t handle = 0; 457 458 KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index")); 459 460 if (sli_group == 0) 461 handle = sli0_s2m_regx_base; 462 else if (sli_group == 1) 463 handle = sli1_s2m_regx_base; 464 else 465 device_printf(sc->dev, "SLI group is not correct\n"); 466 467 if (handle) { 468 /* Clear lower 32-bits of the SLIx register */ 469 regval = bus_space_read_8(sc->reg_bst, handle, 470 PEM_CFG_SLIX_TO_REG(slix)); 471 regval &= ~(0xFFFFFFFFUL); 472 bus_space_write_8(sc->reg_bst, handle, 473 PEM_CFG_SLIX_TO_REG(slix), regval); 474 } 475 } 476 477 static int 478 thunder_pem_link_init(struct thunder_pem_softc *sc) 479 { 480 uint64_t regval; 481 482 /* check whether PEM is safe to access. */ 483 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG); 484 if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) { 485 device_printf(sc->dev, "PEM%d is not ON\n", sc->id); 486 return (ENXIO); 487 } 488 489 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS); 490 regval |= PEM_LINK_ENABLE; 491 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval); 492 493 /* Wait 1ms as per Cavium specification */ 494 DELAY(1000); 495 496 regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032); 497 498 if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) { 499 device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n", 500 sc->id); 501 return (ENXIO); 502 } 503 504 return (0); 505 } 506 507 static int 508 thunder_pem_init(struct thunder_pem_softc *sc) 509 { 510 int i, retval = 0; 511 512 retval = thunder_pem_link_init(sc); 513 if (retval) { 514 device_printf(sc->dev, "%s failed\n", __func__); 515 return retval; 516 } 517 518 /* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */ 519 for (i = 0; i < SLI_ACC_REG_CNT; i++) { 520 thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i); 521 } 522 523 return (retval); 524 } 525 526 static uint64_t 527 thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg) 528 { 529 uint64_t data; 530 531 /* Write to ADDR register */ 532 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 533 PEM_CFG_RD_REG_ALIGN(reg)); 534 bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8, 535 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 536 /* Read from DATA register */ 537 data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh, 538 PEM_CFG_RD)); 539 540 return (data); 541 } 542 543 static uint32_t 544 thunder_pem_read_config(device_t dev, u_int bus, u_int slot, 545 u_int func, u_int reg, int bytes) 546 { 547 uint64_t offset; 548 uint32_t data; 549 struct thunder_pem_softc *sc; 550 bus_space_tag_t t; 551 bus_space_handle_t h; 552 553 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 554 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 555 return (~0U); 556 557 sc = device_get_softc(dev); 558 559 /* Calculate offset */ 560 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 561 (func << PEM_FUNC_SHIFT); 562 t = sc->reg_bst; 563 h = sc->pem_sli_base; 564 565 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 566 PCIE_REGMAX, 0, &h); 567 568 switch (bytes) { 569 case 1: 570 data = bus_space_read_1(t, h, reg); 571 break; 572 case 2: 573 data = le16toh(bus_space_read_2(t, h, reg)); 574 break; 575 case 4: 576 data = le32toh(bus_space_read_4(t, h, reg)); 577 break; 578 default: 579 data = ~0U; 580 break; 581 } 582 583 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 584 585 return (data); 586 } 587 588 static void 589 thunder_pem_write_config(device_t dev, u_int bus, u_int slot, 590 u_int func, u_int reg, uint32_t val, int bytes) 591 { 592 uint64_t offset; 593 struct thunder_pem_softc *sc; 594 bus_space_tag_t t; 595 bus_space_handle_t h; 596 597 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 598 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 599 return; 600 601 sc = device_get_softc(dev); 602 603 /* Calculate offset */ 604 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 605 (func << PEM_FUNC_SHIFT); 606 t = sc->reg_bst; 607 h = sc->pem_sli_base; 608 609 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 610 PCIE_REGMAX, 0, &h); 611 612 switch (bytes) { 613 case 1: 614 bus_space_write_1(t, h, reg, val); 615 break; 616 case 2: 617 bus_space_write_2(t, h, reg, htole16(val)); 618 break; 619 case 4: 620 bus_space_write_4(t, h, reg, htole32(val)); 621 break; 622 default: 623 break; 624 } 625 626 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 627 } 628 629 static struct resource * 630 thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid, 631 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 632 { 633 struct thunder_pem_softc *sc = device_get_softc(dev); 634 struct rman *rm = NULL; 635 struct resource *res; 636 device_t parent_dev; 637 638 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 639 if (type == PCI_RES_BUS) 640 return (pci_domain_alloc_bus(sc->id, child, rid, start, end, 641 count, flags)); 642 #endif 643 rm = thunder_pem_rman(sc, type); 644 if (rm == NULL) { 645 /* Find parent device. On ThunderX we know an exact path. */ 646 parent_dev = device_get_parent(device_get_parent(dev)); 647 return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start, 648 end, count, flags)); 649 } 650 651 if (!RMAN_IS_DEFAULT_RANGE(start, end)) { 652 /* 653 * We might get PHYS addresses here inherited from EFI. 654 * Convert to PCI if necessary. 655 */ 656 if (range_addr_is_phys(sc->ranges, start, count)) { 657 start = range_addr_phys_to_pci(sc->ranges, start); 658 end = start + count - 1; 659 } 660 } 661 662 if (bootverbose) { 663 device_printf(dev, 664 "thunder_pem_alloc_resource: start=%#lx, end=%#lx, count=%#lx\n", 665 start, end, count); 666 } 667 668 res = rman_reserve_resource(rm, start, end, count, flags, child); 669 if (res == NULL) 670 goto fail; 671 672 rman_set_rid(res, *rid); 673 674 if (flags & RF_ACTIVE) 675 if (bus_activate_resource(child, type, *rid, res)) { 676 rman_release_resource(res); 677 goto fail; 678 } 679 680 return (res); 681 682 fail: 683 if (bootverbose) { 684 device_printf(dev, "%s FAIL: type=%d, rid=%d, " 685 "start=%016lx, end=%016lx, count=%016lx, flags=%x\n", 686 __func__, type, *rid, start, end, count, flags); 687 } 688 689 return (NULL); 690 } 691 692 static int 693 thunder_pem_release_resource(device_t dev, device_t child, int type, int rid, 694 struct resource *res) 695 { 696 device_t parent_dev; 697 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 698 struct thunder_pem_softc *sc = device_get_softc(dev); 699 700 if (type == PCI_RES_BUS) 701 return (pci_domain_release_bus(sc->id, child, rid, res)); 702 #endif 703 /* Find parent device. On ThunderX we know an exact path. */ 704 parent_dev = device_get_parent(device_get_parent(dev)); 705 706 if ((type != SYS_RES_MEMORY) && (type != SYS_RES_IOPORT)) 707 return (BUS_RELEASE_RESOURCE(parent_dev, child, 708 type, rid, res)); 709 710 return (rman_release_resource(res)); 711 } 712 713 static struct rman * 714 thunder_pem_rman(struct thunder_pem_softc *sc, int type) 715 { 716 717 switch (type) { 718 case SYS_RES_IOPORT: 719 return (&sc->io_rman); 720 case SYS_RES_MEMORY: 721 return (&sc->mem_rman); 722 default: 723 break; 724 } 725 726 return (NULL); 727 } 728 729 static int 730 thunder_pem_probe(device_t dev) 731 { 732 uint16_t pci_vendor_id; 733 uint16_t pci_device_id; 734 735 pci_vendor_id = pci_get_vendor(dev); 736 pci_device_id = pci_get_device(dev); 737 738 if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) && 739 (pci_device_id == THUNDER_PEM_DEVICE_ID)) { 740 device_set_desc_copy(dev, THUNDER_PEM_DESC); 741 return (0); 742 } 743 744 return (ENXIO); 745 } 746 747 static int 748 thunder_pem_attach(device_t dev) 749 { 750 struct resource_map_request req; 751 struct resource_map map; 752 devclass_t pci_class; 753 device_t parent; 754 struct thunder_pem_softc *sc; 755 int error; 756 int rid; 757 int tuple; 758 uint64_t base, size; 759 struct rman *rman; 760 761 sc = device_get_softc(dev); 762 sc->dev = dev; 763 764 /* Allocate memory for resource */ 765 pci_class = devclass_find("pci"); 766 parent = device_get_parent(dev); 767 if (device_get_devclass(parent) == pci_class) 768 rid = PCIR_BAR(0); 769 else 770 rid = RID_PEM_SPACE; 771 772 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 773 &rid, RF_ACTIVE | RF_UNMAPPED); 774 if (sc->reg == NULL) { 775 device_printf(dev, "Failed to allocate resource\n"); 776 return (ENXIO); 777 } 778 resource_init_map_request(&req); 779 req.memattr = VM_MEMATTR_DEVICE_NP; 780 error = bus_map_resource(dev, SYS_RES_MEMORY, sc->reg, &req, &map); 781 if (error != 0) { 782 device_printf(dev, "could not map memory.\n"); 783 return (error); 784 } 785 rman_set_mapping(sc->reg, &map); 786 787 sc->reg_bst = rman_get_bustag(sc->reg); 788 sc->reg_bsh = rman_get_bushandle(sc->reg); 789 790 /* Create the parent DMA tag to pass down the coherent flag */ 791 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 792 1, 0, /* alignment, bounds */ 793 BUS_SPACE_MAXADDR, /* lowaddr */ 794 BUS_SPACE_MAXADDR, /* highaddr */ 795 NULL, NULL, /* filter, filterarg */ 796 BUS_SPACE_MAXSIZE, /* maxsize */ 797 BUS_SPACE_UNRESTRICTED, /* nsegments */ 798 BUS_SPACE_MAXSIZE, /* maxsegsize */ 799 BUS_DMA_COHERENT, /* flags */ 800 NULL, NULL, /* lockfunc, lockarg */ 801 &sc->dmat); 802 if (error != 0) 803 return (error); 804 805 /* Map SLI, do it only once */ 806 if (!sli0_s2m_regx_base) { 807 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC, 808 SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base); 809 } 810 if (!sli1_s2m_regx_base) { 811 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC + 812 SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0, 813 &sli1_s2m_regx_base); 814 } 815 816 if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) { 817 device_printf(dev, 818 "bus_space_map failed to map slix_s2m_regx_base\n"); 819 goto fail; 820 } 821 822 /* Identify PEM */ 823 if (thunder_pem_identify(dev) != 0) 824 goto fail; 825 826 /* Initialize rman and allocate regions */ 827 sc->mem_rman.rm_type = RMAN_ARRAY; 828 sc->mem_rman.rm_descr = "PEM PCIe Memory"; 829 error = rman_init(&sc->mem_rman); 830 if (error != 0) { 831 device_printf(dev, "memory rman_init() failed. error = %d\n", 832 error); 833 goto fail; 834 } 835 sc->io_rman.rm_type = RMAN_ARRAY; 836 sc->io_rman.rm_descr = "PEM PCIe IO"; 837 error = rman_init(&sc->io_rman); 838 if (error != 0) { 839 device_printf(dev, "IO rman_init() failed. error = %d\n", 840 error); 841 goto fail_mem; 842 } 843 844 /* 845 * We ignore the values that may have been provided in FDT 846 * and configure ranges according to the below formula 847 * for all types of devices. This is because some DTBs provided 848 * by EFI do not have proper ranges property or don't have them 849 * at all. 850 */ 851 /* Fill memory window */ 852 sc->ranges[0].pci_base = PCI_MEMORY_BASE; 853 sc->ranges[0].size = PCI_MEMORY_SIZE; 854 sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 855 sc->ranges[0].pci_base; 856 sc->ranges[0].flags = SYS_RES_MEMORY; 857 858 /* Fill IO window */ 859 sc->ranges[1].pci_base = PCI_IO_BASE; 860 sc->ranges[1].size = PCI_IO_SIZE; 861 sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 862 sc->ranges[1].pci_base; 863 sc->ranges[1].flags = SYS_RES_IOPORT; 864 865 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 866 base = sc->ranges[tuple].pci_base; 867 size = sc->ranges[tuple].size; 868 if (size == 0) 869 continue; /* empty range element */ 870 871 rman = thunder_pem_rman(sc, sc->ranges[tuple].flags); 872 if (rman != NULL) 873 error = rman_manage_region(rman, base, 874 base + size - 1); 875 else 876 error = EINVAL; 877 if (error) { 878 device_printf(dev, 879 "rman_manage_region() failed. error = %d\n", error); 880 rman_fini(&sc->mem_rman); 881 return (error); 882 } 883 if (bootverbose) { 884 device_printf(dev, 885 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx, Flags:0x%jx\n", 886 sc->ranges[tuple].pci_base, 887 sc->ranges[tuple].phys_base, 888 sc->ranges[tuple].size, 889 sc->ranges[tuple].flags); 890 } 891 } 892 893 if (thunder_pem_init(sc)) { 894 device_printf(dev, "Failure during PEM init\n"); 895 goto fail_io; 896 } 897 898 device_add_child(dev, "pci", -1); 899 900 return (bus_generic_attach(dev)); 901 902 fail_io: 903 rman_fini(&sc->io_rman); 904 fail_mem: 905 rman_fini(&sc->mem_rman); 906 fail: 907 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 908 return (ENXIO); 909 } 910 911 static void 912 thunder_pem_release_all(device_t dev) 913 { 914 struct thunder_pem_softc *sc; 915 916 sc = device_get_softc(dev); 917 918 rman_fini(&sc->io_rman); 919 rman_fini(&sc->mem_rman); 920 921 if (sc->reg != NULL) 922 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 923 } 924 925 static int 926 thunder_pem_detach(device_t dev) 927 { 928 929 thunder_pem_release_all(dev); 930 931 return (0); 932 } 933