1 /*- 2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/rman.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <machine/bus.h> 38 39 #include <arm64/coresight/coresight.h> 40 #include <arm64/coresight/coresight_tmc.h> 41 42 #include "coresight_if.h" 43 44 #define TMC_DEBUG 45 #undef TMC_DEBUG 46 47 #ifdef TMC_DEBUG 48 #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) 49 #else 50 #define dprintf(fmt, ...) 51 #endif 52 53 static struct resource_spec tmc_spec[] = { 54 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 55 { -1, 0 } 56 }; 57 58 static int 59 tmc_start(device_t dev) 60 { 61 struct tmc_softc *sc; 62 uint32_t reg; 63 64 sc = device_get_softc(dev); 65 66 if (bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) 67 return (-1); 68 69 /* Enable TMC */ 70 bus_write_4(sc->res, TMC_CTL, CTL_TRACECAPTEN); 71 if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0) 72 panic("Not enabled\n"); 73 74 do { 75 reg = bus_read_4(sc->res, TMC_STS); 76 } while ((reg & STS_TMCREADY) == 1); 77 78 if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0) 79 panic("Not enabled\n"); 80 81 return (0); 82 } 83 84 static int 85 tmc_stop(device_t dev) 86 { 87 struct tmc_softc *sc; 88 uint32_t reg; 89 90 sc = device_get_softc(dev); 91 92 reg = bus_read_4(sc->res, TMC_CTL); 93 reg &= ~CTL_TRACECAPTEN; 94 bus_write_4(sc->res, TMC_CTL, reg); 95 96 do { 97 reg = bus_read_4(sc->res, TMC_STS); 98 } while ((reg & STS_TMCREADY) == 1); 99 100 return (0); 101 } 102 103 static int 104 tmc_configure_etf(device_t dev) 105 { 106 struct tmc_softc *sc; 107 uint32_t reg; 108 109 sc = device_get_softc(dev); 110 111 do { 112 reg = bus_read_4(sc->res, TMC_STS); 113 } while ((reg & STS_TMCREADY) == 0); 114 115 bus_write_4(sc->res, TMC_MODE, MODE_HW_FIFO); 116 bus_write_4(sc->res, TMC_FFCR, FFCR_EN_FMT | FFCR_EN_TI); 117 118 tmc_start(dev); 119 120 dprintf("%s: STS %x, CTL %x, RSZ %x, RRP %x, RWP %x, " 121 "LBUFLEVEL %x, CBUFLEVEL %x\n", __func__, 122 bus_read_4(sc->res, TMC_STS), 123 bus_read_4(sc->res, TMC_CTL), 124 bus_read_4(sc->res, TMC_RSZ), 125 bus_read_4(sc->res, TMC_RRP), 126 bus_read_4(sc->res, TMC_RWP), 127 bus_read_4(sc->res, TMC_CBUFLEVEL), 128 bus_read_4(sc->res, TMC_LBUFLEVEL)); 129 130 return (0); 131 } 132 133 static int 134 tmc_configure_etr(device_t dev, struct endpoint *endp, 135 struct coresight_event *event) 136 { 137 struct tmc_softc *sc; 138 uint32_t reg; 139 140 sc = device_get_softc(dev); 141 142 tmc_stop(dev); 143 144 do { 145 reg = bus_read_4(sc->res, TMC_STS); 146 } while ((reg & STS_TMCREADY) == 0); 147 148 /* Configure TMC */ 149 bus_write_4(sc->res, TMC_MODE, MODE_CIRCULAR_BUFFER); 150 151 reg = AXICTL_PROT_CTRL_BIT1; 152 reg |= AXICTL_WRBURSTLEN_16; 153 154 /* 155 * SG operation is broken on DragonBoard 410c 156 * reg |= AXICTL_SG_MODE; 157 */ 158 159 reg |= AXICTL_AXCACHE_OS; 160 bus_write_4(sc->res, TMC_AXICTL, reg); 161 162 reg = FFCR_EN_FMT | FFCR_EN_TI | FFCR_FON_FLIN | 163 FFCR_FON_TRIG_EVT | FFCR_TRIGON_TRIGIN; 164 bus_write_4(sc->res, TMC_FFCR, reg); 165 166 bus_write_4(sc->res, TMC_TRG, 8); 167 168 bus_write_4(sc->res, TMC_DBALO, event->etr.low); 169 bus_write_4(sc->res, TMC_DBAHI, event->etr.high); 170 bus_write_4(sc->res, TMC_RSZ, event->etr.bufsize / 4); 171 172 bus_write_4(sc->res, TMC_RRP, event->etr.low); 173 bus_write_4(sc->res, TMC_RWP, event->etr.low); 174 175 reg = bus_read_4(sc->res, TMC_STS); 176 reg &= ~STS_FULL; 177 bus_write_4(sc->res, TMC_STS, reg); 178 179 tmc_start(dev); 180 181 return (0); 182 } 183 184 static int 185 tmc_init(device_t dev) 186 { 187 struct tmc_softc *sc; 188 uint32_t reg; 189 190 sc = device_get_softc(dev); 191 192 /* Unlock Coresight */ 193 bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK); 194 195 /* Unlock TMC */ 196 bus_write_4(sc->res, TMC_LAR, CORESIGHT_UNLOCK); 197 198 reg = bus_read_4(sc->res, TMC_DEVID); 199 reg &= DEVID_CONFIGTYPE_M; 200 switch (reg) { 201 case DEVID_CONFIGTYPE_ETR: 202 sc->dev_type = CORESIGHT_ETR; 203 dprintf(dev, "ETR configuration found\n"); 204 break; 205 case DEVID_CONFIGTYPE_ETF: 206 sc->dev_type = CORESIGHT_ETF; 207 dprintf(dev, "ETF configuration found\n"); 208 if (sc->etf_configured == false) { 209 tmc_configure_etf(dev); 210 sc->etf_configured = true; 211 } 212 break; 213 default: 214 sc->dev_type = CORESIGHT_UNKNOWN; 215 break; 216 } 217 218 return (0); 219 } 220 221 static int 222 tmc_enable(device_t dev, struct endpoint *endp, 223 struct coresight_event *event) 224 { 225 struct tmc_softc *sc; 226 uint32_t nev; 227 228 sc = device_get_softc(dev); 229 230 if (sc->dev_type == CORESIGHT_ETF) 231 return (0); 232 233 KASSERT(sc->dev_type == CORESIGHT_ETR, 234 ("Wrong dev_type")); 235 236 /* 237 * Multiple CPUs can call this same time. 238 * We allow only one running configuration. 239 */ 240 241 if (event->etr.flags & ETR_FLAG_ALLOCATE) { 242 event->etr.flags &= ~ETR_FLAG_ALLOCATE; 243 nev = atomic_fetchadd_int(&sc->nev, 1); 244 if (nev == 0) { 245 sc->event = event; 246 tmc_stop(dev); 247 tmc_configure_etr(dev, endp, event); 248 tmc_start(dev); 249 } 250 } 251 252 return (0); 253 } 254 255 static void 256 tmc_disable(device_t dev, struct endpoint *endp, 257 struct coresight_event *event) 258 { 259 struct tmc_softc *sc; 260 uint32_t nev; 261 262 sc = device_get_softc(dev); 263 264 /* ETF configuration is static */ 265 if (sc->dev_type == CORESIGHT_ETF) 266 return; 267 268 KASSERT(sc->dev_type == CORESIGHT_ETR, ("Wrong dev_type")); 269 270 if (event->etr.flags & ETR_FLAG_RELEASE) { 271 event->etr.flags &= ~ETR_FLAG_RELEASE; 272 nev = atomic_fetchadd_int(&sc->nev, -1); 273 if (nev == 1) { 274 tmc_stop(dev); 275 sc->event = NULL; 276 } 277 } 278 } 279 280 static int 281 tmc_read(device_t dev, struct endpoint *endp, 282 struct coresight_event *event) 283 { 284 struct tmc_softc *sc; 285 uint32_t cur_ptr; 286 287 sc = device_get_softc(dev); 288 289 if (sc->dev_type == CORESIGHT_ETF) 290 return (0); 291 292 /* 293 * Ensure the event we are reading information for 294 * is currently configured one. 295 */ 296 if (sc->event != event) 297 return (0); 298 299 if (bus_read_4(sc->res, TMC_STS) & STS_FULL) { 300 event->etr.offset = 0; 301 event->etr.cycle++; 302 tmc_stop(dev); 303 tmc_start(dev); 304 } else { 305 cur_ptr = bus_read_4(sc->res, TMC_RWP); 306 event->etr.offset = (cur_ptr - event->etr.low); 307 } 308 309 return (0); 310 } 311 312 int 313 tmc_attach(device_t dev) 314 { 315 struct coresight_desc desc; 316 struct tmc_softc *sc; 317 318 sc = device_get_softc(dev); 319 sc->dev = dev; 320 321 if (bus_alloc_resources(dev, tmc_spec, &sc->res) != 0) { 322 device_printf(dev, "cannot allocate resources for device\n"); 323 return (ENXIO); 324 } 325 326 desc.pdata = sc->pdata; 327 desc.dev = dev; 328 desc.dev_type = CORESIGHT_TMC; 329 coresight_register(&desc); 330 331 return (0); 332 } 333 334 static device_method_t tmc_methods[] = { 335 /* Device interface */ 336 DEVMETHOD(device_attach, tmc_attach), 337 338 /* Coresight interface */ 339 DEVMETHOD(coresight_init, tmc_init), 340 DEVMETHOD(coresight_enable, tmc_enable), 341 DEVMETHOD(coresight_disable, tmc_disable), 342 DEVMETHOD(coresight_read, tmc_read), 343 DEVMETHOD_END 344 }; 345 346 DEFINE_CLASS_0(tmc, tmc_driver, tmc_methods, sizeof(struct tmc_softc)); 347