1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 32 #include <dev/extres/clk/clk.h> 33 34 #include <arm64/freescale/imx/clk/imx_clk_frac_pll.h> 35 36 #include "clkdev_if.h" 37 38 struct imx_clk_frac_pll_sc { 39 uint32_t offset; 40 }; 41 42 #define WRITE4(_clk, off, val) \ 43 CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) 44 #define READ4(_clk, off, val) \ 45 CLKDEV_READ_4(clknode_get_device(_clk), off, val) 46 #define DEVICE_LOCK(_clk) \ 47 CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) 48 #define DEVICE_UNLOCK(_clk) \ 49 CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) 50 51 #define CFG0 0 52 #define CFG0_PLL_LOCK (1 << 31) 53 #define CFG0_PD (1 << 19) 54 #define CFG0_BYPASS (1 << 14) 55 #define CFG0_NEWDIV_VAL (1 << 12) 56 #define CFG0_NEWDIV_ACK (1 << 11) 57 #define CFG0_OUTPUT_DIV_MASK (0x1f << 0) 58 #define CFG0_OUTPUT_DIV_SHIFT 0 59 #define CFG1 4 60 #define CFG1_FRAC_DIV_MASK (0xffffff << 7) 61 #define CFG1_FRAC_DIV_SHIFT 7 62 #define CFG1_INT_DIV_MASK (0x7f << 0) 63 #define CFG1_INT_DIV_SHIFT 0 64 65 #if 0 66 #define dprintf(format, arg...) \ 67 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) 68 #else 69 #define dprintf(format, arg...) 70 #endif 71 72 static int 73 imx_clk_frac_pll_init(struct clknode *clk, device_t dev) 74 { 75 76 clknode_init_parent_idx(clk, 0); 77 return (0); 78 } 79 80 static int 81 imx_clk_frac_pll_set_gate(struct clknode *clk, bool enable) 82 { 83 struct imx_clk_frac_pll_sc *sc; 84 uint32_t cfg0; 85 int timeout; 86 87 sc = clknode_get_softc(clk); 88 89 DEVICE_LOCK(clk); 90 READ4(clk, sc->offset + CFG0, &cfg0); 91 if (enable) 92 cfg0 &= ~(CFG0_PD); 93 else 94 cfg0 |= CFG0_PD; 95 WRITE4(clk, sc->offset + CFG0, cfg0); 96 97 /* Wait for PLL to lock */ 98 if (enable && ((cfg0 & CFG0_BYPASS) == 0)) { 99 for (timeout = 1000; timeout; timeout--) { 100 READ4(clk, sc->offset + CFG0, &cfg0); 101 if (cfg0 & CFG0_PLL_LOCK) 102 break; 103 DELAY(1); 104 } 105 } 106 107 DEVICE_UNLOCK(clk); 108 109 return (0); 110 } 111 112 static int 113 imx_clk_frac_pll_recalc(struct clknode *clk, uint64_t *freq) 114 { 115 struct imx_clk_frac_pll_sc *sc; 116 uint32_t cfg0, cfg1; 117 uint64_t div, divfi, divff, divf_val; 118 119 sc = clknode_get_softc(clk); 120 121 DEVICE_LOCK(clk); 122 READ4(clk, sc->offset + CFG0, &cfg0); 123 READ4(clk, sc->offset + CFG1, &cfg1); 124 DEVICE_UNLOCK(clk); 125 126 div = (cfg0 & CFG0_OUTPUT_DIV_MASK) >> CFG0_OUTPUT_DIV_SHIFT; 127 div = (div + 1) * 2; 128 divff = (cfg1 & CFG1_FRAC_DIV_MASK) >> CFG1_FRAC_DIV_SHIFT; 129 divfi = (cfg1 & CFG1_INT_DIV_MASK) >> CFG1_INT_DIV_SHIFT; 130 131 /* PLL is bypassed */ 132 if (cfg0 & CFG0_BYPASS) 133 return (0); 134 135 divf_val = 1 + divfi + (divff/0x1000000); 136 *freq = *freq * 8 * divf_val / div; 137 138 return (0); 139 } 140 141 static clknode_method_t imx_clk_frac_pll_clknode_methods[] = { 142 /* Device interface */ 143 CLKNODEMETHOD(clknode_init, imx_clk_frac_pll_init), 144 CLKNODEMETHOD(clknode_set_gate, imx_clk_frac_pll_set_gate), 145 CLKNODEMETHOD(clknode_recalc_freq, imx_clk_frac_pll_recalc), 146 CLKNODEMETHOD_END 147 }; 148 149 DEFINE_CLASS_1(imx_clk_frac_pll_clknode, imx_clk_frac_pll_clknode_class, 150 imx_clk_frac_pll_clknode_methods, sizeof(struct imx_clk_frac_pll_sc), 151 clknode_class); 152 153 int 154 imx_clk_frac_pll_register(struct clkdom *clkdom, 155 struct imx_clk_frac_pll_def *clkdef) 156 { 157 struct clknode *clk; 158 struct imx_clk_frac_pll_sc *sc; 159 160 clk = clknode_create(clkdom, &imx_clk_frac_pll_clknode_class, 161 &clkdef->clkdef); 162 if (clk == NULL) 163 return (1); 164 165 sc = clknode_get_softc(clk); 166 167 sc->offset = clkdef->offset; 168 169 clknode_register(clkdom, clk); 170 171 return (0); 172 } 173