1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _MACHINE_HYPERVISOR_H_ 30 #define _MACHINE_HYPERVISOR_H_ 31 32 /* 33 * These registers are only useful when in hypervisor context, 34 * e.g. specific to EL2, or controlling the hypervisor. 35 */ 36 37 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 38 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 39 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 40 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 41 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 42 #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 43 44 /* CPTR_EL2 - Architecture feature trap register */ 45 #define CPTR_RES0 0x7fefc800 46 #define CPTR_RES1 0x000033ff 47 #define CPTR_TFP 0x00000400 48 #define CPTR_TTA 0x00100000 49 #define CPTR_TCPAC 0x80000000 50 51 /* HCR_EL2 - Hypervisor Config Register */ 52 #define HCR_VM 0x0000000000000001 53 #define HCR_SWIO 0x0000000000000002 54 #define HCR_PTW 0x0000000000000004 55 #define HCR_FMO 0x0000000000000008 56 #define HCR_IMO 0x0000000000000010 57 #define HCR_AMO 0x0000000000000020 58 #define HCR_VF 0x0000000000000040 59 #define HCR_VI 0x0000000000000080 60 #define HCR_VSE 0x0000000000000100 61 #define HCR_FB 0x0000000000000200 62 #define HCR_BSU_MASK 0x0000000000000c00 63 #define HCR_BSU_IS 0x0000000000000400 64 #define HCR_BSU_OS 0x0000000000000800 65 #define HCR_BSU_FS 0x0000000000000c00 66 #define HCR_DC 0x0000000000001000 67 #define HCR_TWI 0x0000000000002000 68 #define HCR_TWE 0x0000000000004000 69 #define HCR_TID0 0x0000000000008000 70 #define HCR_TID1 0x0000000000010000 71 #define HCR_TID2 0x0000000000020000 72 #define HCR_TID3 0x0000000000040000 73 #define HCR_TSC 0x0000000000080000 74 #define HCR_TIDCP 0x0000000000100000 75 #define HCR_TACR 0x0000000000200000 76 #define HCR_TSW 0x0000000000400000 77 #define HCR_TPCP 0x0000000000800000 78 #define HCR_TPU 0x0000000001000000 79 #define HCR_TTLB 0x0000000002000000 80 #define HCR_TVM 0x0000000004000000 81 #define HCR_TGE 0x0000000008000000 82 #define HCR_TDZ 0x0000000010000000 83 #define HCR_HCD 0x0000000020000000 84 #define HCR_TRVM 0x0000000040000000 85 #define HCR_RW 0x0000000080000000 86 #define HCR_CD 0x0000000100000000 87 #define HCR_ID 0x0000000200000000 88 #define HCR_E2H 0x0000000400000000 89 #define HCR_TLOR 0x0000000800000000 90 #define HCR_TERR 0x0000001000000000 91 #define HCR_TEA 0x0000002000000000 92 #define HCR_MIOCNCE 0x0000004000000000 93 /* Bit 39 is reserved */ 94 #define HCR_APK 0x0000010000000000 95 #define HCR_API 0x0000020000000000 96 #define HCR_NV 0x0000040000000000 97 #define HCR_NV1 0x0000080000000000 98 #define HCR_AT 0x0000100000000000 99 100 /* HPFAR_EL2 - Hypervisor IPA Fault Address Register */ 101 #define HPFAR_EL2_FIPA_SHIFT 4 102 #define HPFAR_EL2_FIPA_MASK 0xfffffffff0 103 104 /* ICC_SRE_EL2 */ 105 #define ICC_SRE_EL2_SRE (1U << 0) 106 #define ICC_SRE_EL2_EN (1U << 3) 107 108 /* SCTLR_EL2 - System Control Register */ 109 #define SCTLR_EL2_RES1 0x30c50830 110 #define SCTLR_EL2_M_SHIFT 0 111 #define SCTLR_EL2_M (0x1 << SCTLR_EL2_M_SHIFT) 112 #define SCTLR_EL2_A_SHIFT 1 113 #define SCTLR_EL2_A (0x1 << SCTLR_EL2_A_SHIFT) 114 #define SCTLR_EL2_C_SHIFT 2 115 #define SCTLR_EL2_C (0x1 << SCTLR_EL2_C_SHIFT) 116 #define SCTLR_EL2_SA_SHIFT 3 117 #define SCTLR_EL2_SA (0x1 << SCTLR_EL2_SA_SHIFT) 118 #define SCTLR_EL2_I_SHIFT 12 119 #define SCTLR_EL2_I (0x1 << SCTLR_EL2_I_SHIFT) 120 #define SCTLR_EL2_WXN_SHIFT 19 121 #define SCTLR_EL2_WXN (0x1 << SCTLR_EL2_WXN_SHIFT) 122 #define SCTLR_EL2_EE_SHIFT 25 123 #define SCTLR_EL2_EE (0x1 << SCTLR_EL2_EE_SHIFT) 124 125 /* TCR_EL2 - Translation Control Register */ 126 #define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23)) 127 #define TCR_EL2_T0SZ_SHIFT 0 128 #define TCR_EL2_T0SZ_MASK (0x3f << TCR_EL2_T0SZ_SHIFT) 129 #define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT) 130 /* Bits 7:6 are reserved */ 131 #define TCR_EL2_IRGN0_SHIFT 8 132 #define TCR_EL2_IRGN0_MASK (0x3 << TCR_EL2_IRGN0_SHIFT) 133 #define TCR_EL2_ORGN0_SHIFT 10 134 #define TCR_EL2_ORGN0_MASK (0x3 << TCR_EL2_ORGN0_SHIFT) 135 #define TCR_EL2_SH0_SHIFT 12 136 #define TCR_EL2_SH0_MASK (0x3 << TCR_EL2_SH0_SHIFT) 137 #define TCR_EL2_TG0_SHIFT 14 138 #define TCR_EL2_TG0_MASK (0x3 << TCR_EL2_TG0_SHIFT) 139 #define TCR_EL2_PS_SHIFT 16 140 #define TCR_EL2_PS_32BITS (0 << TCR_EL2_PS_SHIFT) 141 #define TCR_EL2_PS_36BITS (1 << TCR_EL2_PS_SHIFT) 142 #define TCR_EL2_PS_40BITS (2 << TCR_EL2_PS_SHIFT) 143 #define TCR_EL2_PS_42BITS (3 << TCR_EL2_PS_SHIFT) 144 #define TCR_EL2_PS_44BITS (4 << TCR_EL2_PS_SHIFT) 145 #define TCR_EL2_PS_48BITS (5 << TCR_EL2_PS_SHIFT) 146 #define TCR_EL2_PS_52BITS (6 << TCR_EL2_PS_SHIFT) /* ARMv8.2-LPA */ 147 148 /* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */ 149 #define VMPIDR_EL2_U 0x0000000040000000 150 #define VMPIDR_EL2_MT 0x0000000001000000 151 #define VMPIDR_EL2_RES1 0x0000000080000000 152 153 /* VTCR_EL2 - Virtualization Translation Control Register */ 154 #define VTCR_EL2_RES1 (0x1 << 31) 155 #define VTCR_EL2_T0SZ_MASK 0x3f 156 #define VTCR_EL2_SL0_SHIFT 6 157 #define VTCR_EL2_SL0_4K_LVL2 (0x0 << VTCR_EL2_SL0_SHIFT) 158 #define VTCR_EL2_SL0_4K_LVL1 (0x1 << VTCR_EL2_SL0_SHIFT) 159 #define VTCR_EL2_SL0_4K_LVL0 (0x2 << VTCR_EL2_SL0_SHIFT) 160 #define VTCR_EL2_IRGN0_SHIFT 8 161 #define VTCR_EL2_IRGN0_WBWA (0x1 << VTCR_EL2_IRGN0_SHIFT) 162 #define VTCR_EL2_ORGN0_SHIFT 10 163 #define VTCR_EL2_ORGN0_WBWA (0x1 << VTCR_EL2_ORGN0_SHIFT) 164 #define VTCR_EL2_SH0_SHIFT 12 165 #define VTCR_EL2_SH0_NS (0x0 << VTCR_EL2_SH0_SHIFT) 166 #define VTCR_EL2_SH0_OS (0x2 << VTCR_EL2_SH0_SHIFT) 167 #define VTCR_EL2_SH0_IS (0x3 << VTCR_EL2_SH0_SHIFT) 168 #define VTCR_EL2_TG0_SHIFT 14 169 #define VTCR_EL2_TG0_4K (0x0 << VTCR_EL2_TG0_SHIFT) 170 #define VTCR_EL2_TG0_64K (0x1 << VTCR_EL2_TG0_SHIFT) 171 #define VTCR_EL2_TG0_16K (0x2 << VTCR_EL2_TG0_SHIFT) 172 #define VTCR_EL2_PS_SHIFT 16 173 #define VTCR_EL2_PS_32BIT (0x0 << VTCR_EL2_PS_SHIFT) 174 #define VTCR_EL2_PS_36BIT (0x1 << VTCR_EL2_PS_SHIFT) 175 #define VTCR_EL2_PS_40BIT (0x2 << VTCR_EL2_PS_SHIFT) 176 #define VTCR_EL2_PS_42BIT (0x3 << VTCR_EL2_PS_SHIFT) 177 #define VTCR_EL2_PS_44BIT (0x4 << VTCR_EL2_PS_SHIFT) 178 #define VTCR_EL2_PS_48BIT (0x5 << VTCR_EL2_PS_SHIFT) 179 180 /* VTTBR_EL2 - Virtualization Translation Table Base Register */ 181 #define VTTBR_VMID_MASK 0xffff000000000000 182 #define VTTBR_VMID_SHIFT 48 183 #define VTTBR_HOST 0x0000000000000000 184 185 #endif /* !_MACHINE_HYPERVISOR_H_ */ 186