1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com> 5 * 6 * This software was developed by SRI International and the University of 7 * Cambridge Computer Laboratory (Department of Computer Science and 8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the 9 * DARPA SSITH research programme. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 /* 34 * Intel Stratix 10 FPGA Manager. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/malloc.h> 43 #include <sys/rman.h> 44 #include <sys/timeet.h> 45 #include <sys/timetc.h> 46 #include <sys/conf.h> 47 #include <sys/uio.h> 48 #include <sys/sx.h> 49 50 #include <dev/ofw/openfirm.h> 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 54 #include <arm64/intel/stratix10-svc.h> 55 56 #include <machine/bus.h> 57 #include <machine/cpu.h> 58 #include <machine/intr.h> 59 60 #define SVC_BUF_SIZE (2 * 1024 * 1024) 61 62 struct fpgamgr_s10_softc { 63 struct cdev *mgr_cdev; 64 struct cdev *mgr_cdev_partial; 65 device_t dev; 66 device_t s10_svc_dev; 67 struct s10_svc_mem mem; 68 struct sx sx; 69 int opened; 70 }; 71 72 static int 73 fpga_open(struct cdev *dev, int flags __unused, 74 int fmt __unused, struct thread *td __unused) 75 { 76 struct fpgamgr_s10_softc *sc; 77 struct s10_svc_msg msg; 78 int ret; 79 int err; 80 81 sc = dev->si_drv1; 82 83 sx_xlock(&sc->sx); 84 if (sc->opened) { 85 sx_xunlock(&sc->sx); 86 return (EBUSY); 87 } 88 89 err = s10_svc_allocate_memory(sc->s10_svc_dev, 90 &sc->mem, SVC_BUF_SIZE); 91 if (err != 0) { 92 sx_xunlock(&sc->sx); 93 return (ENXIO); 94 } 95 96 bzero(&msg, sizeof(struct s10_svc_msg)); 97 msg.command = COMMAND_RECONFIG; 98 if (dev == sc->mgr_cdev_partial) 99 msg.flags |= COMMAND_RECONFIG_FLAG_PARTIAL; 100 ret = s10_svc_send(sc->s10_svc_dev, &msg); 101 if (ret != 0) { 102 sx_xunlock(&sc->sx); 103 return (ENXIO); 104 } 105 106 sc->opened = 1; 107 sx_xunlock(&sc->sx); 108 109 return (0); 110 } 111 112 static int 113 fpga_write(struct cdev *dev, struct uio *uio, int ioflag) 114 { 115 struct fpgamgr_s10_softc *sc; 116 vm_offset_t addr; 117 int amnt; 118 119 sc = dev->si_drv1; 120 121 sx_xlock(&sc->sx); 122 if (sc->opened == 0) { 123 /* Device closed. */ 124 sx_xunlock(&sc->sx); 125 return (ENXIO); 126 } 127 128 while (uio->uio_resid > 0) { 129 addr = sc->mem.vaddr + sc->mem.fill; 130 if (sc->mem.fill >= SVC_BUF_SIZE) 131 return (ENOMEM); 132 amnt = MIN(uio->uio_resid, (SVC_BUF_SIZE - sc->mem.fill)); 133 uiomove((void *)addr, amnt, uio); 134 sc->mem.fill += amnt; 135 } 136 137 sx_xunlock(&sc->sx); 138 139 return (0); 140 } 141 142 static int 143 fpga_close(struct cdev *dev, int flags __unused, 144 int fmt __unused, struct thread *td __unused) 145 { 146 struct fpgamgr_s10_softc *sc; 147 struct s10_svc_msg msg; 148 int ret; 149 150 sc = dev->si_drv1; 151 152 sx_xlock(&sc->sx); 153 if (sc->opened == 0) { 154 /* Device closed. */ 155 sx_xunlock(&sc->sx); 156 return (ENXIO); 157 } 158 159 /* Submit bitstream */ 160 bzero(&msg, sizeof(struct s10_svc_msg)); 161 msg.command = COMMAND_RECONFIG_DATA_SUBMIT; 162 msg.payload = (void *)sc->mem.paddr; 163 msg.payload_length = sc->mem.fill; 164 ret = s10_svc_send(sc->s10_svc_dev, &msg); 165 if (ret != 0) { 166 device_printf(sc->dev, "Failed to submit data\n"); 167 s10_svc_free_memory(sc->s10_svc_dev, &sc->mem); 168 sc->opened = 0; 169 sx_xunlock(&sc->sx); 170 return (0); 171 } 172 173 /* Claim memory buffer back */ 174 bzero(&msg, sizeof(struct s10_svc_msg)); 175 msg.command = COMMAND_RECONFIG_DATA_CLAIM; 176 s10_svc_send(sc->s10_svc_dev, &msg); 177 178 s10_svc_free_memory(sc->s10_svc_dev, &sc->mem); 179 sc->opened = 0; 180 sx_xunlock(&sc->sx); 181 182 return (0); 183 } 184 185 static int 186 fpga_ioctl(struct cdev *dev, u_long cmd, caddr_t addr, int flags, 187 struct thread *td) 188 { 189 190 return (0); 191 } 192 193 static struct cdevsw fpga_cdevsw = { 194 .d_version = D_VERSION, 195 .d_open = fpga_open, 196 .d_close = fpga_close, 197 .d_write = fpga_write, 198 .d_ioctl = fpga_ioctl, 199 .d_name = "FPGA Manager", 200 }; 201 202 static int 203 fpgamgr_s10_probe(device_t dev) 204 { 205 206 if (!ofw_bus_status_okay(dev)) 207 return (ENXIO); 208 209 if (!ofw_bus_is_compatible(dev, "intel,stratix10-soc-fpga-mgr")) 210 return (ENXIO); 211 212 device_set_desc(dev, "Stratix 10 SOC FPGA Manager"); 213 214 return (BUS_PROBE_DEFAULT); 215 } 216 217 static int 218 fpgamgr_s10_attach(device_t dev) 219 { 220 struct fpgamgr_s10_softc *sc; 221 devclass_t dc; 222 223 sc = device_get_softc(dev); 224 sc->dev = dev; 225 226 dc = devclass_find("s10_svc"); 227 if (dc == NULL) 228 return (ENXIO); 229 230 sc->s10_svc_dev = devclass_get_device(dc, 0); 231 if (sc->s10_svc_dev == NULL) 232 return (ENXIO); 233 234 sc->mgr_cdev = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL, 235 0600, "fpga%d", device_get_unit(sc->dev)); 236 if (sc->mgr_cdev == NULL) { 237 device_printf(dev, "Failed to create character device.\n"); 238 return (ENXIO); 239 } 240 241 sc->mgr_cdev_partial = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL, 242 0600, "fpga_partial%d", device_get_unit(sc->dev)); 243 if (sc->mgr_cdev_partial == NULL) { 244 device_printf(dev, "Failed to create character device.\n"); 245 return (ENXIO); 246 } 247 248 sx_init(&sc->sx, "s10 fpga"); 249 250 sc->mgr_cdev->si_drv1 = sc; 251 sc->mgr_cdev_partial->si_drv1 = sc; 252 253 return (0); 254 } 255 256 static int 257 fpgamgr_s10_detach(device_t dev) 258 { 259 struct fpgamgr_s10_softc *sc; 260 261 sc = device_get_softc(dev); 262 263 destroy_dev(sc->mgr_cdev); 264 destroy_dev(sc->mgr_cdev_partial); 265 266 sx_destroy(&sc->sx); 267 268 return (0); 269 } 270 271 static device_method_t fpgamgr_s10_methods[] = { 272 DEVMETHOD(device_probe, fpgamgr_s10_probe), 273 DEVMETHOD(device_attach, fpgamgr_s10_attach), 274 DEVMETHOD(device_detach, fpgamgr_s10_detach), 275 { 0, 0 } 276 }; 277 278 static driver_t fpgamgr_s10_driver = { 279 "fpgamgr_s10", 280 fpgamgr_s10_methods, 281 sizeof(struct fpgamgr_s10_softc), 282 }; 283 284 DRIVER_MODULE(fpgamgr_s10, simplebus, fpgamgr_s10_driver, 0, 0); 285