xref: /freebsd/sys/arm64/nvidia/tegra210/max77620.c (revision b2f0caf1)
1e9034789SMichal Meloun /*-
2e9034789SMichal Meloun  * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
3e9034789SMichal Meloun  *
4e9034789SMichal Meloun  * Redistribution and use in source and binary forms, with or without
5e9034789SMichal Meloun  * modification, are permitted provided that the following conditions
6e9034789SMichal Meloun  * are met:
7e9034789SMichal Meloun  * 1. Redistributions of source code must retain the above copyright
8e9034789SMichal Meloun  *    notice, this list of conditions and the following disclaimer.
9e9034789SMichal Meloun  * 2. Redistributions in binary form must reproduce the above copyright
10e9034789SMichal Meloun  *    notice, this list of conditions and the following disclaimer in the
11e9034789SMichal Meloun  *    documentation and/or other materials provided with the distribution.
12e9034789SMichal Meloun  *
13e9034789SMichal Meloun  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14e9034789SMichal Meloun  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15e9034789SMichal Meloun  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16e9034789SMichal Meloun  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17e9034789SMichal Meloun  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18e9034789SMichal Meloun  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19e9034789SMichal Meloun  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20e9034789SMichal Meloun  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21e9034789SMichal Meloun  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22e9034789SMichal Meloun  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23e9034789SMichal Meloun  * SUCH DAMAGE.
24e9034789SMichal Meloun  */
25e9034789SMichal Meloun 
26e9034789SMichal Meloun #include <sys/cdefs.h>
27e9034789SMichal Meloun /*
28e9034789SMichal Meloun  * MAX77620 PMIC driver
29e9034789SMichal Meloun  */
30e9034789SMichal Meloun 
31e9034789SMichal Meloun #include <sys/param.h>
32e9034789SMichal Meloun #include <sys/systm.h>
33e9034789SMichal Meloun #include <sys/bus.h>
34e9034789SMichal Meloun #include <sys/gpio.h>
35e9034789SMichal Meloun #include <sys/kernel.h>
36e9034789SMichal Meloun #include <sys/module.h>
37e9034789SMichal Meloun #include <sys/malloc.h>
38e9034789SMichal Meloun #include <sys/rman.h>
39e9034789SMichal Meloun #include <sys/sx.h>
40e9034789SMichal Meloun 
41e9034789SMichal Meloun #include <machine/bus.h>
42e9034789SMichal Meloun 
43*b2f0caf1SEmmanuel Vadot #include <dev/regulator/regulator.h>
44e9034789SMichal Meloun #include <dev/fdt/fdt_pinctrl.h>
45e9034789SMichal Meloun #include <dev/gpio/gpiobusvar.h>
46e9034789SMichal Meloun #include <dev/iicbus/iiconf.h>
47e9034789SMichal Meloun #include <dev/iicbus/iicbus.h>
48e9034789SMichal Meloun #include <dev/ofw/ofw_bus.h>
49e9034789SMichal Meloun #include <dev/ofw/ofw_bus_subr.h>
50e9034789SMichal Meloun 
51c38fe878SEmmanuel Vadot #include <dt-bindings/mfd/max77620.h>
52e9034789SMichal Meloun 
53e9034789SMichal Meloun #include "clock_if.h"
54e9034789SMichal Meloun #include "regdev_if.h"
55e9034789SMichal Meloun 
56e9034789SMichal Meloun #include "max77620.h"
57e9034789SMichal Meloun 
58e9034789SMichal Meloun static struct ofw_compat_data compat_data[] = {
59e9034789SMichal Meloun 	{"maxim,max77620",	1},
60e9034789SMichal Meloun 	{NULL,			0},
61e9034789SMichal Meloun };
62e9034789SMichal Meloun 
63e9034789SMichal Meloun #define	LOCK(_sc)		sx_xlock(&(_sc)->lock)
64e9034789SMichal Meloun #define	UNLOCK(_sc)		sx_xunlock(&(_sc)->lock)
65e9034789SMichal Meloun #define	LOCK_INIT(_sc)		sx_init(&(_sc)->lock, "max77620")
66e9034789SMichal Meloun #define	LOCK_DESTROY(_sc)	sx_destroy(&(_sc)->lock);
67e9034789SMichal Meloun #define	ASSERT_LOCKED(_sc)	sx_assert(&(_sc)->lock, SA_XLOCKED);
68e9034789SMichal Meloun #define	ASSERT_UNLOCKED(_sc)	sx_assert(&(_sc)->lock, SA_UNLOCKED);
69e9034789SMichal Meloun 
70e9034789SMichal Meloun #define	MAX77620_DEVICE_ID	0x0C
71e9034789SMichal Meloun 
72e9034789SMichal Meloun /*
73e9034789SMichal Meloun  * Raw register access function.
74e9034789SMichal Meloun  */
75e9034789SMichal Meloun int
max77620_read(struct max77620_softc * sc,uint8_t reg,uint8_t * val)76e9034789SMichal Meloun max77620_read(struct max77620_softc *sc, uint8_t reg, uint8_t *val)
77e9034789SMichal Meloun {
78e9034789SMichal Meloun 	uint8_t addr;
79e9034789SMichal Meloun 	int rv;
80e9034789SMichal Meloun 	struct iic_msg msgs[2] = {
81e9034789SMichal Meloun 		{0, IIC_M_WR, 1, &addr},
82e9034789SMichal Meloun 		{0, IIC_M_RD, 1, val},
83e9034789SMichal Meloun 	};
84e9034789SMichal Meloun 
85e9034789SMichal Meloun 	msgs[0].slave = sc->bus_addr;
86e9034789SMichal Meloun 	msgs[1].slave = sc->bus_addr;
87e9034789SMichal Meloun 	addr = reg;
88e9034789SMichal Meloun 
89e9034789SMichal Meloun 	rv = iicbus_transfer(sc->dev, msgs, 2);
90e9034789SMichal Meloun 	if (rv != 0) {
91e9034789SMichal Meloun 		device_printf(sc->dev,
92e9034789SMichal Meloun 		    "Error when reading reg 0x%02X, rv: %d\n", reg,  rv);
93e9034789SMichal Meloun 		return (EIO);
94e9034789SMichal Meloun 	}
95e9034789SMichal Meloun 
96e9034789SMichal Meloun 	return (0);
97e9034789SMichal Meloun }
98e9034789SMichal Meloun 
max77620_read_buf(struct max77620_softc * sc,uint8_t reg,uint8_t * buf,size_t size)99e9034789SMichal Meloun int max77620_read_buf(struct max77620_softc *sc, uint8_t reg, uint8_t *buf,
100e9034789SMichal Meloun     size_t size)
101e9034789SMichal Meloun {
102e9034789SMichal Meloun 	uint8_t addr;
103e9034789SMichal Meloun 	int rv;
104e9034789SMichal Meloun 	struct iic_msg msgs[2] = {
105e9034789SMichal Meloun 		{0, IIC_M_WR, 1, &addr},
106e9034789SMichal Meloun 		{0, IIC_M_RD, size, buf},
107e9034789SMichal Meloun 	};
108e9034789SMichal Meloun 
109e9034789SMichal Meloun 	msgs[0].slave = sc->bus_addr;
110e9034789SMichal Meloun 	msgs[1].slave = sc->bus_addr;
111e9034789SMichal Meloun 	addr = reg;
112e9034789SMichal Meloun 
113e9034789SMichal Meloun 	rv = iicbus_transfer(sc->dev, msgs, 2);
114e9034789SMichal Meloun 	if (rv != 0) {
115e9034789SMichal Meloun 		device_printf(sc->dev,
116e9034789SMichal Meloun 		    "Error when reading reg 0x%02X, rv: %d\n", reg,  rv);
117e9034789SMichal Meloun 		return (EIO);
118e9034789SMichal Meloun 	}
119e9034789SMichal Meloun 
120e9034789SMichal Meloun 	return (0);
121e9034789SMichal Meloun }
122e9034789SMichal Meloun 
123e9034789SMichal Meloun int
max77620_write(struct max77620_softc * sc,uint8_t reg,uint8_t val)124e9034789SMichal Meloun max77620_write(struct max77620_softc *sc, uint8_t reg, uint8_t val)
125e9034789SMichal Meloun {
126e9034789SMichal Meloun 	uint8_t data[2];
127e9034789SMichal Meloun 	int rv;
128e9034789SMichal Meloun 
129e9034789SMichal Meloun 	struct iic_msg msgs[1] = {
130e9034789SMichal Meloun 		{0, IIC_M_WR, 2, data},
131e9034789SMichal Meloun 	};
132e9034789SMichal Meloun 
133e9034789SMichal Meloun 	msgs[0].slave = sc->bus_addr;
134e9034789SMichal Meloun 	data[0] = reg;
135e9034789SMichal Meloun 	data[1] = val;
136e9034789SMichal Meloun 
137e9034789SMichal Meloun 	rv = iicbus_transfer(sc->dev, msgs, 1);
138e9034789SMichal Meloun 	if (rv != 0) {
139e9034789SMichal Meloun 		device_printf(sc->dev,
140e9034789SMichal Meloun 		    "Error when writing reg 0x%02X, rv: %d\n", reg, rv);
141e9034789SMichal Meloun 		return (EIO);
142e9034789SMichal Meloun 	}
143e9034789SMichal Meloun 	return (0);
144e9034789SMichal Meloun }
145e9034789SMichal Meloun 
146e9034789SMichal Meloun int
max77620_write_buf(struct max77620_softc * sc,uint8_t reg,uint8_t * buf,size_t size)147e9034789SMichal Meloun max77620_write_buf(struct max77620_softc *sc, uint8_t reg, uint8_t *buf,
148e9034789SMichal Meloun     size_t size)
149e9034789SMichal Meloun {
150e9034789SMichal Meloun 	uint8_t data[1];
151e9034789SMichal Meloun 	int rv;
152e9034789SMichal Meloun 	struct iic_msg msgs[2] = {
153e9034789SMichal Meloun 		{0, IIC_M_WR, 1, data},
154e9034789SMichal Meloun 		{0, IIC_M_WR | IIC_M_NOSTART, size, buf},
155e9034789SMichal Meloun 	};
156e9034789SMichal Meloun 
157e9034789SMichal Meloun 	msgs[0].slave = sc->bus_addr;
158e9034789SMichal Meloun 	msgs[1].slave = sc->bus_addr;
159e9034789SMichal Meloun 	data[0] = reg;
160e9034789SMichal Meloun 
161e9034789SMichal Meloun 	rv = iicbus_transfer(sc->dev, msgs, 2);
162e9034789SMichal Meloun 	if (rv != 0) {
163e9034789SMichal Meloun 		device_printf(sc->dev,
164e9034789SMichal Meloun 		    "Error when writing reg 0x%02X, rv: %d\n", reg, rv);
165e9034789SMichal Meloun 		return (EIO);
166e9034789SMichal Meloun 	}
167e9034789SMichal Meloun 	return (0);
168e9034789SMichal Meloun }
169e9034789SMichal Meloun 
170e9034789SMichal Meloun int
max77620_modify(struct max77620_softc * sc,uint8_t reg,uint8_t clear,uint8_t set)171e9034789SMichal Meloun max77620_modify(struct max77620_softc *sc, uint8_t reg, uint8_t clear,
172e9034789SMichal Meloun     uint8_t set)
173e9034789SMichal Meloun {
174e9034789SMichal Meloun 	uint8_t val;
175e9034789SMichal Meloun 	int rv;
176e9034789SMichal Meloun 
177e9034789SMichal Meloun 	rv = max77620_read(sc, reg, &val);
178e9034789SMichal Meloun 	if (rv != 0)
179e9034789SMichal Meloun 		return (rv);
180e9034789SMichal Meloun 
181e9034789SMichal Meloun 	val &= ~clear;
182e9034789SMichal Meloun 	val |= set;
183e9034789SMichal Meloun 
184e9034789SMichal Meloun 	rv = max77620_write(sc, reg, val);
185e9034789SMichal Meloun 	if (rv != 0)
186e9034789SMichal Meloun 		return (rv);
187e9034789SMichal Meloun 
188e9034789SMichal Meloun 	return (0);
189e9034789SMichal Meloun }
190e9034789SMichal Meloun 
191e9034789SMichal Meloun static int
max77620_parse_fps(struct max77620_softc * sc,int id,phandle_t node)192e9034789SMichal Meloun max77620_parse_fps(struct max77620_softc *sc, int id, phandle_t node)
193e9034789SMichal Meloun {
194e9034789SMichal Meloun 	int val;
195e9034789SMichal Meloun 
196e9034789SMichal Meloun 	if (OF_getencprop(node, "maxim,shutdown-fps-time-period-us", &val,
197e9034789SMichal Meloun 	    sizeof(val)) >= 0) {
198e9034789SMichal Meloun 		val = min(val, MAX77620_FPS_PERIOD_MAX_US);
199e9034789SMichal Meloun 		val = max(val, MAX77620_FPS_PERIOD_MIN_US);
200e9034789SMichal Meloun 		sc->shutdown_fps[id] = val;
201e9034789SMichal Meloun 	}
202e9034789SMichal Meloun 	if (OF_getencprop(node, "maxim,suspend-fps-time-period-us", &val,
203e9034789SMichal Meloun 	    sizeof(val)) >= 0) {
204e9034789SMichal Meloun 		val = min(val, MAX77620_FPS_PERIOD_MAX_US);
205e9034789SMichal Meloun 		val = max(val, MAX77620_FPS_PERIOD_MIN_US);
206e9034789SMichal Meloun 		sc->suspend_fps[id] = val;
207e9034789SMichal Meloun 	}
208e9034789SMichal Meloun 	if (OF_getencprop(node, "maxim,fps-event-source", &val,
209e9034789SMichal Meloun 	    sizeof(val)) >= 0) {
210e9034789SMichal Meloun 		if (val > 2) {
211e9034789SMichal Meloun 			device_printf(sc->dev, "Invalid 'fps-event-source' "
212e9034789SMichal Meloun 			    "value: %d\n", val);
213e9034789SMichal Meloun 			return (EINVAL);
214e9034789SMichal Meloun 		}
215e9034789SMichal Meloun 		sc->event_source[id] = val;
216e9034789SMichal Meloun 	}
217e9034789SMichal Meloun 	return (0);
218e9034789SMichal Meloun }
219e9034789SMichal Meloun 
220e9034789SMichal Meloun static int
max77620_parse_fdt(struct max77620_softc * sc,phandle_t node)221e9034789SMichal Meloun max77620_parse_fdt(struct max77620_softc *sc, phandle_t node)
222e9034789SMichal Meloun {
223e9034789SMichal Meloun 	 phandle_t fpsnode;
224e9034789SMichal Meloun 	 char fps_name[6];
225e9034789SMichal Meloun 	 int i, rv;
226e9034789SMichal Meloun 
227e9034789SMichal Meloun 	for (i = 0; i < MAX77620_FPS_COUNT; i++) {
228e9034789SMichal Meloun 		sc->shutdown_fps[i] = -1;
229e9034789SMichal Meloun 		sc->suspend_fps[i] = -1;
230e9034789SMichal Meloun 		sc->event_source[i] = -1;
231e9034789SMichal Meloun 	}
232e9034789SMichal Meloun 
233e9034789SMichal Meloun 	fpsnode = ofw_bus_find_child(node, "fps");
234e9034789SMichal Meloun 	if (fpsnode > 0) {
235e9034789SMichal Meloun 		for (i = 0; i < MAX77620_FPS_COUNT; i++) {
236e9034789SMichal Meloun 			sprintf(fps_name, "fps%d", i);
237e9034789SMichal Meloun 			node = ofw_bus_find_child(node, fps_name);
238e9034789SMichal Meloun 			if (node <= 0)
239e9034789SMichal Meloun 				continue;
240e9034789SMichal Meloun 			rv = max77620_parse_fps(sc, i, node);
241e9034789SMichal Meloun 			if (rv != 0)
242e9034789SMichal Meloun 				return (rv);
243e9034789SMichal Meloun 		}
244e9034789SMichal Meloun 	}
245e9034789SMichal Meloun 	return (0);
246e9034789SMichal Meloun }
247e9034789SMichal Meloun 
248e9034789SMichal Meloun static int
max77620_get_version(struct max77620_softc * sc)249e9034789SMichal Meloun max77620_get_version(struct max77620_softc *sc)
250e9034789SMichal Meloun {
251e9034789SMichal Meloun 	uint8_t buf[6];
252e9034789SMichal Meloun 	int i;
253e9034789SMichal Meloun 	int rv;
254e9034789SMichal Meloun 
255e9034789SMichal Meloun 	/* Verify ID string (5 bytes ). */
256e9034789SMichal Meloun 	for (i = 0; i <= 6; i++) {
257e9034789SMichal Meloun 		rv = RD1(sc, MAX77620_REG_CID0 + i , buf + i);
258e9034789SMichal Meloun 		if (rv != 0) {
259e9034789SMichal Meloun 			device_printf(sc->dev, "Cannot read chip ID: %d\n", rv);
260e9034789SMichal Meloun 			return (ENXIO);
261e9034789SMichal Meloun 		}
262e9034789SMichal Meloun 	}
263e9034789SMichal Meloun 	if (bootverbose) {
264e9034789SMichal Meloun 		device_printf(sc->dev,
265e9034789SMichal Meloun 		    " ID: [0x%02X, 0x%02X, 0x%02X, 0x%02X]\n",
266e9034789SMichal Meloun 		    buf[0], buf[1], buf[2], buf[3]);
267e9034789SMichal Meloun 	}
268e9034789SMichal Meloun 	device_printf(sc->dev, " MAX77620 version - OTP: 0x%02X, ES: 0x%02X\n",
269e9034789SMichal Meloun 	    buf[4], buf[5]);
270e9034789SMichal Meloun 
271e9034789SMichal Meloun 	return (0);
272e9034789SMichal Meloun }
273e9034789SMichal Meloun 
274e9034789SMichal Meloun static uint8_t
max77620_encode_fps_period(struct max77620_softc * sc,int val)275e9034789SMichal Meloun max77620_encode_fps_period(struct max77620_softc *sc, int val)
276e9034789SMichal Meloun {
277e9034789SMichal Meloun 	uint8_t i;
278e9034789SMichal Meloun 	int period;
279e9034789SMichal Meloun 
280e9034789SMichal Meloun 	period = MAX77620_FPS_PERIOD_MIN_US;
281e9034789SMichal Meloun 	for (i = 0; i < 7; i++) {
282e9034789SMichal Meloun 		if (period >= val)
283e9034789SMichal Meloun 			return (i);
284e9034789SMichal Meloun 		period *= 2;
285e9034789SMichal Meloun 	}
286e9034789SMichal Meloun 	return (i);
287e9034789SMichal Meloun }
288e9034789SMichal Meloun 
289e9034789SMichal Meloun static int
max77620_init(struct max77620_softc * sc)290e9034789SMichal Meloun max77620_init(struct max77620_softc *sc)
291e9034789SMichal Meloun {
29221cc0918SElliott Mitchell 	uint8_t mask, val, tmp;
293e9034789SMichal Meloun 	int i, rv;
294e9034789SMichal Meloun 
295e9034789SMichal Meloun 	mask = 0;
296e9034789SMichal Meloun 	val = 0;
297e9034789SMichal Meloun 	for (i = 0; i < MAX77620_FPS_COUNT; i++) {
298e9034789SMichal Meloun 		if (sc->shutdown_fps[i] != -1) {
299e9034789SMichal Meloun 			mask |= MAX77620_FPS_TIME_PERIOD_MASK;
300e9034789SMichal Meloun 			tmp  = max77620_encode_fps_period(sc,
301e9034789SMichal Meloun 			    sc->shutdown_fps[i]);
302e9034789SMichal Meloun 			val |= (tmp << MAX77620_FPS_TIME_PERIOD_SHIFT) &
303e9034789SMichal Meloun 			    MAX77620_FPS_TIME_PERIOD_MASK;
304e9034789SMichal Meloun 		}
305e9034789SMichal Meloun 
306e9034789SMichal Meloun 		if (sc->event_source[i] != -1) {
307e9034789SMichal Meloun 			mask |= MAX77620_FPS_EN_SRC_MASK;
308e9034789SMichal Meloun 			tmp = sc->event_source[i];
309e9034789SMichal Meloun 			val |= (tmp << MAX77620_FPS_EN_SRC_SHIFT) &
310e9034789SMichal Meloun 			    MAX77620_FPS_EN_SRC_MASK;
311e9034789SMichal Meloun 			if (sc->event_source[i] == 2) {
312e9034789SMichal Meloun 				mask |= MAX77620_FPS_ENFPS_SW_MASK;
313e9034789SMichal Meloun 				val |= MAX77620_FPS_ENFPS_SW;
314e9034789SMichal Meloun 			}
315e9034789SMichal Meloun 
316e9034789SMichal Meloun 		}
317e9034789SMichal Meloun 		rv = RM1(sc, MAX77620_REG_FPS_CFG0 + i, mask, val);
318e9034789SMichal Meloun 		if (rv != 0) {
319e9034789SMichal Meloun 			device_printf(sc->dev, "I/O error: %d\n", rv);
320e9034789SMichal Meloun 			return (ENXIO);
321e9034789SMichal Meloun 		}
322e9034789SMichal Meloun 	}
323e9034789SMichal Meloun 
324e9034789SMichal Meloun 	/* Global mask interrupts */
325e9034789SMichal Meloun 	rv = RM1(sc, MAX77620_REG_INTENLBT, 0x81, 0x81);
326e9034789SMichal Meloun 	rv = RM1(sc, MAX77620_REG_IRQTOPM, 0x81, 0x81);
327e9034789SMichal Meloun 	if (rv != 0)
328e9034789SMichal Meloun 		return (ENXIO);
329e9034789SMichal Meloun 	return (0);
330e9034789SMichal Meloun }
331e9034789SMichal Meloun #ifdef notyet
332e9034789SMichal Meloun static void
max77620_intr(void * arg)333e9034789SMichal Meloun max77620_intr(void *arg)
334e9034789SMichal Meloun {
335e9034789SMichal Meloun 	struct max77620_softc *sc;
336e9034789SMichal Meloun 	uint8_t intenlbt, intlbt, irqtop, irqtopm, irqsd, irqmasksd;
337e9034789SMichal Meloun 	uint8_t irq_lvl2_l0_7, irq_lvl2_l8, irq_lvl2_gpio, irq_msk_l0_7, irq_msk_l8;
338e9034789SMichal Meloun 	uint8_t onoffirq, onoffirqm;
339e9034789SMichal Meloun 
340e9034789SMichal Meloun 	sc = (struct max77620_softc *)arg;
341e9034789SMichal Meloun 	/* XXX Finish temperature alarms. */
342e9034789SMichal Meloun 	RD1(sc, MAX77620_REG_INTENLBT, &intenlbt);
343e9034789SMichal Meloun 	RD1(sc, MAX77620_REG_INTLBT, &intlbt);
344e9034789SMichal Meloun 
345e9034789SMichal Meloun 	RD1(sc, MAX77620_REG_IRQTOP, &irqtop);
346e9034789SMichal Meloun 	RD1(sc, MAX77620_REG_IRQTOPM, &irqtopm);
347e9034789SMichal Meloun 	RD1(sc, MAX77620_REG_IRQSD, &irqsd);
348e9034789SMichal Meloun 	RD1(sc, MAX77620_REG_IRQMASKSD, &irqmasksd);
349e9034789SMichal Meloun 	RD1(sc, MAX77620_REG_IRQ_LVL2_L0_7, &irq_lvl2_l0_7);
350e9034789SMichal Meloun 	RD1(sc, MAX77620_REG_IRQ_MSK_L0_7, &irq_msk_l0_7);
351e9034789SMichal Meloun 	RD1(sc, MAX77620_REG_IRQ_LVL2_L8, &irq_lvl2_l8);
352e9034789SMichal Meloun 	RD1(sc, MAX77620_REG_IRQ_MSK_L8, &irq_msk_l8);
353e9034789SMichal Meloun 	RD1(sc, MAX77620_REG_IRQ_LVL2_GPIO, &irq_lvl2_gpio);
354e9034789SMichal Meloun 	RD1(sc, MAX77620_REG_ONOFFIRQ, &onoffirq);
355e9034789SMichal Meloun 	RD1(sc, MAX77620_REG_ONOFFIRQM, &onoffirqm);
356e9034789SMichal Meloun 	printf("%s: intlbt: 0x%02X, intenlbt: 0x%02X\n", __func__, intlbt, intenlbt);
357e9034789SMichal Meloun 	printf("%s: irqtop: 0x%02X, irqtopm: 0x%02X\n", __func__, irqtop, irqtopm);
358e9034789SMichal Meloun 	printf("%s: irqsd: 0x%02X, irqmasksd: 0x%02X\n", __func__, irqsd, irqmasksd);
359e9034789SMichal Meloun 	printf("%s: onoffirq: 0x%02X, onoffirqm: 0x%02X\n", __func__, onoffirq, onoffirqm);
360e9034789SMichal Meloun 	printf("%s: irq_lvl2_l0_7: 0x%02X, irq_msk_l0_7: 0x%02X\n", __func__, irq_lvl2_l0_7, irq_msk_l0_7);
361e9034789SMichal Meloun 	printf("%s: irq_lvl2_l8: 0x%02X, irq_msk_l8: 0x%02X\n", __func__, irq_lvl2_l8, irq_msk_l8);
362e9034789SMichal Meloun 	printf("%s: irq_lvl2_gpio: 0x%02X\n", __func__, irq_lvl2_gpio);
363e9034789SMichal Meloun }
364e9034789SMichal Meloun #endif
365e9034789SMichal Meloun 
366e9034789SMichal Meloun static int
max77620_probe(device_t dev)367e9034789SMichal Meloun max77620_probe(device_t dev)
368e9034789SMichal Meloun {
369e9034789SMichal Meloun 
370e9034789SMichal Meloun 	if (!ofw_bus_status_okay(dev))
371e9034789SMichal Meloun 		return (ENXIO);
372e9034789SMichal Meloun 
373e9034789SMichal Meloun 	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
374e9034789SMichal Meloun 		return (ENXIO);
375e9034789SMichal Meloun 
376e9034789SMichal Meloun 	device_set_desc(dev, "MAX77620 PMIC");
377e9034789SMichal Meloun 	return (BUS_PROBE_DEFAULT);
378e9034789SMichal Meloun }
379e9034789SMichal Meloun 
380e9034789SMichal Meloun static int
max77620_attach(device_t dev)381e9034789SMichal Meloun max77620_attach(device_t dev)
382e9034789SMichal Meloun {
383e9034789SMichal Meloun 	struct max77620_softc *sc;
3844b9b6a50SJohn Baldwin 	int rv, rid;
385e9034789SMichal Meloun 	phandle_t node;
386e9034789SMichal Meloun 
387e9034789SMichal Meloun 	sc = device_get_softc(dev);
388e9034789SMichal Meloun 	sc->dev = dev;
389e9034789SMichal Meloun 	sc->bus_addr = iicbus_get_addr(dev);
390e9034789SMichal Meloun 	node = ofw_bus_get_node(sc->dev);
391e9034789SMichal Meloun 	rv = 0;
392e9034789SMichal Meloun 	LOCK_INIT(sc);
393e9034789SMichal Meloun 
394e9034789SMichal Meloun 	rid = 0;
395e9034789SMichal Meloun 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
396e9034789SMichal Meloun 	    RF_ACTIVE);
39730ae4168SMichal Meloun #ifdef notyet /* Interrupt parent is not implemented */
398e9034789SMichal Meloun 	if (sc->irq_res == NULL) {
399e9034789SMichal Meloun 		device_printf(dev, "Cannot allocate interrupt.\n");
400e9034789SMichal Meloun 		rv = ENXIO;
401e9034789SMichal Meloun 		goto fail;
402e9034789SMichal Meloun 	}
403e9034789SMichal Meloun #endif
404e9034789SMichal Meloun 	rv = max77620_parse_fdt(sc, node);
405e9034789SMichal Meloun 	if (rv != 0)
406e9034789SMichal Meloun 		goto fail;
407e9034789SMichal Meloun 
408e9034789SMichal Meloun 	rv = max77620_get_version(sc);
409e9034789SMichal Meloun 	if (rv != 0)
410e9034789SMichal Meloun 		goto fail;
411e9034789SMichal Meloun 
412e9034789SMichal Meloun 	rv = max77620_init(sc);
413e9034789SMichal Meloun 	if (rv != 0)
414e9034789SMichal Meloun 		goto fail;
415e9034789SMichal Meloun 	rv = max77620_regulator_attach(sc, node);
416e9034789SMichal Meloun 	if (rv != 0)
417e9034789SMichal Meloun 		goto fail;
418e9034789SMichal Meloun 	rv = max77620_gpio_attach(sc, node);
419e9034789SMichal Meloun 	if (rv != 0)
420e9034789SMichal Meloun 		goto fail;
421e9034789SMichal Meloun 
422e9034789SMichal Meloun 	rv = max77620_rtc_create(sc, node);
423e9034789SMichal Meloun 	if (rv != 0)
424e9034789SMichal Meloun 		goto fail;
425e9034789SMichal Meloun 
426e9034789SMichal Meloun 	fdt_pinctrl_register(dev, NULL);
427e9034789SMichal Meloun 	fdt_pinctrl_configure_by_name(dev, "default");
428e9034789SMichal Meloun 
429e9034789SMichal Meloun 	/* Setup interrupt. */
430e9034789SMichal Meloun #ifdef notyet
431e9034789SMichal Meloun 	rv = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
432e9034789SMichal Meloun 	    NULL, max77620_intr, sc, &sc->irq_h);
433e9034789SMichal Meloun 	if (rv) {
434e9034789SMichal Meloun 		device_printf(dev, "Cannot setup interrupt.\n");
435e9034789SMichal Meloun 		goto fail;
436e9034789SMichal Meloun 	}
437e9034789SMichal Meloun #endif
438e9034789SMichal Meloun 	return (bus_generic_attach(dev));
439e9034789SMichal Meloun 
440e9034789SMichal Meloun fail:
441e9034789SMichal Meloun 	if (sc->irq_h != NULL)
442e9034789SMichal Meloun 		bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
443e9034789SMichal Meloun 	if (sc->irq_res != NULL)
444e9034789SMichal Meloun 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
445e9034789SMichal Meloun 	LOCK_DESTROY(sc);
446e9034789SMichal Meloun 	return (rv);
447e9034789SMichal Meloun }
448e9034789SMichal Meloun 
449e9034789SMichal Meloun static int
max77620_detach(device_t dev)450e9034789SMichal Meloun max77620_detach(device_t dev)
451e9034789SMichal Meloun {
452e9034789SMichal Meloun 	struct max77620_softc *sc;
453e9034789SMichal Meloun 
454e9034789SMichal Meloun 	sc = device_get_softc(dev);
455e9034789SMichal Meloun 	if (sc->irq_h != NULL)
456e9034789SMichal Meloun 		bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
457e9034789SMichal Meloun 	if (sc->irq_res != NULL)
458e9034789SMichal Meloun 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
459e9034789SMichal Meloun 	LOCK_DESTROY(sc);
460e9034789SMichal Meloun 
461e9034789SMichal Meloun 	return (bus_generic_detach(dev));
462e9034789SMichal Meloun }
463e9034789SMichal Meloun 
464e9034789SMichal Meloun static phandle_t
max77620_gpio_get_node(device_t bus,device_t dev)465e9034789SMichal Meloun max77620_gpio_get_node(device_t bus, device_t dev)
466e9034789SMichal Meloun {
467e9034789SMichal Meloun 
468e9034789SMichal Meloun 	/* We only have one child, the GPIO bus, which needs our own node. */
469e9034789SMichal Meloun 	return (ofw_bus_get_node(bus));
470e9034789SMichal Meloun }
471e9034789SMichal Meloun 
472e9034789SMichal Meloun static device_method_t max77620_methods[] = {
473e9034789SMichal Meloun 	/* Device interface */
474e9034789SMichal Meloun 	DEVMETHOD(device_probe,		max77620_probe),
475e9034789SMichal Meloun 	DEVMETHOD(device_attach,	max77620_attach),
476e9034789SMichal Meloun 	DEVMETHOD(device_detach,	max77620_detach),
477e9034789SMichal Meloun 
478e9034789SMichal Meloun 	/* Regdev interface */
479e9034789SMichal Meloun 	DEVMETHOD(regdev_map,		max77620_regulator_map),
480e9034789SMichal Meloun 
481e9034789SMichal Meloun 	/* GPIO protocol interface */
482e9034789SMichal Meloun 	DEVMETHOD(gpio_get_bus,		max77620_gpio_get_bus),
483e9034789SMichal Meloun 	DEVMETHOD(gpio_pin_max,		max77620_gpio_pin_max),
484e9034789SMichal Meloun 	DEVMETHOD(gpio_pin_getname,	max77620_gpio_pin_getname),
485e9034789SMichal Meloun 	DEVMETHOD(gpio_pin_getflags,	max77620_gpio_pin_getflags),
486e9034789SMichal Meloun 	DEVMETHOD(gpio_pin_getcaps,	max77620_gpio_pin_getcaps),
487e9034789SMichal Meloun 	DEVMETHOD(gpio_pin_setflags,	max77620_gpio_pin_setflags),
488e9034789SMichal Meloun 	DEVMETHOD(gpio_pin_get,		max77620_gpio_pin_get),
489e9034789SMichal Meloun 	DEVMETHOD(gpio_pin_set,		max77620_gpio_pin_set),
490e9034789SMichal Meloun 	DEVMETHOD(gpio_pin_toggle,	max77620_gpio_pin_toggle),
491e9034789SMichal Meloun 	DEVMETHOD(gpio_map_gpios,	max77620_gpio_map_gpios),
492e9034789SMichal Meloun 
493e9034789SMichal Meloun 	/* fdt_pinctrl interface */
494e9034789SMichal Meloun 	DEVMETHOD(fdt_pinctrl_configure, max77620_pinmux_configure),
495e9034789SMichal Meloun 
496e9034789SMichal Meloun 	/* ofw_bus interface */
497e9034789SMichal Meloun 	DEVMETHOD(ofw_bus_get_node,	max77620_gpio_get_node),
498e9034789SMichal Meloun 
499e9034789SMichal Meloun 	DEVMETHOD_END
500e9034789SMichal Meloun };
501e9034789SMichal Meloun 
502e9034789SMichal Meloun static DEFINE_CLASS_0(gpio, max77620_driver, max77620_methods,
503e9034789SMichal Meloun     sizeof(struct max77620_softc));
504289f133bSJohn Baldwin EARLY_DRIVER_MODULE(max77620, iicbus, max77620_driver, NULL, NULL, 74);
505