1e9034789SMichal Meloun /*-
24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause
3e9034789SMichal Meloun *
4e9034789SMichal Meloun * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
5e9034789SMichal Meloun *
6e9034789SMichal Meloun * Redistribution and use in source and binary forms, with or without
7e9034789SMichal Meloun * modification, are permitted provided that the following conditions
8e9034789SMichal Meloun * are met:
9e9034789SMichal Meloun * 1. Redistributions of source code must retain the above copyright
10e9034789SMichal Meloun * notice, this list of conditions and the following disclaimer.
11e9034789SMichal Meloun * 2. Redistributions in binary form must reproduce the above copyright
12e9034789SMichal Meloun * notice, this list of conditions and the following disclaimer in the
13e9034789SMichal Meloun * documentation and/or other materials provided with the distribution.
14e9034789SMichal Meloun *
15e9034789SMichal Meloun * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16e9034789SMichal Meloun * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17e9034789SMichal Meloun * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18e9034789SMichal Meloun * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19e9034789SMichal Meloun * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20e9034789SMichal Meloun * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21e9034789SMichal Meloun * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22e9034789SMichal Meloun * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23e9034789SMichal Meloun * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24e9034789SMichal Meloun * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25e9034789SMichal Meloun * SUCH DAMAGE.
26e9034789SMichal Meloun */
27e9034789SMichal Meloun
28e9034789SMichal Meloun #include <sys/param.h>
29e9034789SMichal Meloun #include <sys/systm.h>
30e9034789SMichal Meloun #include <sys/bus.h>
31e9034789SMichal Meloun #include <sys/lock.h>
32e9034789SMichal Meloun #include <sys/mutex.h>
33e9034789SMichal Meloun #include <sys/rman.h>
34e9034789SMichal Meloun
35e9034789SMichal Meloun #include <machine/bus.h>
36e9034789SMichal Meloun
37*be82b3a0SEmmanuel Vadot #include <dev/clk/clk_div.h>
38*be82b3a0SEmmanuel Vadot #include <dev/clk/clk_fixed.h>
39*be82b3a0SEmmanuel Vadot #include <dev/clk/clk_gate.h>
40*be82b3a0SEmmanuel Vadot #include <dev/clk/clk_mux.h>
41e9034789SMichal Meloun
42c38fe878SEmmanuel Vadot #include <dt-bindings/clock/tegra210-car.h>
43e9034789SMichal Meloun #include "tegra210_car.h"
44e9034789SMichal Meloun
45e9034789SMichal Meloun #if 0
46e9034789SMichal Meloun #define dprintf(...) printf(__VA_ARGS__)
47e9034789SMichal Meloun #else
48e9034789SMichal Meloun #define dprintf(...)
49e9034789SMichal Meloun #endif
50e9034789SMichal Meloun
51e9034789SMichal Meloun /* All PLLs. */
52e9034789SMichal Meloun enum pll_type {
53e9034789SMichal Meloun PLL_M,
54e9034789SMichal Meloun PLL_MB,
55e9034789SMichal Meloun PLL_X,
56e9034789SMichal Meloun PLL_C,
57e9034789SMichal Meloun PLL_C2,
58e9034789SMichal Meloun PLL_C3,
59e9034789SMichal Meloun PLL_C4,
60e9034789SMichal Meloun PLL_P,
61e9034789SMichal Meloun PLL_A,
62e9034789SMichal Meloun PLL_A1,
63e9034789SMichal Meloun PLL_U,
64e9034789SMichal Meloun PLL_D,
65e9034789SMichal Meloun PLL_D2,
66e9034789SMichal Meloun PLL_DP,
67e9034789SMichal Meloun PLL_E,
68e9034789SMichal Meloun PLL_REFE};
69e9034789SMichal Meloun /* Flags for PLLs */
70e9034789SMichal Meloun
71e9034789SMichal Meloun #define PLL_FLAG_PDIV_POWER2 0x01 /* P Divider is 2^n */
72e9034789SMichal Meloun #define PLL_FLAG_VCO_OUT 0x02 /* Output VCO directly */
73e9034789SMichal Meloun #define PLL_FLAG_HAVE_SDM 0x04 /* Have SDM implemented */
74e9034789SMichal Meloun #define PLL_FLAG_HAVE_SDA 0x04 /* Have SDA implemented */
75e9034789SMichal Meloun
76e9034789SMichal Meloun /* Common base register bits. */
77e9034789SMichal Meloun #define PLL_BASE_BYPASS (1U << 31)
78e9034789SMichal Meloun #define PLL_BASE_ENABLE (1 << 30)
79e9034789SMichal Meloun #define PLL_BASE_REFDISABLE (1 << 29)
80e9034789SMichal Meloun #define PLL_BASE_LOCK (1 << 27)
81e9034789SMichal Meloun
82e9034789SMichal Meloun #define PLLREFE_MISC_LOCK (1 << 27)
83e9034789SMichal Meloun
84e9034789SMichal Meloun #define PLL_MISC_LOCK_ENABLE (1 << 18)
85e9034789SMichal Meloun #define PLLM_LOCK_ENABLE (1 << 4)
86e9034789SMichal Meloun #define PLLMB_LOCK_ENABLE (1 << 16)
87e9034789SMichal Meloun #define PLLC_LOCK_ENABLE (1 << 24)
88e9034789SMichal Meloun #define PLLC4_LOCK_ENABLE (1 << 30)
89e9034789SMichal Meloun #define PLLA_LOCK_ENABLE (1 << 28)
90e9034789SMichal Meloun #define PLLD2_LOCK_ENABLE (1 << 30)
91e9034789SMichal Meloun #define PLLU_LOCK_ENABLE (1 << 29)
92e9034789SMichal Meloun #define PLLREFE_LOCK_ENABLE (1 << 30)
93e9034789SMichal Meloun #define PLLPD_LOCK_ENABLE (1 << 30)
94e9034789SMichal Meloun #define PLLE_LOCK_ENABLE (1 << 9)
95e9034789SMichal Meloun
96e9034789SMichal Meloun #define PLLM_IDDQ_BIT 5
97e9034789SMichal Meloun #define PLLMB_IDDQ_BIT 17
98e9034789SMichal Meloun #define PLLC_IDDQ_BIT 27
99e9034789SMichal Meloun #define PLLC4_IDDQ_BIT 18
100e9034789SMichal Meloun #define PLLP_IDDQ_BIT 3
101e9034789SMichal Meloun #define PLLA_IDDQ_BIT 25
102e9034789SMichal Meloun #define PLLA1_IDDQ_BIT 27
103e9034789SMichal Meloun #define PLLU_IDDQ_BIT 31
104e9034789SMichal Meloun #define PLLD_IDDQ_BIT 20
105e9034789SMichal Meloun #define PLLD2_IDDQ_BIT 18
106e9034789SMichal Meloun #define PLLX_IDDQ_BIT 3
107e9034789SMichal Meloun #define PLLREFE_IDDQ_BIT 24
108e9034789SMichal Meloun #define PLLDP_IDDQ_BIT 18
109e9034789SMichal Meloun
110e9034789SMichal Meloun
111e9034789SMichal Meloun #define PLL_LOCK_TIMEOUT 5000
112e9034789SMichal Meloun
113e9034789SMichal Meloun /* Post divider <-> register value mapping. */
114e9034789SMichal Meloun struct pdiv_table {
115e9034789SMichal Meloun uint32_t divider; /* real divider */
116e9034789SMichal Meloun uint32_t value; /* register value */
117e9034789SMichal Meloun };
118e9034789SMichal Meloun
119e9034789SMichal Meloun /* Bits definition of M, N and P fields. */
120e9034789SMichal Meloun struct mnp_bits {
121e9034789SMichal Meloun uint32_t m_width;
122e9034789SMichal Meloun uint32_t n_width;
123e9034789SMichal Meloun uint32_t p_width;
124e9034789SMichal Meloun uint32_t m_shift;
125e9034789SMichal Meloun uint32_t n_shift;
126e9034789SMichal Meloun uint32_t p_shift;
127e9034789SMichal Meloun };
128e9034789SMichal Meloun
129e9034789SMichal Meloun struct clk_pll_def {
130e9034789SMichal Meloun struct clknode_init_def clkdef;
131e9034789SMichal Meloun enum pll_type type;
132e9034789SMichal Meloun uint32_t base_reg;
133e9034789SMichal Meloun uint32_t misc_reg;
134e9034789SMichal Meloun uint32_t lock_enable;
135e9034789SMichal Meloun uint32_t iddq_reg;
136e9034789SMichal Meloun uint32_t iddq_mask;
137e9034789SMichal Meloun uint32_t flags;
138e9034789SMichal Meloun struct pdiv_table *pdiv_table;
139e9034789SMichal Meloun struct mnp_bits mnp_bits;
140e9034789SMichal Meloun };
141e9034789SMichal Meloun
142e9034789SMichal Meloun #define PLIST(x) static const char *x[]
143e9034789SMichal Meloun
144e9034789SMichal Meloun #define PLL(_id, cname, pname) \
145e9034789SMichal Meloun .clkdef.id = _id, \
146e9034789SMichal Meloun .clkdef.name = cname, \
147e9034789SMichal Meloun .clkdef.parent_names = (const char *[]){pname}, \
148e9034789SMichal Meloun .clkdef.parent_cnt = 1, \
149e9034789SMichal Meloun .clkdef.flags = CLK_NODE_STATIC_STRINGS
150e9034789SMichal Meloun
151e9034789SMichal Meloun /* multiplexer for pll sources. */
152e9034789SMichal Meloun #define MUX(_id, cname, plists, o, s, w) \
153e9034789SMichal Meloun { \
154e9034789SMichal Meloun .clkdef.id = _id, \
155e9034789SMichal Meloun .clkdef.name = cname, \
156e9034789SMichal Meloun .clkdef.parent_names = plists, \
157e9034789SMichal Meloun .clkdef.parent_cnt = nitems(plists), \
158e9034789SMichal Meloun .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
159e9034789SMichal Meloun .offset = o, \
160e9034789SMichal Meloun .shift = s, \
161e9034789SMichal Meloun .width = w, \
162e9034789SMichal Meloun }
163e9034789SMichal Meloun
164e9034789SMichal Meloun /* Fractional divider (7.1) for PLL branch. */
165e9034789SMichal Meloun #define DIV7_1(_id, cname, plist, o, s) \
166e9034789SMichal Meloun { \
167e9034789SMichal Meloun .clkdef.id = _id, \
168e9034789SMichal Meloun .clkdef.name = cname, \
169e9034789SMichal Meloun .clkdef.parent_names = (const char *[]){plist}, \
170e9034789SMichal Meloun .clkdef.parent_cnt = 1, \
171e9034789SMichal Meloun .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
172e9034789SMichal Meloun .offset = o, \
173e9034789SMichal Meloun .i_shift = (s) + 1, \
174e9034789SMichal Meloun .i_width = 7, \
175e9034789SMichal Meloun .f_shift = s, \
176e9034789SMichal Meloun .f_width = 1, \
177e9034789SMichal Meloun }
178e9034789SMichal Meloun
179e9034789SMichal Meloun /* P divider (2^n). for PLL branch. */
180e9034789SMichal Meloun #define DIV5_E(_id, cname, plist, o, s) \
181e9034789SMichal Meloun { \
182e9034789SMichal Meloun .clkdef.id = _id, \
183e9034789SMichal Meloun .clkdef.name = cname, \
184e9034789SMichal Meloun .clkdef.parent_names = (const char *[]){plist}, \
185e9034789SMichal Meloun .clkdef.parent_cnt = 1, \
186e9034789SMichal Meloun .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
187e9034789SMichal Meloun .offset = o, \
188e9034789SMichal Meloun .i_shift = s, \
189e9034789SMichal Meloun .i_width = 5, \
190e9034789SMichal Meloun }
191e9034789SMichal Meloun
192e9034789SMichal Meloun /* P divider (2^n). for PLL branch. */
193e9034789SMichal Meloun #define DIV_TB(_id, cname, plist, o, s, n, table) \
194e9034789SMichal Meloun { \
195e9034789SMichal Meloun .clkdef.id = _id, \
196e9034789SMichal Meloun .clkdef.name = cname, \
197e9034789SMichal Meloun .clkdef.parent_names = (const char *[]){plist}, \
198e9034789SMichal Meloun .clkdef.parent_cnt = 1, \
199e9034789SMichal Meloun .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
200e9034789SMichal Meloun .div_flags = CLK_DIV_WITH_TABLE | CLK_DIV_ZERO_BASED, \
201e9034789SMichal Meloun .offset = o, \
202e9034789SMichal Meloun .i_shift = s, \
203e9034789SMichal Meloun .i_width = n, \
204e9034789SMichal Meloun .div_table = table, \
205e9034789SMichal Meloun }
206e9034789SMichal Meloun
207e9034789SMichal Meloun /* Standard gate. */
208e9034789SMichal Meloun #define GATE(_id, cname, plist, o, s) \
209e9034789SMichal Meloun { \
210e9034789SMichal Meloun .clkdef.id = _id, \
211e9034789SMichal Meloun .clkdef.name = cname, \
212e9034789SMichal Meloun .clkdef.parent_names = (const char *[]){plist}, \
213e9034789SMichal Meloun .clkdef.parent_cnt = 1, \
214e9034789SMichal Meloun .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
215e9034789SMichal Meloun .offset = o, \
216e9034789SMichal Meloun .shift = s, \
217e9034789SMichal Meloun .mask = 1, \
218e9034789SMichal Meloun .on_value = 1, \
219e9034789SMichal Meloun .off_value = 0, \
220e9034789SMichal Meloun }
221e9034789SMichal Meloun /* Gate for PLL branch. */
222e9034789SMichal Meloun #define GATE_PLL(_id, cname, plist, o, s) \
223e9034789SMichal Meloun { \
224e9034789SMichal Meloun .clkdef.id = _id, \
225e9034789SMichal Meloun .clkdef.name = cname, \
226e9034789SMichal Meloun .clkdef.parent_names = (const char *[]){plist}, \
227e9034789SMichal Meloun .clkdef.parent_cnt = 1, \
228e9034789SMichal Meloun .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
229e9034789SMichal Meloun .offset = o, \
230e9034789SMichal Meloun .shift = s, \
231e9034789SMichal Meloun .mask = 3, \
232e9034789SMichal Meloun .on_value = 3, \
233e9034789SMichal Meloun .off_value = 0, \
234e9034789SMichal Meloun }
235e9034789SMichal Meloun
236e9034789SMichal Meloun /* Fixed rate multipier/divider. */
237e9034789SMichal Meloun #define FACT(_id, cname, pname, _mult, _div) \
238e9034789SMichal Meloun { \
239e9034789SMichal Meloun .clkdef.id = _id, \
240e9034789SMichal Meloun .clkdef.name = cname, \
241e9034789SMichal Meloun .clkdef.parent_names = (const char *[]){pname}, \
242e9034789SMichal Meloun .clkdef.parent_cnt = 1, \
243e9034789SMichal Meloun .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
244e9034789SMichal Meloun .mult = _mult, \
245e9034789SMichal Meloun .div = _div, \
246e9034789SMichal Meloun }
247e9034789SMichal Meloun
248e9034789SMichal Meloun static struct pdiv_table qlin_map[] = {
249e9034789SMichal Meloun { 1, 0},
250e9034789SMichal Meloun { 2, 1},
251e9034789SMichal Meloun { 3, 2},
252e9034789SMichal Meloun { 4, 3},
253e9034789SMichal Meloun { 5, 4},
254e9034789SMichal Meloun { 6, 5},
255e9034789SMichal Meloun { 8, 6},
256e9034789SMichal Meloun { 9, 7},
257e9034789SMichal Meloun {10, 8},
258e9034789SMichal Meloun {12, 9},
259e9034789SMichal Meloun {15, 10},
260e9034789SMichal Meloun {16, 11},
261e9034789SMichal Meloun {18, 12},
262e9034789SMichal Meloun {20, 13},
263e9034789SMichal Meloun {24, 14},
264e9034789SMichal Meloun {30, 15},
265e9034789SMichal Meloun {32, 16},
266e9034789SMichal Meloun { 0, 0},
267e9034789SMichal Meloun };
268e9034789SMichal Meloun
269e9034789SMichal Meloun static struct clk_pll_def pll_clks[] = {
270e9034789SMichal Meloun /* PLLM: 880 MHz Clock source for EMC 2x clock */
271e9034789SMichal Meloun {
272e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_M, "pllM_out0", "osc"),
273e9034789SMichal Meloun .type = PLL_M,
274e9034789SMichal Meloun .base_reg = PLLM_BASE,
275e9034789SMichal Meloun .misc_reg = PLLM_MISC2,
276e9034789SMichal Meloun .lock_enable = PLLM_LOCK_ENABLE,
277e9034789SMichal Meloun .iddq_reg = PLLM_MISC2,
278e9034789SMichal Meloun .iddq_mask = 1 << PLLM_IDDQ_BIT,
279e9034789SMichal Meloun .pdiv_table = qlin_map,
280e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 8, 20},
281e9034789SMichal Meloun },
282e9034789SMichal Meloun /* PLLMB: 880 MHz Clock source for EMC 2x clock */
283e9034789SMichal Meloun {
284e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_M, "pllMB_out0", "osc"),
285e9034789SMichal Meloun .type = PLL_MB,
286e9034789SMichal Meloun .base_reg = PLLMB_BASE,
287e9034789SMichal Meloun .misc_reg = PLLMB_MISC1,
288e9034789SMichal Meloun .lock_enable = PLLMB_LOCK_ENABLE,
289e9034789SMichal Meloun .iddq_reg = PLLMB_MISC1,
290e9034789SMichal Meloun .iddq_mask = 1 << PLLMB_IDDQ_BIT,
291e9034789SMichal Meloun .pdiv_table = qlin_map,
292e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 8, 20},
293e9034789SMichal Meloun },
294e9034789SMichal Meloun /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */
295e9034789SMichal Meloun {
296e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_X, "pllX_out0", "osc_div_clk"),
297e9034789SMichal Meloun .type = PLL_X,
298e9034789SMichal Meloun .base_reg = PLLX_BASE,
299e9034789SMichal Meloun .misc_reg = PLLX_MISC,
300e9034789SMichal Meloun .lock_enable = PLL_MISC_LOCK_ENABLE,
301e9034789SMichal Meloun .iddq_reg = PLLX_MISC_3,
302e9034789SMichal Meloun .iddq_mask = 1 << PLLX_IDDQ_BIT,
303e9034789SMichal Meloun .pdiv_table = qlin_map,
304e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 8, 20},
305e9034789SMichal Meloun },
306e9034789SMichal Meloun /* PLLC: 510 MHz Clock source for camera use */
307e9034789SMichal Meloun {
308e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
309e9034789SMichal Meloun .type = PLL_C,
310e9034789SMichal Meloun .base_reg = PLLC_BASE,
311e9034789SMichal Meloun .misc_reg = PLLC_MISC_0,
312e9034789SMichal Meloun .iddq_reg = PLLC_MISC_1,
313e9034789SMichal Meloun .iddq_mask = 1 << PLLC_IDDQ_BIT,
314e9034789SMichal Meloun .pdiv_table = qlin_map,
315e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 10, 20},
316e9034789SMichal Meloun },
317e9034789SMichal Meloun /* PLLC2: 510 MHz Clock source for SE, VIC, TSECB, NVJPG scaling */
318e9034789SMichal Meloun {
319e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
320e9034789SMichal Meloun .type = PLL_C2,
321e9034789SMichal Meloun .base_reg = PLLC2_BASE,
322e9034789SMichal Meloun .misc_reg = PLLC2_MISC_0,
323e9034789SMichal Meloun .iddq_reg = PLLC2_MISC_1,
324e9034789SMichal Meloun .iddq_mask = 1 << PLLC_IDDQ_BIT,
325e9034789SMichal Meloun .pdiv_table = qlin_map,
326e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 10, 20},
327e9034789SMichal Meloun },
328e9034789SMichal Meloun /* PLLC3: 510 MHz Clock source for NVENC, NVDEC scaling */
329e9034789SMichal Meloun {
330e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
331e9034789SMichal Meloun .type = PLL_C3,
332e9034789SMichal Meloun .base_reg = PLLC3_BASE,
333e9034789SMichal Meloun .misc_reg = PLLC3_MISC_0,
334e9034789SMichal Meloun .lock_enable = PLL_MISC_LOCK_ENABLE,
335e9034789SMichal Meloun .iddq_reg = PLLC3_MISC_1,
336e9034789SMichal Meloun .iddq_mask = 1 << PLLC_IDDQ_BIT,
337e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 10, 20},
338e9034789SMichal Meloun },
339e9034789SMichal Meloun /* PLLC4: 600 MHz Clock source for SD/eMMC ans system busses */
340e9034789SMichal Meloun {
341e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_C4, "pllC4", "pllC4_src"),
342e9034789SMichal Meloun .type = PLL_C4,
343e9034789SMichal Meloun .flags = PLL_FLAG_VCO_OUT,
344e9034789SMichal Meloun .base_reg = PLLC4_BASE,
345e9034789SMichal Meloun .misc_reg = PLLC4_MISC,
346e9034789SMichal Meloun .lock_enable = PLLC4_LOCK_ENABLE,
347e9034789SMichal Meloun .iddq_reg = PLLC4_BASE,
348e9034789SMichal Meloun .iddq_mask = 1 << PLLC4_IDDQ_BIT,
349e9034789SMichal Meloun .pdiv_table = qlin_map,
350e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 8, 19},
351e9034789SMichal Meloun },
352e9034789SMichal Meloun /* PLLP: 408 MHz Clock source for most peripherals */
353e9034789SMichal Meloun {
354e9034789SMichal Meloun /*
355e9034789SMichal Meloun * VCO is directly exposed as pllP_out0, P div is used for
356e9034789SMichal Meloun * pllP_out2
357e9034789SMichal Meloun */
358e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
359e9034789SMichal Meloun .type = PLL_P,
360e9034789SMichal Meloun .flags = PLL_FLAG_VCO_OUT,
361e9034789SMichal Meloun .base_reg = PLLP_BASE,
362e9034789SMichal Meloun .misc_reg = PLLP_MISC,
363e9034789SMichal Meloun .lock_enable = PLL_MISC_LOCK_ENABLE,
364e9034789SMichal Meloun .iddq_reg = PLLP_MISC,
365e9034789SMichal Meloun .iddq_mask = 1 << PLLA_IDDQ_BIT,
366e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 10, 20},
367e9034789SMichal Meloun },
368e9034789SMichal Meloun /* PLLA: Audio clock for precise codec sampling */
369e9034789SMichal Meloun {
370e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_A, "pllA", "osc_div_clk"),
371e9034789SMichal Meloun .type = PLL_A,
372e9034789SMichal Meloun .base_reg = PLLA_BASE,
373e9034789SMichal Meloun .misc_reg = PLLA_MISC,
374e9034789SMichal Meloun .lock_enable = PLLA_LOCK_ENABLE,
375e9034789SMichal Meloun .iddq_reg = PLLA_BASE,
376e9034789SMichal Meloun .iddq_mask = 1 << PLLA_IDDQ_BIT,
377e9034789SMichal Meloun .pdiv_table = qlin_map,
378e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 8, 20},
379e9034789SMichal Meloun },
380e9034789SMichal Meloun /* PLLA1: Audio clock for ADSP */
381e9034789SMichal Meloun {
382e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_A1, "pllA1_out0", "osc_div_clk"),
383e9034789SMichal Meloun .type = PLL_A1,
384e9034789SMichal Meloun .base_reg = PLLA1_BASE,
385e9034789SMichal Meloun .misc_reg = PLLA1_MISC_1,
386e9034789SMichal Meloun .iddq_reg = PLLA1_MISC_1,
387e9034789SMichal Meloun .iddq_mask = 1 << PLLA_IDDQ_BIT,
388e9034789SMichal Meloun .pdiv_table = qlin_map,
389e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 8, 20},
390e9034789SMichal Meloun },
391e9034789SMichal Meloun /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */
392e9034789SMichal Meloun {
393e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_U, "pllU", "osc_div_clk"),
394e9034789SMichal Meloun .type = PLL_U,
395e9034789SMichal Meloun .flags = PLL_FLAG_VCO_OUT | PLL_FLAG_HAVE_SDA,
396e9034789SMichal Meloun .base_reg = PLLU_BASE,
397e9034789SMichal Meloun .misc_reg = PLLU_MISC,
398e9034789SMichal Meloun .lock_enable = PLLU_LOCK_ENABLE,
399e9034789SMichal Meloun .iddq_reg = PLLU_MISC,
400e9034789SMichal Meloun .iddq_mask = 1 << PLLU_IDDQ_BIT,
401e9034789SMichal Meloun .pdiv_table = qlin_map,
402e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 8, 16},
403e9034789SMichal Meloun },
404e9034789SMichal Meloun /* PLLD: 594 MHz Clock sources for the DSI and display subsystem */
405e9034789SMichal Meloun {
406e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_D, "pllD_out", "osc_div_clk"),
407e9034789SMichal Meloun .type = PLL_D,
408e9034789SMichal Meloun .flags = PLL_FLAG_PDIV_POWER2,
409e9034789SMichal Meloun .base_reg = PLLD_BASE,
410e9034789SMichal Meloun .misc_reg = PLLD_MISC,
411e9034789SMichal Meloun .lock_enable = PLL_MISC_LOCK_ENABLE,
412e9034789SMichal Meloun .iddq_reg = PLLA1_MISC_1,
413e9034789SMichal Meloun .iddq_mask = 1 << PLLA_IDDQ_BIT,
414e9034789SMichal Meloun .mnp_bits = {8, 8, 3, 0, 11, 20},
415e9034789SMichal Meloun },
416e9034789SMichal Meloun /* PLLD2: 594 MHz Clock sources for the DSI and display subsystem */
417e9034789SMichal Meloun {
418e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_D2, "pllD2_out", "pllD2_src"),
419e9034789SMichal Meloun .type = PLL_D2,
420e9034789SMichal Meloun .flags = PLL_FLAG_HAVE_SDM,
421e9034789SMichal Meloun .base_reg = PLLD2_BASE,
422e9034789SMichal Meloun .misc_reg = PLLD2_MISC,
423e9034789SMichal Meloun .lock_enable = PLLD2_LOCK_ENABLE,
424e9034789SMichal Meloun .iddq_reg = PLLD2_BASE,
425e9034789SMichal Meloun .iddq_mask = 1 << PLLD_IDDQ_BIT,
426e9034789SMichal Meloun .pdiv_table = qlin_map,
427e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 8, 19},
428e9034789SMichal Meloun },
429e9034789SMichal Meloun /* PLLREFE: 624 Mhz*/
430e9034789SMichal Meloun {
431e9034789SMichal Meloun PLL(0, "pllREFE", "osc_div_clk"),
432e9034789SMichal Meloun .type = PLL_REFE,
433e9034789SMichal Meloun .flags = PLL_FLAG_VCO_OUT,
434e9034789SMichal Meloun .base_reg = PLLREFE_BASE,
435e9034789SMichal Meloun .misc_reg = PLLREFE_MISC,
436e9034789SMichal Meloun .lock_enable = PLLREFE_LOCK_ENABLE,
437e9034789SMichal Meloun .iddq_reg = PLLREFE_MISC,
438e9034789SMichal Meloun .iddq_mask = 1 << PLLREFE_IDDQ_BIT,
439e9034789SMichal Meloun .pdiv_table = qlin_map,
440e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 8, 16},
441e9034789SMichal Meloun },
442e9034789SMichal Meloun /* PLLE: 100 MHz reference clock for PCIe/SATA/USB 3.0 (spread spectrum) */
443e9034789SMichal Meloun {
444e9034789SMichal Meloun PLL(TEGRA210_CLK_PLL_E, "pllE_out0", "pllE_src"),
445e9034789SMichal Meloun .type = PLL_E,
446e9034789SMichal Meloun .base_reg = PLLE_BASE,
447e9034789SMichal Meloun .misc_reg = PLLE_MISC,
448e9034789SMichal Meloun .lock_enable = PLLE_LOCK_ENABLE,
449e9034789SMichal Meloun .pdiv_table = qlin_map,
450e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 8, 24},
451e9034789SMichal Meloun },
452e9034789SMichal Meloun /* PLLDP: 270 MHz Clock source fordisplay SOR (spread spectrum) */
453e9034789SMichal Meloun {
454e9034789SMichal Meloun PLL(0, "pllDP_out0", "pllDP_src"),
455e9034789SMichal Meloun .type = PLL_DP,
456e9034789SMichal Meloun .flags = PLL_FLAG_HAVE_SDM,
457e9034789SMichal Meloun .base_reg = PLLDP_BASE,
458e9034789SMichal Meloun .misc_reg = PLLDP_MISC,
459e9034789SMichal Meloun .lock_enable = PLLPD_LOCK_ENABLE,
460e9034789SMichal Meloun .iddq_reg = PLLDP_BASE,
461e9034789SMichal Meloun .iddq_mask = 1 << PLLDP_IDDQ_BIT,
462e9034789SMichal Meloun .pdiv_table = qlin_map,
463e9034789SMichal Meloun .mnp_bits = {8, 8, 5, 0, 8, 19},
464e9034789SMichal Meloun },
465e9034789SMichal Meloun };
466e9034789SMichal Meloun
467e9034789SMichal Meloun /* Fixed rate dividers. */
468e9034789SMichal Meloun static struct clk_fixed_def tegra210_pll_fdivs[] = {
469e9034789SMichal Meloun FACT(0, "pllP_UD", "pllP_out0", 1, 1),
470e9034789SMichal Meloun FACT(0, "pllC_UD", "pllC_out0", 1, 1),
471e9034789SMichal Meloun FACT(0, "pllD_UD", "pllD_out0", 1, 1),
472e9034789SMichal Meloun FACT(0, "pllM_UD", "pllM_out0", 1, 1),
473e9034789SMichal Meloun FACT(0, "pllMB_UD", "pllMB_out0", 1, 1),
474e9034789SMichal Meloun FACT(TEGRA210_CLK_PLL_D_OUT0, "pllD_out0", "pllD_out", 1, 2),
475e9034789SMichal Meloun
476e9034789SMichal Meloun FACT(0, "pllC4_out1", "pllC4", 1, 3),
477e9034789SMichal Meloun FACT(0, "pllC4_out2", "pllC4", 1, 5),
478e9034789SMichal Meloun FACT(0, "pllD2_out0", "pllD2_out", 1, 2),
479e9034789SMichal Meloun
480e9034789SMichal Meloun /* Aliases used in super mux. */
481e9034789SMichal Meloun FACT(0, "pllX_out0_alias", "pllX_out0", 1, 1),
482e9034789SMichal Meloun FACT(0, "dfllCPU_out_alias", "dfllCPU_out", 1, 1),
483e9034789SMichal Meloun };
484e9034789SMichal Meloun
485e9034789SMichal Meloun /* MUXes for PLL sources. */
486e9034789SMichal Meloun PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */
487e9034789SMichal Meloun PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"};
488e9034789SMichal Meloun PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out0"};
489e9034789SMichal Meloun static struct clk_mux_def tegra210_pll_sources[] = {
490e9034789SMichal Meloun /* Core clocks. */
491e9034789SMichal Meloun MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2),
492e9034789SMichal Meloun MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2),
493e9034789SMichal Meloun MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2),
494e9034789SMichal Meloun MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1),
495e9034789SMichal Meloun MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1),
496e9034789SMichal Meloun };
497e9034789SMichal Meloun
498e9034789SMichal Meloun /* Gates for PLL branches. */
499e9034789SMichal Meloun static struct clk_gate_def tegra210_pll_gates[] = {
500e9034789SMichal Meloun /* Core clocks. */
501e9034789SMichal Meloun GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0),
502e9034789SMichal Meloun
503e9034789SMichal Meloun GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0),
504e9034789SMichal Meloun GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0),
505e9034789SMichal Meloun GATE_PLL(TEGRA210_CLK_PLL_P_OUT4, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16),
506e9034789SMichal Meloun GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16),
507e9034789SMichal Meloun
508e9034789SMichal Meloun GATE_PLL(0, "pllU_out1", "pllU_out1_div", PLLU_OUTA, 0),
509e9034789SMichal Meloun GATE_PLL(0, "pllU_out2", "pllU_out2_div", PLLU_OUTA, 16),
510e9034789SMichal Meloun GATE(0, "pllU_480", "pllU", PLLU_BASE, 22),
511e9034789SMichal Meloun GATE(0, "pllU_60", "pllU_out2", PLLU_BASE, 23),
512e9034789SMichal Meloun GATE(0, "pllU_48", "pllU_out1", PLLU_BASE, 25),
513e9034789SMichal Meloun
514e9034789SMichal Meloun GATE_PLL(0, "pllREFE_out1", "pllREFE_out1_div", PLLREFE_OUT, 0),
515e9034789SMichal Meloun GATE_PLL(0, "pllC4_out3", "pllC4_out3_div", PLLC4_OUT, 0),
516e9034789SMichal Meloun
517e9034789SMichal Meloun GATE_PLL(0, "pllA_out0", "pllA_out0_div", PLLA_OUT, 0),
518e9034789SMichal Meloun };
519e9034789SMichal Meloun
520e9034789SMichal Meloun struct clk_div_table tegra210_pll_pdiv_tbl[] = {
521e9034789SMichal Meloun /* value , divider */
522e9034789SMichal Meloun { 0, 1 },
523e9034789SMichal Meloun { 1, 2 },
524e9034789SMichal Meloun { 2, 3 },
525e9034789SMichal Meloun { 3, 4 },
526e9034789SMichal Meloun { 4, 5 },
527e9034789SMichal Meloun { 5, 6 },
528e9034789SMichal Meloun { 6, 8 },
529e9034789SMichal Meloun { 7, 10 },
530e9034789SMichal Meloun { 8, 12 },
531e9034789SMichal Meloun { 9, 16 },
532e9034789SMichal Meloun {10, 12 },
533e9034789SMichal Meloun {11, 16 },
534e9034789SMichal Meloun {12, 20 },
535e9034789SMichal Meloun {13, 24 },
536e9034789SMichal Meloun {14, 32 },
537e9034789SMichal Meloun { 0, 0 },
538e9034789SMichal Meloun };
539e9034789SMichal Meloun
540e9034789SMichal Meloun /* Dividers for PLL branches. */
541e9034789SMichal Meloun static struct clk_div_def tegra210_pll_divs[] = {
542e9034789SMichal Meloun /* Core clocks. */
543e9034789SMichal Meloun DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 8),
544e9034789SMichal Meloun
545e9034789SMichal Meloun DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8),
546e9034789SMichal Meloun DIV_TB(0, "pllP_out2", "pllP_out0", PLLP_BASE, 20, 5, tegra210_pll_pdiv_tbl),
547e9034789SMichal Meloun DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8),
548e9034789SMichal Meloun DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24),
549e9034789SMichal Meloun DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24),
550e9034789SMichal Meloun
551e9034789SMichal Meloun DIV_TB(0, "pllU_out0", "pllU", PLLU_BASE, 16, 5, tegra210_pll_pdiv_tbl),
552e9034789SMichal Meloun DIV7_1(0, "pllU_out1_div", "pllU_out0", PLLU_OUTA, 8),
553e9034789SMichal Meloun DIV7_1(0, "pllU_out2_div", "pllU_out0", PLLU_OUTA, 24),
554e9034789SMichal Meloun
555e9034789SMichal Meloun DIV_TB(0, "pllREFE_out0", "pllREFE", PLLREFE_BASE, 16, 5, tegra210_pll_pdiv_tbl),
556e9034789SMichal Meloun DIV7_1(0, "pllREFE_out1_div", "pllREFE", PLLREFE_OUT, 8),
557e9034789SMichal Meloun
558e9034789SMichal Meloun DIV_TB(TEGRA210_CLK_PLL_C4_OUT0,
559e9034789SMichal Meloun "pllC4_out0", "pllC4", PLLC4_BASE, 19, 5, tegra210_pll_pdiv_tbl),
560e9034789SMichal Meloun DIV7_1(0, "pllC4_out3_div", "pllC4_out0", PLLC4_OUT, 8),
561e9034789SMichal Meloun
562e9034789SMichal Meloun DIV7_1(0, "pllA_out0_div", "pllA", PLLA_OUT, 8),
563e9034789SMichal Meloun
564e9034789SMichal Meloun };
565e9034789SMichal Meloun
566e9034789SMichal Meloun static int tegra210_pll_init(struct clknode *clk, device_t dev);
567e9034789SMichal Meloun static int tegra210_pll_set_gate(struct clknode *clk, bool enable);
5687c0ec663SMichal Meloun static int tegra210_pll_get_gate(struct clknode *clk, bool *enabled);
569e9034789SMichal Meloun static int tegra210_pll_recalc(struct clknode *clk, uint64_t *freq);
570e9034789SMichal Meloun static int tegra210_pll_set_freq(struct clknode *clknode, uint64_t fin,
571e9034789SMichal Meloun uint64_t *fout, int flags, int *stop);
572e9034789SMichal Meloun struct pll_sc {
573e9034789SMichal Meloun device_t clkdev;
574e9034789SMichal Meloun enum pll_type type;
575e9034789SMichal Meloun uint32_t base_reg;
576e9034789SMichal Meloun uint32_t misc_reg;
577e9034789SMichal Meloun uint32_t lock_enable;
578e9034789SMichal Meloun uint32_t iddq_reg;
579e9034789SMichal Meloun uint32_t iddq_mask;
580e9034789SMichal Meloun uint32_t flags;
581e9034789SMichal Meloun struct pdiv_table *pdiv_table;
582e9034789SMichal Meloun struct mnp_bits mnp_bits;
583e9034789SMichal Meloun };
584e9034789SMichal Meloun
585e9034789SMichal Meloun static clknode_method_t tegra210_pll_methods[] = {
586e9034789SMichal Meloun /* Device interface */
587e9034789SMichal Meloun CLKNODEMETHOD(clknode_init, tegra210_pll_init),
588e9034789SMichal Meloun CLKNODEMETHOD(clknode_set_gate, tegra210_pll_set_gate),
5897c0ec663SMichal Meloun CLKNODEMETHOD(clknode_get_gate, tegra210_pll_get_gate),
590e9034789SMichal Meloun CLKNODEMETHOD(clknode_recalc_freq, tegra210_pll_recalc),
591e9034789SMichal Meloun CLKNODEMETHOD(clknode_set_freq, tegra210_pll_set_freq),
592e9034789SMichal Meloun CLKNODEMETHOD_END
593e9034789SMichal Meloun };
594e9034789SMichal Meloun DEFINE_CLASS_1(tegra210_pll, tegra210_pll_class, tegra210_pll_methods,
595e9034789SMichal Meloun sizeof(struct pll_sc), clknode_class);
596e9034789SMichal Meloun
597e9034789SMichal Meloun static int
pll_enable(struct pll_sc * sc)598e9034789SMichal Meloun pll_enable(struct pll_sc *sc)
599e9034789SMichal Meloun {
600e9034789SMichal Meloun uint32_t reg;
601e9034789SMichal Meloun
602e9034789SMichal Meloun
603e9034789SMichal Meloun RD4(sc, sc->base_reg, ®);
604e9034789SMichal Meloun if (sc->type != PLL_E)
605e9034789SMichal Meloun reg &= ~PLL_BASE_BYPASS;
606e9034789SMichal Meloun reg |= PLL_BASE_ENABLE;
607e9034789SMichal Meloun WR4(sc, sc->base_reg, reg);
608e9034789SMichal Meloun return (0);
609e9034789SMichal Meloun }
610e9034789SMichal Meloun
611e9034789SMichal Meloun static int
pll_disable(struct pll_sc * sc)612e9034789SMichal Meloun pll_disable(struct pll_sc *sc)
613e9034789SMichal Meloun {
614e9034789SMichal Meloun uint32_t reg;
615e9034789SMichal Meloun
616e9034789SMichal Meloun RD4(sc, sc->base_reg, ®);
617e9034789SMichal Meloun if (sc->type != PLL_E)
618e9034789SMichal Meloun reg |= PLL_BASE_BYPASS;
619e9034789SMichal Meloun reg &= ~PLL_BASE_ENABLE;
620e9034789SMichal Meloun WR4(sc, sc->base_reg, reg);
621e9034789SMichal Meloun return (0);
622e9034789SMichal Meloun }
623e9034789SMichal Meloun
624e9034789SMichal Meloun static uint32_t
pdiv_to_reg(struct pll_sc * sc,uint32_t p_div)625e9034789SMichal Meloun pdiv_to_reg(struct pll_sc *sc, uint32_t p_div)
626e9034789SMichal Meloun {
627e9034789SMichal Meloun struct pdiv_table *tbl;
628e9034789SMichal Meloun
629e9034789SMichal Meloun tbl = sc->pdiv_table;
630e9034789SMichal Meloun if (tbl == NULL) {
631e9034789SMichal Meloun if (sc->flags & PLL_FLAG_PDIV_POWER2)
632e9034789SMichal Meloun return (ffs(p_div) - 1);
633e9034789SMichal Meloun else
634e9034789SMichal Meloun return (p_div);
635e9034789SMichal Meloun }
636e9034789SMichal Meloun
637e9034789SMichal Meloun while (tbl->divider != 0) {
638e9034789SMichal Meloun if (p_div <= tbl->divider)
639e9034789SMichal Meloun return (tbl->value);
640e9034789SMichal Meloun tbl++;
641e9034789SMichal Meloun }
642e9034789SMichal Meloun return (0xFFFFFFFF);
643e9034789SMichal Meloun }
644e9034789SMichal Meloun
645e9034789SMichal Meloun static uint32_t
reg_to_pdiv(struct pll_sc * sc,uint32_t reg)646e9034789SMichal Meloun reg_to_pdiv(struct pll_sc *sc, uint32_t reg)
647e9034789SMichal Meloun {
648e9034789SMichal Meloun struct pdiv_table *tbl;
649e9034789SMichal Meloun
650e9034789SMichal Meloun tbl = sc->pdiv_table;
651e9034789SMichal Meloun if (tbl == NULL) {
652e9034789SMichal Meloun if (sc->flags & PLL_FLAG_PDIV_POWER2)
653e9034789SMichal Meloun return (1 << reg);
654e9034789SMichal Meloun else
655e9034789SMichal Meloun return (reg == 0 ? 1: reg);
656e9034789SMichal Meloun }
657e9034789SMichal Meloun while (tbl->divider) {
658e9034789SMichal Meloun if (reg == tbl->value)
659e9034789SMichal Meloun return (tbl->divider);
660e9034789SMichal Meloun tbl++;
661e9034789SMichal Meloun }
662e9034789SMichal Meloun return (0);
663e9034789SMichal Meloun }
664e9034789SMichal Meloun
665e9034789SMichal Meloun static uint32_t
get_masked(uint32_t val,uint32_t shift,uint32_t width)666e9034789SMichal Meloun get_masked(uint32_t val, uint32_t shift, uint32_t width)
667e9034789SMichal Meloun {
668e9034789SMichal Meloun
669e9034789SMichal Meloun return ((val >> shift) & ((1 << width) - 1));
670e9034789SMichal Meloun }
671e9034789SMichal Meloun
672e9034789SMichal Meloun static uint32_t
set_masked(uint32_t val,uint32_t v,uint32_t shift,uint32_t width)673e9034789SMichal Meloun set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width)
674e9034789SMichal Meloun {
675e9034789SMichal Meloun
676e9034789SMichal Meloun val &= ~(((1 << width) - 1) << shift);
677e9034789SMichal Meloun val |= (v & ((1 << width) - 1)) << shift;
678e9034789SMichal Meloun return (val);
679e9034789SMichal Meloun }
680e9034789SMichal Meloun
681e9034789SMichal Meloun static void
get_divisors(struct pll_sc * sc,uint32_t * m,uint32_t * n,uint32_t * p)682e9034789SMichal Meloun get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p)
683e9034789SMichal Meloun {
684e9034789SMichal Meloun uint32_t val;
685e9034789SMichal Meloun struct mnp_bits *mnp_bits;
686e9034789SMichal Meloun
687e9034789SMichal Meloun mnp_bits = &sc->mnp_bits;
688e9034789SMichal Meloun RD4(sc, sc->base_reg, &val);
689e9034789SMichal Meloun *m = get_masked(val, mnp_bits->m_shift, mnp_bits->m_width);
690e9034789SMichal Meloun *n = get_masked(val, mnp_bits->n_shift, mnp_bits->n_width);
691e9034789SMichal Meloun *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width);
692e9034789SMichal Meloun }
693e9034789SMichal Meloun
694e9034789SMichal Meloun static uint32_t
set_divisors(struct pll_sc * sc,uint32_t val,uint32_t m,uint32_t n,uint32_t p)695e9034789SMichal Meloun set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n,
696e9034789SMichal Meloun uint32_t p)
697e9034789SMichal Meloun {
698e9034789SMichal Meloun struct mnp_bits *mnp_bits;
699e9034789SMichal Meloun
700e9034789SMichal Meloun mnp_bits = &sc->mnp_bits;
701e9034789SMichal Meloun val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width);
702e9034789SMichal Meloun val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width);
703e9034789SMichal Meloun val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width);
704e9034789SMichal Meloun return (val);
705e9034789SMichal Meloun }
706e9034789SMichal Meloun
707e9034789SMichal Meloun static bool
is_locked(struct pll_sc * sc)708e9034789SMichal Meloun is_locked(struct pll_sc *sc)
709e9034789SMichal Meloun {
710e9034789SMichal Meloun uint32_t reg;
711e9034789SMichal Meloun
712e9034789SMichal Meloun switch (sc->type) {
713e9034789SMichal Meloun case PLL_REFE:
714e9034789SMichal Meloun RD4(sc, sc->misc_reg, ®);
715e9034789SMichal Meloun reg &= PLLREFE_MISC_LOCK;
716e9034789SMichal Meloun break;
717e9034789SMichal Meloun
718e9034789SMichal Meloun case PLL_E:
719e9034789SMichal Meloun RD4(sc, sc->misc_reg, ®);
720e9034789SMichal Meloun reg &= PLLE_MISC_LOCK;
721e9034789SMichal Meloun break;
722e9034789SMichal Meloun
723e9034789SMichal Meloun default:
724e9034789SMichal Meloun RD4(sc, sc->base_reg, ®);
725e9034789SMichal Meloun reg &= PLL_BASE_LOCK;
726e9034789SMichal Meloun break;
727e9034789SMichal Meloun }
728e9034789SMichal Meloun return (reg != 0);
729e9034789SMichal Meloun }
730e9034789SMichal Meloun
731e9034789SMichal Meloun static int
wait_for_lock(struct pll_sc * sc)732e9034789SMichal Meloun wait_for_lock(struct pll_sc *sc)
733e9034789SMichal Meloun {
734e9034789SMichal Meloun int i;
735e9034789SMichal Meloun
736e9034789SMichal Meloun for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) {
737e9034789SMichal Meloun if (is_locked(sc))
738e9034789SMichal Meloun break;
739e9034789SMichal Meloun DELAY(10);
740e9034789SMichal Meloun }
741e9034789SMichal Meloun if (i <= 0) {
742e9034789SMichal Meloun printf("PLL lock timeout\n");
743e9034789SMichal Meloun return (ETIMEDOUT);
744e9034789SMichal Meloun }
745e9034789SMichal Meloun return (0);
746e9034789SMichal Meloun }
747e9034789SMichal Meloun
748e9034789SMichal Meloun static int
plle_enable(struct pll_sc * sc)749e9034789SMichal Meloun plle_enable(struct pll_sc *sc)
750e9034789SMichal Meloun {
751e9034789SMichal Meloun uint32_t reg;
752e9034789SMichal Meloun int rv;
753e9034789SMichal Meloun uint32_t pll_m = 2;
754e9034789SMichal Meloun uint32_t pll_n = 125;
755e9034789SMichal Meloun uint32_t pll_cml = 14;
756e9034789SMichal Meloun
757e9034789SMichal Meloun /* Disable lock override. */
758e9034789SMichal Meloun RD4(sc, sc->base_reg, ®);
759e9034789SMichal Meloun reg &= ~PLLE_BASE_LOCK_OVERRIDE;
760e9034789SMichal Meloun WR4(sc, sc->base_reg, reg);
761e9034789SMichal Meloun
762e9034789SMichal Meloun /* Enable SW control */
763e9034789SMichal Meloun RD4(sc, PLLE_AUX, ®);
764e9034789SMichal Meloun reg |= PLLE_AUX_ENABLE_SWCTL;
765e9034789SMichal Meloun reg &= ~PLLE_AUX_SEQ_ENABLE;
766e9034789SMichal Meloun WR4(sc, PLLE_AUX, reg);
767e9034789SMichal Meloun DELAY(10);
768e9034789SMichal Meloun
769e9034789SMichal Meloun RD4(sc, sc->misc_reg, ®);
770e9034789SMichal Meloun reg |= PLLE_MISC_LOCK_ENABLE;
771e9034789SMichal Meloun reg |= PLLE_MISC_IDDQ_SWCTL;
772e9034789SMichal Meloun reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;
773e9034789SMichal Meloun reg |= PLLE_MISC_PTS;
774e9034789SMichal Meloun reg &= ~PLLE_MISC_VREG_BG_CTRL(~0);
775e9034789SMichal Meloun reg &= ~PLLE_MISC_VREG_CTRL(~0);
776e9034789SMichal Meloun WR4(sc, sc->misc_reg, reg);
777e9034789SMichal Meloun DELAY(10);
778e9034789SMichal Meloun
779e9034789SMichal Meloun RD4(sc, PLLE_SS_CNTL, ®);
780e9034789SMichal Meloun reg |= PLLE_SS_CNTL_DISABLE;
781e9034789SMichal Meloun WR4(sc, PLLE_SS_CNTL, reg);
782e9034789SMichal Meloun
783e9034789SMichal Meloun RD4(sc, sc->base_reg, ®);
784e9034789SMichal Meloun reg = set_divisors(sc, reg, pll_m, pll_n, pll_cml);
785e9034789SMichal Meloun WR4(sc, sc->base_reg, reg);
786e9034789SMichal Meloun DELAY(10);
787e9034789SMichal Meloun
788e9034789SMichal Meloun pll_enable(sc);
789e9034789SMichal Meloun rv = wait_for_lock(sc);
790e9034789SMichal Meloun if (rv != 0)
791e9034789SMichal Meloun return (rv);
792e9034789SMichal Meloun
793e9034789SMichal Meloun RD4(sc, PLLE_SS_CNTL, ®);
794e9034789SMichal Meloun reg &= ~PLLE_SS_CNTL_SSCINCINTRV(~0);
795e9034789SMichal Meloun reg &= ~PLLE_SS_CNTL_SSCINC(~0);
796e9034789SMichal Meloun reg &= ~PLLE_SS_CNTL_SSCINVERT;
797e9034789SMichal Meloun reg &= ~PLLE_SS_CNTL_SSCCENTER;
798e9034789SMichal Meloun reg &= ~PLLE_SS_CNTL_SSCMAX(~0);
799e9034789SMichal Meloun reg |= PLLE_SS_CNTL_SSCINCINTRV(0x23);
800e9034789SMichal Meloun reg |= PLLE_SS_CNTL_SSCINC(0x1);
801e9034789SMichal Meloun reg |= PLLE_SS_CNTL_SSCMAX(0x21);
802e9034789SMichal Meloun WR4(sc, PLLE_SS_CNTL, reg);
803e9034789SMichal Meloun reg &= ~PLLE_SS_CNTL_SSCBYP;
804e9034789SMichal Meloun reg &= ~PLLE_SS_CNTL_BYPASS_SS;
805e9034789SMichal Meloun WR4(sc, PLLE_SS_CNTL, reg);
806e9034789SMichal Meloun DELAY(10);
807e9034789SMichal Meloun
808e9034789SMichal Meloun reg &= ~PLLE_SS_CNTL_INTERP_RESET;
809e9034789SMichal Meloun WR4(sc, PLLE_SS_CNTL, reg);
810e9034789SMichal Meloun DELAY(10);
811e9034789SMichal Meloun
812e9034789SMichal Meloun /* HW control of brick pll. */
813e9034789SMichal Meloun RD4(sc, sc->misc_reg, ®);
814e9034789SMichal Meloun reg &= ~PLLE_MISC_IDDQ_SWCTL;
815e9034789SMichal Meloun WR4(sc, sc->misc_reg, reg);
816e9034789SMichal Meloun
817e9034789SMichal Meloun RD4(sc, PLLE_AUX, ®);
818e9034789SMichal Meloun reg |= PLLE_AUX_USE_LOCKDET;
819e9034789SMichal Meloun reg |= PLLE_AUX_SS_SEQ_INCLUDE;
820e9034789SMichal Meloun reg &= ~PLLE_AUX_ENABLE_SWCTL;
821e9034789SMichal Meloun reg &= ~PLLE_AUX_SS_SWCTL;
822e9034789SMichal Meloun WR4(sc, PLLE_AUX, reg);
823e9034789SMichal Meloun reg |= PLLE_AUX_SEQ_START_STATE;
824e9034789SMichal Meloun DELAY(10);
825e9034789SMichal Meloun reg |= PLLE_AUX_SEQ_ENABLE;
826e9034789SMichal Meloun WR4(sc, PLLE_AUX, reg);
827e9034789SMichal Meloun
828e9034789SMichal Meloun /* Enable and start XUSBIO PLL HW control*/
829e9034789SMichal Meloun RD4(sc, XUSBIO_PLL_CFG0, ®);
830e9034789SMichal Meloun reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
831e9034789SMichal Meloun reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
832e9034789SMichal Meloun reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
833e9034789SMichal Meloun reg |= XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
834e9034789SMichal Meloun reg &= ~XUSBIO_PLL_CFG0_SEQ_ENABLE;
835e9034789SMichal Meloun WR4(sc, XUSBIO_PLL_CFG0, reg);
836e9034789SMichal Meloun DELAY(10);
837e9034789SMichal Meloun
838e9034789SMichal Meloun reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
839e9034789SMichal Meloun WR4(sc, XUSBIO_PLL_CFG0, reg);
840e9034789SMichal Meloun
841e9034789SMichal Meloun
842e9034789SMichal Meloun /* Enable and start SATA PLL HW control */
843e9034789SMichal Meloun RD4(sc, SATA_PLL_CFG0, ®);
844e9034789SMichal Meloun reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
845e9034789SMichal Meloun reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE;
846e9034789SMichal Meloun reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
847e9034789SMichal Meloun reg |= SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ;
848e9034789SMichal Meloun reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL;
849e9034789SMichal Meloun reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE;
850e9034789SMichal Meloun reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE;
851e9034789SMichal Meloun reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE;
852e9034789SMichal Meloun reg &= ~SATA_PLL_CFG0_SEQ_ENABLE;
853e9034789SMichal Meloun WR4(sc, SATA_PLL_CFG0, reg);
854e9034789SMichal Meloun DELAY(10);
855e9034789SMichal Meloun reg |= SATA_PLL_CFG0_SEQ_ENABLE;
856e9034789SMichal Meloun WR4(sc, SATA_PLL_CFG0, reg);
857e9034789SMichal Meloun
858e9034789SMichal Meloun /* Enable HW control of PCIe PLL. */
859e9034789SMichal Meloun RD4(sc, PCIE_PLL_CFG, ®);
860e9034789SMichal Meloun reg |= PCIE_PLL_CFG_SEQ_ENABLE;
861e9034789SMichal Meloun WR4(sc, PCIE_PLL_CFG, reg);
862e9034789SMichal Meloun
863e9034789SMichal Meloun return (0);
864e9034789SMichal Meloun }
865e9034789SMichal Meloun
866e9034789SMichal Meloun static int
tegra210_pll_set_gate(struct clknode * clknode,bool enable)867e9034789SMichal Meloun tegra210_pll_set_gate(struct clknode *clknode, bool enable)
868e9034789SMichal Meloun {
869e9034789SMichal Meloun int rv;
870e9034789SMichal Meloun struct pll_sc *sc;
871e9034789SMichal Meloun
872e9034789SMichal Meloun sc = clknode_get_softc(clknode);
873e9034789SMichal Meloun if (enable == 0) {
874e9034789SMichal Meloun rv = pll_disable(sc);
875e9034789SMichal Meloun return(rv);
876e9034789SMichal Meloun }
877e9034789SMichal Meloun
878e9034789SMichal Meloun if (sc->type == PLL_E)
879e9034789SMichal Meloun rv = plle_enable(sc);
880e9034789SMichal Meloun else
881e9034789SMichal Meloun rv = pll_enable(sc);
882e9034789SMichal Meloun return (rv);
883e9034789SMichal Meloun }
884e9034789SMichal Meloun
885e9034789SMichal Meloun static int
tegra210_pll_get_gate(struct clknode * clknode,bool * enabled)8867c0ec663SMichal Meloun tegra210_pll_get_gate(struct clknode *clknode, bool *enabled)
8877c0ec663SMichal Meloun {
8887c0ec663SMichal Meloun uint32_t reg;
8897c0ec663SMichal Meloun struct pll_sc *sc;
8907c0ec663SMichal Meloun
8917c0ec663SMichal Meloun sc = clknode_get_softc(clknode);
8927c0ec663SMichal Meloun RD4(sc, sc->base_reg, ®);
8937c0ec663SMichal Meloun *enabled = reg & PLL_BASE_ENABLE ? true: false;
8947c0ec663SMichal Meloun WR4(sc, sc->base_reg, reg);
8957c0ec663SMichal Meloun return (0);
8967c0ec663SMichal Meloun }
8977c0ec663SMichal Meloun
8987c0ec663SMichal Meloun static int
pll_set_std(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags,uint32_t m,uint32_t n,uint32_t p)899e9034789SMichal Meloun pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags,
900e9034789SMichal Meloun uint32_t m, uint32_t n, uint32_t p)
901e9034789SMichal Meloun {
902e9034789SMichal Meloun uint32_t reg;
903e9034789SMichal Meloun struct mnp_bits *mnp_bits;
904e9034789SMichal Meloun int rv;
905e9034789SMichal Meloun
906e9034789SMichal Meloun mnp_bits = &sc->mnp_bits;
907e9034789SMichal Meloun if (m >= (1 << mnp_bits->m_width))
908e9034789SMichal Meloun return (ERANGE);
909e9034789SMichal Meloun if (n >= (1 << mnp_bits->n_width))
910e9034789SMichal Meloun return (ERANGE);
911e9034789SMichal Meloun if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
912e9034789SMichal Meloun return (ERANGE);
913e9034789SMichal Meloun
914e9034789SMichal Meloun if (flags & CLK_SET_DRYRUN) {
915e9034789SMichal Meloun if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
916e9034789SMichal Meloun (*fout != (((fin / m) * n) /p)))
917e9034789SMichal Meloun return (ERANGE);
918e9034789SMichal Meloun
919e9034789SMichal Meloun *fout = ((fin / m) * n) /p;
920e9034789SMichal Meloun
921e9034789SMichal Meloun return (0);
922e9034789SMichal Meloun }
923e9034789SMichal Meloun
924e9034789SMichal Meloun pll_disable(sc);
925e9034789SMichal Meloun
926e9034789SMichal Meloun /* take pll out of IDDQ */
927e9034789SMichal Meloun if (sc->iddq_reg != 0)
928e9034789SMichal Meloun MD4(sc, sc->iddq_reg, sc->iddq_mask, 0);
929e9034789SMichal Meloun
930e9034789SMichal Meloun RD4(sc, sc->base_reg, ®);
931e9034789SMichal Meloun reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width);
932e9034789SMichal Meloun reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width);
933e9034789SMichal Meloun reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
934e9034789SMichal Meloun mnp_bits->p_width);
935e9034789SMichal Meloun WR4(sc, sc->base_reg, reg);
936e9034789SMichal Meloun
937e9034789SMichal Meloun /* Enable PLL. */
938e9034789SMichal Meloun RD4(sc, sc->base_reg, ®);
939e9034789SMichal Meloun reg |= PLL_BASE_ENABLE;
940e9034789SMichal Meloun WR4(sc, sc->base_reg, reg);
941e9034789SMichal Meloun
942e9034789SMichal Meloun /* Enable lock detection. */
943e9034789SMichal Meloun RD4(sc, sc->misc_reg, ®);
944e9034789SMichal Meloun reg |= sc->lock_enable;
945e9034789SMichal Meloun WR4(sc, sc->misc_reg, reg);
946e9034789SMichal Meloun
947e9034789SMichal Meloun rv = wait_for_lock(sc);
948e9034789SMichal Meloun if (rv != 0) {
949e9034789SMichal Meloun /* Disable PLL */
950e9034789SMichal Meloun RD4(sc, sc->base_reg, ®);
951e9034789SMichal Meloun reg &= ~PLL_BASE_ENABLE;
952e9034789SMichal Meloun WR4(sc, sc->base_reg, reg);
953e9034789SMichal Meloun return (rv);
954e9034789SMichal Meloun }
955e9034789SMichal Meloun RD4(sc, sc->misc_reg, ®);
956e9034789SMichal Meloun
957e9034789SMichal Meloun pll_enable(sc);
958e9034789SMichal Meloun *fout = ((fin / m) * n) / p;
959e9034789SMichal Meloun return 0;
960e9034789SMichal Meloun }
961e9034789SMichal Meloun
962e9034789SMichal Meloun static int
plla_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)963e9034789SMichal Meloun plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
964e9034789SMichal Meloun {
965e9034789SMichal Meloun uint32_t m, n, p;
966e9034789SMichal Meloun
967e9034789SMichal Meloun p = 1;
968e9034789SMichal Meloun m = 3;
969e9034789SMichal Meloun n = (*fout * p * m + fin / 2)/ fin;
970e9034789SMichal Meloun dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
971e9034789SMichal Meloun return (pll_set_std(sc, fin, fout, flags, m, n, p));
972e9034789SMichal Meloun }
973e9034789SMichal Meloun
974e9034789SMichal Meloun static int
pllc_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)975e9034789SMichal Meloun pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
976e9034789SMichal Meloun {
977e9034789SMichal Meloun uint32_t m, n, p;
978e9034789SMichal Meloun
979e9034789SMichal Meloun p = 2;
980e9034789SMichal Meloun m = 3;
981e9034789SMichal Meloun n = (*fout * p * m + fin / 2)/ fin;
982e9034789SMichal Meloun dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
983e9034789SMichal Meloun return (pll_set_std( sc, fin, fout, flags, m, n, p));
984e9034789SMichal Meloun }
985e9034789SMichal Meloun
986e9034789SMichal Meloun static int
pllc4_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)987e9034789SMichal Meloun pllc4_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
988e9034789SMichal Meloun {
989e9034789SMichal Meloun uint32_t m, n, p;
990e9034789SMichal Meloun
991e9034789SMichal Meloun p = 1;
992e9034789SMichal Meloun m = 4;
993e9034789SMichal Meloun n = (*fout * p * m + fin / 2)/ fin;
994e9034789SMichal Meloun dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
995e9034789SMichal Meloun return (pll_set_std( sc, fin, fout, flags, m, n, p));
996e9034789SMichal Meloun }
997e9034789SMichal Meloun
998e9034789SMichal Meloun static int
plldp_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)999e9034789SMichal Meloun plldp_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
1000e9034789SMichal Meloun {
1001e9034789SMichal Meloun uint32_t m, n, p;
1002e9034789SMichal Meloun
1003e9034789SMichal Meloun p = 1;
1004e9034789SMichal Meloun m = 4;
1005e9034789SMichal Meloun n = (*fout * p * m + fin / 2)/ fin;
1006e9034789SMichal Meloun dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
1007e9034789SMichal Meloun return (pll_set_std( sc, fin, fout, flags, m, n, p));
1008e9034789SMichal Meloun }
1009e9034789SMichal Meloun
1010e9034789SMichal Meloun
1011e9034789SMichal Meloun /*
1012e9034789SMichal Meloun * PLLD2 is used as source for pixel clock for HDMI.
1013e9034789SMichal Meloun * We must be able to set it frequency very flexibly and
1014e9034789SMichal Meloun * precisely (within 5% tolerance limit allowed by HDMI specs).
1015e9034789SMichal Meloun *
1016e9034789SMichal Meloun * For this reason, it is necessary to search the full state space.
1017e9034789SMichal Meloun * Fortunately, thanks to early cycle terminations, performance
1018e9034789SMichal Meloun * is within acceptable limits.
1019e9034789SMichal Meloun */
1020e9034789SMichal Meloun #define PLLD2_PFD_MIN 12000000 /* 12 MHz */
1021e9034789SMichal Meloun #define PLLD2_PFD_MAX 38400000 /* 38.4 MHz */
1022e9034789SMichal Meloun #define PLLD2_VCO_MIN 750000000 /* 750 MHz */
1023e9034789SMichal Meloun #define PLLD2_VCO_MAX 1500000000 /* 1.5 GHz */
1024e9034789SMichal Meloun
1025e9034789SMichal Meloun static int
plld2_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)1026e9034789SMichal Meloun plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
1027e9034789SMichal Meloun {
1028e9034789SMichal Meloun uint32_t m, n, p;
1029e9034789SMichal Meloun uint32_t best_m, best_n, best_p;
1030e9034789SMichal Meloun uint64_t vco, pfd;
1031e9034789SMichal Meloun int64_t err, best_err;
1032e9034789SMichal Meloun struct mnp_bits *mnp_bits;
1033e9034789SMichal Meloun struct pdiv_table *tbl;
1034e9034789SMichal Meloun int p_idx, rv;
1035e9034789SMichal Meloun
1036e9034789SMichal Meloun mnp_bits = &sc->mnp_bits;
1037e9034789SMichal Meloun tbl = sc->pdiv_table;
1038e9034789SMichal Meloun best_err = INT64_MAX;
1039e9034789SMichal Meloun
1040e9034789SMichal Meloun for (p_idx = 0; tbl[p_idx].divider != 0; p_idx++) {
1041e9034789SMichal Meloun p = tbl[p_idx].divider;
1042e9034789SMichal Meloun
1043e9034789SMichal Meloun /* Check constraints */
1044e9034789SMichal Meloun vco = *fout * p;
1045e9034789SMichal Meloun if (vco < PLLD2_VCO_MIN)
1046e9034789SMichal Meloun continue;
1047e9034789SMichal Meloun if (vco > PLLD2_VCO_MAX)
1048e9034789SMichal Meloun break;
1049e9034789SMichal Meloun
1050e9034789SMichal Meloun for (m = 1; m < (1 << mnp_bits->m_width); m++) {
1051e9034789SMichal Meloun n = (*fout * p * m + fin / 2) / fin;
1052e9034789SMichal Meloun
1053e9034789SMichal Meloun /* Check constraints */
1054e9034789SMichal Meloun if (n == 0)
1055e9034789SMichal Meloun continue;
1056e9034789SMichal Meloun if (n >= (1 << mnp_bits->n_width))
1057e9034789SMichal Meloun break;
1058e9034789SMichal Meloun vco = (fin * n) / m;
1059e9034789SMichal Meloun if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN)
1060e9034789SMichal Meloun continue;
1061e9034789SMichal Meloun pfd = fin / m;
1062e9034789SMichal Meloun if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN)
1063e9034789SMichal Meloun continue;
1064e9034789SMichal Meloun
1065e9034789SMichal Meloun /* Constraints passed, save best result */
1066e9034789SMichal Meloun err = *fout - vco / p;
1067e9034789SMichal Meloun if (err < 0)
1068e9034789SMichal Meloun err = -err;
1069e9034789SMichal Meloun if (err < best_err) {
1070e9034789SMichal Meloun best_err = err;
1071e9034789SMichal Meloun best_p = p;
1072e9034789SMichal Meloun best_m = m;
1073e9034789SMichal Meloun best_n = n;
1074e9034789SMichal Meloun }
1075e9034789SMichal Meloun if (err == 0)
1076e9034789SMichal Meloun goto done;
1077e9034789SMichal Meloun }
1078e9034789SMichal Meloun }
1079e9034789SMichal Meloun done:
1080e9034789SMichal Meloun /*
1081e9034789SMichal Meloun * HDMI specification allows 5% pixel clock tolerance,
1082e9034789SMichal Meloun * we will by a slightly stricter
1083e9034789SMichal Meloun */
1084e9034789SMichal Meloun if (best_err > ((*fout * 100) / 4))
1085e9034789SMichal Meloun return (ERANGE);
1086e9034789SMichal Meloun
1087e9034789SMichal Meloun if (flags & CLK_SET_DRYRUN)
1088e9034789SMichal Meloun return (0);
1089e9034789SMichal Meloun rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p);
1090e9034789SMichal Meloun /* XXXX Panic for rv == ERANGE ? */
1091e9034789SMichal Meloun return (rv);
1092e9034789SMichal Meloun }
1093e9034789SMichal Meloun
1094e9034789SMichal Meloun static int
pllrefe_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)1095e9034789SMichal Meloun pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
1096e9034789SMichal Meloun {
1097e9034789SMichal Meloun uint32_t m, n, p;
1098e9034789SMichal Meloun
1099e9034789SMichal Meloun m = 1;
1100e9034789SMichal Meloun p = 1;
1101e9034789SMichal Meloun n = *fout * p * m / fin;
1102e9034789SMichal Meloun dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
1103e9034789SMichal Meloun return (pll_set_std(sc, fin, fout, flags, m, n, p));
1104e9034789SMichal Meloun }
1105e9034789SMichal Meloun
1106e9034789SMichal Meloun #define PLLX_PFD_MIN 12000000LL /* 12 MHz */
1107e9034789SMichal Meloun #define PLLX_PFD_MAX 38400000LL /* 38.4 MHz */
1108e9034789SMichal Meloun #define PLLX_VCO_MIN 900000000LL /* 0.9 GHz */
1109e9034789SMichal Meloun #define PLLX_VCO_MAX 3000000000LL /* 3 GHz */
1110e9034789SMichal Meloun
1111e9034789SMichal Meloun static int
pllx_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)1112e9034789SMichal Meloun pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
1113e9034789SMichal Meloun {
1114e9034789SMichal Meloun struct mnp_bits *mnp_bits;
1115e9034789SMichal Meloun uint32_t m, n, p;
1116e9034789SMichal Meloun uint32_t old_m, old_n, old_p;
1117e9034789SMichal Meloun uint32_t reg;
1118e9034789SMichal Meloun int i, rv;
1119e9034789SMichal Meloun
1120e9034789SMichal Meloun mnp_bits = &sc->mnp_bits;
1121e9034789SMichal Meloun
1122e9034789SMichal Meloun get_divisors(sc, &old_m, &old_n, &old_p);
1123e9034789SMichal Meloun old_p = reg_to_pdiv(sc, old_p);
1124e9034789SMichal Meloun
1125e9034789SMichal Meloun /* Pre-divider is fixed, Compute post-divider */
1126e9034789SMichal Meloun m = old_m;
1127e9034789SMichal Meloun p = 1;
1128e9034789SMichal Meloun while ((*fout * p) < PLLX_VCO_MIN)
1129e9034789SMichal Meloun p++;
1130e9034789SMichal Meloun if ((*fout * p) > PLLX_VCO_MAX)
1131e9034789SMichal Meloun return (ERANGE);
1132e9034789SMichal Meloun
1133e9034789SMichal Meloun n = (*fout * p * m + fin / 2) / fin;
1134e9034789SMichal Meloun dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
1135e9034789SMichal Meloun
1136e9034789SMichal Meloun if (m >= (1 << mnp_bits->m_width))
1137e9034789SMichal Meloun return (ERANGE);
1138e9034789SMichal Meloun if (n >= (1 << mnp_bits->n_width))
1139e9034789SMichal Meloun return (ERANGE);
1140e9034789SMichal Meloun if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
1141e9034789SMichal Meloun return (ERANGE);
1142e9034789SMichal Meloun
1143e9034789SMichal Meloun if (flags & CLK_SET_DRYRUN) {
1144e9034789SMichal Meloun if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
1145e9034789SMichal Meloun (*fout != (((fin / m) * n) /p)))
1146e9034789SMichal Meloun return (ERANGE);
1147e9034789SMichal Meloun *fout = ((fin / m) * n) /p;
1148e9034789SMichal Meloun return (0);
1149e9034789SMichal Meloun }
1150e9034789SMichal Meloun
1151e9034789SMichal Meloun /* If new post-divider is bigger that original, set it now. */
1152e9034789SMichal Meloun if (p < old_p) {
1153e9034789SMichal Meloun RD4(sc, sc->base_reg, ®);
1154e9034789SMichal Meloun reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
1155e9034789SMichal Meloun mnp_bits->p_width);
1156e9034789SMichal Meloun WR4(sc, sc->base_reg, reg);
1157e9034789SMichal Meloun }
1158e9034789SMichal Meloun DELAY(100);
1159e9034789SMichal Meloun
1160e9034789SMichal Meloun /* vvv Program dynamic VCO ramp. vvv */
1161e9034789SMichal Meloun /* 1 - disable dynamic ramp mode. */
1162e9034789SMichal Meloun RD4(sc, PLLX_MISC_2, ®);
1163e9034789SMichal Meloun reg &= ~PLLX_MISC_2_EN_DYNRAMP;
1164e9034789SMichal Meloun WR4(sc, PLLX_MISC_2, reg);
1165e9034789SMichal Meloun
1166e9034789SMichal Meloun /* 2 - Setup new ndiv. */
1167e9034789SMichal Meloun RD4(sc, PLLX_MISC_2, ®);
1168e9034789SMichal Meloun reg &= ~PLLX_MISC_2_NDIV_NEW(~0);
1169e9034789SMichal Meloun reg |= PLLX_MISC_2_NDIV_NEW(n);
1170e9034789SMichal Meloun WR4(sc, PLLX_MISC_2, reg);
1171e9034789SMichal Meloun
1172e9034789SMichal Meloun /* 3 - enable dynamic ramp. */
1173e9034789SMichal Meloun RD4(sc, PLLX_MISC_2, ®);
1174e9034789SMichal Meloun reg |= PLLX_MISC_2_EN_DYNRAMP;
1175e9034789SMichal Meloun WR4(sc, PLLX_MISC_2, reg);
1176e9034789SMichal Meloun
1177e9034789SMichal Meloun /* 4 - wait for done. */
1178e9034789SMichal Meloun for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) {
1179e9034789SMichal Meloun RD4(sc, PLLX_MISC_2, ®);
1180e9034789SMichal Meloun if (reg & PLLX_MISC_2_DYNRAMP_DONE)
1181e9034789SMichal Meloun break;
1182e9034789SMichal Meloun DELAY(10);
1183e9034789SMichal Meloun }
1184e9034789SMichal Meloun if (i <= 0) {
1185e9034789SMichal Meloun printf("PLL X dynamic ramp timedout\n");
1186e9034789SMichal Meloun return (ETIMEDOUT);
1187e9034789SMichal Meloun }
1188e9034789SMichal Meloun
1189e9034789SMichal Meloun /* 5 - copy new ndiv to base register. */
1190e9034789SMichal Meloun RD4(sc, sc->base_reg, ®);
1191e9034789SMichal Meloun reg = set_masked(reg, n, mnp_bits->n_shift,
1192e9034789SMichal Meloun mnp_bits->n_width);
1193e9034789SMichal Meloun WR4(sc, sc->base_reg, reg);
1194e9034789SMichal Meloun
1195e9034789SMichal Meloun /* 6 - disable dynamic ramp mode. */
1196e9034789SMichal Meloun RD4(sc, PLLX_MISC_2, ®);
1197e9034789SMichal Meloun reg &= ~PLLX_MISC_2_EN_DYNRAMP;
1198e9034789SMichal Meloun WR4(sc, PLLX_MISC_2, reg);
1199e9034789SMichal Meloun
1200e9034789SMichal Meloun rv = wait_for_lock(sc);
1201e9034789SMichal Meloun if (rv != 0) {
1202e9034789SMichal Meloun printf("PLL X is not locked !!\n");
1203e9034789SMichal Meloun }
1204e9034789SMichal Meloun /* ^^^ Dynamic ramp done. ^^^ */
1205e9034789SMichal Meloun
1206e9034789SMichal Meloun /* If new post-divider is smaller that original, set it. */
1207e9034789SMichal Meloun if (p > old_p) {
1208e9034789SMichal Meloun RD4(sc, sc->base_reg, ®);
1209e9034789SMichal Meloun reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
1210e9034789SMichal Meloun mnp_bits->p_width);
1211e9034789SMichal Meloun WR4(sc, sc->base_reg, reg);
1212e9034789SMichal Meloun }
1213e9034789SMichal Meloun
1214e9034789SMichal Meloun *fout = ((fin / m) * n) / p;
1215e9034789SMichal Meloun return (0);
1216e9034789SMichal Meloun }
1217e9034789SMichal Meloun
1218e9034789SMichal Meloun /* Simplified setup for 38.4 MHz clock. */
1219e9034789SMichal Meloun #define PLLX_STEP_A 0x04
1220e9034789SMichal Meloun #define PLLX_STEP_B 0x05
1221e9034789SMichal Meloun static int
pllx_init(struct pll_sc * sc)1222e9034789SMichal Meloun pllx_init(struct pll_sc *sc)
1223e9034789SMichal Meloun {
1224e9034789SMichal Meloun uint32_t reg;
1225e9034789SMichal Meloun
1226e9034789SMichal Meloun RD4(sc, PLLX_MISC, ®);
1227e9034789SMichal Meloun reg = PLLX_MISC_LOCK_ENABLE;
1228e9034789SMichal Meloun WR4(sc, PLLX_MISC, reg);
1229e9034789SMichal Meloun
1230e9034789SMichal Meloun /* Setup dynamic ramp. */
1231e9034789SMichal Meloun reg = 0;
1232e9034789SMichal Meloun reg |= PLLX_MISC_2_DYNRAMP_STEPA(PLLX_STEP_A);
1233e9034789SMichal Meloun reg |= PLLX_MISC_2_DYNRAMP_STEPB(PLLX_STEP_B);
1234e9034789SMichal Meloun WR4(sc, PLLX_MISC_2, reg);
1235e9034789SMichal Meloun
1236e9034789SMichal Meloun /* Disable SDM. */
1237e9034789SMichal Meloun reg = 0;
1238e9034789SMichal Meloun WR4(sc, PLLX_MISC_4, reg);
1239e9034789SMichal Meloun WR4(sc, PLLX_MISC_5, reg);
1240e9034789SMichal Meloun
1241e9034789SMichal Meloun return (0);
1242e9034789SMichal Meloun }
1243e9034789SMichal Meloun
1244e9034789SMichal Meloun static int
tegra210_pll_set_freq(struct clknode * clknode,uint64_t fin,uint64_t * fout,int flags,int * stop)1245e9034789SMichal Meloun tegra210_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout,
1246e9034789SMichal Meloun int flags, int *stop)
1247e9034789SMichal Meloun {
1248e9034789SMichal Meloun *stop = 1;
1249e9034789SMichal Meloun int rv;
1250e9034789SMichal Meloun struct pll_sc *sc;
1251e9034789SMichal Meloun
1252e9034789SMichal Meloun sc = clknode_get_softc(clknode);
1253e9034789SMichal Meloun dprintf("%s: %s requested freq: %lu, input freq: %lu\n", __func__,
1254e9034789SMichal Meloun clknode_get_name(clknode), *fout, fin);
1255e9034789SMichal Meloun switch (sc->type) {
1256e9034789SMichal Meloun case PLL_A:
1257e9034789SMichal Meloun rv = plla_set_freq(sc, fin, fout, flags);
1258e9034789SMichal Meloun break;
1259e9034789SMichal Meloun
1260e9034789SMichal Meloun case PLL_C:
1261e9034789SMichal Meloun case PLL_C2:
1262e9034789SMichal Meloun case PLL_C3:
1263e9034789SMichal Meloun rv = pllc_set_freq(sc, fin, fout, flags);
1264e9034789SMichal Meloun break;
1265e9034789SMichal Meloun
1266e9034789SMichal Meloun case PLL_C4:
1267e9034789SMichal Meloun rv = pllc4_set_freq(sc, fin, fout, flags);
1268e9034789SMichal Meloun break;
1269e9034789SMichal Meloun
1270e9034789SMichal Meloun case PLL_D2:
1271e9034789SMichal Meloun rv = plld2_set_freq(sc, fin, fout, flags);
1272e9034789SMichal Meloun break;
1273e9034789SMichal Meloun
1274e9034789SMichal Meloun case PLL_DP:
1275e9034789SMichal Meloun rv = plldp_set_freq(sc, fin, fout, flags);
1276e9034789SMichal Meloun break;
1277e9034789SMichal Meloun
1278e9034789SMichal Meloun case PLL_REFE:
1279e9034789SMichal Meloun rv = pllrefe_set_freq(sc, fin, fout, flags);
1280e9034789SMichal Meloun break;
1281e9034789SMichal Meloun
1282e9034789SMichal Meloun case PLL_X:
1283e9034789SMichal Meloun rv = pllx_set_freq(sc, fin, fout, flags);
1284e9034789SMichal Meloun break;
1285e9034789SMichal Meloun
1286e9034789SMichal Meloun case PLL_U:
1287e9034789SMichal Meloun if (*fout == 480000000) /* PLLU is fixed to 480 MHz */
1288e9034789SMichal Meloun rv = 0;
1289e9034789SMichal Meloun else
1290e9034789SMichal Meloun rv = ERANGE;
1291e9034789SMichal Meloun break;
1292e9034789SMichal Meloun default:
1293e9034789SMichal Meloun rv = ENXIO;
1294e9034789SMichal Meloun break;
1295e9034789SMichal Meloun }
1296e9034789SMichal Meloun
1297e9034789SMichal Meloun return (rv);
1298e9034789SMichal Meloun }
1299e9034789SMichal Meloun
1300e9034789SMichal Meloun
1301e9034789SMichal Meloun static int
tegra210_pll_init(struct clknode * clk,device_t dev)1302e9034789SMichal Meloun tegra210_pll_init(struct clknode *clk, device_t dev)
1303e9034789SMichal Meloun {
1304e9034789SMichal Meloun struct pll_sc *sc;
1305e9034789SMichal Meloun uint32_t reg, rv;
1306e9034789SMichal Meloun
1307e9034789SMichal Meloun sc = clknode_get_softc(clk);
1308e9034789SMichal Meloun
1309e9034789SMichal Meloun if (sc->type == PLL_X) {
1310e9034789SMichal Meloun rv = pllx_init(sc);
1311e9034789SMichal Meloun if (rv != 0)
1312e9034789SMichal Meloun return (rv);
1313e9034789SMichal Meloun }
1314e9034789SMichal Meloun
1315e9034789SMichal Meloun /* If PLL is enabled, enable lock detect too. */
1316e9034789SMichal Meloun RD4(sc, sc->base_reg, ®);
1317e9034789SMichal Meloun if (reg & PLL_BASE_ENABLE) {
1318e9034789SMichal Meloun RD4(sc, sc->misc_reg, ®);
1319e9034789SMichal Meloun reg |= sc->lock_enable;
1320e9034789SMichal Meloun WR4(sc, sc->misc_reg, reg);
1321e9034789SMichal Meloun }
1322e9034789SMichal Meloun if (sc->type == PLL_REFE) {
1323e9034789SMichal Meloun RD4(sc, sc->misc_reg, ®);
1324e9034789SMichal Meloun reg &= ~(1 << 29); /* Disable lock override */
1325e9034789SMichal Meloun WR4(sc, sc->misc_reg, reg);
1326e9034789SMichal Meloun }
1327e9034789SMichal Meloun clknode_init_parent_idx(clk, 0);
1328e9034789SMichal Meloun return(0);
1329e9034789SMichal Meloun }
1330e9034789SMichal Meloun
1331e9034789SMichal Meloun static int
tegra210_pll_recalc(struct clknode * clk,uint64_t * freq)1332e9034789SMichal Meloun tegra210_pll_recalc(struct clknode *clk, uint64_t *freq)
1333e9034789SMichal Meloun {
1334e9034789SMichal Meloun struct pll_sc *sc;
1335e9034789SMichal Meloun uint32_t m, n, p, pr;
1336e9034789SMichal Meloun uint32_t reg, misc_reg;
1337e9034789SMichal Meloun int locked;
1338e9034789SMichal Meloun
1339e9034789SMichal Meloun sc = clknode_get_softc(clk);
1340e9034789SMichal Meloun
1341e9034789SMichal Meloun RD4(sc, sc->base_reg, ®);
1342e9034789SMichal Meloun RD4(sc, sc->misc_reg, &misc_reg);
1343e9034789SMichal Meloun
1344e9034789SMichal Meloun get_divisors(sc, &m, &n, &pr);
1345e9034789SMichal Meloun
1346e9034789SMichal Meloun /* If VCO is directlu exposed, P divider is handled by external node */
1347e9034789SMichal Meloun if (sc->flags & PLL_FLAG_VCO_OUT)
1348e9034789SMichal Meloun p = 1;
1349e9034789SMichal Meloun else
1350e9034789SMichal Meloun p = reg_to_pdiv(sc, pr);
1351e9034789SMichal Meloun
1352e9034789SMichal Meloun locked = is_locked(sc);
1353e9034789SMichal Meloun
1354e9034789SMichal Meloun dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): "
1355e9034789SMichal Meloun "e: %d, r: %d, o: %d - %s\n", __func__,
1356e9034789SMichal Meloun clknode_get_name(clk), reg, misc_reg, m, n, p, pr,
1357e9034789SMichal Meloun (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1,
1358e9034789SMichal Meloun locked ? "locked" : "unlocked");
1359e9034789SMichal Meloun
1360e9034789SMichal Meloun if ((m == 0) || (n == 0) || (p == 0)) {
1361e9034789SMichal Meloun *freq = 0;
1362e9034789SMichal Meloun return (EINVAL);
1363e9034789SMichal Meloun }
1364e9034789SMichal Meloun if (!locked) {
1365e9034789SMichal Meloun *freq = 0;
1366e9034789SMichal Meloun return (0);
1367e9034789SMichal Meloun }
1368e9034789SMichal Meloun *freq = ((*freq / m) * n) / p;
1369e9034789SMichal Meloun return (0);
1370e9034789SMichal Meloun }
1371e9034789SMichal Meloun
1372e9034789SMichal Meloun static int
pll_register(struct clkdom * clkdom,struct clk_pll_def * clkdef)1373e9034789SMichal Meloun pll_register(struct clkdom *clkdom, struct clk_pll_def *clkdef)
1374e9034789SMichal Meloun {
1375e9034789SMichal Meloun struct clknode *clk;
1376e9034789SMichal Meloun struct pll_sc *sc;
1377e9034789SMichal Meloun
1378e9034789SMichal Meloun clk = clknode_create(clkdom, &tegra210_pll_class, &clkdef->clkdef);
1379e9034789SMichal Meloun if (clk == NULL)
1380e9034789SMichal Meloun return (ENXIO);
1381e9034789SMichal Meloun
1382e9034789SMichal Meloun sc = clknode_get_softc(clk);
1383e9034789SMichal Meloun sc->clkdev = clknode_get_device(clk);
1384e9034789SMichal Meloun sc->type = clkdef->type;
1385e9034789SMichal Meloun sc->base_reg = clkdef->base_reg;
1386e9034789SMichal Meloun sc->misc_reg = clkdef->misc_reg;
1387e9034789SMichal Meloun sc->lock_enable = clkdef->lock_enable;
1388e9034789SMichal Meloun sc->iddq_reg = clkdef->iddq_reg;
1389e9034789SMichal Meloun sc->iddq_mask = clkdef->iddq_mask;
1390e9034789SMichal Meloun sc->flags = clkdef->flags;
1391e9034789SMichal Meloun sc->pdiv_table = clkdef->pdiv_table;
1392e9034789SMichal Meloun sc->mnp_bits = clkdef->mnp_bits;
1393e9034789SMichal Meloun clknode_register(clkdom, clk);
1394e9034789SMichal Meloun return (0);
1395e9034789SMichal Meloun }
1396e9034789SMichal Meloun
config_utmi_pll(struct tegra210_car_softc * sc)1397e9034789SMichal Meloun static void config_utmi_pll(struct tegra210_car_softc *sc)
1398e9034789SMichal Meloun {
1399e9034789SMichal Meloun uint32_t reg;
1400e9034789SMichal Meloun /*
1401e9034789SMichal Meloun * XXX Simplified UTMIP settings for 38.4MHz base clock.
1402e9034789SMichal Meloun */
1403e9034789SMichal Meloun #define ENABLE_DELAY_COUNT 0x00
1404e9034789SMichal Meloun #define STABLE_COUNT 0x00
1405e9034789SMichal Meloun #define ACTIVE_DELAY_COUNT 0x06
1406e9034789SMichal Meloun #define XTAL_FREQ_COUNT 0x80
1407e9034789SMichal Meloun
1408e9034789SMichal Meloun CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1409e9034789SMichal Meloun reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1410e9034789SMichal Meloun CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1411e9034789SMichal Meloun
1412e9034789SMichal Meloun CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®);
1413e9034789SMichal Meloun reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1414e9034789SMichal Meloun reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT);
1415e9034789SMichal Meloun reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1416e9034789SMichal Meloun reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT);
1417e9034789SMichal Meloun CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg);
1418e9034789SMichal Meloun
1419e9034789SMichal Meloun CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®);
1420e9034789SMichal Meloun reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1421e9034789SMichal Meloun reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT);
1422e9034789SMichal Meloun reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1423e9034789SMichal Meloun reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT);
1424e9034789SMichal Meloun reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1425e9034789SMichal Meloun CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
1426e9034789SMichal Meloun
1427e9034789SMichal Meloun reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1428e9034789SMichal Meloun reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1429e9034789SMichal Meloun CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
1430e9034789SMichal Meloun DELAY(20);
1431e9034789SMichal Meloun
1432e9034789SMichal Meloun /* Setup samplers. */
1433e9034789SMichal Meloun CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®);
1434e9034789SMichal Meloun reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
1435e9034789SMichal Meloun reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
1436e9034789SMichal Meloun reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
1437e9034789SMichal Meloun reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1438e9034789SMichal Meloun reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1439e9034789SMichal Meloun reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
1440e9034789SMichal Meloun CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg);
1441e9034789SMichal Meloun
1442e9034789SMichal Meloun /* Powerup UTMIP. */
1443e9034789SMichal Meloun CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®);
1444e9034789SMichal Meloun reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1445e9034789SMichal Meloun reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1446e9034789SMichal Meloun CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
1447e9034789SMichal Meloun DELAY(10);
1448e9034789SMichal Meloun
1449e9034789SMichal Meloun /* Prepare UTMIP sequencer. */
1450e9034789SMichal Meloun CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1451e9034789SMichal Meloun reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1452e9034789SMichal Meloun reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1453e9034789SMichal Meloun CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1454e9034789SMichal Meloun DELAY(10);
1455e9034789SMichal Meloun
1456e9034789SMichal Meloun CLKDEV_READ_4(sc->dev, XUSB_PLL_CFG0, ®);
1457e9034789SMichal Meloun reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
1458e9034789SMichal Meloun CLKDEV_WRITE_4(sc->dev, XUSB_PLL_CFG0, reg);
1459e9034789SMichal Meloun DELAY(10);
1460e9034789SMichal Meloun
1461e9034789SMichal Meloun /* HW control of UTMIPLL. */
1462e9034789SMichal Meloun CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1463e9034789SMichal Meloun reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1464e9034789SMichal Meloun CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1465e9034789SMichal Meloun }
1466e9034789SMichal Meloun
1467e9034789SMichal Meloun void
tegra210_init_plls(struct tegra210_car_softc * sc)1468e9034789SMichal Meloun tegra210_init_plls(struct tegra210_car_softc *sc)
1469e9034789SMichal Meloun {
1470e9034789SMichal Meloun int i, rv;
1471e9034789SMichal Meloun
1472e9034789SMichal Meloun for (i = 0; i < nitems(tegra210_pll_sources); i++) {
1473e9034789SMichal Meloun rv = clknode_mux_register(sc->clkdom, tegra210_pll_sources + i);
1474e9034789SMichal Meloun if (rv != 0)
1475e9034789SMichal Meloun panic("clk_mux_register failed");
1476e9034789SMichal Meloun }
1477e9034789SMichal Meloun
1478e9034789SMichal Meloun for (i = 0; i < nitems(pll_clks); i++) {
1479e9034789SMichal Meloun rv = pll_register(sc->clkdom, pll_clks + i);
1480e9034789SMichal Meloun if (rv != 0)
1481e9034789SMichal Meloun panic("pll_register failed");
1482e9034789SMichal Meloun }
1483e9034789SMichal Meloun
1484e9034789SMichal Meloun config_utmi_pll(sc);
1485e9034789SMichal Meloun
1486e9034789SMichal Meloun for (i = 0; i < nitems(tegra210_pll_fdivs); i++) {
1487e9034789SMichal Meloun rv = clknode_fixed_register(sc->clkdom, tegra210_pll_fdivs + i);
1488e9034789SMichal Meloun if (rv != 0)
1489e9034789SMichal Meloun panic("clk_fixed_register failed");
1490e9034789SMichal Meloun }
1491e9034789SMichal Meloun
1492e9034789SMichal Meloun for (i = 0; i < nitems(tegra210_pll_gates); i++) {
1493e9034789SMichal Meloun rv = clknode_gate_register(sc->clkdom, tegra210_pll_gates + i);
1494e9034789SMichal Meloun if (rv != 0)
1495e9034789SMichal Meloun panic("clk_gate_register failed");
1496e9034789SMichal Meloun }
1497e9034789SMichal Meloun
1498e9034789SMichal Meloun for (i = 0; i < nitems(tegra210_pll_divs); i++) {
1499e9034789SMichal Meloun rv = clknode_div_register(sc->clkdom, tegra210_pll_divs + i);
1500e9034789SMichal Meloun if (rv != 0)
1501e9034789SMichal Meloun panic("clk_div_register failed");
1502e9034789SMichal Meloun }
1503e9034789SMichal Meloun }
1504