15723e5acSSøren Schmidt /*- 25723e5acSSøren Schmidt * Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk> 35723e5acSSøren Schmidt * 45723e5acSSøren Schmidt * Redistribution and use in source and binary forms, with or without 55723e5acSSøren Schmidt * modification, are permitted provided that the following conditions 65723e5acSSøren Schmidt * are met: 75723e5acSSøren Schmidt * 1. Redistributions of source code must retain the above copyright 85723e5acSSøren Schmidt * notice, this list of conditions and the following disclaimer. 95723e5acSSøren Schmidt * 2. Redistributions in binary form must reproduce the above copyright 105723e5acSSøren Schmidt * notice, this list of conditions and the following disclaimer in the 115723e5acSSøren Schmidt * documentation and/or other materials provided with the distribution. 125723e5acSSøren Schmidt * 135723e5acSSøren Schmidt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 145723e5acSSøren Schmidt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 155723e5acSSøren Schmidt * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 165723e5acSSøren Schmidt * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 175723e5acSSøren Schmidt * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 185723e5acSSøren Schmidt * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 195723e5acSSøren Schmidt * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 205723e5acSSøren Schmidt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 215723e5acSSøren Schmidt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 225723e5acSSøren Schmidt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 235723e5acSSøren Schmidt * SUCH DAMAGE. 245723e5acSSøren Schmidt * 255723e5acSSøren Schmidt * $Id: rk3568_combphy.c 893 2022-07-26 09:47:22Z sos $ 265723e5acSSøren Schmidt */ 275723e5acSSøren Schmidt 285723e5acSSøren Schmidt #include <sys/cdefs.h> 295723e5acSSøren Schmidt #include <sys/param.h> 305723e5acSSøren Schmidt #include <sys/bus.h> 315723e5acSSøren Schmidt #include <sys/kernel.h> 325723e5acSSøren Schmidt #include <sys/module.h> 335723e5acSSøren Schmidt #include <sys/mutex.h> 345723e5acSSøren Schmidt #include <sys/rman.h> 355723e5acSSøren Schmidt #include <machine/bus.h> 365723e5acSSøren Schmidt 375723e5acSSøren Schmidt #include <dev/ofw/openfirm.h> 385723e5acSSøren Schmidt #include <dev/ofw/ofw_bus.h> 395723e5acSSøren Schmidt #include <dev/ofw/ofw_bus_subr.h> 405723e5acSSøren Schmidt 415723e5acSSøren Schmidt #include <dev/fdt/simple_mfd.h> 425723e5acSSøren Schmidt 435723e5acSSøren Schmidt #include <dev/extres/clk/clk.h> 445723e5acSSøren Schmidt #include <dev/extres/hwreset/hwreset.h> 455723e5acSSøren Schmidt #include <dev/extres/regulator/regulator.h> 465723e5acSSøren Schmidt #include <dev/extres/syscon/syscon.h> 475723e5acSSøren Schmidt #include <dev/extres/phy/phy.h> 485723e5acSSøren Schmidt 495723e5acSSøren Schmidt #include <contrib/device-tree/include/dt-bindings/phy/phy.h> 505723e5acSSøren Schmidt 515723e5acSSøren Schmidt #include "syscon_if.h" 525723e5acSSøren Schmidt #include "phydev_if.h" 535723e5acSSøren Schmidt #include "phynode_if.h" 545723e5acSSøren Schmidt 555723e5acSSøren Schmidt 565723e5acSSøren Schmidt static struct ofw_compat_data compat_data[] = { 575723e5acSSøren Schmidt {"rockchip,rk3568-naneng-combphy", 1}, 585723e5acSSøren Schmidt {NULL, 0} 595723e5acSSøren Schmidt }; 605723e5acSSøren Schmidt 615723e5acSSøren Schmidt struct rk3568_combphy_softc { 625723e5acSSøren Schmidt device_t dev; 635723e5acSSøren Schmidt phandle_t node; 645723e5acSSøren Schmidt struct resource *mem; 655723e5acSSøren Schmidt struct phynode *phynode; 665723e5acSSøren Schmidt struct syscon *pipe_grf; 675723e5acSSøren Schmidt struct syscon *pipe_phy_grf; 685723e5acSSøren Schmidt clk_t ref_clk; 695723e5acSSøren Schmidt clk_t apb_clk; 705723e5acSSøren Schmidt clk_t pipe_clk; 715723e5acSSøren Schmidt hwreset_t phy_reset; 725723e5acSSøren Schmidt int mode; 735723e5acSSøren Schmidt }; 745723e5acSSøren Schmidt 755723e5acSSøren Schmidt #define PHYREG6 0x14 765723e5acSSøren Schmidt #define PHYREG6_PLL_DIV_MASK 0xc0 775723e5acSSøren Schmidt #define PHYREG6_PLL_DIV_2 (1 << 6) 785723e5acSSøren Schmidt #define PHYREG7 0x18 795723e5acSSøren Schmidt #define PHYREG7_TX_RTERM_50OHM (8 << 4) 805723e5acSSøren Schmidt #define PHYREG7_RX_RTERM_44OHM (15 << 0) 815723e5acSSøren Schmidt #define PHYREG8 0x1c 825723e5acSSøren Schmidt #define PHYREG8_SSC_EN 0x10 835723e5acSSøren Schmidt #define PHYREG11 0x28 845723e5acSSøren Schmidt #define PHYREG11_SU_TRIM_0_7 0xf0 855723e5acSSøren Schmidt #define PHYREG12 0x2c 865723e5acSSøren Schmidt #define PHYREG12_PLL_LPF_ADJ_VALUE 4 875723e5acSSøren Schmidt #define PHYREG15 0x38 885723e5acSSøren Schmidt #define PHYREG15_CTLE_EN 0x01 895723e5acSSøren Schmidt #define PHYREG15_SSC_CNT_MASK 0xc0 905723e5acSSøren Schmidt #define PHYREG15_SSC_CNT_VALUE (1 << 6) 915723e5acSSøren Schmidt #define PHYREG16 0x3c 925723e5acSSøren Schmidt #define PHYREG16_SSC_CNT_VALUE 0x5f 935723e5acSSøren Schmidt #define PHYREG18 0x44 945723e5acSSøren Schmidt #define PHYREG18_PLL_LOOP 0x32 955723e5acSSøren Schmidt #define PHYREG32 0x7c 965723e5acSSøren Schmidt #define PHYREG32_SSC_MASK 0xf0 975723e5acSSøren Schmidt #define PHYREG32_SSC_UPWARD (0 << 4) 985723e5acSSøren Schmidt #define PHYREG32_SSC_DOWNWARD (1 << 4) 995723e5acSSøren Schmidt #define PHYREG32_SSC_OFFSET_500PPM (1 << 6) 1005723e5acSSøren Schmidt #define PHYREG33 0x80 1015723e5acSSøren Schmidt #define PHYREG33_PLL_KVCO_MASK 0x1c 1025723e5acSSøren Schmidt #define PHYREG33_PLL_KVCO_VALUE (2 << 2) 1035723e5acSSøren Schmidt 1045723e5acSSøren Schmidt #define PIPE_MASK_ALL (0xffff << 16) 1055723e5acSSøren Schmidt #define PIPE_PHY_GRF_PIPE_CON0 0x00 1065723e5acSSøren Schmidt #define PIPE_DATABUSWIDTH_MASK 0x3 1075723e5acSSøren Schmidt #define PIPE_DATABUSWIDTH_32BIT 0 1085723e5acSSøren Schmidt #define PIPE_DATABUSWIDTH_16BIT 1 1095723e5acSSøren Schmidt #define PIPE_PHYMODE_MASK (3 << 2) 1105723e5acSSøren Schmidt #define PIPE_PHYMODE_PCIE (0 << 2) 1115723e5acSSøren Schmidt #define PIPE_PHYMODE_USB3 (1 << 2) 1125723e5acSSøren Schmidt #define PIPE_PHYMODE_SATA (2 << 2) 1135723e5acSSøren Schmidt #define PIPE_RATE_MASK (3 << 4) 1145723e5acSSøren Schmidt #define PIPE_RATE_PCIE_2_5GBPS (0 << 4) 1155723e5acSSøren Schmidt #define PIPE_RATE_PCIE_5GBPS (1 << 4) 1165723e5acSSøren Schmidt #define PIPE_RATE_USB3_5GBPS (0 << 4) 1175723e5acSSøren Schmidt #define PIPE_RATE_SATA_1GBPS5 (0 << 4) 1185723e5acSSøren Schmidt #define PIPE_RATE_SATA_3GBPS (1 << 4) 1195723e5acSSøren Schmidt #define PIPE_RATE_SATA_6GBPS (2 << 4) 1205723e5acSSøren Schmidt #define PIPE_MAC_PCLKREQ_N (1 << 8) 1215723e5acSSøren Schmidt #define PIPE_L1SUB_ENTREQ (1 << 9) 1225723e5acSSøren Schmidt #define PIPE_RXTERM (1 << 12) 1235723e5acSSøren Schmidt #define PIPE_PHY_GRF_PIPE_CON1 0x04 1245723e5acSSøren Schmidt #define PHY_CLK_SEL_MASK (3 << 13) 1255723e5acSSøren Schmidt #define PHY_CLK_SEL_24M (0 << 13) 1265723e5acSSøren Schmidt #define PHY_CLK_SEL_25M (1 << 13) 1275723e5acSSøren Schmidt #define PHY_CLK_SEL_100M (2 << 13) 1285723e5acSSøren Schmidt #define PIPE_PHY_GRF_PIPE_CON2 0x08 1295723e5acSSøren Schmidt #define SEL_PIPE_TXCOMPLIANCE_I (1 << 15) 1305723e5acSSøren Schmidt #define SEL_PIPE_TXELECIDLE (1 << 12) 1315723e5acSSøren Schmidt #define SEL_PIPE_RXTERM (1 << 8) 1325723e5acSSøren Schmidt #define SEL_PIPE_BYPASS_CODEC (1 << 7) 1335723e5acSSøren Schmidt #define SEL_PIPE_PIPE_EBUF (1 << 6) 1345723e5acSSøren Schmidt #define SEL_PIPE_PIPE_PHYMODE (1 << 1) 1355723e5acSSøren Schmidt #define SEL_PIPE_DATABUSWIDTH (1 << 0) 1365723e5acSSøren Schmidt #define PIPE_PHY_GRF_PIPE_CON3 0x0c 1375723e5acSSøren Schmidt #define PIPE_SEL_MASK (3 << 13) 1385723e5acSSøren Schmidt #define PIPE_SEL_PCIE (0 << 13) 1395723e5acSSøren Schmidt #define PIPE_SEL_USB3 (1 << 13) 1405723e5acSSøren Schmidt #define PIPE_SEL_SATA (2 << 13) 1415723e5acSSøren Schmidt #define PIPE_CLK_REF_SRC_I_MASK (3 << 8) 1425723e5acSSøren Schmidt #define PIPE_CLK_REF_SRC_I_PLL_CKREF_INNER (2 << 8) 1435723e5acSSøren Schmidt #define PIPE_RXELECIDLE (1 << 10) 1445723e5acSSøren Schmidt #define PIPE_FROM_PCIE_IO (1 << 11) 1455723e5acSSøren Schmidt 1465723e5acSSøren Schmidt #define PIPE_GRF_PIPE_CON0 0x00 1475723e5acSSøren Schmidt #define SATA2_PHY_SPDMODE_1GBPS5 (0 << 12) 1485723e5acSSøren Schmidt #define SATA2_PHY_SPDMODE_3GBPS (1 << 12) 1495723e5acSSøren Schmidt #define SATA2_PHY_SPDMODE_6GBPS (2 << 12) 1505723e5acSSøren Schmidt #define SATA1_PHY_SPDMODE_1GBPS5 (0 << 8) 1515723e5acSSøren Schmidt #define SATA1_PHY_SPDMODE_3GBPS (1 << 8) 1525723e5acSSøren Schmidt #define SATA1_PHY_SPDMODE_6GBPS (2 << 8) 1535723e5acSSøren Schmidt #define SATA0_PHY_SPDMODE_1GBPS5 (0 << 4) 1545723e5acSSøren Schmidt #define SATA0_PHY_SPDMODE_3GBPS (1 << 4) 1555723e5acSSøren Schmidt #define SATA0_PHY_SPDMODE_6GBPS (2 << 4) 1565723e5acSSøren Schmidt 1575723e5acSSøren Schmidt #define PIPE_GRF_SATA_CON0 0x10 1585723e5acSSøren Schmidt #define PIPE_GRF_SATA_CON1 0x14 1595723e5acSSøren Schmidt #define PIPE_GRF_SATA_CON2 0x18 1605723e5acSSøren Schmidt #define PIPE_GRF_XPCS_CON0 0x40 1615723e5acSSøren Schmidt 1625723e5acSSøren Schmidt 1635723e5acSSøren Schmidt /* PHY class and methods */ 1645723e5acSSøren Schmidt static int 1655723e5acSSøren Schmidt rk3568_combphy_enable(struct phynode *phynode, bool enable) 1665723e5acSSøren Schmidt { 1675723e5acSSøren Schmidt device_t dev = phynode_get_device(phynode); 1685723e5acSSøren Schmidt struct rk3568_combphy_softc *sc = device_get_softc(dev); 1695723e5acSSøren Schmidt uint64_t rate; 1705723e5acSSøren Schmidt 1715723e5acSSøren Schmidt if (enable == false) 1725723e5acSSøren Schmidt return (0); 1735723e5acSSøren Schmidt 1745723e5acSSøren Schmidt switch (sc->mode) { 1755723e5acSSøren Schmidt case PHY_TYPE_SATA: 1765723e5acSSøren Schmidt device_printf(dev, "configuring for SATA"); 1775723e5acSSøren Schmidt 1785723e5acSSøren Schmidt /* tx_rterm 50 ohm & rx_rterm 44 ohm */ 1795723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG7, 1805723e5acSSøren Schmidt PHYREG7_TX_RTERM_50OHM | PHYREG7_RX_RTERM_44OHM); 1815723e5acSSøren Schmidt 1825723e5acSSøren Schmidt /* Adaptive CTLE */ 1835723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG15, 1845723e5acSSøren Schmidt bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN); 1855723e5acSSøren Schmidt 1865723e5acSSøren Schmidt /* config grf_pipe for PCIe */ 1875723e5acSSøren Schmidt SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3, 1885723e5acSSøren Schmidt PIPE_MASK_ALL | PIPE_SEL_SATA | PIPE_RXELECIDLE | 0x7); 1895723e5acSSøren Schmidt 1905723e5acSSøren Schmidt SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON2, 1915723e5acSSøren Schmidt PIPE_MASK_ALL | SEL_PIPE_TXCOMPLIANCE_I | 1925723e5acSSøren Schmidt SEL_PIPE_DATABUSWIDTH | 0xc3); 1935723e5acSSøren Schmidt 1945723e5acSSøren Schmidt SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON0, 1955723e5acSSøren Schmidt PIPE_MASK_ALL | PIPE_RXTERM | PIPE_DATABUSWIDTH_16BIT | 1965723e5acSSøren Schmidt PIPE_RATE_SATA_3GBPS | PIPE_PHYMODE_SATA); 1975723e5acSSøren Schmidt 1985723e5acSSøren Schmidt SYSCON_WRITE_4(sc->pipe_grf, PIPE_GRF_PIPE_CON0, 1995723e5acSSøren Schmidt PIPE_MASK_ALL | SATA0_PHY_SPDMODE_6GBPS | 2005723e5acSSøren Schmidt SATA1_PHY_SPDMODE_6GBPS | SATA2_PHY_SPDMODE_6GBPS); 2015723e5acSSøren Schmidt break; 2025723e5acSSøren Schmidt 2035723e5acSSøren Schmidt case PHY_TYPE_PCIE: 2045723e5acSSøren Schmidt device_printf(dev, "configuring for PCIe"); 2055723e5acSSøren Schmidt 2065723e5acSSøren Schmidt /* Set SSC downward spread spectrum */ 2075723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG32, 2085723e5acSSøren Schmidt (bus_read_4(sc->mem, PHYREG32) & PHYREG32_SSC_MASK) | 2095723e5acSSøren Schmidt PHYREG32_SSC_DOWNWARD); 2105723e5acSSøren Schmidt 2115723e5acSSøren Schmidt /* config grf_pipe for PCIe */ 2125723e5acSSøren Schmidt SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3, 2135723e5acSSøren Schmidt PIPE_MASK_ALL | PIPE_SEL_PCIE | 2145723e5acSSøren Schmidt PIPE_CLK_REF_SRC_I_PLL_CKREF_INNER); 2155723e5acSSøren Schmidt SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON2, 2165723e5acSSøren Schmidt PIPE_MASK_ALL | SEL_PIPE_RXTERM | SEL_PIPE_DATABUSWIDTH); 2175723e5acSSøren Schmidt SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON0, 2185723e5acSSøren Schmidt PIPE_MASK_ALL | PIPE_RXTERM | PIPE_DATABUSWIDTH_32BIT | 2195723e5acSSøren Schmidt PIPE_RATE_PCIE_2_5GBPS | PIPE_PHYMODE_PCIE); 2205723e5acSSøren Schmidt break; 2215723e5acSSøren Schmidt 2225723e5acSSøren Schmidt case PHY_TYPE_USB3: 2235723e5acSSøren Schmidt device_printf(dev, "configuring for USB3"); 2245723e5acSSøren Schmidt 2255723e5acSSøren Schmidt /* Set SSC downward spread spectrum */ 2265723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG32, 2275723e5acSSøren Schmidt (bus_read_4(sc->mem, PHYREG32) & PHYREG32_SSC_MASK) | 2285723e5acSSøren Schmidt PHYREG32_SSC_DOWNWARD); 2295723e5acSSøren Schmidt 2305723e5acSSøren Schmidt /* Adaptive CTLE */ 2315723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG15, 2325723e5acSSøren Schmidt bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN); 2335723e5acSSøren Schmidt 2345723e5acSSøren Schmidt /* Set PLL KVCO fine tuning signals */ 2355723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG33, 2365723e5acSSøren Schmidt (bus_read_4(sc->mem, PHYREG33) & PHYREG33_PLL_KVCO_MASK) | 2375723e5acSSøren Schmidt PHYREG33_PLL_KVCO_VALUE); 2385723e5acSSøren Schmidt 2395723e5acSSøren Schmidt /* Enable controlling random jitter. */ 2405723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG12, PHYREG12_PLL_LPF_ADJ_VALUE); 2415723e5acSSøren Schmidt 2425723e5acSSøren Schmidt /* Set PLL input clock divider 1/2 */ 2435723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG6, 2445723e5acSSøren Schmidt (bus_read_4(sc->mem, PHYREG6) & PHYREG6_PLL_DIV_MASK) | 2455723e5acSSøren Schmidt PHYREG6_PLL_DIV_2); 2465723e5acSSøren Schmidt 2475723e5acSSøren Schmidt /* Set PLL loop divider */ 2485723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG18, PHYREG18_PLL_LOOP); 2495723e5acSSøren Schmidt 2505723e5acSSøren Schmidt /* Set PLL LPF R1 to su_trim[0:7] */ 2515723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG11, PHYREG11_SU_TRIM_0_7); 2525723e5acSSøren Schmidt 2535723e5acSSøren Schmidt /* config grf_pipe for USB3 */ 2545723e5acSSøren Schmidt SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3, 2555723e5acSSøren Schmidt PIPE_MASK_ALL | PIPE_SEL_USB3); 2565723e5acSSøren Schmidt SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON2, 2575723e5acSSøren Schmidt PIPE_MASK_ALL); 2585723e5acSSøren Schmidt SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON0, 2595723e5acSSøren Schmidt PIPE_MASK_ALL | PIPE_DATABUSWIDTH_16BIT | 2605723e5acSSøren Schmidt PIPE_PHYMODE_USB3 | PIPE_RATE_USB3_5GBPS); 2615723e5acSSøren Schmidt break; 2625723e5acSSøren Schmidt 2635723e5acSSøren Schmidt default: 2645723e5acSSøren Schmidt printf("Unsupported mode=%d\n", sc->mode); 2655723e5acSSøren Schmidt return (-1); 2665723e5acSSøren Schmidt } 2675723e5acSSøren Schmidt 2685723e5acSSøren Schmidt clk_get_freq(sc->ref_clk, &rate); 2695723e5acSSøren Schmidt printf(" ref_clk=%lu\n", rate); 2705723e5acSSøren Schmidt 2715723e5acSSøren Schmidt switch (rate) { 2725723e5acSSøren Schmidt case 24000000: 2735723e5acSSøren Schmidt SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON1, 2745723e5acSSøren Schmidt (PHY_CLK_SEL_MASK << 16) | PHY_CLK_SEL_24M); 2755723e5acSSøren Schmidt 2765723e5acSSøren Schmidt if (sc->mode == PHY_TYPE_USB3 || sc->mode == PHY_TYPE_SATA) { 2775723e5acSSøren Schmidt /* Adaptive CTLE */ 2785723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG15, 2795723e5acSSøren Schmidt (bus_read_4(sc->mem, PHYREG15) & 2805723e5acSSøren Schmidt PHYREG15_SSC_CNT_MASK) | PHYREG15_SSC_CNT_VALUE); 2815723e5acSSøren Schmidt 2825723e5acSSøren Schmidt /* SSC control period */ 2835723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG16, PHYREG16_SSC_CNT_VALUE); 2845723e5acSSøren Schmidt } 2855723e5acSSøren Schmidt break; 2865723e5acSSøren Schmidt 2875723e5acSSøren Schmidt case 25000000: 2885723e5acSSøren Schmidt SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON1, 2895723e5acSSøren Schmidt (PHY_CLK_SEL_MASK << 16) | PHY_CLK_SEL_25M); 2905723e5acSSøren Schmidt break; 2915723e5acSSøren Schmidt 2925723e5acSSøren Schmidt case 100000000: 2935723e5acSSøren Schmidt SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON1, 2945723e5acSSøren Schmidt (PHY_CLK_SEL_MASK << 16) | PHY_CLK_SEL_100M); 2955723e5acSSøren Schmidt 2965723e5acSSøren Schmidt if (sc->mode == PHY_TYPE_PCIE) { 2975723e5acSSøren Schmidt /* Set PLL KVCO fine tuning signals */ 2985723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG33, 2995723e5acSSøren Schmidt (bus_read_4(sc->mem, PHYREG33) & 3005723e5acSSøren Schmidt PHYREG33_PLL_KVCO_MASK) | PHYREG33_PLL_KVCO_VALUE); 3015723e5acSSøren Schmidt 3025723e5acSSøren Schmidt /* Enable controlling random jitter. */ 3035723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG12, 3045723e5acSSøren Schmidt PHYREG12_PLL_LPF_ADJ_VALUE); 3055723e5acSSøren Schmidt 3065723e5acSSøren Schmidt /* Set PLL input clock divider 1/2 */ 3075723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG6, 3085723e5acSSøren Schmidt (bus_read_4(sc->mem, PHYREG6) & 3095723e5acSSøren Schmidt PHYREG6_PLL_DIV_MASK) | PHYREG6_PLL_DIV_2); 3105723e5acSSøren Schmidt 3115723e5acSSøren Schmidt /* Set PLL loop divider */ 3125723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG18, PHYREG18_PLL_LOOP); 3135723e5acSSøren Schmidt 3145723e5acSSøren Schmidt /* Set PLL LPF R1 to su_trim[0:7] */ 3155723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG11, PHYREG11_SU_TRIM_0_7); 3165723e5acSSøren Schmidt } 3175723e5acSSøren Schmidt if (sc->mode == PHY_TYPE_SATA) { 3185723e5acSSøren Schmidt /* Set SSC downward spread spectrum */ 3195723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG32, 3205723e5acSSøren Schmidt (bus_read_4(sc->mem, PHYREG32) & ~0x000000f0) | 3215723e5acSSøren Schmidt PHYREG32_SSC_DOWNWARD | PHYREG32_SSC_OFFSET_500PPM); 3225723e5acSSøren Schmidt } 3235723e5acSSøren Schmidt break; 3245723e5acSSøren Schmidt 3255723e5acSSøren Schmidt default: 3265723e5acSSøren Schmidt device_printf(dev, "unknown ref rate=%lu\n", rate); 3275723e5acSSøren Schmidt break; 3285723e5acSSøren Schmidt } 3295723e5acSSøren Schmidt 3305723e5acSSøren Schmidt if (OF_hasprop(sc->node, "rockchip,ext-refclk")) { 3315723e5acSSøren Schmidt device_printf(dev, "UNSUPPORTED rockchip,ext-refclk\n"); 3325723e5acSSøren Schmidt } 3335723e5acSSøren Schmidt if (OF_hasprop(sc->node, "rockchip,enable-ssc")) { 3345723e5acSSøren Schmidt device_printf(dev, "setting rockchip,enable-ssc\n"); 3355723e5acSSøren Schmidt bus_write_4(sc->mem, PHYREG8, 3365723e5acSSøren Schmidt bus_read_4(sc->mem, PHYREG8) | PHYREG8_SSC_EN); 3375723e5acSSøren Schmidt } 3385723e5acSSøren Schmidt 3395723e5acSSøren Schmidt if (hwreset_deassert(sc->phy_reset)) 3405723e5acSSøren Schmidt device_printf(dev, "phy_reset failed to clear\n"); 3415723e5acSSøren Schmidt 3425723e5acSSøren Schmidt return (0); 3435723e5acSSøren Schmidt } 3445723e5acSSøren Schmidt 3455723e5acSSøren Schmidt static phynode_method_t rk3568_combphy_phynode_methods[] = { 3465723e5acSSøren Schmidt PHYNODEMETHOD(phynode_enable, rk3568_combphy_enable), 3475723e5acSSøren Schmidt 3485723e5acSSøren Schmidt PHYNODEMETHOD_END 3495723e5acSSøren Schmidt }; 3505723e5acSSøren Schmidt DEFINE_CLASS_1(rk3568_combphy_phynode, rk3568_combphy_phynode_class, 3515723e5acSSøren Schmidt rk3568_combphy_phynode_methods, 0, phynode_class); 3525723e5acSSøren Schmidt 3535723e5acSSøren Schmidt 3545723e5acSSøren Schmidt /* Device class and methods */ 3555723e5acSSøren Schmidt static int 3565723e5acSSøren Schmidt rk3568_combphy_probe(device_t dev) 3575723e5acSSøren Schmidt { 3585723e5acSSøren Schmidt 3595723e5acSSøren Schmidt if (!ofw_bus_status_okay(dev)) 3605723e5acSSøren Schmidt return (ENXIO); 3615723e5acSSøren Schmidt if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 3625723e5acSSøren Schmidt return (ENXIO); 3635723e5acSSøren Schmidt device_set_desc(dev, "RockChip combo PHY"); 3645723e5acSSøren Schmidt return (BUS_PROBE_DEFAULT); 3655723e5acSSøren Schmidt } 3665723e5acSSøren Schmidt 3675723e5acSSøren Schmidt static int 3685723e5acSSøren Schmidt rk3568_combphy_attach(device_t dev) 3695723e5acSSøren Schmidt { 3705723e5acSSøren Schmidt struct rk3568_combphy_softc *sc = device_get_softc(dev); 3715723e5acSSøren Schmidt struct phynode_init_def phy_init; 3725723e5acSSøren Schmidt struct phynode *phynode; 3735723e5acSSøren Schmidt int rid = 0; 3745723e5acSSøren Schmidt 3755723e5acSSøren Schmidt sc->dev = dev; 3765723e5acSSøren Schmidt sc->node = ofw_bus_get_node(dev); 3775723e5acSSøren Schmidt 3785723e5acSSøren Schmidt /* Get memory resource */ 3795723e5acSSøren Schmidt if (!(sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 3805723e5acSSøren Schmidt &rid, RF_ACTIVE))) { 3815723e5acSSøren Schmidt device_printf(dev, "Cannot allocate memory resources\n"); 3825723e5acSSøren Schmidt return (ENXIO); 3835723e5acSSøren Schmidt } 3845723e5acSSøren Schmidt 3855723e5acSSøren Schmidt /* Get syncons handles */ 3865723e5acSSøren Schmidt if (OF_hasprop(sc->node, "rockchip,pipe-grf") && 3875723e5acSSøren Schmidt syscon_get_by_ofw_property(dev, sc->node, "rockchip,pipe-grf", 3885723e5acSSøren Schmidt &sc->pipe_grf)) 3895723e5acSSøren Schmidt return (ENXIO); 3905723e5acSSøren Schmidt if (OF_hasprop(sc->node, "rockchip,pipe-phy-grf") && 3915723e5acSSøren Schmidt syscon_get_by_ofw_property(dev, sc->node, "rockchip,pipe-phy-grf", 3925723e5acSSøren Schmidt &sc->pipe_phy_grf)) 3935723e5acSSøren Schmidt return (ENXIO); 3945723e5acSSøren Schmidt 3955723e5acSSøren Schmidt /* Get & enable clocks */ 3965723e5acSSøren Schmidt if (clk_get_by_ofw_name(dev, 0, "ref", &sc->ref_clk)) { 3975723e5acSSøren Schmidt device_printf(dev, "getting ref failed\n"); 3985723e5acSSøren Schmidt return (ENXIO); 3995723e5acSSøren Schmidt } 4005723e5acSSøren Schmidt if (clk_enable(sc->ref_clk)) 4015723e5acSSøren Schmidt device_printf(dev, "enable ref failed\n"); 4025723e5acSSøren Schmidt if (clk_get_by_ofw_name(dev, 0, "apb", &sc->apb_clk)) { 4035723e5acSSøren Schmidt device_printf(dev, "getting apb failed\n"); 4045723e5acSSøren Schmidt return (ENXIO); 4055723e5acSSøren Schmidt } 4065723e5acSSøren Schmidt if (clk_enable(sc->apb_clk)) 4075723e5acSSøren Schmidt device_printf(dev, "enable apb failed\n"); 4085723e5acSSøren Schmidt if (clk_get_by_ofw_name(dev, 0, "pipe", &sc->pipe_clk)) { 4095723e5acSSøren Schmidt device_printf(dev, "getting pipe failed\n"); 4105723e5acSSøren Schmidt return (ENXIO); 4115723e5acSSøren Schmidt } 4125723e5acSSøren Schmidt if (clk_enable(sc->pipe_clk)) 4135723e5acSSøren Schmidt device_printf(dev, "enable pipe failed\n"); 4145723e5acSSøren Schmidt 4155723e5acSSøren Schmidt /* get & assert reset */ 4165723e5acSSøren Schmidt if (hwreset_get_by_ofw_idx(dev, sc->node, 0, &sc->phy_reset)) { 4175723e5acSSøren Schmidt device_printf(dev, "Cannot get reset\n"); 4185723e5acSSøren Schmidt return (ENXIO); 4195723e5acSSøren Schmidt } 4205723e5acSSøren Schmidt hwreset_assert(sc->phy_reset); 4215723e5acSSøren Schmidt 4225723e5acSSøren Schmidt bzero(&phy_init, sizeof(phy_init)); 4235723e5acSSøren Schmidt phy_init.id = 0; 4245723e5acSSøren Schmidt phy_init.ofw_node = sc->node; 4255723e5acSSøren Schmidt if (!(phynode = phynode_create(dev, &rk3568_combphy_phynode_class, 4265723e5acSSøren Schmidt &phy_init))) { 4275723e5acSSøren Schmidt device_printf(dev, "failed to create combphy PHY\n"); 4285723e5acSSøren Schmidt return (ENXIO); 4295723e5acSSøren Schmidt } 4305723e5acSSøren Schmidt if (!phynode_register(phynode)) { 4315723e5acSSøren Schmidt device_printf(dev, "failed to register combphy PHY\n"); 4325723e5acSSøren Schmidt return (ENXIO); 4335723e5acSSøren Schmidt } 4345723e5acSSøren Schmidt sc->phynode = phynode; 4355723e5acSSøren Schmidt sc->mode = 0; 4365723e5acSSøren Schmidt 4375723e5acSSøren Schmidt return (0); 4385723e5acSSøren Schmidt } 4395723e5acSSøren Schmidt 4405723e5acSSøren Schmidt static int 4415723e5acSSøren Schmidt rk3568_combphy_map(device_t dev, phandle_t xref, int ncells, pcell_t *cells, 4425723e5acSSøren Schmidt intptr_t *id) 4435723e5acSSøren Schmidt { 4445723e5acSSøren Schmidt struct rk3568_combphy_softc *sc = device_get_softc(dev); 4455723e5acSSøren Schmidt 4465723e5acSSøren Schmidt if (phydev_default_ofw_map(dev, xref, ncells, cells, id)) 4475723e5acSSøren Schmidt return (ERANGE); 4485723e5acSSøren Schmidt 4495723e5acSSøren Schmidt /* Store the phy mode that is handed to us in id */ 4505723e5acSSøren Schmidt sc->mode = *id; 4515723e5acSSøren Schmidt 4525723e5acSSøren Schmidt /* Set our id to 0 so the std phy_get_*() works as usual */ 4535723e5acSSøren Schmidt *id = 0; 4545723e5acSSøren Schmidt 4555723e5acSSøren Schmidt return (0); 4565723e5acSSøren Schmidt } 4575723e5acSSøren Schmidt 4585723e5acSSøren Schmidt static device_method_t rk3568_combphy_methods[] = { 4595723e5acSSøren Schmidt DEVMETHOD(device_probe, rk3568_combphy_probe), 4605723e5acSSøren Schmidt DEVMETHOD(device_attach, rk3568_combphy_attach), 4615723e5acSSøren Schmidt DEVMETHOD(phydev_map, rk3568_combphy_map), 4625723e5acSSøren Schmidt 4635723e5acSSøren Schmidt DEVMETHOD_END 4645723e5acSSøren Schmidt }; 4655723e5acSSøren Schmidt 4665723e5acSSøren Schmidt DEFINE_CLASS_1(rk3568_combphy, rk3568_combphy_driver, rk3568_combphy_methods, 4675723e5acSSøren Schmidt sizeof(struct simple_mfd_softc), simple_mfd_driver); 4685723e5acSSøren Schmidt EARLY_DRIVER_MODULE(rk3568_combphy, simplebus, rk3568_combphy_driver, 4695723e5acSSøren Schmidt 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE); 470