1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/gpio.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/intr.h> 46 47 #include <dev/gpio/gpiobusvar.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/extres/clk/clk.h> 51 52 #include "gpio_if.h" 53 54 #include "fdt_pinctrl_if.h" 55 56 #define RK_GPIO_SWPORTA_DR 0x00 /* Data register */ 57 #define RK_GPIO_SWPORTA_DDR 0x04 /* Data direction register */ 58 59 #define RK_GPIO_INTEN 0x30 /* Interrupt enable register */ 60 #define RK_GPIO_INTMASK 0x34 /* Interrupt mask register */ 61 #define RK_GPIO_INTTYPE_LEVEL 0x38 /* Interrupt level register */ 62 #define RK_GPIO_INT_POLARITY 0x3C /* Interrupt polarity register */ 63 #define RK_GPIO_INT_STATUS 0x40 /* Interrupt status register */ 64 #define RK_GPIO_INT_RAWSTATUS 0x44 /* Raw Interrupt status register */ 65 66 #define RK_GPIO_DEBOUNCE 0x48 /* Debounce enable register */ 67 68 #define RK_GPIO_PORTA_EOI 0x4C /* Clear interrupt register */ 69 #define RK_GPIO_EXT_PORTA 0x50 /* External port register */ 70 71 #define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */ 72 73 #define RK_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 74 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) 75 76 struct rk_gpio_softc { 77 device_t sc_dev; 78 device_t sc_busdev; 79 struct mtx sc_mtx; 80 struct resource *sc_res[2]; 81 bus_space_tag_t sc_bst; 82 bus_space_handle_t sc_bsh; 83 clk_t clk; 84 device_t pinctrl; 85 }; 86 87 static struct ofw_compat_data compat_data[] = { 88 {"rockchip,gpio-bank", 1}, 89 {NULL, 0} 90 }; 91 92 static struct resource_spec rk_gpio_spec[] = { 93 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 94 { SYS_RES_IRQ, 0, RF_ACTIVE }, 95 { -1, 0 } 96 }; 97 98 static int rk_gpio_detach(device_t dev); 99 100 #define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 101 #define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 102 #define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 103 104 #define RK_GPIO_WRITE(_sc, _off, _val) \ 105 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) 106 #define RK_GPIO_READ(_sc, _off) \ 107 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) 108 109 static int 110 rk_gpio_probe(device_t dev) 111 { 112 113 if (!ofw_bus_status_okay(dev)) 114 return (ENXIO); 115 116 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 117 return (ENXIO); 118 119 device_set_desc(dev, "RockChip GPIO Bank controller"); 120 return (BUS_PROBE_DEFAULT); 121 } 122 123 static int 124 rk_gpio_attach(device_t dev) 125 { 126 struct rk_gpio_softc *sc; 127 phandle_t node; 128 int err; 129 130 sc = device_get_softc(dev); 131 sc->sc_dev = dev; 132 sc->pinctrl = device_get_parent(dev); 133 134 node = ofw_bus_get_node(sc->sc_dev); 135 if (!OF_hasprop(node, "gpio-controller")) 136 return (ENXIO); 137 138 mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN); 139 140 if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) { 141 device_printf(dev, "could not allocate resources\n"); 142 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 143 mtx_destroy(&sc->sc_mtx); 144 return (ENXIO); 145 } 146 147 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 148 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 149 150 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) { 151 device_printf(dev, "Cannot get clock\n"); 152 rk_gpio_detach(dev); 153 return (ENXIO); 154 } 155 err = clk_enable(sc->clk); 156 if (err != 0) { 157 device_printf(dev, "Could not enable clock %s\n", 158 clk_get_name(sc->clk)); 159 rk_gpio_detach(dev); 160 return (ENXIO); 161 } 162 163 sc->sc_busdev = gpiobus_attach_bus(dev); 164 if (sc->sc_busdev == NULL) { 165 rk_gpio_detach(dev); 166 return (ENXIO); 167 } 168 169 return (0); 170 } 171 172 static int 173 rk_gpio_detach(device_t dev) 174 { 175 struct rk_gpio_softc *sc; 176 177 sc = device_get_softc(dev); 178 179 if (sc->sc_busdev) 180 gpiobus_detach_bus(dev); 181 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 182 mtx_destroy(&sc->sc_mtx); 183 clk_disable(sc->clk); 184 185 return(0); 186 } 187 188 static device_t 189 rk_gpio_get_bus(device_t dev) 190 { 191 struct rk_gpio_softc *sc; 192 193 sc = device_get_softc(dev); 194 195 return (sc->sc_busdev); 196 } 197 198 static int 199 rk_gpio_pin_max(device_t dev, int *maxpin) 200 { 201 202 /* Each bank have always 32 pins */ 203 /* XXX not true*/ 204 *maxpin = 31; 205 return (0); 206 } 207 208 static int 209 rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 210 { 211 struct rk_gpio_softc *sc; 212 uint32_t bank; 213 214 sc = device_get_softc(dev); 215 216 if (pin >= 32) 217 return (EINVAL); 218 219 bank = pin / 8; 220 pin = pin - (bank * 8); 221 RK_GPIO_LOCK(sc); 222 snprintf(name, GPIOMAXNAME, "P%c%d", bank + 'A', pin); 223 RK_GPIO_UNLOCK(sc); 224 225 return (0); 226 } 227 228 static int 229 rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 230 { 231 struct rk_gpio_softc *sc; 232 uint32_t reg; 233 int rv; 234 bool is_gpio; 235 236 sc = device_get_softc(dev); 237 238 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, &is_gpio); 239 if (rv != 0) 240 return (rv); 241 if (!is_gpio) 242 return (EINVAL); 243 244 *flags = 0; 245 rv = FDT_PINCTRL_GET_FLAGS(sc->pinctrl, dev, pin, flags); 246 if (rv != 0) 247 return (rv); 248 249 RK_GPIO_LOCK(sc); 250 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); 251 RK_GPIO_UNLOCK(sc); 252 253 if (reg & (1 << pin)) 254 *flags |= GPIO_PIN_OUTPUT; 255 else 256 *flags |= GPIO_PIN_INPUT; 257 258 return (0); 259 } 260 261 static int 262 rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 263 { 264 265 *caps = RK_GPIO_DEFAULT_CAPS; 266 return (0); 267 } 268 269 static int 270 rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 271 { 272 struct rk_gpio_softc *sc; 273 uint32_t reg; 274 int rv; 275 bool is_gpio; 276 277 sc = device_get_softc(dev); 278 279 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, &is_gpio); 280 if (rv != 0) 281 return (rv); 282 if (!is_gpio) 283 return (EINVAL); 284 285 rv = FDT_PINCTRL_SET_FLAGS(sc->pinctrl, dev, pin, flags); 286 if (rv != 0) 287 return (rv); 288 289 RK_GPIO_LOCK(sc); 290 291 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); 292 if (flags & GPIO_PIN_INPUT) 293 reg &= ~(1 << pin); 294 else if (flags & GPIO_PIN_OUTPUT) 295 reg |= (1 << pin); 296 297 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg); 298 RK_GPIO_UNLOCK(sc); 299 300 return (0); 301 } 302 303 static int 304 rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 305 { 306 struct rk_gpio_softc *sc; 307 uint32_t reg; 308 309 sc = device_get_softc(dev); 310 311 RK_GPIO_LOCK(sc); 312 reg = RK_GPIO_READ(sc, RK_GPIO_EXT_PORTA); 313 RK_GPIO_UNLOCK(sc); 314 315 *val = reg & (1 << pin) ? 1 : 0; 316 317 return (0); 318 } 319 320 static int 321 rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 322 { 323 struct rk_gpio_softc *sc; 324 uint32_t reg; 325 326 sc = device_get_softc(dev); 327 328 RK_GPIO_LOCK(sc); 329 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); 330 if (value) 331 reg |= (1 << pin); 332 else 333 reg &= ~(1 << pin); 334 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); 335 RK_GPIO_UNLOCK(sc); 336 337 return (0); 338 } 339 340 static int 341 rk_gpio_pin_toggle(device_t dev, uint32_t pin) 342 { 343 struct rk_gpio_softc *sc; 344 uint32_t reg; 345 346 sc = device_get_softc(dev); 347 348 RK_GPIO_LOCK(sc); 349 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); 350 if (reg & (1 << pin)) 351 reg &= ~(1 << pin); 352 else 353 reg |= (1 << pin); 354 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); 355 RK_GPIO_UNLOCK(sc); 356 357 return (0); 358 } 359 360 static int 361 rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 362 uint32_t change_pins, uint32_t *orig_pins) 363 { 364 struct rk_gpio_softc *sc; 365 uint32_t reg; 366 367 sc = device_get_softc(dev); 368 369 RK_GPIO_LOCK(sc); 370 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); 371 if (orig_pins) 372 *orig_pins = reg; 373 374 if ((clear_pins | change_pins) != 0) { 375 reg = (reg & ~clear_pins) ^ change_pins; 376 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); 377 } 378 RK_GPIO_UNLOCK(sc); 379 380 return (0); 381 } 382 383 static int 384 rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 385 uint32_t *pin_flags) 386 { 387 struct rk_gpio_softc *sc; 388 uint32_t reg, set, mask, flags; 389 int i; 390 391 sc = device_get_softc(dev); 392 393 if (first_pin != 0 || num_pins > 32) 394 return (EINVAL); 395 396 set = 0; 397 mask = 0; 398 for (i = 0; i < num_pins; i++) { 399 mask = (mask << 1) | 1; 400 flags = pin_flags[i]; 401 if (flags & GPIO_PIN_INPUT) { 402 set &= ~(1 << i); 403 } else if (flags & GPIO_PIN_OUTPUT) { 404 set |= (1 << i); 405 } 406 } 407 408 RK_GPIO_LOCK(sc); 409 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); 410 reg &= ~mask; 411 reg |= set; 412 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg); 413 RK_GPIO_UNLOCK(sc); 414 415 return (0); 416 } 417 418 static int 419 rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 420 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 421 { 422 423 /* The gpios are mapped as <pin flags> */ 424 *pin = gpios[0]; 425 *flags = gpios[1]; 426 return (0); 427 } 428 429 static phandle_t 430 rk_gpio_get_node(device_t bus, device_t dev) 431 { 432 433 /* We only have one child, the GPIO bus, which needs our own node. */ 434 return (ofw_bus_get_node(bus)); 435 } 436 437 static device_method_t rk_gpio_methods[] = { 438 /* Device interface */ 439 DEVMETHOD(device_probe, rk_gpio_probe), 440 DEVMETHOD(device_attach, rk_gpio_attach), 441 DEVMETHOD(device_detach, rk_gpio_detach), 442 443 /* GPIO protocol */ 444 DEVMETHOD(gpio_get_bus, rk_gpio_get_bus), 445 DEVMETHOD(gpio_pin_max, rk_gpio_pin_max), 446 DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname), 447 DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags), 448 DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps), 449 DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags), 450 DEVMETHOD(gpio_pin_get, rk_gpio_pin_get), 451 DEVMETHOD(gpio_pin_set, rk_gpio_pin_set), 452 DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle), 453 DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32), 454 DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32), 455 DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios), 456 457 /* ofw_bus interface */ 458 DEVMETHOD(ofw_bus_get_node, rk_gpio_get_node), 459 460 DEVMETHOD_END 461 }; 462 463 static driver_t rk_gpio_driver = { 464 "gpio", 465 rk_gpio_methods, 466 sizeof(struct rk_gpio_softc), 467 }; 468 469 static devclass_t rk_gpio_devclass; 470 471 /* 472 * GPIO driver is always a child of rk_pinctrl driver and should be probed 473 * and attached within rk_pinctrl_attach function. Due to this, bus pass order 474 * must be same as bus pass order of rk_pinctrl driver. 475 */ 476 EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver, 477 rk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 478