1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/gpio.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/intr.h> 46 47 #include <dev/gpio/gpiobusvar.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/extres/clk/clk.h> 51 52 #include "gpio_if.h" 53 54 #include "fdt_pinctrl_if.h" 55 56 #define RK_GPIO_SWPORTA_DR 0x00 /* Data register */ 57 #define RK_GPIO_SWPORTA_DDR 0x04 /* Data direction register */ 58 59 #define RK_GPIO_INTEN 0x30 /* Interrupt enable register */ 60 #define RK_GPIO_INTMASK 0x34 /* Interrupt mask register */ 61 #define RK_GPIO_INTTYPE_LEVEL 0x38 /* Interrupt level register */ 62 #define RK_GPIO_INT_POLARITY 0x3C /* Interrupt polarity register */ 63 #define RK_GPIO_INT_STATUS 0x40 /* Interrupt status register */ 64 #define RK_GPIO_INT_RAWSTATUS 0x44 /* Raw Interrupt status register */ 65 66 #define RK_GPIO_DEBOUNCE 0x48 /* Debounce enable register */ 67 68 #define RK_GPIO_PORTA_EOI 0x4C /* Clear interrupt register */ 69 #define RK_GPIO_EXT_PORTA 0x50 /* External port register */ 70 71 #define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */ 72 73 #define RK_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 74 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) 75 76 struct rk_gpio_softc { 77 device_t sc_dev; 78 device_t sc_busdev; 79 struct mtx sc_mtx; 80 struct resource *sc_res[2]; 81 bus_space_tag_t sc_bst; 82 bus_space_handle_t sc_bsh; 83 clk_t clk; 84 device_t pinctrl; 85 }; 86 87 static struct ofw_compat_data compat_data[] = { 88 {"rockchip,gpio-bank", 1}, 89 {NULL, 0} 90 }; 91 92 static struct resource_spec rk_gpio_spec[] = { 93 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 94 { SYS_RES_IRQ, 0, RF_ACTIVE }, 95 { -1, 0 } 96 }; 97 98 static int rk_gpio_detach(device_t dev); 99 100 #define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 101 #define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 102 #define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 103 104 #define RK_GPIO_WRITE(_sc, _off, _val) \ 105 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) 106 #define RK_GPIO_READ(_sc, _off) \ 107 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) 108 109 static int 110 rk_gpio_probe(device_t dev) 111 { 112 113 if (!ofw_bus_status_okay(dev)) 114 return (ENXIO); 115 116 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 117 return (ENXIO); 118 119 device_set_desc(dev, "RockChip GPIO Bank controller"); 120 return (BUS_PROBE_DEFAULT); 121 } 122 123 static int 124 rk_gpio_attach(device_t dev) 125 { 126 struct rk_gpio_softc *sc; 127 phandle_t node; 128 int err; 129 130 sc = device_get_softc(dev); 131 sc->sc_dev = dev; 132 sc->pinctrl = device_get_parent(dev); 133 134 node = ofw_bus_get_node(sc->sc_dev); 135 if (!OF_hasprop(node, "gpio-controller")) 136 return (ENXIO); 137 138 mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN); 139 140 if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) { 141 device_printf(dev, "could not allocate resources\n"); 142 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 143 mtx_destroy(&sc->sc_mtx); 144 return (ENXIO); 145 } 146 147 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 148 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 149 150 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) { 151 device_printf(dev, "Cannot get clock\n"); 152 rk_gpio_detach(dev); 153 return (ENXIO); 154 } 155 err = clk_enable(sc->clk); 156 if (err != 0) { 157 device_printf(dev, "Could not enable clock %s\n", 158 clk_get_name(sc->clk)); 159 rk_gpio_detach(dev); 160 return (ENXIO); 161 } 162 163 sc->sc_busdev = gpiobus_attach_bus(dev); 164 if (sc->sc_busdev == NULL) { 165 rk_gpio_detach(dev); 166 return (ENXIO); 167 } 168 169 return (0); 170 } 171 172 static int 173 rk_gpio_detach(device_t dev) 174 { 175 struct rk_gpio_softc *sc; 176 177 sc = device_get_softc(dev); 178 179 if (sc->sc_busdev) 180 gpiobus_detach_bus(dev); 181 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 182 mtx_destroy(&sc->sc_mtx); 183 clk_disable(sc->clk); 184 185 return(0); 186 } 187 188 static device_t 189 rk_gpio_get_bus(device_t dev) 190 { 191 struct rk_gpio_softc *sc; 192 193 sc = device_get_softc(dev); 194 195 return (sc->sc_busdev); 196 } 197 198 static int 199 rk_gpio_pin_max(device_t dev, int *maxpin) 200 { 201 202 /* Each bank have always 32 pins */ 203 /* XXX not true*/ 204 *maxpin = 31; 205 return (0); 206 } 207 208 static int 209 rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 210 { 211 struct rk_gpio_softc *sc; 212 213 sc = device_get_softc(dev); 214 215 if (pin >= 32) 216 return (EINVAL); 217 218 RK_GPIO_LOCK(sc); 219 snprintf(name, GPIOMAXNAME, "gpio%d", pin); 220 RK_GPIO_UNLOCK(sc); 221 222 return (0); 223 } 224 225 static int 226 rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 227 { 228 struct rk_gpio_softc *sc; 229 uint32_t reg; 230 int rv; 231 bool is_gpio; 232 233 sc = device_get_softc(dev); 234 235 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, &is_gpio); 236 if (rv != 0) 237 return (rv); 238 if (!is_gpio) 239 return (EINVAL); 240 241 *flags = 0; 242 rv = FDT_PINCTRL_GET_FLAGS(sc->pinctrl, dev, pin, flags); 243 if (rv != 0) 244 return (rv); 245 246 RK_GPIO_LOCK(sc); 247 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); 248 RK_GPIO_UNLOCK(sc); 249 250 if (reg & (1 << pin)) 251 *flags |= GPIO_PIN_OUTPUT; 252 else 253 *flags |= GPIO_PIN_INPUT; 254 255 return (0); 256 } 257 258 static int 259 rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 260 { 261 262 *caps = RK_GPIO_DEFAULT_CAPS; 263 return (0); 264 } 265 266 static int 267 rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 268 { 269 struct rk_gpio_softc *sc; 270 uint32_t reg; 271 int rv; 272 bool is_gpio; 273 274 sc = device_get_softc(dev); 275 276 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, &is_gpio); 277 if (rv != 0) 278 return (rv); 279 if (!is_gpio) 280 return (EINVAL); 281 282 rv = FDT_PINCTRL_SET_FLAGS(sc->pinctrl, dev, pin, flags); 283 if (rv != 0) 284 return (rv); 285 286 RK_GPIO_LOCK(sc); 287 288 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); 289 if (flags & GPIO_PIN_INPUT) 290 reg &= ~(1 << pin); 291 else if (flags & GPIO_PIN_OUTPUT) 292 reg |= (1 << pin); 293 294 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg); 295 RK_GPIO_UNLOCK(sc); 296 297 return (0); 298 } 299 300 static int 301 rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 302 { 303 struct rk_gpio_softc *sc; 304 uint32_t reg; 305 306 sc = device_get_softc(dev); 307 308 RK_GPIO_LOCK(sc); 309 reg = RK_GPIO_READ(sc, RK_GPIO_EXT_PORTA); 310 RK_GPIO_UNLOCK(sc); 311 312 *val = reg & (1 << pin) ? 1 : 0; 313 314 return (0); 315 } 316 317 static int 318 rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 319 { 320 struct rk_gpio_softc *sc; 321 uint32_t reg; 322 323 sc = device_get_softc(dev); 324 325 RK_GPIO_LOCK(sc); 326 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); 327 if (value) 328 reg |= (1 << pin); 329 else 330 reg &= ~(1 << pin); 331 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); 332 RK_GPIO_UNLOCK(sc); 333 334 return (0); 335 } 336 337 static int 338 rk_gpio_pin_toggle(device_t dev, uint32_t pin) 339 { 340 struct rk_gpio_softc *sc; 341 uint32_t reg; 342 343 sc = device_get_softc(dev); 344 345 RK_GPIO_LOCK(sc); 346 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); 347 if (reg & (1 << pin)) 348 reg &= ~(1 << pin); 349 else 350 reg |= (1 << pin); 351 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); 352 RK_GPIO_UNLOCK(sc); 353 354 return (0); 355 } 356 357 static int 358 rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 359 uint32_t change_pins, uint32_t *orig_pins) 360 { 361 struct rk_gpio_softc *sc; 362 uint32_t reg; 363 364 sc = device_get_softc(dev); 365 366 RK_GPIO_LOCK(sc); 367 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); 368 if (orig_pins) 369 *orig_pins = reg; 370 371 if ((clear_pins | change_pins) != 0) { 372 reg = (reg & ~clear_pins) ^ change_pins; 373 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); 374 } 375 RK_GPIO_UNLOCK(sc); 376 377 return (0); 378 } 379 380 static int 381 rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 382 uint32_t *pin_flags) 383 { 384 struct rk_gpio_softc *sc; 385 uint32_t reg, set, mask, flags; 386 int i; 387 388 sc = device_get_softc(dev); 389 390 if (first_pin != 0 || num_pins > 32) 391 return (EINVAL); 392 393 set = 0; 394 mask = 0; 395 for (i = 0; i < num_pins; i++) { 396 mask = (mask << 1) | 1; 397 flags = pin_flags[i]; 398 if (flags & GPIO_PIN_INPUT) { 399 set &= ~(1 << i); 400 } else if (flags & GPIO_PIN_OUTPUT) { 401 set |= (1 << i); 402 } 403 } 404 405 RK_GPIO_LOCK(sc); 406 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); 407 reg &= ~mask; 408 reg |= set; 409 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg); 410 RK_GPIO_UNLOCK(sc); 411 412 return (0); 413 } 414 415 static int 416 rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 417 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 418 { 419 420 /* The gpios are mapped as <pin flags> */ 421 *pin = gpios[0]; 422 *flags = gpios[1]; 423 return (0); 424 } 425 426 static phandle_t 427 rk_gpio_get_node(device_t bus, device_t dev) 428 { 429 430 /* We only have one child, the GPIO bus, which needs our own node. */ 431 return (ofw_bus_get_node(bus)); 432 } 433 434 static device_method_t rk_gpio_methods[] = { 435 /* Device interface */ 436 DEVMETHOD(device_probe, rk_gpio_probe), 437 DEVMETHOD(device_attach, rk_gpio_attach), 438 DEVMETHOD(device_detach, rk_gpio_detach), 439 440 /* GPIO protocol */ 441 DEVMETHOD(gpio_get_bus, rk_gpio_get_bus), 442 DEVMETHOD(gpio_pin_max, rk_gpio_pin_max), 443 DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname), 444 DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags), 445 DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps), 446 DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags), 447 DEVMETHOD(gpio_pin_get, rk_gpio_pin_get), 448 DEVMETHOD(gpio_pin_set, rk_gpio_pin_set), 449 DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle), 450 DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32), 451 DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32), 452 DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios), 453 454 /* ofw_bus interface */ 455 DEVMETHOD(ofw_bus_get_node, rk_gpio_get_node), 456 457 DEVMETHOD_END 458 }; 459 460 static driver_t rk_gpio_driver = { 461 "gpio", 462 rk_gpio_methods, 463 sizeof(struct rk_gpio_softc), 464 }; 465 466 static devclass_t rk_gpio_devclass; 467 468 /* 469 * GPIO driver is always a child of rk_pinctrl driver and should be probed 470 * and attached within rk_pinctrl_attach function. Due to this, bus pass order 471 * must be same as bus pass order of rk_pinctrl driver. 472 */ 473 EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver, 474 rk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 475