1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2019 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/resource.h> 42 #include <machine/bus.h> 43 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dev/extres/clk/clk.h> 48 #include <dev/extres/hwreset/hwreset.h> 49 #include <dev/extres/syscon/syscon.h> 50 51 #include "syscon_if.h" 52 53 #include "opt_snd.h" 54 #include <dev/sound/pcm/sound.h> 55 #include <dev/sound/fdt/audio_dai.h> 56 #include "audio_dai_if.h" 57 58 #define AUDIO_BUFFER_SIZE 48000 * 4 59 60 #define I2S_TXCR 0x0000 61 #define I2S_CSR_2 (0 << 15) 62 #define I2S_CSR_4 (1 << 15) 63 #define I2S_CSR_6 (2 << 15) 64 #define I2S_CSR_8 (3 << 15) 65 #define I2S_TXCR_IBM_NORMAL (0 << 9) 66 #define I2S_TXCR_IBM_LJ (1 << 9) 67 #define I2S_TXCR_IBM_RJ (2 << 9) 68 #define I2S_TXCR_PBM_NODELAY (0 << 7) 69 #define I2S_TXCR_PBM_1 (1 << 7) 70 #define I2S_TXCR_PBM_2 (2 << 7) 71 #define I2S_TXCR_PBM_3 (3 << 7) 72 #define I2S_TXCR_TFS_I2S (0 << 5) 73 #define I2S_TXCR_TFS_PCM (1 << 5) 74 #define I2S_TXCR_VDW_16 (0xf << 0) 75 #define I2S_RXCR 0x0004 76 #define I2S_RXCR_IBM_NORMAL (0 << 9) 77 #define I2S_RXCR_IBM_LJ (1 << 9) 78 #define I2S_RXCR_IBM_RJ (2 << 9) 79 #define I2S_RXCR_PBM_NODELAY (0 << 7) 80 #define I2S_RXCR_PBM_1 (1 << 7) 81 #define I2S_RXCR_PBM_2 (2 << 7) 82 #define I2S_RXCR_PBM_3 (3 << 7) 83 #define I2S_RXCR_TFS_I2S (0 << 5) 84 #define I2S_RXCR_TFS_PCM (1 << 5) 85 #define I2S_RXCR_VDW_16 (0xf << 0) 86 #define I2S_CKR 0x0008 87 #define I2S_CKR_MSS_MASK (1 << 27) 88 #define I2S_CKR_MSS_MASTER (0 << 27) 89 #define I2S_CKR_MSS_SLAVE (1 << 27) 90 #define I2S_CKR_CKP (1 << 26) 91 #define I2S_CKR_MDIV(n) (((n) - 1) << 16) 92 #define I2S_CKR_MDIV_MASK (0xff << 16) 93 #define I2S_CKR_RSD(n) (((n) - 1) << 8) 94 #define I2S_CKR_RSD_MASK (0xff << 8) 95 #define I2S_CKR_TSD(n) (((n) - 1) << 0) 96 #define I2S_CKR_TSD_MASK (0xff << 0) 97 #define I2S_TXFIFOLR 0x000c 98 #define TXFIFO0LR_MASK 0x3f 99 #define I2S_DMACR 0x0010 100 #define I2S_DMACR_RDE_ENABLE (1 << 24) 101 #define I2S_DMACR_RDL(n) ((n) << 16) 102 #define I2S_DMACR_TDE_ENABLE (1 << 8) 103 #define I2S_DMACR_TDL(n) ((n) << 0) 104 #define I2S_INTCR 0x0014 105 #define I2S_INTCR_RFT(n) (((n) - 1) << 20) 106 #define I2S_INTCR_TFT(n) (((n) - 1) << 4) 107 #define I2S_INTCR_RXFIE (1 << 16) 108 #define I2S_INTCR_TXUIC (1 << 2) 109 #define I2S_INTCR_TXEIE (1 << 0) 110 #define I2S_INTSR 0x0018 111 #define I2S_INTSR_RXFI (1 << 16) 112 #define I2S_INTSR_TXUI (1 << 1) 113 #define I2S_INTSR_TXEI (1 << 0) 114 #define I2S_XFER 0x001c 115 #define I2S_XFER_RXS_START (1 << 1) 116 #define I2S_XFER_TXS_START (1 << 0) 117 #define I2S_CLR 0x0020 118 #define I2S_CLR_RXC (1 << 1) 119 #define I2S_CLR_TXC (1 << 0) 120 #define I2S_TXDR 0x0024 121 #define I2S_RXDR 0x0028 122 #define I2S_RXFIFOLR 0x002c 123 #define RXFIFO0LR_MASK 0x3f 124 125 /* syscon */ 126 #define GRF_SOC_CON8 0xe220 127 #define I2S_IO_DIRECTION_MASK 7 128 #define I2S_IO_DIRECTION_SHIFT 11 129 #define I2S_IO_8CH_OUT_2CH_IN 0 130 #define I2S_IO_6CH_OUT_4CH_IN 4 131 #define I2S_IO_4CH_OUT_6CH_IN 6 132 #define I2S_IO_2CH_OUT_8CH_IN 7 133 134 #define DIV_ROUND_CLOSEST(n,d) (((n) + (d) / 2) / (d)) 135 136 #define RK_I2S_SAMPLING_RATE 48000 137 #define FIFO_SIZE 32 138 139 static struct ofw_compat_data compat_data[] = { 140 { "rockchip,rk3066-i2s", 1 }, 141 { "rockchip,rk3399-i2s", 1 }, 142 { NULL, 0 } 143 }; 144 145 static struct resource_spec rk_i2s_spec[] = { 146 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 147 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 148 { -1, 0 } 149 }; 150 151 struct rk_i2s_softc { 152 device_t dev; 153 struct resource *res[2]; 154 struct mtx mtx; 155 clk_t clk; 156 clk_t hclk; 157 void * intrhand; 158 struct syscon *grf; 159 /* pointers to playback/capture buffers */ 160 uint32_t play_ptr; 161 uint32_t rec_ptr; 162 }; 163 164 #define RK_I2S_LOCK(sc) mtx_lock(&(sc)->mtx) 165 #define RK_I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 166 #define RK_I2S_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) 167 #define RK_I2S_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 168 169 static int rk_i2s_probe(device_t dev); 170 static int rk_i2s_attach(device_t dev); 171 static int rk_i2s_detach(device_t dev); 172 173 static uint32_t sc_fmt[] = { 174 SND_FORMAT(AFMT_S16_LE, 2, 0), 175 0 176 }; 177 static struct pcmchan_caps rk_i2s_caps = {RK_I2S_SAMPLING_RATE, RK_I2S_SAMPLING_RATE, sc_fmt, 0}; 178 179 180 static int 181 rk_i2s_init(struct rk_i2s_softc *sc) 182 { 183 uint32_t val; 184 int error; 185 186 clk_set_freq(sc->clk, RK_I2S_SAMPLING_RATE * 256, 187 CLK_SET_ROUND_DOWN); 188 error = clk_enable(sc->clk); 189 if (error != 0) { 190 device_printf(sc->dev, "cannot enable i2s_clk clock\n"); 191 return (ENXIO); 192 } 193 194 val = I2S_INTCR_TFT(FIFO_SIZE/2); 195 val |= I2S_INTCR_RFT(FIFO_SIZE/2); 196 RK_I2S_WRITE_4(sc, I2S_INTCR, val); 197 198 if (sc->grf && ofw_bus_is_compatible(sc->dev, "rockchip,rk3399-i2s")) { 199 val = (I2S_IO_2CH_OUT_8CH_IN << I2S_IO_DIRECTION_SHIFT); 200 val |= (I2S_IO_DIRECTION_MASK << I2S_IO_DIRECTION_SHIFT) << 16; 201 SYSCON_WRITE_4(sc->grf, GRF_SOC_CON8, val); 202 203 #if 0 204 // HACK: enable IO domain 205 val = (1 << 1); 206 val |= (1 << 1) << 16; 207 SYSCON_WRITE_4(sc->grf, 0xe640, val); 208 #endif 209 } 210 211 RK_I2S_WRITE_4(sc, I2S_XFER, 0); 212 213 return (0); 214 } 215 216 static int 217 rk_i2s_probe(device_t dev) 218 { 219 if (!ofw_bus_status_okay(dev)) 220 return (ENXIO); 221 222 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 223 return (ENXIO); 224 225 device_set_desc(dev, "Rockchip I2S"); 226 return (BUS_PROBE_DEFAULT); 227 } 228 229 static int 230 rk_i2s_attach(device_t dev) 231 { 232 struct rk_i2s_softc *sc; 233 int error; 234 phandle_t node; 235 236 sc = device_get_softc(dev); 237 sc->dev = dev; 238 239 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 240 241 if (bus_alloc_resources(dev, rk_i2s_spec, sc->res) != 0) { 242 device_printf(dev, "cannot allocate resources for device\n"); 243 error = ENXIO; 244 goto fail; 245 } 246 247 error = clk_get_by_ofw_name(dev, 0, "i2s_hclk", &sc->hclk); 248 if (error != 0) { 249 device_printf(dev, "cannot get i2s_hclk clock\n"); 250 goto fail; 251 } 252 253 error = clk_get_by_ofw_name(dev, 0, "i2s_clk", &sc->clk); 254 if (error != 0) { 255 device_printf(dev, "cannot get i2s_clk clock\n"); 256 goto fail; 257 } 258 259 /* Activate the module clock. */ 260 error = clk_enable(sc->hclk); 261 if (error != 0) { 262 device_printf(dev, "cannot enable i2s_hclk clock\n"); 263 goto fail; 264 } 265 266 node = ofw_bus_get_node(dev); 267 if (OF_hasprop(node, "rockchip,grf") && 268 syscon_get_by_ofw_property(dev, node, 269 "rockchip,grf", &sc->grf) != 0) { 270 device_printf(dev, "cannot get grf driver handle\n"); 271 return (ENXIO); 272 } 273 274 rk_i2s_init(sc); 275 276 OF_device_register_xref(OF_xref_from_node(node), dev); 277 278 return (0); 279 280 fail: 281 rk_i2s_detach(dev); 282 return (error); 283 } 284 285 static int 286 rk_i2s_detach(device_t dev) 287 { 288 struct rk_i2s_softc *i2s; 289 290 i2s = device_get_softc(dev); 291 292 if (i2s->hclk != NULL) 293 clk_release(i2s->hclk); 294 if (i2s->clk) 295 clk_release(i2s->clk); 296 297 if (i2s->intrhand != NULL) 298 bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand); 299 300 bus_release_resources(dev, rk_i2s_spec, i2s->res); 301 mtx_destroy(&i2s->mtx); 302 303 return (0); 304 } 305 306 static int 307 rk_i2s_dai_init(device_t dev, uint32_t format) 308 { 309 uint32_t val, txcr, rxcr; 310 struct rk_i2s_softc *sc; 311 int fmt, pol, clk; 312 313 sc = device_get_softc(dev); 314 315 fmt = AUDIO_DAI_FORMAT_FORMAT(format); 316 pol = AUDIO_DAI_FORMAT_POLARITY(format); 317 clk = AUDIO_DAI_FORMAT_CLOCK(format); 318 319 /* Set format */ 320 val = RK_I2S_READ_4(sc, I2S_CKR); 321 322 val &= ~(I2S_CKR_MSS_MASK); 323 switch (clk) { 324 case AUDIO_DAI_CLOCK_CBM_CFM: 325 val |= I2S_CKR_MSS_MASTER; 326 break; 327 case AUDIO_DAI_CLOCK_CBS_CFS: 328 val |= I2S_CKR_MSS_SLAVE; 329 break; 330 default: 331 return (EINVAL); 332 } 333 334 switch (pol) { 335 case AUDIO_DAI_POLARITY_IB_NF: 336 val |= I2S_CKR_CKP; 337 break; 338 case AUDIO_DAI_POLARITY_NB_NF: 339 val &= ~I2S_CKR_CKP; 340 break; 341 default: 342 return (EINVAL); 343 } 344 345 RK_I2S_WRITE_4(sc, I2S_CKR, val); 346 347 txcr = I2S_TXCR_VDW_16 | I2S_CSR_2; 348 rxcr = I2S_RXCR_VDW_16 | I2S_CSR_2; 349 350 switch (fmt) { 351 case AUDIO_DAI_FORMAT_I2S: 352 txcr |= I2S_TXCR_IBM_NORMAL; 353 rxcr |= I2S_RXCR_IBM_NORMAL; 354 break; 355 case AUDIO_DAI_FORMAT_LJ: 356 txcr |= I2S_TXCR_IBM_LJ; 357 rxcr |= I2S_RXCR_IBM_LJ; 358 break; 359 case AUDIO_DAI_FORMAT_RJ: 360 txcr |= I2S_TXCR_IBM_RJ; 361 rxcr |= I2S_RXCR_IBM_RJ; 362 break; 363 case AUDIO_DAI_FORMAT_DSPA: 364 txcr |= I2S_TXCR_TFS_PCM; 365 rxcr |= I2S_RXCR_TFS_PCM; 366 txcr |= I2S_TXCR_PBM_1; 367 rxcr |= I2S_RXCR_PBM_1; 368 break; 369 case AUDIO_DAI_FORMAT_DSPB: 370 txcr |= I2S_TXCR_TFS_PCM; 371 rxcr |= I2S_RXCR_TFS_PCM; 372 txcr |= I2S_TXCR_PBM_2; 373 rxcr |= I2S_RXCR_PBM_2; 374 break; 375 default: 376 return EINVAL; 377 } 378 379 RK_I2S_WRITE_4(sc, I2S_TXCR, txcr); 380 RK_I2S_WRITE_4(sc, I2S_RXCR, rxcr); 381 382 RK_I2S_WRITE_4(sc, I2S_XFER, 0); 383 384 return (0); 385 } 386 387 388 static int 389 rk_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf) 390 { 391 struct rk_i2s_softc *sc; 392 uint32_t status; 393 uint32_t level; 394 uint32_t val = 0x00; 395 int ret = 0; 396 397 sc = device_get_softc(dev); 398 399 RK_I2S_LOCK(sc); 400 status = RK_I2S_READ_4(sc, I2S_INTSR); 401 402 if (status & I2S_INTSR_TXEI) { 403 level = RK_I2S_READ_4(sc, I2S_TXFIFOLR) & TXFIFO0LR_MASK; 404 uint8_t *samples; 405 uint32_t count, size, readyptr, written; 406 count = sndbuf_getready(play_buf); 407 size = sndbuf_getsize(play_buf); 408 readyptr = sndbuf_getreadyptr(play_buf); 409 410 /* FIXME: check actual count size */ 411 samples = (uint8_t*)sndbuf_getbuf(play_buf); 412 written = 0; 413 for (; level < FIFO_SIZE - 1; level++) { 414 val = (samples[readyptr++ % size] << 0); 415 val |= (samples[readyptr++ % size] << 8); 416 val |= (samples[readyptr++ % size] << 16); 417 val |= (samples[readyptr++ % size] << 24); 418 written += 4; 419 RK_I2S_WRITE_4(sc, I2S_TXDR, val); 420 } 421 sc->play_ptr += written; 422 sc->play_ptr %= size; 423 ret |= AUDIO_DAI_PLAY_INTR; 424 } 425 426 if (status & I2S_INTSR_RXFI) { 427 level = RK_I2S_READ_4(sc, I2S_RXFIFOLR) & RXFIFO0LR_MASK; 428 uint8_t *samples; 429 uint32_t count, size, freeptr, recorded; 430 count = sndbuf_getfree(rec_buf); 431 size = sndbuf_getsize(rec_buf); 432 freeptr = sndbuf_getfreeptr(rec_buf); 433 samples = (uint8_t*)sndbuf_getbuf(rec_buf); 434 recorded = 0; 435 if (level > count / 4) 436 level = count / 4; 437 438 for (; level > 0; level--) { 439 val = RK_I2S_READ_4(sc, I2S_RXDR); 440 samples[freeptr++ % size] = val & 0xff; 441 samples[freeptr++ % size] = (val >> 8) & 0xff; 442 samples[freeptr++ % size] = (val >> 16) & 0xff; 443 samples[freeptr++ % size] = (val >> 24) & 0xff; 444 recorded += 4; 445 } 446 sc->rec_ptr += recorded; 447 sc->rec_ptr %= size; 448 ret |= AUDIO_DAI_REC_INTR; 449 } 450 451 RK_I2S_UNLOCK(sc); 452 453 return (ret); 454 } 455 456 static struct pcmchan_caps * 457 rk_i2s_dai_get_caps(device_t dev) 458 { 459 return (&rk_i2s_caps); 460 } 461 462 static int 463 rk_i2s_dai_trigger(device_t dev, int go, int pcm_dir) 464 { 465 struct rk_i2s_softc *sc = device_get_softc(dev); 466 uint32_t val; 467 uint32_t clear_bit; 468 469 if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) 470 return (EINVAL); 471 472 switch (go) { 473 case PCMTRIG_START: 474 val = RK_I2S_READ_4(sc, I2S_INTCR); 475 if (pcm_dir == PCMDIR_PLAY) 476 val |= I2S_INTCR_TXEIE; 477 else if (pcm_dir == PCMDIR_REC) 478 val |= I2S_INTCR_RXFIE; 479 RK_I2S_WRITE_4(sc, I2S_INTCR, val); 480 481 val = I2S_XFER_TXS_START | I2S_XFER_RXS_START; 482 RK_I2S_WRITE_4(sc, I2S_XFER, val); 483 break; 484 485 case PCMTRIG_STOP: 486 case PCMTRIG_ABORT: 487 val = RK_I2S_READ_4(sc, I2S_INTCR); 488 if (pcm_dir == PCMDIR_PLAY) 489 val &= ~I2S_INTCR_TXEIE; 490 else if (pcm_dir == PCMDIR_REC) 491 val &= ~I2S_INTCR_RXFIE; 492 RK_I2S_WRITE_4(sc, I2S_INTCR, val); 493 494 /* 495 * If there is no other activity going on, stop transfers 496 */ 497 if ((val & (I2S_INTCR_TXEIE | I2S_INTCR_RXFIE)) == 0) { 498 RK_I2S_WRITE_4(sc, I2S_XFER, 0); 499 500 if (pcm_dir == PCMDIR_PLAY) 501 clear_bit = I2S_CLR_TXC; 502 else if (pcm_dir == PCMDIR_REC) 503 clear_bit = I2S_CLR_RXC; 504 else 505 return (EINVAL); 506 507 val = RK_I2S_READ_4(sc, I2S_CLR); 508 val |= clear_bit; 509 RK_I2S_WRITE_4(sc, I2S_CLR, val); 510 511 while ((RK_I2S_READ_4(sc, I2S_CLR) & clear_bit) != 0) 512 DELAY(1); 513 } 514 515 RK_I2S_LOCK(sc); 516 if (pcm_dir == PCMDIR_PLAY) 517 sc->play_ptr = 0; 518 else 519 sc->rec_ptr = 0; 520 RK_I2S_UNLOCK(sc); 521 break; 522 } 523 524 return (0); 525 } 526 527 static uint32_t 528 rk_i2s_dai_get_ptr(device_t dev, int pcm_dir) 529 { 530 struct rk_i2s_softc *sc; 531 uint32_t ptr; 532 533 sc = device_get_softc(dev); 534 535 RK_I2S_LOCK(sc); 536 if (pcm_dir == PCMDIR_PLAY) 537 ptr = sc->play_ptr; 538 else 539 ptr = sc->rec_ptr; 540 RK_I2S_UNLOCK(sc); 541 542 return ptr; 543 } 544 545 static int 546 rk_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg) 547 { 548 struct rk_i2s_softc *sc = device_get_softc(dev); 549 550 if (bus_setup_intr(dev, sc->res[1], 551 INTR_TYPE_MISC | INTR_MPSAFE, NULL, intr_handler, intr_arg, 552 &sc->intrhand)) { 553 device_printf(dev, "cannot setup interrupt handler\n"); 554 return (ENXIO); 555 } 556 557 return (0); 558 } 559 560 static uint32_t 561 rk_i2s_dai_set_chanformat(device_t dev, uint32_t format) 562 { 563 564 return (0); 565 } 566 567 static int 568 rk_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir) 569 { 570 struct rk_i2s_softc *sc; 571 int error; 572 573 sc = device_get_softc(dev); 574 error = clk_disable(sc->clk); 575 if (error != 0) { 576 device_printf(sc->dev, "could not disable i2s_clk clock\n"); 577 return (error); 578 } 579 580 error = clk_set_freq(sc->clk, rate, CLK_SET_ROUND_DOWN); 581 if (error != 0) 582 device_printf(sc->dev, "could not set i2s_clk freq\n"); 583 584 error = clk_enable(sc->clk); 585 if (error != 0) { 586 device_printf(sc->dev, "could not enable i2s_clk clock\n"); 587 return (error); 588 } 589 590 return (0); 591 } 592 593 static uint32_t 594 rk_i2s_dai_set_chanspeed(device_t dev, uint32_t speed) 595 { 596 struct rk_i2s_softc *sc; 597 int error; 598 uint32_t val; 599 uint32_t bus_clock_div, lr_clock_div; 600 uint64_t bus_clk_freq; 601 uint64_t clk_freq; 602 603 sc = device_get_softc(dev); 604 605 /* Set format */ 606 val = RK_I2S_READ_4(sc, I2S_CKR); 607 608 if ((val & I2S_CKR_MSS_SLAVE) == 0) { 609 error = clk_get_freq(sc->clk, &clk_freq); 610 if (error != 0) { 611 device_printf(sc->dev, "failed to get clk frequency: err=%d\n", error); 612 return (error); 613 } 614 bus_clk_freq = 2 * 32 * speed; 615 bus_clock_div = DIV_ROUND_CLOSEST(clk_freq, bus_clk_freq); 616 lr_clock_div = bus_clk_freq / speed; 617 618 val &= ~(I2S_CKR_MDIV_MASK | I2S_CKR_RSD_MASK | I2S_CKR_TSD_MASK); 619 val |= I2S_CKR_MDIV(bus_clock_div); 620 val |= I2S_CKR_RSD(lr_clock_div); 621 val |= I2S_CKR_TSD(lr_clock_div); 622 623 RK_I2S_WRITE_4(sc, I2S_CKR, val); 624 } 625 626 return (speed); 627 } 628 629 static device_method_t rk_i2s_methods[] = { 630 /* Device interface */ 631 DEVMETHOD(device_probe, rk_i2s_probe), 632 DEVMETHOD(device_attach, rk_i2s_attach), 633 DEVMETHOD(device_detach, rk_i2s_detach), 634 635 DEVMETHOD(audio_dai_init, rk_i2s_dai_init), 636 DEVMETHOD(audio_dai_setup_intr, rk_i2s_dai_setup_intr), 637 DEVMETHOD(audio_dai_set_sysclk, rk_i2s_dai_set_sysclk), 638 DEVMETHOD(audio_dai_set_chanspeed, rk_i2s_dai_set_chanspeed), 639 DEVMETHOD(audio_dai_set_chanformat, rk_i2s_dai_set_chanformat), 640 DEVMETHOD(audio_dai_intr, rk_i2s_dai_intr), 641 DEVMETHOD(audio_dai_get_caps, rk_i2s_dai_get_caps), 642 DEVMETHOD(audio_dai_trigger, rk_i2s_dai_trigger), 643 DEVMETHOD(audio_dai_get_ptr, rk_i2s_dai_get_ptr), 644 645 DEVMETHOD_END 646 }; 647 648 static driver_t rk_i2s_driver = { 649 "i2s", 650 rk_i2s_methods, 651 sizeof(struct rk_i2s_softc), 652 }; 653 654 static devclass_t rk_i2s_devclass; 655 656 DRIVER_MODULE(rk_i2s, simplebus, rk_i2s_driver, rk_i2s_devclass, 0, 0); 657 SIMPLEBUS_PNP_INFO(compat_data); 658