1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Emmanuel Vadot <manu@FreeBSD.Org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Rockchip PHY TYPEC 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/rman.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/gpio.h> 39 #include <machine/bus.h> 40 41 #include <dev/fdt/fdt_common.h> 42 #include <dev/ofw/ofw_bus.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 #include <dev/ofw/ofw_subr.h> 45 46 #include <dev/clk/clk.h> 47 #include <dev/phy/phy_usb.h> 48 #include <dev/syscon/syscon.h> 49 #include <dev/hwreset/hwreset.h> 50 51 #include "syscon_if.h" 52 53 #define GRF_USB3OTG_BASE(x) (0x2430 + (0x10 * x)) 54 #define GRF_USB3OTG_CON0(x) (GRF_USB3OTG_BASE(x) + 0x0) 55 #define GRF_USB3OTG_CON1(x) (GRF_USB3OTG_BASE(x) + 0x4) 56 #define USB3OTG_CON1_U3_DIS (1 << 0) 57 58 #define GRF_USB3PHY_BASE(x) (0x0e580 + (0xc * (x))) 59 #define GRF_USB3PHY_CON0(x) (GRF_USB3PHY_BASE(x) + 0x0) 60 #define USB3PHY_CON0_USB2_ONLY (1 << 3) 61 #define GRF_USB3PHY_CON1(x) (GRF_USB3PHY_BASE(x) + 0x4) 62 #define GRF_USB3PHY_CON2(x) (GRF_USB3PHY_BASE(x) + 0x8) 63 #define GRF_USB3PHY_STATUS0 0x0e5c0 64 #define GRF_USB3PHY_STATUS1 0x0e5c4 65 66 #define CMN_PLL0_VCOCAL_INIT (0x84 << 2) 67 #define CMN_PLL0_VCOCAL_ITER (0x85 << 2) 68 #define CMN_PLL0_INTDIV (0x94 << 2) 69 #define CMN_PLL0_FRACDIV (0x95 << 2) 70 #define CMN_PLL0_HIGH_THR (0x96 << 2) 71 #define CMN_PLL0_DSM_DIAG (0x97 << 2) 72 #define CMN_PLL0_SS_CTRL1 (0x98 << 2) 73 #define CMN_PLL0_SS_CTRL2 (0x99 << 2) 74 #define CMN_DIAG_PLL0_FBH_OVRD (0x1c0 << 2) 75 #define CMN_DIAG_PLL0_FBL_OVRD (0x1c1 << 2) 76 #define CMN_DIAG_PLL0_OVRD (0x1c2 << 2) 77 #define CMN_DIAG_PLL0_V2I_TUNE (0x1c5 << 2) 78 #define CMN_DIAG_PLL0_CP_TUNE (0x1c6 << 2) 79 #define CMN_DIAG_PLL0_LF_PROG (0x1c7 << 2) 80 #define CMN_DIAG_HSCLK_SEL (0x1e0 << 2) 81 #define CMN_DIAG_HSCLK_SEL_PLL_CONFIG 0x30 82 #define CMN_DIAG_HSCLK_SEL_PLL_MASK 0x33 83 84 #define TX_TXCC_MGNFS_MULT_000(lane) ((0x4050 | ((lane) << 9)) << 2) 85 #define XCVR_DIAG_BIDI_CTRL(lane) ((0x40e8 | ((lane) << 9)) << 2) 86 #define XCVR_DIAG_LANE_FCM_EN_MGN(lane) ((0x40f2 | ((lane) << 9)) << 2) 87 #define TX_PSC_A0(lane) ((0x4100 | ((lane) << 9)) << 2) 88 #define TX_PSC_A1(lane) ((0x4101 | ((lane) << 9)) << 2) 89 #define TX_PSC_A2(lane) ((0x4102 | ((lane) << 9)) << 2) 90 #define TX_PSC_A3(lane) ((0x4103 | ((lane) << 9)) << 2) 91 #define TX_RCVDET_EN_TMR(lane) ((0x4122 | ((lane) << 9)) << 2) 92 #define TX_RCVDET_ST_TMR(lane) ((0x4123 | ((lane) << 9)) << 2) 93 94 #define RX_PSC_A0(lane) ((0x8000 | ((lane) << 9)) << 2) 95 #define RX_PSC_A1(lane) ((0x8001 | ((lane) << 9)) << 2) 96 #define RX_PSC_A2(lane) ((0x8002 | ((lane) << 9)) << 2) 97 #define RX_PSC_A3(lane) ((0x8003 | ((lane) << 9)) << 2) 98 #define RX_PSC_CAL(lane) ((0x8006 | ((lane) << 9)) << 2) 99 #define RX_PSC_RDY(lane) ((0x8007 | ((lane) << 9)) << 2) 100 #define RX_SIGDET_HL_FILT_TMR(lane) ((0x8090 | ((lane) << 9)) << 2) 101 #define RX_REE_CTRL_DATA_MASK(lane) ((0x81bb | ((lane) << 9)) << 2) 102 #define RX_DIAG_SIGDET_TUNE(lane) ((0x81dc | ((lane) << 9)) << 2) 103 104 #define PMA_LANE_CFG (0xc000 << 2) 105 #define PIN_ASSIGN_D_F 0x5100 106 #define DP_MODE_CTL (0xc008 << 2) 107 #define DP_MODE_ENTER_A2 0xc104 108 #define PMA_CMN_CTRL1 (0xc800 << 2) 109 #define PMA_CMN_CTRL1_READY (1 << 0) 110 111 static struct ofw_compat_data compat_data[] = { 112 { "rockchip,rk3399-typec-phy", 1 }, 113 { NULL, 0 } 114 }; 115 116 static struct resource_spec rk_typec_phy_spec[] = { 117 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 118 { -1, 0 } 119 }; 120 121 struct rk_typec_phy_softc { 122 device_t dev; 123 struct resource *res; 124 struct syscon *grf; 125 clk_t tcpdcore; 126 clk_t tcpdphy_ref; 127 hwreset_t rst_uphy; 128 hwreset_t rst_pipe; 129 hwreset_t rst_tcphy; 130 int mode; 131 int phy_ctrl_id; 132 }; 133 134 #define RK_TYPEC_PHY_READ(sc, reg) bus_read_4(sc->res, (reg)) 135 #define RK_TYPEC_PHY_WRITE(sc, reg, val) bus_write_4(sc->res, (reg), (val)) 136 137 /* Phy class and methods. */ 138 static int rk_typec_phy_enable(struct phynode *phynode, bool enable); 139 static int rk_typec_phy_get_mode(struct phynode *phy, int *mode); 140 static int rk_typec_phy_set_mode(struct phynode *phy, int mode); 141 static phynode_method_t rk_typec_phy_phynode_methods[] = { 142 PHYNODEMETHOD(phynode_enable, rk_typec_phy_enable), 143 PHYNODEMETHOD(phynode_usb_get_mode, rk_typec_phy_get_mode), 144 PHYNODEMETHOD(phynode_usb_set_mode, rk_typec_phy_set_mode), 145 146 PHYNODEMETHOD_END 147 }; 148 149 DEFINE_CLASS_1(rk_typec_phy_phynode, rk_typec_phy_phynode_class, 150 rk_typec_phy_phynode_methods, 151 sizeof(struct phynode_usb_sc), phynode_usb_class); 152 153 enum RK3399_USBPHY { 154 RK3399_TYPEC_PHY_DP = 0, 155 RK3399_TYPEC_PHY_USB3, 156 }; 157 158 static void 159 rk_typec_phy_set_usb2_only(struct rk_typec_phy_softc *sc, bool usb2only) 160 { 161 uint32_t reg; 162 163 /* Disable usb3tousb2 only */ 164 reg = SYSCON_READ_4(sc->grf, GRF_USB3PHY_CON0(sc->phy_ctrl_id)); 165 if (usb2only) 166 reg |= USB3PHY_CON0_USB2_ONLY; 167 else 168 reg &= ~USB3PHY_CON0_USB2_ONLY; 169 /* Write Mask */ 170 reg |= (USB3PHY_CON0_USB2_ONLY) << 16; 171 SYSCON_WRITE_4(sc->grf, GRF_USB3PHY_CON0(sc->phy_ctrl_id), reg); 172 173 /* Enable the USB3 Super Speed port */ 174 reg = SYSCON_READ_4(sc->grf, GRF_USB3OTG_CON1(sc->phy_ctrl_id)); 175 if (usb2only) 176 reg |= USB3OTG_CON1_U3_DIS; 177 else 178 reg &= ~USB3OTG_CON1_U3_DIS; 179 /* Write Mask */ 180 reg |= (USB3OTG_CON1_U3_DIS) << 16; 181 SYSCON_WRITE_4(sc->grf, GRF_USB3OTG_CON1(sc->phy_ctrl_id), reg); 182 } 183 184 static int 185 rk_typec_phy_enable(struct phynode *phynode, bool enable) 186 { 187 struct rk_typec_phy_softc *sc; 188 device_t dev; 189 intptr_t phy; 190 uint32_t reg; 191 int err, retry; 192 193 dev = phynode_get_device(phynode); 194 phy = phynode_get_id(phynode); 195 sc = device_get_softc(dev); 196 197 if (phy != RK3399_TYPEC_PHY_USB3) 198 return (ERANGE); 199 200 rk_typec_phy_set_usb2_only(sc, false); 201 202 err = clk_enable(sc->tcpdcore); 203 if (err != 0) { 204 device_printf(dev, "Could not enable clock %s\n", 205 clk_get_name(sc->tcpdcore)); 206 return (ENXIO); 207 } 208 err = clk_enable(sc->tcpdphy_ref); 209 if (err != 0) { 210 device_printf(dev, "Could not enable clock %s\n", 211 clk_get_name(sc->tcpdphy_ref)); 212 clk_disable(sc->tcpdcore); 213 return (ENXIO); 214 } 215 216 hwreset_deassert(sc->rst_tcphy); 217 218 /* 24M configuration, magic values from rockchip */ 219 RK_TYPEC_PHY_WRITE(sc, PMA_CMN_CTRL1, 0x830); 220 for (int i = 0; i < 4; i++) { 221 RK_TYPEC_PHY_WRITE(sc, XCVR_DIAG_LANE_FCM_EN_MGN(i), 0x90); 222 RK_TYPEC_PHY_WRITE(sc, TX_RCVDET_EN_TMR(i), 0x960); 223 RK_TYPEC_PHY_WRITE(sc, TX_RCVDET_ST_TMR(i), 0x30); 224 } 225 reg = RK_TYPEC_PHY_READ(sc, CMN_DIAG_HSCLK_SEL); 226 reg &= ~CMN_DIAG_HSCLK_SEL_PLL_MASK; 227 reg |= CMN_DIAG_HSCLK_SEL_PLL_CONFIG; 228 RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_HSCLK_SEL, reg); 229 230 /* PLL configuration, magic values from rockchip */ 231 RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_VCOCAL_INIT, 0xf0); 232 RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_VCOCAL_ITER, 0x18); 233 RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_INTDIV, 0xd0); 234 RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_FRACDIV, 0x4a4a); 235 RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_HIGH_THR, 0x34); 236 RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_SS_CTRL1, 0x1ee); 237 RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_SS_CTRL2, 0x7f03); 238 RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_DSM_DIAG, 0x20); 239 RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_OVRD, 0); 240 RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_FBH_OVRD, 0); 241 RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_FBL_OVRD, 0); 242 RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_V2I_TUNE, 0x7); 243 RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_CP_TUNE, 0x45); 244 RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_LF_PROG, 0x8); 245 246 /* Configure the TX and RX line, magic values from rockchip */ 247 RK_TYPEC_PHY_WRITE(sc, TX_PSC_A0(0), 0x7799); 248 RK_TYPEC_PHY_WRITE(sc, TX_PSC_A1(0), 0x7798); 249 RK_TYPEC_PHY_WRITE(sc, TX_PSC_A2(0), 0x5098); 250 RK_TYPEC_PHY_WRITE(sc, TX_PSC_A3(0), 0x5098); 251 RK_TYPEC_PHY_WRITE(sc, TX_TXCC_MGNFS_MULT_000(0), 0x0); 252 RK_TYPEC_PHY_WRITE(sc, XCVR_DIAG_BIDI_CTRL(0), 0xbf); 253 254 RK_TYPEC_PHY_WRITE(sc, RX_PSC_A0(1), 0xa6fd); 255 RK_TYPEC_PHY_WRITE(sc, RX_PSC_A1(1), 0xa6fd); 256 RK_TYPEC_PHY_WRITE(sc, RX_PSC_A2(1), 0xa410); 257 RK_TYPEC_PHY_WRITE(sc, RX_PSC_A3(1), 0x2410); 258 RK_TYPEC_PHY_WRITE(sc, RX_PSC_CAL(1), 0x23ff); 259 RK_TYPEC_PHY_WRITE(sc, RX_SIGDET_HL_FILT_TMR(1), 0x13); 260 RK_TYPEC_PHY_WRITE(sc, RX_REE_CTRL_DATA_MASK(1), 0x03e7); 261 RK_TYPEC_PHY_WRITE(sc, RX_DIAG_SIGDET_TUNE(1), 0x1004); 262 RK_TYPEC_PHY_WRITE(sc, RX_PSC_RDY(1), 0x2010); 263 RK_TYPEC_PHY_WRITE(sc, XCVR_DIAG_BIDI_CTRL(1), 0xfb); 264 265 RK_TYPEC_PHY_WRITE(sc, PMA_LANE_CFG, PIN_ASSIGN_D_F); 266 267 RK_TYPEC_PHY_WRITE(sc, DP_MODE_CTL, DP_MODE_ENTER_A2); 268 269 hwreset_deassert(sc->rst_uphy); 270 271 for (retry = 10000; retry > 0; retry--) { 272 reg = RK_TYPEC_PHY_READ(sc, PMA_CMN_CTRL1); 273 if (reg & PMA_CMN_CTRL1_READY) 274 break; 275 DELAY(10); 276 } 277 if (retry == 0) { 278 device_printf(sc->dev, "Timeout waiting for PMA\n"); 279 return (ENXIO); 280 } 281 282 hwreset_deassert(sc->rst_pipe); 283 284 return (0); 285 } 286 287 static int 288 rk_typec_phy_get_mode(struct phynode *phynode, int *mode) 289 { 290 struct rk_typec_phy_softc *sc; 291 intptr_t phy; 292 device_t dev; 293 294 dev = phynode_get_device(phynode); 295 phy = phynode_get_id(phynode); 296 sc = device_get_softc(dev); 297 298 if (phy != RK3399_TYPEC_PHY_USB3) 299 return (ERANGE); 300 301 *mode = sc->mode; 302 303 return (0); 304 } 305 306 static int 307 rk_typec_phy_set_mode(struct phynode *phynode, int mode) 308 { 309 struct rk_typec_phy_softc *sc; 310 intptr_t phy; 311 device_t dev; 312 313 dev = phynode_get_device(phynode); 314 phy = phynode_get_id(phynode); 315 sc = device_get_softc(dev); 316 317 if (phy != RK3399_TYPEC_PHY_USB3) 318 return (ERANGE); 319 320 sc->mode = mode; 321 322 return (0); 323 } 324 325 static int 326 rk_typec_phy_probe(device_t dev) 327 { 328 329 if (!ofw_bus_status_okay(dev)) 330 return (ENXIO); 331 332 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 333 return (ENXIO); 334 335 device_set_desc(dev, "Rockchip RK3399 PHY TYPEC"); 336 return (BUS_PROBE_DEFAULT); 337 } 338 339 static int 340 rk_typec_phy_attach(device_t dev) 341 { 342 struct rk_typec_phy_softc *sc; 343 struct phynode_init_def phy_init; 344 struct phynode *phynode; 345 phandle_t node, usb3; 346 phandle_t reg_prop[4]; 347 348 sc = device_get_softc(dev); 349 sc->dev = dev; 350 node = ofw_bus_get_node(dev); 351 352 /* 353 * Find out which phy we are. 354 * There is not property for this so we need to know the 355 * address to use the correct GRF registers. 356 */ 357 if (OF_getencprop(node, "reg", reg_prop, sizeof(reg_prop)) <= 0) { 358 device_printf(dev, "Cannot guess phy controller id\n"); 359 return (ENXIO); 360 } 361 switch (reg_prop[1]) { 362 case 0xff7c0000: 363 sc->phy_ctrl_id = 0; 364 break; 365 case 0xff800000: 366 sc->phy_ctrl_id = 1; 367 break; 368 default: 369 device_printf(dev, "Unknown address %x for typec-phy\n", reg_prop[1]); 370 return (ENXIO); 371 } 372 373 if (bus_alloc_resources(dev, rk_typec_phy_spec, &sc->res) != 0) { 374 device_printf(dev, "cannot allocate resources for device\n"); 375 goto fail; 376 } 377 378 if (syscon_get_by_ofw_property(dev, node, 379 "rockchip,grf", &sc->grf) != 0) { 380 device_printf(dev, "Cannot get syscon handle\n"); 381 goto fail; 382 } 383 384 if (clk_get_by_ofw_name(dev, 0, "tcpdcore", &sc->tcpdcore) != 0) { 385 device_printf(dev, "Cannot get tcpdcore clock\n"); 386 goto fail; 387 } 388 if (clk_get_by_ofw_name(dev, 0, "tcpdphy-ref", &sc->tcpdphy_ref) != 0) { 389 device_printf(dev, "Cannot get tcpdphy-ref clock\n"); 390 goto fail; 391 } 392 393 if (hwreset_get_by_ofw_name(dev, 0, "uphy", &sc->rst_uphy) != 0) { 394 device_printf(dev, "Cannot get uphy reset\n"); 395 goto fail; 396 } 397 if (hwreset_get_by_ofw_name(dev, 0, "uphy-pipe", &sc->rst_pipe) != 0) { 398 device_printf(dev, "Cannot get uphy-pipe reset\n"); 399 goto fail; 400 } 401 if (hwreset_get_by_ofw_name(dev, 0, "uphy-tcphy", &sc->rst_tcphy) != 0) { 402 device_printf(dev, "Cannot get uphy-tcphy reset\n"); 403 goto fail; 404 } 405 406 /* 407 * Make sure that the module is asserted 408 * We need to deassert in a certain order when we enable the phy 409 */ 410 hwreset_assert(sc->rst_uphy); 411 hwreset_assert(sc->rst_pipe); 412 hwreset_assert(sc->rst_tcphy); 413 414 /* Set the assigned clocks parent and freq */ 415 if (clk_set_assigned(dev, node) != 0) { 416 device_printf(dev, "clk_set_assigned failed\n"); 417 goto fail; 418 } 419 420 /* Only usb3 port is supported right now */ 421 usb3 = ofw_bus_find_child(node, "usb3-port"); 422 if (usb3 == 0) { 423 device_printf(dev, "Cannot find usb3-port child node\n"); 424 goto fail; 425 } 426 /* If the child isn't enable attach the driver 427 * but do not register the PHY. 428 */ 429 if (!ofw_bus_node_status_okay(usb3)) 430 return (0); 431 432 phy_init.id = RK3399_TYPEC_PHY_USB3; 433 phy_init.ofw_node = usb3; 434 phynode = phynode_create(dev, &rk_typec_phy_phynode_class, &phy_init); 435 if (phynode == NULL) { 436 device_printf(dev, "failed to create phy usb3-port\n"); 437 goto fail; 438 } 439 if (phynode_register(phynode) == NULL) { 440 device_printf(dev, "failed to register phy usb3-port\n"); 441 goto fail; 442 } 443 444 OF_device_register_xref(OF_xref_from_node(usb3), dev); 445 446 return (0); 447 448 fail: 449 bus_release_resources(dev, rk_typec_phy_spec, &sc->res); 450 451 return (ENXIO); 452 } 453 454 static device_method_t rk_typec_phy_methods[] = { 455 /* Device interface */ 456 DEVMETHOD(device_probe, rk_typec_phy_probe), 457 DEVMETHOD(device_attach, rk_typec_phy_attach), 458 459 DEVMETHOD_END 460 }; 461 462 static driver_t rk_typec_phy_driver = { 463 "rk_typec_phy", 464 rk_typec_phy_methods, 465 sizeof(struct rk_typec_phy_softc) 466 }; 467 468 EARLY_DRIVER_MODULE(rk_typec_phy, simplebus, rk_typec_phy_driver, 0, 0, 469 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE); 470 MODULE_VERSION(rk_typec_phy, 1); 471