1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/gpio.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/malloc.h> 36 #include <sys/rman.h> 37 38 #include <machine/bus.h> 39 40 #include <dev/extres/clk/clk.h> 41 #include <dev/extres/hwreset/hwreset.h> 42 #include <dev/extres/phy/phy_usb.h> 43 #include <dev/extres/regulator/regulator.h> 44 #include <dev/extres/syscon/syscon.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <dev/extres/syscon/syscon.h> 49 #include <dev/fdt/simple_mfd.h> 50 #include "phynode_if.h" 51 #include "phynode_usb_if.h" 52 #include "syscon_if.h" 53 54 55 56 /* Phy registers */ 57 #define UOC_CON0 0x00 58 #define UOC_CON0_SIDDQ (1 << 13) 59 #define UOC_CON0_DISABLE (1 << 4) 60 #define UOC_CON0_COMMON_ON_N (1 << 0) 61 62 #define UOC_CON2 0x08 63 #define UOC_CON2_SOFT_CON_SEL (1 << 2) 64 65 #define UOC_CON3 0x0c 66 67 68 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 69 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 70 71 72 static struct ofw_compat_data compat_data[] = { 73 {"rockchip,rk3288-usb-phy", 1}, 74 {NULL, 0}, 75 }; 76 77 struct rk_usbphy_softc { 78 device_t dev; 79 }; 80 81 struct rk_phynode_sc { 82 struct phynode_usb_sc usb_sc; 83 uint32_t base; 84 int mode; 85 clk_t clk; 86 hwreset_t hwreset; 87 regulator_t supply_vbus; 88 struct syscon *syscon; 89 }; 90 91 static int 92 rk_phynode_phy_enable(struct phynode *phy, bool enable) 93 { 94 struct rk_phynode_sc *sc; 95 int rv; 96 97 sc = phynode_get_softc(phy); 98 99 rv = SYSCON_MODIFY_4(sc->syscon, 100 sc->base + UOC_CON0, 101 UOC_CON0_SIDDQ << 16 | UOC_CON0_SIDDQ, 102 enable ? 0 : UOC_CON0_SIDDQ); 103 104 return (rv); 105 106 } 107 108 static int 109 rk_phynode_get_mode(struct phynode *phynode, int *mode) 110 { 111 struct rk_phynode_sc *sc; 112 113 sc = phynode_get_softc(phynode); 114 *mode = sc->mode; 115 return (0); 116 } 117 118 static int 119 rk_phynode_set_mode(struct phynode *phynode, int mode) 120 { 121 struct rk_phynode_sc *sc; 122 123 sc = phynode_get_softc(phynode); 124 sc->mode = mode; 125 126 return (0); 127 } 128 129 130 /* Phy controller class and methods. */ 131 static phynode_method_t rk_phynode_methods[] = { 132 PHYNODEUSBMETHOD(phynode_enable, rk_phynode_phy_enable), 133 PHYNODEMETHOD(phynode_usb_get_mode, rk_phynode_get_mode), 134 PHYNODEMETHOD(phynode_usb_set_mode, rk_phynode_set_mode), 135 PHYNODEUSBMETHOD_END 136 }; 137 DEFINE_CLASS_1(rk_phynode, rk_phynode_class, rk_phynode_methods, 138 sizeof(struct rk_phynode_sc), phynode_usb_class); 139 140 static int 141 rk_usbphy_init_phy(struct rk_usbphy_softc *sc, phandle_t node) 142 { 143 struct phynode *phynode; 144 struct phynode_init_def phy_init; 145 struct rk_phynode_sc *phy_sc; 146 int rv; 147 uint32_t base; 148 clk_t clk; 149 hwreset_t hwreset; 150 regulator_t supply_vbus; 151 struct syscon *syscon; 152 153 clk = NULL; 154 hwreset = NULL; 155 supply_vbus = NULL; 156 157 rv = OF_getencprop(node, "reg", &base, sizeof(base)); 158 if (rv <= 0) { 159 device_printf(sc->dev, "cannot get 'reg' property.\n"); 160 goto fail; 161 } 162 163 /* FDT resources. All are optional. */ 164 rv = clk_get_by_ofw_name(sc->dev, node, "phyclk", &clk); 165 if (rv != 0 && rv != ENOENT) { 166 device_printf(sc->dev, "cannot get 'phyclk' clock.\n"); 167 goto fail; 168 } 169 rv = hwreset_get_by_ofw_name(sc->dev, node, "phy-reset", &hwreset); 170 if (rv != 0 && rv != ENOENT) { 171 device_printf(sc->dev, "Cannot get 'phy-reset' reset\n"); 172 goto fail; 173 } 174 rv = regulator_get_by_ofw_property(sc->dev, node, "vbus-supply", 175 &supply_vbus); 176 if (rv != 0 && rv != ENOENT) { 177 device_printf(sc->dev, "Cannot get 'vbus' regulator.\n"); 178 goto fail; 179 } 180 181 rv = SYSCON_GET_HANDLE(sc->dev, &syscon); 182 if (rv != 0) { 183 device_printf(sc->dev, "Cannot get parent syscon\n"); 184 goto fail; 185 } 186 187 /* Init HW resources */ 188 if (hwreset != NULL) { 189 rv = hwreset_assert(hwreset); 190 if (rv != 0) { 191 device_printf(sc->dev, "Cannot assert reset\n"); 192 goto fail; 193 } 194 } 195 if (clk != NULL) { 196 rv = clk_enable(clk); 197 if (rv != 0) { 198 device_printf(sc->dev, 199 "Cannot enable 'phyclk' clock.\n"); 200 goto fail; 201 } 202 } 203 204 if (hwreset != NULL) { 205 rv = hwreset_deassert(hwreset); 206 if (rv != 0) { 207 device_printf(sc->dev, "Cannot deassert reset\n"); 208 goto fail; 209 } 210 } 211 212 /* Create and register phy. */ 213 bzero(&phy_init, sizeof(phy_init)); 214 phy_init.id = 1; 215 phy_init.ofw_node = node; 216 phynode = phynode_create(sc->dev, &rk_phynode_class, &phy_init); 217 if (phynode == NULL) { 218 device_printf(sc->dev, "Cannot create phy.\n"); 219 return (ENXIO); 220 } 221 222 phy_sc = phynode_get_softc(phynode); 223 phy_sc->base = base; 224 phy_sc->clk = clk; 225 phy_sc->hwreset = hwreset; 226 phy_sc->supply_vbus = supply_vbus; 227 phy_sc->syscon = syscon; 228 if (phynode_register(phynode) == NULL) { 229 device_printf(sc->dev, "Cannot register phy.\n"); 230 return (ENXIO); 231 } 232 /* XXX It breaks boot */ 233 /* rk_phynode_phy_enable(phynode, 1); */ 234 return (0); 235 236 fail: 237 if (supply_vbus != NULL) 238 regulator_release(supply_vbus); 239 if (clk != NULL) 240 clk_release(clk); 241 if (hwreset != NULL) 242 hwreset_release(hwreset); 243 244 return (ENXIO); 245 } 246 247 static int 248 rk_usbphy_probe(device_t dev) 249 { 250 251 if (!ofw_bus_status_okay(dev)) 252 return (ENXIO); 253 254 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 255 return (ENXIO); 256 257 device_set_desc(dev, "RockChip USB Phy"); 258 return (BUS_PROBE_DEFAULT); 259 } 260 261 static int 262 rk_usbphy_attach(device_t dev) 263 { 264 struct rk_usbphy_softc *sc; 265 phandle_t node, child; 266 int rv; 267 268 sc = device_get_softc(dev); 269 sc->dev = dev; 270 node = ofw_bus_get_node(sc->dev); 271 272 /* Attach child devices */ 273 for (child = OF_child(node); child > 0; child = OF_peer(child)) { 274 rv = rk_usbphy_init_phy(sc, child); 275 if (rv != 0) 276 goto fail; 277 } 278 return (bus_generic_attach(dev)); 279 280 fail: 281 return (ENXIO); 282 } 283 284 static int 285 rk_usbphy_detach(device_t dev) 286 { 287 return (0); 288 } 289 290 static device_method_t rk_usbphy_methods[] = { 291 /* Device interface */ 292 DEVMETHOD(device_probe, rk_usbphy_probe), 293 DEVMETHOD(device_attach, rk_usbphy_attach), 294 DEVMETHOD(device_detach, rk_usbphy_detach), 295 DEVMETHOD_END 296 }; 297 298 static DEFINE_CLASS_0(rk_usbphy, rk_usbphy_driver, rk_usbphy_methods, 299 sizeof(struct rk_usbphy_softc)); 300 EARLY_DRIVER_MODULE(rk_usbphy, simplebus, rk_usbphy_driver, NULL, NULL, 301 BUS_PASS_TIMER + BUS_PASS_ORDER_LAST); 302