1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2015 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_IO_H_ 32 #define _LINUX_IO_H_ 33 34 #include <machine/vm.h> 35 #include <sys/endian.h> 36 #include <sys/types.h> 37 38 #include <linux/compiler.h> 39 #include <linux/types.h> 40 41 static inline uint32_t 42 __raw_readl(const volatile void *addr) 43 { 44 return *(const volatile uint32_t *)addr; 45 } 46 47 static inline void 48 __raw_writel(uint32_t b, volatile void *addr) 49 { 50 *(volatile uint32_t *)addr = b; 51 } 52 53 static inline uint64_t 54 __raw_readq(const volatile void *addr) 55 { 56 return *(const volatile uint64_t *)addr; 57 } 58 59 static inline void 60 __raw_writeq(uint64_t b, volatile void *addr) 61 { 62 *(volatile uint64_t *)addr = b; 63 } 64 65 /* 66 * XXX This is all x86 specific. It should be bus space access. 67 */ 68 #define mmiowb() barrier() 69 70 #undef writel 71 static inline void 72 writel(uint32_t b, void *addr) 73 { 74 *(volatile uint32_t *)addr = b; 75 } 76 77 #undef writeq 78 static inline void 79 writeq(uint64_t b, void *addr) 80 { 81 *(volatile uint64_t *)addr = b; 82 } 83 84 #undef writeb 85 static inline void 86 writeb(uint8_t b, void *addr) 87 { 88 *(volatile uint8_t *)addr = b; 89 } 90 91 #undef writew 92 static inline void 93 writew(uint16_t b, void *addr) 94 { 95 *(volatile uint16_t *)addr = b; 96 } 97 98 #undef ioread8 99 static inline uint8_t 100 ioread8(const volatile void *addr) 101 { 102 return *(const volatile uint8_t *)addr; 103 } 104 105 #undef ioread16 106 static inline uint16_t 107 ioread16(const volatile void *addr) 108 { 109 return *(const volatile uint16_t *)addr; 110 } 111 112 #undef ioread16be 113 static inline uint16_t 114 ioread16be(const volatile void *addr) 115 { 116 return be16toh(*(const volatile uint16_t *)addr); 117 } 118 119 #undef ioread32 120 static inline uint32_t 121 ioread32(const volatile void *addr) 122 { 123 return *(const volatile uint32_t *)addr; 124 } 125 126 #undef ioread32be 127 static inline uint32_t 128 ioread32be(const volatile void *addr) 129 { 130 return be32toh(*(const volatile uint32_t *)addr); 131 } 132 133 #undef iowrite8 134 static inline void 135 iowrite8(uint8_t v, volatile void *addr) 136 { 137 *(volatile uint8_t *)addr = v; 138 } 139 140 #undef iowrite16 141 static inline void 142 iowrite16(uint16_t v, volatile void *addr) 143 { 144 *(volatile uint16_t *)addr = v; 145 } 146 147 #undef iowrite32 148 static inline void 149 iowrite32(uint32_t v, volatile void *addr) 150 { 151 *(volatile uint32_t *)addr = v; 152 } 153 154 #undef iowrite32be 155 static inline void 156 iowrite32be(uint32_t v, volatile void *addr) 157 { 158 *(volatile uint32_t *)addr = htobe32(v); 159 } 160 161 #undef readb 162 static inline uint8_t 163 readb(const volatile void *addr) 164 { 165 return *(const volatile uint8_t *)addr; 166 } 167 168 #undef readw 169 static inline uint16_t 170 readw(const volatile void *addr) 171 { 172 return *(const volatile uint16_t *)addr; 173 } 174 175 #undef readl 176 static inline uint32_t 177 readl(const volatile void *addr) 178 { 179 return *(const volatile uint32_t *)addr; 180 } 181 182 #if defined(__i386__) || defined(__amd64__) 183 static inline void 184 _outb(u_char data, u_int port) 185 { 186 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port)); 187 } 188 #endif 189 190 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 191 void *_ioremap_attr(vm_paddr_t phys_addr, unsigned long size, int attr); 192 #else 193 #define _ioremap_attr(...) NULL 194 #endif 195 196 #define ioremap_nocache(addr, size) \ 197 _ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE) 198 #define ioremap_wc(addr, size) \ 199 _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_COMBINING) 200 #define ioremap_wb(addr, size) \ 201 _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_BACK) 202 #define ioremap_wt(addr, size) \ 203 _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_THROUGH) 204 #define ioremap(addr, size) \ 205 _ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE) 206 void iounmap(void *addr); 207 208 #define memset_io(a, b, c) memset((a), (b), (c)) 209 #define memcpy_fromio(a, b, c) memcpy((a), (b), (c)) 210 #define memcpy_toio(a, b, c) memcpy((a), (b), (c)) 211 212 static inline void 213 __iowrite32_copy(void *to, void *from, size_t count) 214 { 215 uint32_t *src; 216 uint32_t *dst; 217 int i; 218 219 for (i = 0, src = from, dst = to; i < count; i++, src++, dst++) 220 __raw_writel(*src, dst); 221 } 222 223 static inline void 224 __iowrite64_copy(void *to, void *from, size_t count) 225 { 226 #ifdef __LP64__ 227 uint64_t *src; 228 uint64_t *dst; 229 int i; 230 231 for (i = 0, src = from, dst = to; i < count; i++, src++, dst++) 232 __raw_writeq(*src, dst); 233 #else 234 __iowrite32_copy(to, from, count * 2); 235 #endif 236 } 237 238 enum { 239 MEMREMAP_WB = 1 << 0, 240 MEMREMAP_WT = 1 << 1, 241 MEMREMAP_WC = 1 << 2, 242 }; 243 244 static inline void * 245 memremap(resource_size_t offset, size_t size, unsigned long flags) 246 { 247 void *addr = NULL; 248 249 if ((flags & MEMREMAP_WB) && 250 (addr = ioremap_wb(offset, size)) != NULL) 251 goto done; 252 if ((flags & MEMREMAP_WT) && 253 (addr = ioremap_wt(offset, size)) != NULL) 254 goto done; 255 if ((flags & MEMREMAP_WC) && 256 (addr = ioremap_wc(offset, size)) != NULL) 257 goto done; 258 done: 259 return (addr); 260 } 261 262 static inline void 263 memunmap(void *addr) 264 { 265 /* XXX May need to check if this is RAM */ 266 iounmap(addr); 267 } 268 269 #endif /* _LINUX_IO_H_ */ 270