1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013, 2014 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_IO_H_ 32 #define _LINUX_IO_H_ 33 34 #include <machine/vm.h> 35 #include <sys/endian.h> 36 #include <sys/types.h> 37 38 static inline uint32_t 39 __raw_readl(const volatile void *addr) 40 { 41 return *(const volatile uint32_t *)addr; 42 } 43 44 static inline void 45 __raw_writel(uint32_t b, volatile void *addr) 46 { 47 *(volatile uint32_t *)addr = b; 48 } 49 50 static inline uint64_t 51 __raw_readq(const volatile void *addr) 52 { 53 return *(const volatile uint64_t *)addr; 54 } 55 56 static inline void 57 __raw_writeq(uint64_t b, volatile void *addr) 58 { 59 *(volatile uint64_t *)addr = b; 60 } 61 62 /* 63 * XXX This is all x86 specific. It should be bus space access. 64 */ 65 #define mmiowb() 66 67 #undef writel 68 static inline void 69 writel(uint32_t b, void *addr) 70 { 71 *(volatile uint32_t *)addr = b; 72 } 73 74 #undef writeq 75 static inline void 76 writeq(uint64_t b, void *addr) 77 { 78 *(volatile uint64_t *)addr = b; 79 } 80 81 #undef writeb 82 static inline void 83 writeb(uint8_t b, void *addr) 84 { 85 *(volatile uint8_t *)addr = b; 86 } 87 88 #undef writew 89 static inline void 90 writew(uint16_t b, void *addr) 91 { 92 *(volatile uint16_t *)addr = b; 93 } 94 95 #undef ioread32be 96 static inline uint32_t 97 ioread32be(const volatile void *addr) 98 { 99 return be32toh(*(const volatile uint32_t *)addr); 100 } 101 102 #undef iowrite32be 103 static inline void 104 iowrite32be(uint32_t v, volatile void *addr) 105 { 106 *(volatile uint32_t *)addr = htobe32(v); 107 } 108 109 void *_ioremap_attr(vm_paddr_t phys_addr, unsigned long size, int attr); 110 #define ioremap_nocache(addr, size) \ 111 _ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE) 112 #define ioremap_wc(addr, size) \ 113 _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_COMBINING) 114 #define ioremap ioremap_nocache 115 void iounmap(void *addr); 116 117 #define memset_io(a, b, c) memset((a), (b), (c)) 118 #define memcpy_fromio(a, b, c) memcpy((a), (b), (c)) 119 #define memcpy_toio(a, b, c) memcpy((a), (b), (c)) 120 121 static inline void 122 __iowrite64_copy(void *to, void *from, size_t count) 123 { 124 #ifdef __LP64__ 125 uint64_t *src; 126 uint64_t *dst; 127 int i; 128 129 for (i = 0, src = from, dst = to; i < count; i++, src++, dst++) 130 __raw_writeq(*src, dst); 131 #else 132 uint32_t *src; 133 uint32_t *dst; 134 int i; 135 136 count *= 2; 137 for (i = 0, src = from, dst = to; i < count; i++, src++, dst++) 138 __raw_writel(*src, dst); 139 #endif 140 } 141 142 143 #endif /* _LINUX_IO_H_ */ 144