1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/nv.h> 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <asm/memtype.h> 61 #include <linux/device.h> 62 #include <linux/pci_ids.h> 63 #include <linux/pm.h> 64 65 struct pci_device_id { 66 uint32_t vendor; 67 uint32_t device; 68 uint32_t subvendor; 69 uint32_t subdevice; 70 uint32_t class; 71 uint32_t class_mask; 72 uintptr_t driver_data; 73 }; 74 75 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 76 #define MODULE_DEVICE_TABLE(_bus, _table) \ 77 \ 78 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 79 DEVMETHOD_END \ 80 }; \ 81 \ 82 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 83 "lkpi_" #_bus #_table, \ 84 _ ## _bus ## _ ## _table ## _methods, \ 85 0 \ 86 }; \ 87 \ 88 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 89 0, 0); \ 90 \ 91 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 92 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 93 94 #define PCI_ANY_ID -1U 95 96 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 97 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 98 #define PCI_FUNC(devfn) ((devfn) & 0x07) 99 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 100 101 #define PCI_VDEVICE(_vendor, _device) \ 102 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 103 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 104 #define PCI_DEVICE(_vendor, _device) \ 105 .vendor = (_vendor), .device = (_device), \ 106 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 107 108 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 109 110 #define PCI_STD_NUM_BARS 6 111 #define PCI_VENDOR_ID PCIR_VENDOR 112 #define PCI_DEVICE_ID PCIR_DEVICE 113 #define PCI_COMMAND PCIR_COMMAND 114 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 115 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 116 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 117 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 118 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 119 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 120 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 121 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 122 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 123 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 124 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 125 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 126 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 127 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 128 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 129 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 130 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 131 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 132 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 133 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 134 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 135 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 136 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 137 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 138 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 139 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 140 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 141 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 142 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 143 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 144 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 145 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 146 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 147 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 148 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 149 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 150 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 151 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 152 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 153 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 154 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 155 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 156 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 157 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 158 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 159 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 160 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 161 #define PCI_EXP_LNKCTL2_TLS 0x000f 162 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 163 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 164 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 165 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 166 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 167 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 168 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 169 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 170 171 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 172 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 173 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 174 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 175 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 176 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 177 178 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 179 #define PCI_EXP_DEVSTA_TRPND 0x0020 180 181 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 182 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 183 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 184 185 enum pci_bus_speed { 186 PCI_SPEED_UNKNOWN = -1, 187 PCIE_SPEED_2_5GT, 188 PCIE_SPEED_5_0GT, 189 PCIE_SPEED_8_0GT, 190 PCIE_SPEED_16_0GT, 191 PCIE_SPEED_32_0GT, 192 PCIE_SPEED_64_0GT, 193 }; 194 195 enum pcie_link_width { 196 PCIE_LNK_WIDTH_RESRV = 0x00, 197 PCIE_LNK_X1 = 0x01, 198 PCIE_LNK_X2 = 0x02, 199 PCIE_LNK_X4 = 0x04, 200 PCIE_LNK_X8 = 0x08, 201 PCIE_LNK_X12 = 0x0c, 202 PCIE_LNK_X16 = 0x10, 203 PCIE_LNK_X32 = 0x20, 204 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 205 }; 206 207 #define PCIE_LINK_STATE_L0S 0x00000001 208 #define PCIE_LINK_STATE_L1 0x00000002 209 #define PCIE_LINK_STATE_CLKPM 0x00000004 210 211 typedef int pci_power_t; 212 213 #define PCI_D0 PCI_POWERSTATE_D0 214 #define PCI_D1 PCI_POWERSTATE_D1 215 #define PCI_D2 PCI_POWERSTATE_D2 216 #define PCI_D3hot PCI_POWERSTATE_D3 217 #define PCI_D3cold 4 218 219 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 220 221 extern const char *pci_power_names[6]; 222 223 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 224 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 225 226 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 227 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 228 229 #define PCI_L1SS_CTL1 0x8 230 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 231 232 #define PCI_IRQ_LEGACY 0x01 233 #define PCI_IRQ_MSI 0x02 234 #define PCI_IRQ_MSIX 0x04 235 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 236 237 struct pci_dev; 238 239 struct pci_driver { 240 struct list_head node; 241 char *name; 242 const struct pci_device_id *id_table; 243 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 244 void (*remove)(struct pci_dev *dev); 245 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 246 int (*resume) (struct pci_dev *dev); /* Device woken up */ 247 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 248 driver_t bsddriver; 249 devclass_t bsdclass; 250 struct device_driver driver; 251 const struct pci_error_handlers *err_handler; 252 bool isdrm; 253 int bsd_probe_return; 254 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 255 const nvlist_t *pf_config); 256 void (*bsd_iov_uninit)(device_t dev); 257 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 258 const nvlist_t *vf_config); 259 }; 260 261 struct pci_bus { 262 struct pci_dev *self; 263 int domain; 264 int number; 265 }; 266 267 extern struct list_head pci_drivers; 268 extern struct list_head pci_devices; 269 extern spinlock_t pci_lock; 270 271 #define __devexit_p(x) x 272 273 #define module_pci_driver(_driver) \ 274 \ 275 static inline int \ 276 _pci_init(void) \ 277 { \ 278 \ 279 return (linux_pci_register_driver(&_driver)); \ 280 } \ 281 \ 282 static inline void \ 283 _pci_exit(void) \ 284 { \ 285 \ 286 linux_pci_unregister_driver(&_driver); \ 287 } \ 288 \ 289 module_init(_pci_init); \ 290 module_exit(_pci_exit) 291 292 struct msi_msg { 293 uint32_t data; 294 }; 295 296 struct msi_desc { 297 struct msi_msg msg; 298 struct { 299 bool is_64; 300 } msi_attrib; 301 }; 302 303 /* 304 * If we find drivers accessing this from multiple KPIs we may have to 305 * refcount objects of this structure. 306 */ 307 struct pci_mmio_region { 308 TAILQ_ENTRY(pci_mmio_region) next; 309 struct resource *res; 310 int rid; 311 int type; 312 }; 313 314 struct pci_dev { 315 struct device dev; 316 struct list_head links; 317 struct pci_driver *pdrv; 318 struct pci_bus *bus; 319 struct pci_dev *root; 320 pci_power_t current_state; 321 uint16_t device; 322 uint16_t vendor; 323 uint16_t subsystem_vendor; 324 uint16_t subsystem_device; 325 unsigned int irq; 326 unsigned int devfn; 327 uint32_t class; 328 uint8_t revision; 329 uint8_t msi_cap; 330 uint8_t msix_cap; 331 bool managed; /* devres "pcim_*(). */ 332 bool want_iomap_res; 333 bool msi_enabled; 334 bool msix_enabled; 335 phys_addr_t rom; 336 size_t romlen; 337 struct msi_desc **msi_desc; 338 char *path_name; 339 340 TAILQ_HEAD(, pci_mmio_region) mmio; 341 }; 342 343 /* We need some meta-struct to keep track of these for devres. */ 344 struct pci_devres { 345 bool enable_io; 346 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 347 uint8_t region_mask; 348 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 349 }; 350 struct pcim_iomap_devres { 351 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 352 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 353 }; 354 355 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 356 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 357 unsigned int flags); 358 bool pci_device_is_present(struct pci_dev *pdev); 359 360 /* Internal helper function(s). */ 361 struct pci_dev *lkpinew_pci_dev(device_t); 362 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev); 363 void lkpi_pci_devres_release(struct device *, void *); 364 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size); 365 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev); 366 void lkpi_pcim_iomap_table_release(struct device *, void *); 367 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 368 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 369 370 static inline bool 371 dev_is_pci(struct device *dev) 372 { 373 374 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 375 } 376 377 static inline int 378 pci_resource_type(struct pci_dev *pdev, int bar) 379 { 380 struct pci_map *pm; 381 382 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 383 if (!pm) 384 return (-1); 385 386 if (PCI_BAR_IO(pm->pm_value)) 387 return (SYS_RES_IOPORT); 388 else 389 return (SYS_RES_MEMORY); 390 } 391 392 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 393 struct resource_list *rl, int type, int rid); 394 395 static inline struct resource_list_entry * 396 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 397 { 398 struct pci_devinfo *dinfo; 399 struct resource_list *rl; 400 struct resource_list_entry *rle; 401 402 dinfo = device_get_ivars(pdev->dev.bsddev); 403 rl = &dinfo->resources; 404 rle = resource_list_find(rl, type, rid); 405 /* Reserve resources for this BAR if needed. */ 406 if (rle == NULL && reserve_bar) 407 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 408 return (rle); 409 } 410 411 static inline struct resource_list_entry * 412 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 413 { 414 int type; 415 416 type = pci_resource_type(pdev, bar); 417 if (type < 0) 418 return (NULL); 419 bar = PCIR_BAR(bar); 420 return (linux_pci_get_rle(pdev, type, bar, reserve)); 421 } 422 423 static inline struct device * 424 linux_pci_find_irq_dev(unsigned int irq) 425 { 426 struct pci_dev *pdev; 427 struct device *found; 428 429 found = NULL; 430 spin_lock(&pci_lock); 431 list_for_each_entry(pdev, &pci_devices, links) { 432 if (irq == pdev->dev.irq || 433 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 434 found = &pdev->dev; 435 break; 436 } 437 } 438 spin_unlock(&pci_lock); 439 return (found); 440 } 441 442 /* 443 * All drivers just seem to want to inspect the type not flags. 444 */ 445 static inline int 446 pci_resource_flags(struct pci_dev *pdev, int bar) 447 { 448 int type; 449 450 type = pci_resource_type(pdev, bar); 451 if (type < 0) 452 return (0); 453 return (1 << type); 454 } 455 456 static inline const char * 457 pci_name(struct pci_dev *d) 458 { 459 return d->path_name; 460 } 461 462 static inline void * 463 pci_get_drvdata(struct pci_dev *pdev) 464 { 465 466 return dev_get_drvdata(&pdev->dev); 467 } 468 469 static inline void 470 pci_set_drvdata(struct pci_dev *pdev, void *data) 471 { 472 473 dev_set_drvdata(&pdev->dev, data); 474 } 475 476 static inline struct pci_dev * 477 pci_dev_get(struct pci_dev *pdev) 478 { 479 480 if (pdev != NULL) 481 get_device(&pdev->dev); 482 return (pdev); 483 } 484 485 static __inline void 486 pci_dev_put(struct pci_dev *pdev) 487 { 488 489 if (pdev != NULL) 490 put_device(&pdev->dev); 491 } 492 493 static inline int 494 pci_enable_device(struct pci_dev *pdev) 495 { 496 497 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 498 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 499 return (0); 500 } 501 502 static inline void 503 pci_disable_device(struct pci_dev *pdev) 504 { 505 506 pci_disable_busmaster(pdev->dev.bsddev); 507 } 508 509 static inline int 510 pci_set_master(struct pci_dev *pdev) 511 { 512 513 pci_enable_busmaster(pdev->dev.bsddev); 514 return (0); 515 } 516 517 static inline int 518 pci_set_power_state(struct pci_dev *pdev, int state) 519 { 520 521 pci_set_powerstate(pdev->dev.bsddev, state); 522 return (0); 523 } 524 525 static inline int 526 pci_clear_master(struct pci_dev *pdev) 527 { 528 529 pci_disable_busmaster(pdev->dev.bsddev); 530 return (0); 531 } 532 533 static inline bool 534 pci_is_root_bus(struct pci_bus *pbus) 535 { 536 537 return (pbus->self == NULL); 538 } 539 540 static inline struct pci_dev * 541 pci_upstream_bridge(struct pci_dev *pdev) 542 { 543 544 if (pci_is_root_bus(pdev->bus)) 545 return (NULL); 546 547 /* 548 * If we do not have a (proper) "upstream bridge" set, e.g., we point 549 * to ourselves, try to handle this case on the fly like we do 550 * for pcie_find_root_port(). 551 */ 552 if (pdev == pdev->bus->self) { 553 device_t bridge; 554 555 bridge = device_get_parent(pdev->dev.bsddev); 556 if (bridge == NULL) 557 goto done; 558 bridge = device_get_parent(bridge); 559 if (bridge == NULL) 560 goto done; 561 if (device_get_devclass(device_get_parent(bridge)) != 562 devclass_find("pci")) 563 goto done; 564 565 /* 566 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 567 * for it so it can be returned. 568 */ 569 pdev->bus->self = lkpinew_pci_dev(bridge); 570 } 571 done: 572 return (pdev->bus->self); 573 } 574 575 static inline struct pci_devres * 576 lkpi_pci_devres_find(struct pci_dev *pdev) 577 { 578 579 if (!pdev->managed) 580 return (NULL); 581 582 return (lkpi_pci_devres_get_alloc(pdev)); 583 } 584 585 static inline void 586 pci_release_region(struct pci_dev *pdev, int bar) 587 { 588 struct resource_list_entry *rle; 589 struct pci_devres *dr; 590 struct pci_mmio_region *mmio, *p; 591 592 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 593 return; 594 595 /* 596 * As we implicitly track the requests we also need to clear them on 597 * release. Do clear before resource release. 598 */ 599 dr = lkpi_pci_devres_find(pdev); 600 if (dr != NULL) { 601 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 602 " region_table res %p != rel->res %p\n", __func__, pdev, 603 bar, dr->region_table[bar], rle->res)); 604 dr->region_table[bar] = NULL; 605 dr->region_mask &= ~(1 << bar); 606 } 607 608 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 609 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 610 continue; 611 TAILQ_REMOVE(&pdev->mmio, mmio, next); 612 free(mmio, M_DEVBUF); 613 } 614 615 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 616 } 617 618 static inline void 619 pci_release_regions(struct pci_dev *pdev) 620 { 621 int i; 622 623 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 624 pci_release_region(pdev, i); 625 } 626 627 static inline int 628 pci_request_regions(struct pci_dev *pdev, const char *res_name) 629 { 630 int error; 631 int i; 632 633 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 634 error = pci_request_region(pdev, i, res_name); 635 if (error && error != -ENODEV) { 636 pci_release_regions(pdev); 637 return (error); 638 } 639 } 640 return (0); 641 } 642 643 static inline void 644 lkpi_pci_disable_msix(struct pci_dev *pdev) 645 { 646 647 pci_release_msi(pdev->dev.bsddev); 648 649 /* 650 * The MSIX IRQ numbers associated with this PCI device are no 651 * longer valid and might be re-assigned. Make sure 652 * linux_pci_find_irq_dev() does no longer see them by 653 * resetting their references to zero: 654 */ 655 pdev->dev.irq_start = 0; 656 pdev->dev.irq_end = 0; 657 pdev->msix_enabled = false; 658 } 659 /* Only for consistency. No conflict on that one. */ 660 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 661 662 static inline void 663 lkpi_pci_disable_msi(struct pci_dev *pdev) 664 { 665 666 pci_release_msi(pdev->dev.bsddev); 667 668 pdev->dev.irq_start = 0; 669 pdev->dev.irq_end = 0; 670 pdev->irq = pdev->dev.irq; 671 pdev->msi_enabled = false; 672 } 673 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 674 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 675 676 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 677 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 678 679 static inline bus_addr_t 680 pci_bus_address(struct pci_dev *pdev, int bar) 681 { 682 683 return (pci_resource_start(pdev, bar)); 684 } 685 686 #define PCI_CAP_ID_EXP PCIY_EXPRESS 687 #define PCI_CAP_ID_PCIX PCIY_PCIX 688 #define PCI_CAP_ID_AGP PCIY_AGP 689 #define PCI_CAP_ID_PM PCIY_PMG 690 691 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 692 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 693 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 694 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 695 #define PCI_EXP_LNKSTA PCIER_LINK_STA 696 697 static inline int 698 pci_find_capability(struct pci_dev *pdev, int capid) 699 { 700 int reg; 701 702 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 703 return (0); 704 return (reg); 705 } 706 707 static inline int pci_pcie_cap(struct pci_dev *dev) 708 { 709 return pci_find_capability(dev, PCI_CAP_ID_EXP); 710 } 711 712 static inline int 713 pci_find_ext_capability(struct pci_dev *pdev, int capid) 714 { 715 int reg; 716 717 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 718 return (0); 719 return (reg); 720 } 721 722 #define PCIM_PCAP_PME_SHIFT 11 723 static __inline bool 724 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 725 { 726 struct pci_devinfo *dinfo; 727 pcicfgregs *cfg; 728 729 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 730 return (false); 731 732 dinfo = device_get_ivars(pdev->dev.bsddev); 733 cfg = &dinfo->cfg; 734 735 if (cfg->pp.pp_cap == 0) 736 return (false); 737 738 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 739 return (true); 740 741 return (false); 742 } 743 744 static inline int 745 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 746 { 747 748 if (!pci_enable_aspm) 749 return (-EPERM); 750 751 return (-ENXIO); 752 } 753 754 static inline int 755 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 756 { 757 758 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 759 return (0); 760 } 761 762 static inline int 763 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 764 { 765 766 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 767 return (0); 768 } 769 770 static inline int 771 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 772 { 773 774 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 775 return (0); 776 } 777 778 static inline int 779 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 780 { 781 782 pci_write_config(pdev->dev.bsddev, where, val, 1); 783 return (0); 784 } 785 786 static inline int 787 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 788 { 789 790 pci_write_config(pdev->dev.bsddev, where, val, 2); 791 return (0); 792 } 793 794 static inline int 795 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 796 { 797 798 pci_write_config(pdev->dev.bsddev, where, val, 4); 799 return (0); 800 } 801 802 int linux_pci_register_driver(struct pci_driver *pdrv); 803 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 804 void linux_pci_unregister_driver(struct pci_driver *pdrv); 805 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 806 807 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 808 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 809 810 struct msix_entry { 811 int entry; 812 int vector; 813 }; 814 815 /* 816 * Enable msix, positive errors indicate actual number of available 817 * vectors. Negative errors are failures. 818 * 819 * NB: define added to prevent this definition of pci_enable_msix from 820 * clashing with the native FreeBSD version. 821 */ 822 #define pci_enable_msix(...) \ 823 linux_pci_enable_msix(__VA_ARGS__) 824 825 static inline int 826 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 827 { 828 struct resource_list_entry *rle; 829 int error; 830 int avail; 831 int i; 832 833 avail = pci_msix_count(pdev->dev.bsddev); 834 if (avail < nreq) { 835 if (avail == 0) 836 return -EINVAL; 837 return avail; 838 } 839 avail = nreq; 840 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 841 return error; 842 /* 843 * Handle case where "pci_alloc_msix()" may allocate less 844 * interrupts than available and return with no error: 845 */ 846 if (avail < nreq) { 847 pci_release_msi(pdev->dev.bsddev); 848 return avail; 849 } 850 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 851 pdev->dev.irq_start = rle->start; 852 pdev->dev.irq_end = rle->start + avail; 853 for (i = 0; i < nreq; i++) 854 entries[i].vector = pdev->dev.irq_start + i; 855 pdev->msix_enabled = true; 856 return (0); 857 } 858 859 #define pci_enable_msix_range(...) \ 860 linux_pci_enable_msix_range(__VA_ARGS__) 861 862 static inline int 863 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 864 int minvec, int maxvec) 865 { 866 int nvec = maxvec; 867 int rc; 868 869 if (maxvec < minvec) 870 return (-ERANGE); 871 872 do { 873 rc = pci_enable_msix(dev, entries, nvec); 874 if (rc < 0) { 875 return (rc); 876 } else if (rc > 0) { 877 if (rc < minvec) 878 return (-ENOSPC); 879 nvec = rc; 880 } 881 } while (rc); 882 return (nvec); 883 } 884 885 #define pci_enable_msi(pdev) \ 886 linux_pci_enable_msi(pdev) 887 888 static inline int 889 _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec) 890 { 891 struct resource_list_entry *rle; 892 int error; 893 int nvec; 894 895 if (maxvec < minvec) 896 return (-EINVAL); 897 898 nvec = pci_msi_count(pdev->dev.bsddev); 899 if (nvec < 1 || nvec < minvec) 900 return (-ENOSPC); 901 902 nvec = min(nvec, maxvec); 903 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &nvec)) != 0) 904 return error; 905 906 /* Native PCI might only ever ask for 32 vectors. */ 907 if (nvec < minvec) { 908 pci_release_msi(pdev->dev.bsddev); 909 return (-ENOSPC); 910 } 911 912 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 913 pdev->dev.irq_start = rle->start; 914 pdev->dev.irq_end = rle->start + nvec; 915 pdev->irq = rle->start; 916 pdev->msi_enabled = true; 917 return (0); 918 } 919 920 static inline int 921 pci_enable_msi(struct pci_dev *pdev) 922 { 923 924 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 925 } 926 927 static inline int 928 pci_channel_offline(struct pci_dev *pdev) 929 { 930 931 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 932 } 933 934 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 935 { 936 return -ENODEV; 937 } 938 939 static inline void pci_disable_sriov(struct pci_dev *dev) 940 { 941 } 942 943 static inline void * 944 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 945 { 946 struct resource *res; 947 948 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 949 if (res == NULL) 950 return (NULL); 951 /* This is a FreeBSD extension so we can use bus_*(). */ 952 if (pdev->want_iomap_res) 953 return (res); 954 return ((void *)rman_get_bushandle(res)); 955 } 956 957 static inline void 958 pci_iounmap(struct pci_dev *pdev, void *res) 959 { 960 struct pci_mmio_region *mmio, *p; 961 962 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 963 if (res != (void *)rman_get_bushandle(mmio->res)) 964 continue; 965 bus_release_resource(pdev->dev.bsddev, 966 mmio->type, mmio->rid, mmio->res); 967 TAILQ_REMOVE(&pdev->mmio, mmio, next); 968 free(mmio, M_DEVBUF); 969 return; 970 } 971 } 972 973 static inline void 974 lkpi_pci_save_state(struct pci_dev *pdev) 975 { 976 977 pci_save_state(pdev->dev.bsddev); 978 } 979 980 static inline void 981 lkpi_pci_restore_state(struct pci_dev *pdev) 982 { 983 984 pci_restore_state(pdev->dev.bsddev); 985 } 986 987 #define pci_save_state(dev) lkpi_pci_save_state(dev) 988 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 989 990 static inline int 991 pci_reset_function(struct pci_dev *pdev) 992 { 993 994 return (-ENOSYS); 995 } 996 997 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 998 const struct pci_device_id _table[] __devinitdata 999 1000 /* XXX This should not be necessary. */ 1001 #define pcix_set_mmrbc(d, v) 0 1002 #define pcix_get_max_mmrbc(d) 0 1003 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 1004 1005 #define PCI_DMA_BIDIRECTIONAL 0 1006 #define PCI_DMA_TODEVICE 1 1007 #define PCI_DMA_FROMDEVICE 2 1008 #define PCI_DMA_NONE 3 1009 1010 #define pci_pool dma_pool 1011 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 1012 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 1013 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 1014 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 1015 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 1016 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 1017 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1018 _size, _vaddr, _dma_handle) 1019 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 1020 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1021 _sg, _nents, (enum dma_data_direction)_dir) 1022 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 1023 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1024 (_ptr), (_size), (enum dma_data_direction)_dir) 1025 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 1026 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1027 _addr, _size, (enum dma_data_direction)_dir) 1028 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 1029 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1030 _sg, _nents, (enum dma_data_direction)_dir) 1031 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 1032 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 1033 _offset, _size, (enum dma_data_direction)_dir) 1034 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 1035 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1036 _dma_address, _size, (enum dma_data_direction)_dir) 1037 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1038 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1039 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1040 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1041 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1042 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1043 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1044 #define pci_unmap_addr dma_unmap_addr 1045 #define pci_unmap_addr_set dma_unmap_addr_set 1046 #define pci_unmap_len dma_unmap_len 1047 #define pci_unmap_len_set dma_unmap_len_set 1048 1049 typedef unsigned int __bitwise pci_channel_state_t; 1050 typedef unsigned int __bitwise pci_ers_result_t; 1051 1052 enum pci_channel_state { 1053 pci_channel_io_normal = 1, 1054 pci_channel_io_frozen = 2, 1055 pci_channel_io_perm_failure = 3, 1056 }; 1057 1058 enum pci_ers_result { 1059 PCI_ERS_RESULT_NONE = 1, 1060 PCI_ERS_RESULT_CAN_RECOVER = 2, 1061 PCI_ERS_RESULT_NEED_RESET = 3, 1062 PCI_ERS_RESULT_DISCONNECT = 4, 1063 PCI_ERS_RESULT_RECOVERED = 5, 1064 }; 1065 1066 /* PCI bus error event callbacks */ 1067 struct pci_error_handlers { 1068 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1069 enum pci_channel_state error); 1070 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1071 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1072 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1073 void (*resume)(struct pci_dev *dev); 1074 }; 1075 1076 /* FreeBSD does not support SRIOV - yet */ 1077 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1078 { 1079 return dev; 1080 } 1081 1082 static inline bool pci_is_pcie(struct pci_dev *dev) 1083 { 1084 return !!pci_pcie_cap(dev); 1085 } 1086 1087 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1088 { 1089 int pos; 1090 u16 reg16; 1091 1092 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1093 if (!pos) 1094 return 0; 1095 1096 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1097 1098 return reg16; 1099 } 1100 1101 static inline int pci_pcie_type(struct pci_dev *dev) 1102 { 1103 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1104 } 1105 1106 static inline int pcie_cap_version(struct pci_dev *dev) 1107 { 1108 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1109 } 1110 1111 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1112 { 1113 int type = pci_pcie_type(dev); 1114 1115 return pcie_cap_version(dev) > 1 || 1116 type == PCI_EXP_TYPE_ROOT_PORT || 1117 type == PCI_EXP_TYPE_ENDPOINT || 1118 type == PCI_EXP_TYPE_LEG_END; 1119 } 1120 1121 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1122 { 1123 return true; 1124 } 1125 1126 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1127 { 1128 int type = pci_pcie_type(dev); 1129 1130 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1131 (type == PCI_EXP_TYPE_DOWNSTREAM && 1132 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1133 } 1134 1135 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1136 { 1137 int type = pci_pcie_type(dev); 1138 1139 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1140 type == PCI_EXP_TYPE_RC_EC; 1141 } 1142 1143 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1144 { 1145 if (!pci_is_pcie(dev)) 1146 return false; 1147 1148 switch (pos) { 1149 case PCI_EXP_FLAGS_TYPE: 1150 return true; 1151 case PCI_EXP_DEVCAP: 1152 case PCI_EXP_DEVCTL: 1153 case PCI_EXP_DEVSTA: 1154 return pcie_cap_has_devctl(dev); 1155 case PCI_EXP_LNKCAP: 1156 case PCI_EXP_LNKCTL: 1157 case PCI_EXP_LNKSTA: 1158 return pcie_cap_has_lnkctl(dev); 1159 case PCI_EXP_SLTCAP: 1160 case PCI_EXP_SLTCTL: 1161 case PCI_EXP_SLTSTA: 1162 return pcie_cap_has_sltctl(dev); 1163 case PCI_EXP_RTCTL: 1164 case PCI_EXP_RTCAP: 1165 case PCI_EXP_RTSTA: 1166 return pcie_cap_has_rtctl(dev); 1167 case PCI_EXP_DEVCAP2: 1168 case PCI_EXP_DEVCTL2: 1169 case PCI_EXP_LNKCAP2: 1170 case PCI_EXP_LNKCTL2: 1171 case PCI_EXP_LNKSTA2: 1172 return pcie_cap_version(dev) > 1; 1173 default: 1174 return false; 1175 } 1176 } 1177 1178 static inline int 1179 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1180 { 1181 if (pos & 3) 1182 return -EINVAL; 1183 1184 if (!pcie_capability_reg_implemented(dev, pos)) 1185 return -EINVAL; 1186 1187 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1188 } 1189 1190 static inline int 1191 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1192 { 1193 if (pos & 3) 1194 return -EINVAL; 1195 1196 if (!pcie_capability_reg_implemented(dev, pos)) 1197 return -EINVAL; 1198 1199 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1200 } 1201 1202 static inline int 1203 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1204 { 1205 if (pos & 1) 1206 return -EINVAL; 1207 1208 if (!pcie_capability_reg_implemented(dev, pos)) 1209 return 0; 1210 1211 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1212 } 1213 1214 static inline int 1215 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1216 { 1217 int error; 1218 uint16_t v; 1219 1220 error = pcie_capability_read_word(dev, pos, &v); 1221 if (error != 0) 1222 return (error); 1223 1224 v |= val; 1225 1226 error = pcie_capability_write_word(dev, pos, v); 1227 return (error); 1228 } 1229 1230 static inline int 1231 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1232 { 1233 int error; 1234 uint16_t v; 1235 1236 error = pcie_capability_read_word(dev, pos, &v); 1237 if (error != 0) 1238 return (error); 1239 1240 v &= ~val; 1241 1242 error = pcie_capability_write_word(dev, pos, v); 1243 return (error); 1244 } 1245 1246 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1247 enum pci_bus_speed *speed, enum pcie_link_width *width) 1248 { 1249 *speed = PCI_SPEED_UNKNOWN; 1250 *width = PCIE_LNK_WIDTH_UNKNOWN; 1251 return (0); 1252 } 1253 1254 static inline int 1255 pci_num_vf(struct pci_dev *dev) 1256 { 1257 return (0); 1258 } 1259 1260 static inline enum pci_bus_speed 1261 pcie_get_speed_cap(struct pci_dev *dev) 1262 { 1263 device_t root; 1264 uint32_t lnkcap, lnkcap2; 1265 int error, pos; 1266 1267 root = device_get_parent(dev->dev.bsddev); 1268 if (root == NULL) 1269 return (PCI_SPEED_UNKNOWN); 1270 root = device_get_parent(root); 1271 if (root == NULL) 1272 return (PCI_SPEED_UNKNOWN); 1273 root = device_get_parent(root); 1274 if (root == NULL) 1275 return (PCI_SPEED_UNKNOWN); 1276 1277 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1278 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1279 return (PCI_SPEED_UNKNOWN); 1280 1281 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1282 return (PCI_SPEED_UNKNOWN); 1283 1284 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1285 1286 if (lnkcap2) { /* PCIe r3.0-compliant */ 1287 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1288 return (PCIE_SPEED_2_5GT); 1289 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1290 return (PCIE_SPEED_5_0GT); 1291 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1292 return (PCIE_SPEED_8_0GT); 1293 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1294 return (PCIE_SPEED_16_0GT); 1295 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1296 return (PCIE_SPEED_32_0GT); 1297 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1298 return (PCIE_SPEED_64_0GT); 1299 } else { /* pre-r3.0 */ 1300 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1301 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1302 return (PCIE_SPEED_2_5GT); 1303 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1304 return (PCIE_SPEED_5_0GT); 1305 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1306 return (PCIE_SPEED_8_0GT); 1307 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1308 return (PCIE_SPEED_16_0GT); 1309 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1310 return (PCIE_SPEED_32_0GT); 1311 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1312 return (PCIE_SPEED_64_0GT); 1313 } 1314 return (PCI_SPEED_UNKNOWN); 1315 } 1316 1317 static inline enum pcie_link_width 1318 pcie_get_width_cap(struct pci_dev *dev) 1319 { 1320 uint32_t lnkcap; 1321 1322 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1323 if (lnkcap) 1324 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1325 1326 return (PCIE_LNK_WIDTH_UNKNOWN); 1327 } 1328 1329 static inline int 1330 pcie_get_mps(struct pci_dev *dev) 1331 { 1332 return (pci_get_max_payload(dev->dev.bsddev)); 1333 } 1334 1335 static inline uint32_t 1336 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1337 { 1338 1339 switch(spd) { 1340 case PCIE_SPEED_64_0GT: 1341 return (64000 * 128 / 130); 1342 case PCIE_SPEED_32_0GT: 1343 return (32000 * 128 / 130); 1344 case PCIE_SPEED_16_0GT: 1345 return (16000 * 128 / 130); 1346 case PCIE_SPEED_8_0GT: 1347 return (8000 * 128 / 130); 1348 case PCIE_SPEED_5_0GT: 1349 return (5000 * 8 / 10); 1350 case PCIE_SPEED_2_5GT: 1351 return (2500 * 8 / 10); 1352 default: 1353 return (0); 1354 } 1355 } 1356 1357 static inline uint32_t 1358 pcie_bandwidth_available(struct pci_dev *pdev, 1359 struct pci_dev **limiting, 1360 enum pci_bus_speed *speed, 1361 enum pcie_link_width *width) 1362 { 1363 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1364 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1365 1366 if (speed) 1367 *speed = nspeed; 1368 if (width) 1369 *width = nwidth; 1370 1371 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1372 } 1373 1374 static inline bool 1375 pcie_aspm_enabled(struct pci_dev *pdev) 1376 { 1377 return (false); 1378 } 1379 1380 static inline struct pci_dev * 1381 pcie_find_root_port(struct pci_dev *pdev) 1382 { 1383 device_t root; 1384 1385 if (pdev->root != NULL) 1386 return (pdev->root); 1387 1388 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1389 if (root == NULL) 1390 return (NULL); 1391 1392 pdev->root = lkpinew_pci_dev(root); 1393 return (pdev->root); 1394 } 1395 1396 /* This is needed when people rip out the device "HotPlug". */ 1397 static inline void 1398 pci_lock_rescan_remove(void) 1399 { 1400 } 1401 1402 static inline void 1403 pci_unlock_rescan_remove(void) 1404 { 1405 } 1406 1407 static __inline void 1408 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1409 { 1410 } 1411 1412 /* 1413 * The following functions can be used to attach/detach the LinuxKPI's 1414 * PCI device runtime. The pci_driver and pci_device_id pointer is 1415 * allowed to be NULL. Other pointers must be all valid. 1416 * The pci_dev structure should be zero-initialized before passed 1417 * to the linux_pci_attach_device function. 1418 */ 1419 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1420 const struct pci_device_id *, struct pci_dev *); 1421 extern int linux_pci_detach_device(struct pci_dev *); 1422 1423 static inline int 1424 pci_dev_present(const struct pci_device_id *cur) 1425 { 1426 while (cur != NULL && (cur->vendor || cur->device)) { 1427 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1428 return (1); 1429 } 1430 cur++; 1431 } 1432 return (0); 1433 } 1434 1435 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1436 unsigned int bus, unsigned int devfn); 1437 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1438 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1439 1440 static inline int 1441 pci_domain_nr(struct pci_bus *pbus) 1442 { 1443 1444 return (pbus->domain); 1445 } 1446 1447 static inline int 1448 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1449 int pos, uint32_t *val, int len) 1450 { 1451 1452 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1453 return (0); 1454 } 1455 1456 static inline int 1457 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1458 { 1459 uint32_t tmp; 1460 int ret; 1461 1462 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1463 *val = (u16)tmp; 1464 return (ret); 1465 } 1466 1467 static inline int 1468 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1469 { 1470 uint32_t tmp; 1471 int ret; 1472 1473 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1474 *val = (u8)tmp; 1475 return (ret); 1476 } 1477 1478 static inline int 1479 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1480 uint32_t val, int size) 1481 { 1482 1483 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1484 return (0); 1485 } 1486 1487 static inline int 1488 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1489 uint8_t val) 1490 { 1491 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1492 } 1493 1494 static inline int 1495 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1496 uint16_t val) 1497 { 1498 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1499 } 1500 1501 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1502 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1503 1504 /* -------------------------------------------------------------------------- */ 1505 1506 static inline int 1507 pcim_enable_device(struct pci_dev *pdev) 1508 { 1509 struct pci_devres *dr; 1510 int error; 1511 1512 /* Here we cannot run through the pdev->managed check. */ 1513 dr = lkpi_pci_devres_get_alloc(pdev); 1514 if (dr == NULL) 1515 return (-ENOMEM); 1516 1517 /* If resources were enabled before do not do it again. */ 1518 if (dr->enable_io) 1519 return (0); 1520 1521 error = pci_enable_device(pdev); 1522 if (error == 0) 1523 dr->enable_io = true; 1524 1525 /* This device is not managed. */ 1526 pdev->managed = true; 1527 1528 return (error); 1529 } 1530 1531 static inline void __iomem ** 1532 pcim_iomap_table(struct pci_dev *pdev) 1533 { 1534 struct pcim_iomap_devres *dr; 1535 1536 dr = lkpi_pcim_iomap_devres_find(pdev); 1537 if (dr == NULL) 1538 return (NULL); 1539 1540 /* 1541 * If the driver has manually set a flag to be able to request the 1542 * resource to use bus_read/write_<n>, return the shadow table. 1543 */ 1544 if (pdev->want_iomap_res) 1545 return ((void **)dr->res_table); 1546 1547 /* This is the Linux default. */ 1548 return (dr->mmio_table); 1549 } 1550 1551 static inline int 1552 pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, const char *name) 1553 { 1554 struct pcim_iomap_devres *dr; 1555 void *res; 1556 uint32_t mappings; 1557 int bar; 1558 1559 dr = lkpi_pcim_iomap_devres_find(pdev); 1560 if (dr == NULL) 1561 return (-ENOMEM); 1562 1563 /* Now iomap all the requested (by "mask") ones. */ 1564 for (bar = mappings = 0; mappings != mask; bar++) { 1565 if ((mask & (1 << bar)) == 0) 1566 continue; 1567 1568 /* Request double is not allowed. */ 1569 if (dr->mmio_table[bar] != NULL) { 1570 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1571 __func__, bar, dr->mmio_table[bar]); 1572 goto err; 1573 } 1574 1575 res = _lkpi_pci_iomap(pdev, bar, 0); 1576 if (res == NULL) 1577 goto err; 1578 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1579 dr->res_table[bar] = res; 1580 1581 mappings |= (1 << bar); 1582 } 1583 1584 return (0); 1585 err: 1586 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1587 if ((mappings & (1 << bar)) != 0) { 1588 res = dr->mmio_table[bar]; 1589 if (res == NULL) 1590 continue; 1591 pci_iounmap(pdev, res); 1592 } 1593 } 1594 1595 return (-EINVAL); 1596 } 1597 1598 static inline int 1599 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1600 { 1601 uint32_t requests, req_mask; 1602 int bar, error; 1603 1604 /* Request all the BARs ("regions") we do not iomap. */ 1605 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1606 for (bar = requests = 0; requests != req_mask; bar++) { 1607 if ((req_mask & (1 << bar)) == 0) 1608 continue; 1609 error = pci_request_region(pdev, bar, name); 1610 if (error != 0 && error != -ENODEV) 1611 goto err; 1612 requests |= (1 << bar); 1613 } 1614 1615 error = pcim_iomap_regions(pdev, mask, name); 1616 if (error != 0) 1617 goto err; 1618 1619 return (0); 1620 1621 err: 1622 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1623 if ((requests & (1 << bar)) != 0) 1624 pci_release_region(pdev, bar); 1625 } 1626 1627 return (-EINVAL); 1628 } 1629 1630 /* 1631 * We cannot simply re-define pci_get_device() as we would normally do 1632 * and then hide it in linux_pci.c as too many semi-native drivers still 1633 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1634 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1635 */ 1636 static inline struct pci_dev * 1637 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1638 { 1639 1640 return (lkpi_pci_get_device(vendor, device, odev)); 1641 } 1642 1643 /* This is a FreeBSD extension so we can use bus_*(). */ 1644 static inline void 1645 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1646 { 1647 pdev->want_iomap_res = true; 1648 } 1649 1650 static inline bool 1651 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1652 { 1653 1654 return (false); 1655 } 1656 1657 static inline void * 1658 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1659 { 1660 1661 return (NULL); 1662 } 1663 1664 static inline void 1665 pci_ignore_hotplug(struct pci_dev *pdev) 1666 { 1667 } 1668 1669 static inline const char * 1670 pci_power_name(pci_power_t state) 1671 { 1672 int pstate = state + 1; 1673 1674 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1675 return (pci_power_names[pstate]); 1676 else 1677 return (pci_power_names[0]); 1678 } 1679 1680 static inline int 1681 pcie_get_readrq(struct pci_dev *dev) 1682 { 1683 u16 ctl; 1684 1685 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1686 return (-EINVAL); 1687 1688 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1689 } 1690 1691 static inline bool 1692 pci_is_enabled(struct pci_dev *pdev) 1693 { 1694 1695 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1696 PCIM_CMD_BUSMASTEREN) != 0); 1697 } 1698 1699 static inline int 1700 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1701 { 1702 1703 return (0); 1704 } 1705 1706 static inline int 1707 pci_assign_resource(struct pci_dev *pdev, int bar) 1708 { 1709 1710 return (0); 1711 } 1712 1713 static inline int 1714 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1715 { 1716 1717 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1718 if (vector != 0) 1719 return (-EINVAL); 1720 return (pdev->irq); 1721 } 1722 1723 if (pdev->msix_enabled || pdev->msi_enabled) { 1724 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1725 return (-EINVAL); 1726 return (pdev->dev.irq_start + vector); 1727 } 1728 1729 return (-ENXIO); 1730 } 1731 1732 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1733