1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/pciio.h> 41 #include <sys/rman.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pci_private.h> 45 46 #include <machine/resource.h> 47 48 #include <linux/list.h> 49 #include <linux/dmapool.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/compiler.h> 52 #include <linux/errno.h> 53 #include <asm/atomic.h> 54 #include <linux/device.h> 55 56 struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class; 62 uint32_t class_mask; 63 uintptr_t driver_data; 64 }; 65 66 #define MODULE_DEVICE_TABLE(bus, table) 67 68 #define PCI_BASE_CLASS_DISPLAY 0x03 69 #define PCI_CLASS_DISPLAY_VGA 0x0300 70 #define PCI_CLASS_DISPLAY_OTHER 0x0380 71 #define PCI_BASE_CLASS_BRIDGE 0x06 72 #define PCI_CLASS_BRIDGE_ISA 0x0601 73 74 #define PCI_ANY_ID (-1) 75 #define PCI_VENDOR_ID_APPLE 0x106b 76 #define PCI_VENDOR_ID_ASUSTEK 0x1043 77 #define PCI_VENDOR_ID_ATI 0x1002 78 #define PCI_VENDOR_ID_DELL 0x1028 79 #define PCI_VENDOR_ID_HP 0x103c 80 #define PCI_VENDOR_ID_IBM 0x1014 81 #define PCI_VENDOR_ID_INTEL 0x8086 82 #define PCI_VENDOR_ID_MELLANOX 0x15b3 83 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 84 #define PCI_VENDOR_ID_SERVERWORKS 0x1166 85 #define PCI_VENDOR_ID_SONY 0x104d 86 #define PCI_VENDOR_ID_TOPSPIN 0x1867 87 #define PCI_VENDOR_ID_VIA 0x1106 88 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 89 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 90 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 91 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 92 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 93 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 94 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 95 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 96 #define PCI_SUBDEVICE_ID_QEMU 0x1100 97 98 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 99 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 100 #define PCI_FUNC(devfn) ((devfn) & 0x07) 101 102 #define PCI_VDEVICE(_vendor, _device) \ 103 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 104 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 105 #define PCI_DEVICE(_vendor, _device) \ 106 .vendor = (_vendor), .device = (_device), \ 107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 108 109 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 110 111 #define PCI_VENDOR_ID PCIR_DEVVENDOR 112 #define PCI_COMMAND PCIR_COMMAND 113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 115 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 116 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 117 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 118 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 119 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 120 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 121 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 122 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 123 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 124 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 125 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 126 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 127 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 128 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 129 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 130 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 131 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 132 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 133 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 134 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 135 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 136 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 137 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 138 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 139 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 140 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 141 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 142 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 143 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 144 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 145 146 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 147 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 148 #define PCI_EXP_DEVSTA_TRPND 0x0020 149 150 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 151 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 152 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 153 154 enum pci_bus_speed { 155 PCI_SPEED_UNKNOWN = -1, 156 PCIE_SPEED_2_5GT, 157 PCIE_SPEED_5_0GT, 158 PCIE_SPEED_8_0GT, 159 }; 160 161 enum pcie_link_width { 162 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 163 }; 164 165 typedef int pci_power_t; 166 167 #define PCI_D0 PCI_POWERSTATE_D0 168 #define PCI_D1 PCI_POWERSTATE_D1 169 #define PCI_D2 PCI_POWERSTATE_D2 170 #define PCI_D3hot PCI_POWERSTATE_D3 171 #define PCI_D3cold 4 172 173 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 174 175 struct pci_dev; 176 177 struct pci_driver { 178 struct list_head links; 179 char *name; 180 const struct pci_device_id *id_table; 181 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 182 void (*remove)(struct pci_dev *dev); 183 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 184 int (*resume) (struct pci_dev *dev); /* Device woken up */ 185 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 186 driver_t bsddriver; 187 devclass_t bsdclass; 188 struct device_driver driver; 189 const struct pci_error_handlers *err_handler; 190 bool isdrm; 191 }; 192 193 struct pci_bus { 194 struct pci_dev *self; 195 int number; 196 }; 197 198 extern struct list_head pci_drivers; 199 extern struct list_head pci_devices; 200 extern spinlock_t pci_lock; 201 202 #define __devexit_p(x) x 203 204 struct pci_dev { 205 struct device dev; 206 struct list_head links; 207 struct pci_driver *pdrv; 208 struct pci_bus *bus; 209 uint64_t dma_mask; 210 uint16_t device; 211 uint16_t vendor; 212 uint16_t subsystem_vendor; 213 uint16_t subsystem_device; 214 unsigned int irq; 215 unsigned int devfn; 216 uint32_t class; 217 uint8_t revision; 218 }; 219 220 static inline struct resource_list_entry * 221 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 222 { 223 struct pci_devinfo *dinfo; 224 struct resource_list *rl; 225 226 dinfo = device_get_ivars(pdev->dev.bsddev); 227 rl = &dinfo->resources; 228 return resource_list_find(rl, type, rid); 229 } 230 231 static inline struct resource_list_entry * 232 linux_pci_get_bar(struct pci_dev *pdev, int bar) 233 { 234 struct resource_list_entry *rle; 235 236 bar = PCIR_BAR(bar); 237 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 238 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 239 return (rle); 240 } 241 242 static inline struct device * 243 linux_pci_find_irq_dev(unsigned int irq) 244 { 245 struct pci_dev *pdev; 246 struct device *found; 247 248 found = NULL; 249 spin_lock(&pci_lock); 250 list_for_each_entry(pdev, &pci_devices, links) { 251 if (irq == pdev->dev.irq || 252 (irq >= pdev->dev.msix && irq < pdev->dev.msix_max)) { 253 found = &pdev->dev; 254 break; 255 } 256 } 257 spin_unlock(&pci_lock); 258 return (found); 259 } 260 261 static inline unsigned long 262 pci_resource_start(struct pci_dev *pdev, int bar) 263 { 264 struct resource_list_entry *rle; 265 266 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 267 return (0); 268 return rle->start; 269 } 270 271 static inline unsigned long 272 pci_resource_len(struct pci_dev *pdev, int bar) 273 { 274 struct resource_list_entry *rle; 275 276 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 277 return (0); 278 return rle->count; 279 } 280 281 static inline int 282 pci_resource_type(struct pci_dev *pdev, int bar) 283 { 284 struct pci_map *pm; 285 286 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 287 if (!pm) 288 return (-1); 289 290 if (PCI_BAR_IO(pm->pm_value)) 291 return (SYS_RES_IOPORT); 292 else 293 return (SYS_RES_MEMORY); 294 } 295 296 /* 297 * All drivers just seem to want to inspect the type not flags. 298 */ 299 static inline int 300 pci_resource_flags(struct pci_dev *pdev, int bar) 301 { 302 int type; 303 304 type = pci_resource_type(pdev, bar); 305 if (type < 0) 306 return (0); 307 return (1 << type); 308 } 309 310 static inline const char * 311 pci_name(struct pci_dev *d) 312 { 313 314 return device_get_desc(d->dev.bsddev); 315 } 316 317 static inline void * 318 pci_get_drvdata(struct pci_dev *pdev) 319 { 320 321 return dev_get_drvdata(&pdev->dev); 322 } 323 324 static inline void 325 pci_set_drvdata(struct pci_dev *pdev, void *data) 326 { 327 328 dev_set_drvdata(&pdev->dev, data); 329 } 330 331 static inline int 332 pci_enable_device(struct pci_dev *pdev) 333 { 334 335 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 336 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 337 return (0); 338 } 339 340 static inline void 341 pci_disable_device(struct pci_dev *pdev) 342 { 343 344 pci_disable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 345 pci_disable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 346 } 347 348 static inline int 349 pci_set_master(struct pci_dev *pdev) 350 { 351 352 pci_enable_busmaster(pdev->dev.bsddev); 353 return (0); 354 } 355 356 static inline int 357 pci_set_power_state(struct pci_dev *pdev, int state) 358 { 359 360 pci_set_powerstate(pdev->dev.bsddev, state); 361 return (0); 362 } 363 364 static inline int 365 pci_clear_master(struct pci_dev *pdev) 366 { 367 368 pci_disable_busmaster(pdev->dev.bsddev); 369 return (0); 370 } 371 372 static inline int 373 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 374 { 375 int rid; 376 int type; 377 378 type = pci_resource_type(pdev, bar); 379 if (type < 0) 380 return (-ENODEV); 381 rid = PCIR_BAR(bar); 382 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 383 RF_ACTIVE) == NULL) 384 return (-EINVAL); 385 return (0); 386 } 387 388 static inline void 389 pci_release_region(struct pci_dev *pdev, int bar) 390 { 391 struct resource_list_entry *rle; 392 393 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 394 return; 395 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 396 } 397 398 static inline void 399 pci_release_regions(struct pci_dev *pdev) 400 { 401 int i; 402 403 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 404 pci_release_region(pdev, i); 405 } 406 407 static inline int 408 pci_request_regions(struct pci_dev *pdev, const char *res_name) 409 { 410 int error; 411 int i; 412 413 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 414 error = pci_request_region(pdev, i, res_name); 415 if (error && error != -ENODEV) { 416 pci_release_regions(pdev); 417 return (error); 418 } 419 } 420 return (0); 421 } 422 423 static inline void 424 pci_disable_msix(struct pci_dev *pdev) 425 { 426 427 pci_release_msi(pdev->dev.bsddev); 428 } 429 430 static inline bus_addr_t 431 pci_bus_address(struct pci_dev *pdev, int bar) 432 { 433 434 return (pci_resource_start(pdev, bar)); 435 } 436 437 #define PCI_CAP_ID_EXP PCIY_EXPRESS 438 #define PCI_CAP_ID_PCIX PCIY_PCIX 439 #define PCI_CAP_ID_AGP PCIY_AGP 440 #define PCI_CAP_ID_PM PCIY_PMG 441 442 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 443 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 444 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 445 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 446 #define PCI_EXP_LNKSTA PCIER_LINK_STA 447 448 static inline int 449 pci_find_capability(struct pci_dev *pdev, int capid) 450 { 451 int reg; 452 453 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 454 return (0); 455 return (reg); 456 } 457 458 static inline int pci_pcie_cap(struct pci_dev *dev) 459 { 460 return pci_find_capability(dev, PCI_CAP_ID_EXP); 461 } 462 463 464 static inline int 465 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 466 { 467 468 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 469 return (0); 470 } 471 472 static inline int 473 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 474 { 475 476 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 477 return (0); 478 } 479 480 static inline int 481 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 482 { 483 484 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 485 return (0); 486 } 487 488 static inline int 489 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 490 { 491 492 pci_write_config(pdev->dev.bsddev, where, val, 1); 493 return (0); 494 } 495 496 static inline int 497 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 498 { 499 500 pci_write_config(pdev->dev.bsddev, where, val, 2); 501 return (0); 502 } 503 504 static inline int 505 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 506 { 507 508 pci_write_config(pdev->dev.bsddev, where, val, 4); 509 return (0); 510 } 511 512 int linux_pci_register_driver(struct pci_driver *pdrv); 513 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 514 void linux_pci_unregister_driver(struct pci_driver *pdrv); 515 516 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 517 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 518 519 struct msix_entry { 520 int entry; 521 int vector; 522 }; 523 524 /* 525 * Enable msix, positive errors indicate actual number of available 526 * vectors. Negative errors are failures. 527 * 528 * NB: define added to prevent this definition of pci_enable_msix from 529 * clashing with the native FreeBSD version. 530 */ 531 #define pci_enable_msix linux_pci_enable_msix 532 static inline int 533 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 534 { 535 struct resource_list_entry *rle; 536 int error; 537 int avail; 538 int i; 539 540 avail = pci_msix_count(pdev->dev.bsddev); 541 if (avail < nreq) { 542 if (avail == 0) 543 return -EINVAL; 544 return avail; 545 } 546 avail = nreq; 547 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 548 return error; 549 /* 550 * Handle case where "pci_alloc_msix()" may allocate less 551 * interrupts than available and return with no error: 552 */ 553 if (avail < nreq) { 554 pci_release_msi(pdev->dev.bsddev); 555 return avail; 556 } 557 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 558 pdev->dev.msix = rle->start; 559 pdev->dev.msix_max = rle->start + avail; 560 for (i = 0; i < nreq; i++) 561 entries[i].vector = pdev->dev.msix + i; 562 return (0); 563 } 564 565 #define pci_enable_msix_range linux_pci_enable_msix_range 566 static inline int 567 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 568 int minvec, int maxvec) 569 { 570 int nvec = maxvec; 571 int rc; 572 573 if (maxvec < minvec) 574 return (-ERANGE); 575 576 do { 577 rc = pci_enable_msix(dev, entries, nvec); 578 if (rc < 0) { 579 return (rc); 580 } else if (rc > 0) { 581 if (rc < minvec) 582 return (-ENOSPC); 583 nvec = rc; 584 } 585 } while (rc); 586 return (nvec); 587 } 588 589 static inline int pci_channel_offline(struct pci_dev *pdev) 590 { 591 return false; 592 } 593 594 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 595 { 596 return -ENODEV; 597 } 598 static inline void pci_disable_sriov(struct pci_dev *dev) 599 { 600 } 601 602 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 603 const struct pci_device_id _table[] __devinitdata 604 605 606 /* XXX This should not be necessary. */ 607 #define pcix_set_mmrbc(d, v) 0 608 #define pcix_get_max_mmrbc(d) 0 609 #define pcie_set_readrq(d, v) 0 610 611 #define PCI_DMA_BIDIRECTIONAL 0 612 #define PCI_DMA_TODEVICE 1 613 #define PCI_DMA_FROMDEVICE 2 614 #define PCI_DMA_NONE 3 615 616 #define pci_pool dma_pool 617 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 618 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 619 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 620 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 621 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 622 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 623 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 624 _size, _vaddr, _dma_handle) 625 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 626 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 627 _sg, _nents, (enum dma_data_direction)_dir) 628 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 629 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 630 (_ptr), (_size), (enum dma_data_direction)_dir) 631 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 632 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 633 _addr, _size, (enum dma_data_direction)_dir) 634 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 635 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 636 _sg, _nents, (enum dma_data_direction)_dir) 637 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 638 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 639 _offset, _size, (enum dma_data_direction)_dir) 640 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 641 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 642 _dma_address, _size, (enum dma_data_direction)_dir) 643 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 644 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 645 dma_mapping_error(&(_pdev)->dev, _dma_addr) 646 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 647 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 648 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 649 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 650 #define pci_unmap_addr dma_unmap_addr 651 #define pci_unmap_addr_set dma_unmap_addr_set 652 #define pci_unmap_len dma_unmap_len 653 #define pci_unmap_len_set dma_unmap_len_set 654 655 typedef unsigned int __bitwise pci_channel_state_t; 656 typedef unsigned int __bitwise pci_ers_result_t; 657 658 enum pci_channel_state { 659 pci_channel_io_normal = 1, 660 pci_channel_io_frozen = 2, 661 pci_channel_io_perm_failure = 3, 662 }; 663 664 enum pci_ers_result { 665 PCI_ERS_RESULT_NONE = 1, 666 PCI_ERS_RESULT_CAN_RECOVER = 2, 667 PCI_ERS_RESULT_NEED_RESET = 3, 668 PCI_ERS_RESULT_DISCONNECT = 4, 669 PCI_ERS_RESULT_RECOVERED = 5, 670 }; 671 672 673 /* PCI bus error event callbacks */ 674 struct pci_error_handlers { 675 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 676 enum pci_channel_state error); 677 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 678 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 679 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 680 void (*resume)(struct pci_dev *dev); 681 }; 682 683 /* FreeBSD does not support SRIOV - yet */ 684 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 685 { 686 return dev; 687 } 688 689 static inline bool pci_is_pcie(struct pci_dev *dev) 690 { 691 return !!pci_pcie_cap(dev); 692 } 693 694 static inline u16 pcie_flags_reg(struct pci_dev *dev) 695 { 696 int pos; 697 u16 reg16; 698 699 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 700 if (!pos) 701 return 0; 702 703 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 704 705 return reg16; 706 } 707 708 709 static inline int pci_pcie_type(struct pci_dev *dev) 710 { 711 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 712 } 713 714 static inline int pcie_cap_version(struct pci_dev *dev) 715 { 716 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 717 } 718 719 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 720 { 721 int type = pci_pcie_type(dev); 722 723 return pcie_cap_version(dev) > 1 || 724 type == PCI_EXP_TYPE_ROOT_PORT || 725 type == PCI_EXP_TYPE_ENDPOINT || 726 type == PCI_EXP_TYPE_LEG_END; 727 } 728 729 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 730 { 731 return true; 732 } 733 734 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 735 { 736 int type = pci_pcie_type(dev); 737 738 return pcie_cap_version(dev) > 1 || 739 type == PCI_EXP_TYPE_ROOT_PORT || 740 (type == PCI_EXP_TYPE_DOWNSTREAM && 741 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 742 } 743 744 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 745 { 746 int type = pci_pcie_type(dev); 747 748 return pcie_cap_version(dev) > 1 || 749 type == PCI_EXP_TYPE_ROOT_PORT || 750 type == PCI_EXP_TYPE_RC_EC; 751 } 752 753 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 754 { 755 if (!pci_is_pcie(dev)) 756 return false; 757 758 switch (pos) { 759 case PCI_EXP_FLAGS_TYPE: 760 return true; 761 case PCI_EXP_DEVCAP: 762 case PCI_EXP_DEVCTL: 763 case PCI_EXP_DEVSTA: 764 return pcie_cap_has_devctl(dev); 765 case PCI_EXP_LNKCAP: 766 case PCI_EXP_LNKCTL: 767 case PCI_EXP_LNKSTA: 768 return pcie_cap_has_lnkctl(dev); 769 case PCI_EXP_SLTCAP: 770 case PCI_EXP_SLTCTL: 771 case PCI_EXP_SLTSTA: 772 return pcie_cap_has_sltctl(dev); 773 case PCI_EXP_RTCTL: 774 case PCI_EXP_RTCAP: 775 case PCI_EXP_RTSTA: 776 return pcie_cap_has_rtctl(dev); 777 case PCI_EXP_DEVCAP2: 778 case PCI_EXP_DEVCTL2: 779 case PCI_EXP_LNKCAP2: 780 case PCI_EXP_LNKCTL2: 781 case PCI_EXP_LNKSTA2: 782 return pcie_cap_version(dev) > 1; 783 default: 784 return false; 785 } 786 } 787 788 static inline int 789 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 790 { 791 if (pos & 3) 792 return -EINVAL; 793 794 if (!pcie_capability_reg_implemented(dev, pos)) 795 return -EINVAL; 796 797 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 798 } 799 800 static inline int 801 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 802 { 803 if (pos & 3) 804 return -EINVAL; 805 806 if (!pcie_capability_reg_implemented(dev, pos)) 807 return -EINVAL; 808 809 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 810 } 811 812 static inline int 813 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 814 { 815 if (pos & 1) 816 return -EINVAL; 817 818 if (!pcie_capability_reg_implemented(dev, pos)) 819 return 0; 820 821 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 822 } 823 824 static inline int pcie_get_minimum_link(struct pci_dev *dev, 825 enum pci_bus_speed *speed, enum pcie_link_width *width) 826 { 827 *speed = PCI_SPEED_UNKNOWN; 828 *width = PCIE_LNK_WIDTH_UNKNOWN; 829 return (0); 830 } 831 832 static inline int 833 pci_num_vf(struct pci_dev *dev) 834 { 835 return (0); 836 } 837 838 #endif /* _LINUX_PCI_H_ */ 839