1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/nv.h> 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <asm/memtype.h> 61 #include <linux/device.h> 62 #include <linux/pci_ids.h> 63 #include <linux/pm.h> 64 65 struct pci_device_id { 66 uint32_t vendor; 67 uint32_t device; 68 uint32_t subvendor; 69 uint32_t subdevice; 70 uint32_t class; 71 uint32_t class_mask; 72 uintptr_t driver_data; 73 }; 74 75 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 76 #define MODULE_DEVICE_TABLE(_bus, _table) \ 77 \ 78 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 79 DEVMETHOD_END \ 80 }; \ 81 \ 82 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 83 "lkpi_" #_bus #_table, \ 84 _ ## _bus ## _ ## _table ## _methods, \ 85 0 \ 86 }; \ 87 \ 88 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 89 0, 0); \ 90 \ 91 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 92 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 93 94 #define PCI_ANY_ID -1U 95 96 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 97 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 98 #define PCI_FUNC(devfn) ((devfn) & 0x07) 99 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 100 101 #define PCI_VDEVICE(_vendor, _device) \ 102 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 103 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 104 #define PCI_DEVICE(_vendor, _device) \ 105 .vendor = (_vendor), .device = (_device), \ 106 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 107 108 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 109 110 #define PCI_STD_NUM_BARS 6 111 #define PCI_VENDOR_ID PCIR_VENDOR 112 #define PCI_DEVICE_ID PCIR_DEVICE 113 #define PCI_COMMAND PCIR_COMMAND 114 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 115 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 116 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 117 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 118 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 119 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 120 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 121 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 122 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 123 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 124 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 125 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 126 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 127 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 128 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 129 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 130 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 131 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 132 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 133 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 134 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 135 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 136 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 137 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 138 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 139 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 140 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 141 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 142 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 143 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 144 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 145 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 146 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 147 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 148 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 149 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 150 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 151 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 152 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 153 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 154 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 155 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 156 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 157 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 158 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 159 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 160 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 161 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 162 #define PCI_EXP_LNKCTL2_TLS 0x000f 163 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 164 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 165 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 166 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 167 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 168 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 169 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 170 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 171 172 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 173 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 174 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 175 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 176 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 177 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 178 179 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 180 #define PCI_EXP_DEVSTA_TRPND 0x0020 181 182 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 183 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 184 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 185 186 enum pci_bus_speed { 187 PCI_SPEED_UNKNOWN = -1, 188 PCIE_SPEED_2_5GT, 189 PCIE_SPEED_5_0GT, 190 PCIE_SPEED_8_0GT, 191 PCIE_SPEED_16_0GT, 192 PCIE_SPEED_32_0GT, 193 PCIE_SPEED_64_0GT, 194 }; 195 196 enum pcie_link_width { 197 PCIE_LNK_WIDTH_RESRV = 0x00, 198 PCIE_LNK_X1 = 0x01, 199 PCIE_LNK_X2 = 0x02, 200 PCIE_LNK_X4 = 0x04, 201 PCIE_LNK_X8 = 0x08, 202 PCIE_LNK_X12 = 0x0c, 203 PCIE_LNK_X16 = 0x10, 204 PCIE_LNK_X32 = 0x20, 205 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 206 }; 207 208 #define PCIE_LINK_STATE_L0S 0x00000001 209 #define PCIE_LINK_STATE_L1 0x00000002 210 #define PCIE_LINK_STATE_CLKPM 0x00000004 211 212 typedef int pci_power_t; 213 214 #define PCI_D0 PCI_POWERSTATE_D0 215 #define PCI_D1 PCI_POWERSTATE_D1 216 #define PCI_D2 PCI_POWERSTATE_D2 217 #define PCI_D3hot PCI_POWERSTATE_D3 218 #define PCI_D3cold 4 219 220 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 221 222 extern const char *pci_power_names[6]; 223 224 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 225 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 226 227 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 228 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 229 230 #define PCI_L1SS_CTL1 0x8 231 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 232 233 #define PCI_IRQ_LEGACY 0x01 234 #define PCI_IRQ_MSI 0x02 235 #define PCI_IRQ_MSIX 0x04 236 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 237 238 struct pci_dev; 239 240 struct pci_driver { 241 struct list_head node; 242 char *name; 243 const struct pci_device_id *id_table; 244 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 245 void (*remove)(struct pci_dev *dev); 246 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 247 int (*resume) (struct pci_dev *dev); /* Device woken up */ 248 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 249 driver_t bsddriver; 250 devclass_t bsdclass; 251 struct device_driver driver; 252 const struct pci_error_handlers *err_handler; 253 bool isdrm; 254 int bsd_probe_return; 255 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 256 const nvlist_t *pf_config); 257 void (*bsd_iov_uninit)(device_t dev); 258 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 259 const nvlist_t *vf_config); 260 }; 261 262 struct pci_bus { 263 struct pci_dev *self; 264 /* struct pci_bus *parent */ 265 int domain; 266 int number; 267 }; 268 269 extern struct list_head pci_drivers; 270 extern struct list_head pci_devices; 271 extern spinlock_t pci_lock; 272 273 #define __devexit_p(x) x 274 275 #define module_pci_driver(_driver) \ 276 \ 277 static inline int \ 278 _pci_init(void) \ 279 { \ 280 \ 281 return (linux_pci_register_driver(&_driver)); \ 282 } \ 283 \ 284 static inline void \ 285 _pci_exit(void) \ 286 { \ 287 \ 288 linux_pci_unregister_driver(&_driver); \ 289 } \ 290 \ 291 module_init(_pci_init); \ 292 module_exit(_pci_exit) 293 294 struct msi_msg { 295 uint32_t data; 296 }; 297 298 struct pci_msi_desc { 299 struct { 300 bool is_64; 301 } msi_attrib; 302 }; 303 304 struct msi_desc { 305 struct msi_msg msg; 306 struct pci_msi_desc pci; 307 }; 308 309 /* 310 * If we find drivers accessing this from multiple KPIs we may have to 311 * refcount objects of this structure. 312 */ 313 struct pci_mmio_region { 314 TAILQ_ENTRY(pci_mmio_region) next; 315 struct resource *res; 316 int rid; 317 int type; 318 }; 319 320 struct pci_dev { 321 struct device dev; 322 struct list_head links; 323 struct pci_driver *pdrv; 324 struct pci_bus *bus; 325 struct pci_dev *root; 326 pci_power_t current_state; 327 uint16_t device; 328 uint16_t vendor; 329 uint16_t subsystem_vendor; 330 uint16_t subsystem_device; 331 unsigned int irq; 332 unsigned int devfn; 333 uint32_t class; 334 uint8_t revision; 335 uint8_t msi_cap; 336 uint8_t msix_cap; 337 bool managed; /* devres "pcim_*(). */ 338 bool want_iomap_res; 339 bool msi_enabled; 340 bool msix_enabled; 341 phys_addr_t rom; 342 size_t romlen; 343 struct msi_desc **msi_desc; 344 char *path_name; 345 346 TAILQ_HEAD(, pci_mmio_region) mmio; 347 }; 348 349 /* We need some meta-struct to keep track of these for devres. */ 350 struct pci_devres { 351 bool enable_io; 352 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 353 uint8_t region_mask; 354 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 355 }; 356 struct pcim_iomap_devres { 357 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 358 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 359 }; 360 361 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 362 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 363 unsigned int flags); 364 bool pci_device_is_present(struct pci_dev *pdev); 365 366 /* Internal helper function(s). */ 367 struct pci_dev *lkpinew_pci_dev(device_t); 368 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev); 369 void lkpi_pci_devres_release(struct device *, void *); 370 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size); 371 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev); 372 void lkpi_pcim_iomap_table_release(struct device *, void *); 373 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 374 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 375 376 static inline bool 377 dev_is_pci(struct device *dev) 378 { 379 380 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 381 } 382 383 static inline int 384 pci_resource_type(struct pci_dev *pdev, int bar) 385 { 386 struct pci_map *pm; 387 388 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 389 if (!pm) 390 return (-1); 391 392 if (PCI_BAR_IO(pm->pm_value)) 393 return (SYS_RES_IOPORT); 394 else 395 return (SYS_RES_MEMORY); 396 } 397 398 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 399 struct resource_list *rl, int type, int rid); 400 401 static inline struct resource_list_entry * 402 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 403 { 404 struct pci_devinfo *dinfo; 405 struct resource_list *rl; 406 struct resource_list_entry *rle; 407 408 dinfo = device_get_ivars(pdev->dev.bsddev); 409 rl = &dinfo->resources; 410 rle = resource_list_find(rl, type, rid); 411 /* Reserve resources for this BAR if needed. */ 412 if (rle == NULL && reserve_bar) 413 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 414 return (rle); 415 } 416 417 static inline struct resource_list_entry * 418 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 419 { 420 int type; 421 422 type = pci_resource_type(pdev, bar); 423 if (type < 0) 424 return (NULL); 425 bar = PCIR_BAR(bar); 426 return (linux_pci_get_rle(pdev, type, bar, reserve)); 427 } 428 429 static inline struct device * 430 linux_pci_find_irq_dev(unsigned int irq) 431 { 432 struct pci_dev *pdev; 433 struct device *found; 434 435 found = NULL; 436 spin_lock(&pci_lock); 437 list_for_each_entry(pdev, &pci_devices, links) { 438 if (irq == pdev->dev.irq || 439 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 440 found = &pdev->dev; 441 break; 442 } 443 } 444 spin_unlock(&pci_lock); 445 return (found); 446 } 447 448 /* 449 * All drivers just seem to want to inspect the type not flags. 450 */ 451 static inline int 452 pci_resource_flags(struct pci_dev *pdev, int bar) 453 { 454 int type; 455 456 type = pci_resource_type(pdev, bar); 457 if (type < 0) 458 return (0); 459 return (1 << type); 460 } 461 462 static inline const char * 463 pci_name(struct pci_dev *d) 464 { 465 return d->path_name; 466 } 467 468 static inline void * 469 pci_get_drvdata(struct pci_dev *pdev) 470 { 471 472 return dev_get_drvdata(&pdev->dev); 473 } 474 475 static inline void 476 pci_set_drvdata(struct pci_dev *pdev, void *data) 477 { 478 479 dev_set_drvdata(&pdev->dev, data); 480 } 481 482 static inline struct pci_dev * 483 pci_dev_get(struct pci_dev *pdev) 484 { 485 486 if (pdev != NULL) 487 get_device(&pdev->dev); 488 return (pdev); 489 } 490 491 static __inline void 492 pci_dev_put(struct pci_dev *pdev) 493 { 494 495 if (pdev != NULL) 496 put_device(&pdev->dev); 497 } 498 499 static inline int 500 pci_enable_device(struct pci_dev *pdev) 501 { 502 503 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 504 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 505 return (0); 506 } 507 508 static inline void 509 pci_disable_device(struct pci_dev *pdev) 510 { 511 512 pci_disable_busmaster(pdev->dev.bsddev); 513 } 514 515 static inline int 516 pci_set_master(struct pci_dev *pdev) 517 { 518 519 pci_enable_busmaster(pdev->dev.bsddev); 520 return (0); 521 } 522 523 static inline int 524 pci_set_power_state(struct pci_dev *pdev, int state) 525 { 526 527 pci_set_powerstate(pdev->dev.bsddev, state); 528 return (0); 529 } 530 531 static inline int 532 pci_clear_master(struct pci_dev *pdev) 533 { 534 535 pci_disable_busmaster(pdev->dev.bsddev); 536 return (0); 537 } 538 539 static inline bool 540 pci_is_root_bus(struct pci_bus *pbus) 541 { 542 543 return (pbus->self == NULL); 544 } 545 546 static inline struct pci_dev * 547 pci_upstream_bridge(struct pci_dev *pdev) 548 { 549 550 if (pci_is_root_bus(pdev->bus)) 551 return (NULL); 552 553 /* 554 * If we do not have a (proper) "upstream bridge" set, e.g., we point 555 * to ourselves, try to handle this case on the fly like we do 556 * for pcie_find_root_port(). 557 */ 558 if (pdev == pdev->bus->self) { 559 device_t bridge; 560 561 bridge = device_get_parent(pdev->dev.bsddev); 562 if (bridge == NULL) 563 goto done; 564 bridge = device_get_parent(bridge); 565 if (bridge == NULL) 566 goto done; 567 if (device_get_devclass(device_get_parent(bridge)) != 568 devclass_find("pci")) 569 goto done; 570 571 /* 572 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 573 * for it so it can be returned. 574 */ 575 pdev->bus->self = lkpinew_pci_dev(bridge); 576 } 577 done: 578 return (pdev->bus->self); 579 } 580 581 static inline struct pci_devres * 582 lkpi_pci_devres_find(struct pci_dev *pdev) 583 { 584 585 if (!pdev->managed) 586 return (NULL); 587 588 return (lkpi_pci_devres_get_alloc(pdev)); 589 } 590 591 static inline void 592 pci_release_region(struct pci_dev *pdev, int bar) 593 { 594 struct resource_list_entry *rle; 595 struct pci_devres *dr; 596 struct pci_mmio_region *mmio, *p; 597 598 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 599 return; 600 601 /* 602 * As we implicitly track the requests we also need to clear them on 603 * release. Do clear before resource release. 604 */ 605 dr = lkpi_pci_devres_find(pdev); 606 if (dr != NULL) { 607 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 608 " region_table res %p != rel->res %p\n", __func__, pdev, 609 bar, dr->region_table[bar], rle->res)); 610 dr->region_table[bar] = NULL; 611 dr->region_mask &= ~(1 << bar); 612 } 613 614 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 615 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 616 continue; 617 TAILQ_REMOVE(&pdev->mmio, mmio, next); 618 free(mmio, M_DEVBUF); 619 } 620 621 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 622 } 623 624 static inline void 625 pci_release_regions(struct pci_dev *pdev) 626 { 627 int i; 628 629 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 630 pci_release_region(pdev, i); 631 } 632 633 static inline int 634 pci_request_regions(struct pci_dev *pdev, const char *res_name) 635 { 636 int error; 637 int i; 638 639 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 640 error = pci_request_region(pdev, i, res_name); 641 if (error && error != -ENODEV) { 642 pci_release_regions(pdev); 643 return (error); 644 } 645 } 646 return (0); 647 } 648 649 static inline void 650 lkpi_pci_disable_msix(struct pci_dev *pdev) 651 { 652 653 pci_release_msi(pdev->dev.bsddev); 654 655 /* 656 * The MSIX IRQ numbers associated with this PCI device are no 657 * longer valid and might be re-assigned. Make sure 658 * linux_pci_find_irq_dev() does no longer see them by 659 * resetting their references to zero: 660 */ 661 pdev->dev.irq_start = 0; 662 pdev->dev.irq_end = 0; 663 pdev->msix_enabled = false; 664 } 665 /* Only for consistency. No conflict on that one. */ 666 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 667 668 static inline void 669 lkpi_pci_disable_msi(struct pci_dev *pdev) 670 { 671 672 pci_release_msi(pdev->dev.bsddev); 673 674 pdev->dev.irq_start = 0; 675 pdev->dev.irq_end = 0; 676 pdev->irq = pdev->dev.irq; 677 pdev->msi_enabled = false; 678 } 679 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 680 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 681 682 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 683 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 684 685 static inline bus_addr_t 686 pci_bus_address(struct pci_dev *pdev, int bar) 687 { 688 689 return (pci_resource_start(pdev, bar)); 690 } 691 692 #define PCI_CAP_ID_EXP PCIY_EXPRESS 693 #define PCI_CAP_ID_PCIX PCIY_PCIX 694 #define PCI_CAP_ID_AGP PCIY_AGP 695 #define PCI_CAP_ID_PM PCIY_PMG 696 697 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 698 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 699 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 700 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 701 #define PCI_EXP_LNKSTA PCIER_LINK_STA 702 703 static inline int 704 pci_find_capability(struct pci_dev *pdev, int capid) 705 { 706 int reg; 707 708 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 709 return (0); 710 return (reg); 711 } 712 713 static inline int pci_pcie_cap(struct pci_dev *dev) 714 { 715 return pci_find_capability(dev, PCI_CAP_ID_EXP); 716 } 717 718 static inline int 719 pci_find_ext_capability(struct pci_dev *pdev, int capid) 720 { 721 int reg; 722 723 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 724 return (0); 725 return (reg); 726 } 727 728 #define PCIM_PCAP_PME_SHIFT 11 729 static __inline bool 730 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 731 { 732 struct pci_devinfo *dinfo; 733 pcicfgregs *cfg; 734 735 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 736 return (false); 737 738 dinfo = device_get_ivars(pdev->dev.bsddev); 739 cfg = &dinfo->cfg; 740 741 if (cfg->pp.pp_cap == 0) 742 return (false); 743 744 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 745 return (true); 746 747 return (false); 748 } 749 750 static inline int 751 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 752 { 753 754 if (!pci_enable_aspm) 755 return (-EPERM); 756 757 return (-ENXIO); 758 } 759 760 static inline int 761 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 762 { 763 764 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 765 return (0); 766 } 767 768 static inline int 769 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 770 { 771 772 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 773 return (0); 774 } 775 776 static inline int 777 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 778 { 779 780 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 781 return (0); 782 } 783 784 static inline int 785 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 786 { 787 788 pci_write_config(pdev->dev.bsddev, where, val, 1); 789 return (0); 790 } 791 792 static inline int 793 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 794 { 795 796 pci_write_config(pdev->dev.bsddev, where, val, 2); 797 return (0); 798 } 799 800 static inline int 801 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 802 { 803 804 pci_write_config(pdev->dev.bsddev, where, val, 4); 805 return (0); 806 } 807 808 int linux_pci_register_driver(struct pci_driver *pdrv); 809 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 810 void linux_pci_unregister_driver(struct pci_driver *pdrv); 811 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 812 813 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 814 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 815 816 struct msix_entry { 817 int entry; 818 int vector; 819 }; 820 821 /* 822 * Enable msix, positive errors indicate actual number of available 823 * vectors. Negative errors are failures. 824 * 825 * NB: define added to prevent this definition of pci_enable_msix from 826 * clashing with the native FreeBSD version. 827 */ 828 #define pci_enable_msix(...) \ 829 linux_pci_enable_msix(__VA_ARGS__) 830 831 static inline int 832 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 833 { 834 struct resource_list_entry *rle; 835 int error; 836 int avail; 837 int i; 838 839 avail = pci_msix_count(pdev->dev.bsddev); 840 if (avail < nreq) { 841 if (avail == 0) 842 return -EINVAL; 843 return avail; 844 } 845 avail = nreq; 846 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 847 return error; 848 /* 849 * Handle case where "pci_alloc_msix()" may allocate less 850 * interrupts than available and return with no error: 851 */ 852 if (avail < nreq) { 853 pci_release_msi(pdev->dev.bsddev); 854 return avail; 855 } 856 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 857 pdev->dev.irq_start = rle->start; 858 pdev->dev.irq_end = rle->start + avail; 859 for (i = 0; i < nreq; i++) 860 entries[i].vector = pdev->dev.irq_start + i; 861 pdev->msix_enabled = true; 862 return (0); 863 } 864 865 #define pci_enable_msix_range(...) \ 866 linux_pci_enable_msix_range(__VA_ARGS__) 867 868 static inline int 869 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 870 int minvec, int maxvec) 871 { 872 int nvec = maxvec; 873 int rc; 874 875 if (maxvec < minvec) 876 return (-ERANGE); 877 878 do { 879 rc = pci_enable_msix(dev, entries, nvec); 880 if (rc < 0) { 881 return (rc); 882 } else if (rc > 0) { 883 if (rc < minvec) 884 return (-ENOSPC); 885 nvec = rc; 886 } 887 } while (rc); 888 return (nvec); 889 } 890 891 #define pci_enable_msi(pdev) \ 892 linux_pci_enable_msi(pdev) 893 894 static inline int 895 _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec) 896 { 897 struct resource_list_entry *rle; 898 int error; 899 int nvec; 900 901 if (maxvec < minvec) 902 return (-EINVAL); 903 904 nvec = pci_msi_count(pdev->dev.bsddev); 905 if (nvec < 1 || nvec < minvec) 906 return (-ENOSPC); 907 908 nvec = min(nvec, maxvec); 909 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &nvec)) != 0) 910 return error; 911 912 /* Native PCI might only ever ask for 32 vectors. */ 913 if (nvec < minvec) { 914 pci_release_msi(pdev->dev.bsddev); 915 return (-ENOSPC); 916 } 917 918 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 919 pdev->dev.irq_start = rle->start; 920 pdev->dev.irq_end = rle->start + nvec; 921 pdev->irq = rle->start; 922 pdev->msi_enabled = true; 923 return (0); 924 } 925 926 static inline int 927 pci_enable_msi(struct pci_dev *pdev) 928 { 929 930 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 931 } 932 933 static inline int 934 pci_channel_offline(struct pci_dev *pdev) 935 { 936 937 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 938 } 939 940 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 941 { 942 return -ENODEV; 943 } 944 945 static inline void pci_disable_sriov(struct pci_dev *dev) 946 { 947 } 948 949 static inline void * 950 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 951 { 952 struct resource *res; 953 954 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 955 if (res == NULL) 956 return (NULL); 957 /* This is a FreeBSD extension so we can use bus_*(). */ 958 if (pdev->want_iomap_res) 959 return (res); 960 return ((void *)rman_get_bushandle(res)); 961 } 962 963 static inline void 964 pci_iounmap(struct pci_dev *pdev, void *res) 965 { 966 struct pci_mmio_region *mmio, *p; 967 968 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 969 if (res != (void *)rman_get_bushandle(mmio->res)) 970 continue; 971 bus_release_resource(pdev->dev.bsddev, 972 mmio->type, mmio->rid, mmio->res); 973 TAILQ_REMOVE(&pdev->mmio, mmio, next); 974 free(mmio, M_DEVBUF); 975 return; 976 } 977 } 978 979 static inline void 980 lkpi_pci_save_state(struct pci_dev *pdev) 981 { 982 983 pci_save_state(pdev->dev.bsddev); 984 } 985 986 static inline void 987 lkpi_pci_restore_state(struct pci_dev *pdev) 988 { 989 990 pci_restore_state(pdev->dev.bsddev); 991 } 992 993 #define pci_save_state(dev) lkpi_pci_save_state(dev) 994 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 995 996 static inline int 997 pci_reset_function(struct pci_dev *pdev) 998 { 999 1000 return (-ENOSYS); 1001 } 1002 1003 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 1004 const struct pci_device_id _table[] __devinitdata 1005 1006 /* XXX This should not be necessary. */ 1007 #define pcix_set_mmrbc(d, v) 0 1008 #define pcix_get_max_mmrbc(d) 0 1009 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 1010 1011 #define PCI_DMA_BIDIRECTIONAL 0 1012 #define PCI_DMA_TODEVICE 1 1013 #define PCI_DMA_FROMDEVICE 2 1014 #define PCI_DMA_NONE 3 1015 1016 #define pci_pool dma_pool 1017 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 1018 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 1019 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 1020 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 1021 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 1022 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 1023 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1024 _size, _vaddr, _dma_handle) 1025 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 1026 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1027 _sg, _nents, (enum dma_data_direction)_dir) 1028 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 1029 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1030 (_ptr), (_size), (enum dma_data_direction)_dir) 1031 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 1032 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1033 _addr, _size, (enum dma_data_direction)_dir) 1034 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 1035 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1036 _sg, _nents, (enum dma_data_direction)_dir) 1037 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 1038 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 1039 _offset, _size, (enum dma_data_direction)_dir) 1040 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 1041 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1042 _dma_address, _size, (enum dma_data_direction)_dir) 1043 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1044 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1045 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1046 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1047 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1048 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1049 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1050 #define pci_unmap_addr dma_unmap_addr 1051 #define pci_unmap_addr_set dma_unmap_addr_set 1052 #define pci_unmap_len dma_unmap_len 1053 #define pci_unmap_len_set dma_unmap_len_set 1054 1055 typedef unsigned int __bitwise pci_channel_state_t; 1056 typedef unsigned int __bitwise pci_ers_result_t; 1057 1058 enum pci_channel_state { 1059 pci_channel_io_normal = 1, 1060 pci_channel_io_frozen = 2, 1061 pci_channel_io_perm_failure = 3, 1062 }; 1063 1064 enum pci_ers_result { 1065 PCI_ERS_RESULT_NONE = 1, 1066 PCI_ERS_RESULT_CAN_RECOVER = 2, 1067 PCI_ERS_RESULT_NEED_RESET = 3, 1068 PCI_ERS_RESULT_DISCONNECT = 4, 1069 PCI_ERS_RESULT_RECOVERED = 5, 1070 }; 1071 1072 /* PCI bus error event callbacks */ 1073 struct pci_error_handlers { 1074 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1075 enum pci_channel_state error); 1076 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1077 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1078 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1079 void (*resume)(struct pci_dev *dev); 1080 }; 1081 1082 /* FreeBSD does not support SRIOV - yet */ 1083 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1084 { 1085 return dev; 1086 } 1087 1088 static inline bool pci_is_pcie(struct pci_dev *dev) 1089 { 1090 return !!pci_pcie_cap(dev); 1091 } 1092 1093 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1094 { 1095 int pos; 1096 u16 reg16; 1097 1098 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1099 if (!pos) 1100 return 0; 1101 1102 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1103 1104 return reg16; 1105 } 1106 1107 static inline int pci_pcie_type(struct pci_dev *dev) 1108 { 1109 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1110 } 1111 1112 static inline int pcie_cap_version(struct pci_dev *dev) 1113 { 1114 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1115 } 1116 1117 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1118 { 1119 int type = pci_pcie_type(dev); 1120 1121 return pcie_cap_version(dev) > 1 || 1122 type == PCI_EXP_TYPE_ROOT_PORT || 1123 type == PCI_EXP_TYPE_ENDPOINT || 1124 type == PCI_EXP_TYPE_LEG_END; 1125 } 1126 1127 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1128 { 1129 return true; 1130 } 1131 1132 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1133 { 1134 int type = pci_pcie_type(dev); 1135 1136 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1137 (type == PCI_EXP_TYPE_DOWNSTREAM && 1138 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1139 } 1140 1141 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1142 { 1143 int type = pci_pcie_type(dev); 1144 1145 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1146 type == PCI_EXP_TYPE_RC_EC; 1147 } 1148 1149 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1150 { 1151 if (!pci_is_pcie(dev)) 1152 return false; 1153 1154 switch (pos) { 1155 case PCI_EXP_FLAGS_TYPE: 1156 return true; 1157 case PCI_EXP_DEVCAP: 1158 case PCI_EXP_DEVCTL: 1159 case PCI_EXP_DEVSTA: 1160 return pcie_cap_has_devctl(dev); 1161 case PCI_EXP_LNKCAP: 1162 case PCI_EXP_LNKCTL: 1163 case PCI_EXP_LNKSTA: 1164 return pcie_cap_has_lnkctl(dev); 1165 case PCI_EXP_SLTCAP: 1166 case PCI_EXP_SLTCTL: 1167 case PCI_EXP_SLTSTA: 1168 return pcie_cap_has_sltctl(dev); 1169 case PCI_EXP_RTCTL: 1170 case PCI_EXP_RTCAP: 1171 case PCI_EXP_RTSTA: 1172 return pcie_cap_has_rtctl(dev); 1173 case PCI_EXP_DEVCAP2: 1174 case PCI_EXP_DEVCTL2: 1175 case PCI_EXP_LNKCAP2: 1176 case PCI_EXP_LNKCTL2: 1177 case PCI_EXP_LNKSTA2: 1178 return pcie_cap_version(dev) > 1; 1179 default: 1180 return false; 1181 } 1182 } 1183 1184 static inline int 1185 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1186 { 1187 *dst = 0; 1188 if (pos & 3) 1189 return -EINVAL; 1190 1191 if (!pcie_capability_reg_implemented(dev, pos)) 1192 return -EINVAL; 1193 1194 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1195 } 1196 1197 static inline int 1198 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1199 { 1200 *dst = 0; 1201 if (pos & 3) 1202 return -EINVAL; 1203 1204 if (!pcie_capability_reg_implemented(dev, pos)) 1205 return -EINVAL; 1206 1207 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1208 } 1209 1210 static inline int 1211 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1212 { 1213 if (pos & 1) 1214 return -EINVAL; 1215 1216 if (!pcie_capability_reg_implemented(dev, pos)) 1217 return 0; 1218 1219 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1220 } 1221 1222 static inline int 1223 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1224 { 1225 int error; 1226 uint16_t v; 1227 1228 error = pcie_capability_read_word(dev, pos, &v); 1229 if (error != 0) 1230 return (error); 1231 1232 v |= val; 1233 1234 error = pcie_capability_write_word(dev, pos, v); 1235 return (error); 1236 } 1237 1238 static inline int 1239 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1240 { 1241 int error; 1242 uint16_t v; 1243 1244 error = pcie_capability_read_word(dev, pos, &v); 1245 if (error != 0) 1246 return (error); 1247 1248 v &= ~val; 1249 1250 error = pcie_capability_write_word(dev, pos, v); 1251 return (error); 1252 } 1253 1254 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1255 enum pci_bus_speed *speed, enum pcie_link_width *width) 1256 { 1257 *speed = PCI_SPEED_UNKNOWN; 1258 *width = PCIE_LNK_WIDTH_UNKNOWN; 1259 return (0); 1260 } 1261 1262 static inline int 1263 pci_num_vf(struct pci_dev *dev) 1264 { 1265 return (0); 1266 } 1267 1268 static inline enum pci_bus_speed 1269 pcie_get_speed_cap(struct pci_dev *dev) 1270 { 1271 device_t root; 1272 uint32_t lnkcap, lnkcap2; 1273 int error, pos; 1274 1275 root = device_get_parent(dev->dev.bsddev); 1276 if (root == NULL) 1277 return (PCI_SPEED_UNKNOWN); 1278 root = device_get_parent(root); 1279 if (root == NULL) 1280 return (PCI_SPEED_UNKNOWN); 1281 root = device_get_parent(root); 1282 if (root == NULL) 1283 return (PCI_SPEED_UNKNOWN); 1284 1285 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1286 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1287 return (PCI_SPEED_UNKNOWN); 1288 1289 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1290 return (PCI_SPEED_UNKNOWN); 1291 1292 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1293 1294 if (lnkcap2) { /* PCIe r3.0-compliant */ 1295 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1296 return (PCIE_SPEED_2_5GT); 1297 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1298 return (PCIE_SPEED_5_0GT); 1299 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1300 return (PCIE_SPEED_8_0GT); 1301 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1302 return (PCIE_SPEED_16_0GT); 1303 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1304 return (PCIE_SPEED_32_0GT); 1305 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1306 return (PCIE_SPEED_64_0GT); 1307 } else { /* pre-r3.0 */ 1308 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1309 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1310 return (PCIE_SPEED_2_5GT); 1311 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1312 return (PCIE_SPEED_5_0GT); 1313 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1314 return (PCIE_SPEED_8_0GT); 1315 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1316 return (PCIE_SPEED_16_0GT); 1317 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1318 return (PCIE_SPEED_32_0GT); 1319 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1320 return (PCIE_SPEED_64_0GT); 1321 } 1322 return (PCI_SPEED_UNKNOWN); 1323 } 1324 1325 static inline enum pcie_link_width 1326 pcie_get_width_cap(struct pci_dev *dev) 1327 { 1328 uint32_t lnkcap; 1329 1330 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1331 if (lnkcap) 1332 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1333 1334 return (PCIE_LNK_WIDTH_UNKNOWN); 1335 } 1336 1337 static inline int 1338 pcie_get_mps(struct pci_dev *dev) 1339 { 1340 return (pci_get_max_payload(dev->dev.bsddev)); 1341 } 1342 1343 static inline uint32_t 1344 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1345 { 1346 1347 switch(spd) { 1348 case PCIE_SPEED_64_0GT: 1349 return (64000 * 128 / 130); 1350 case PCIE_SPEED_32_0GT: 1351 return (32000 * 128 / 130); 1352 case PCIE_SPEED_16_0GT: 1353 return (16000 * 128 / 130); 1354 case PCIE_SPEED_8_0GT: 1355 return (8000 * 128 / 130); 1356 case PCIE_SPEED_5_0GT: 1357 return (5000 * 8 / 10); 1358 case PCIE_SPEED_2_5GT: 1359 return (2500 * 8 / 10); 1360 default: 1361 return (0); 1362 } 1363 } 1364 1365 static inline uint32_t 1366 pcie_bandwidth_available(struct pci_dev *pdev, 1367 struct pci_dev **limiting, 1368 enum pci_bus_speed *speed, 1369 enum pcie_link_width *width) 1370 { 1371 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1372 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1373 1374 if (speed) 1375 *speed = nspeed; 1376 if (width) 1377 *width = nwidth; 1378 1379 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1380 } 1381 1382 static inline bool 1383 pcie_aspm_enabled(struct pci_dev *pdev) 1384 { 1385 return (false); 1386 } 1387 1388 static inline struct pci_dev * 1389 pcie_find_root_port(struct pci_dev *pdev) 1390 { 1391 device_t root; 1392 1393 if (pdev->root != NULL) 1394 return (pdev->root); 1395 1396 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1397 if (root == NULL) 1398 return (NULL); 1399 1400 pdev->root = lkpinew_pci_dev(root); 1401 return (pdev->root); 1402 } 1403 1404 /* This is needed when people rip out the device "HotPlug". */ 1405 static inline void 1406 pci_lock_rescan_remove(void) 1407 { 1408 } 1409 1410 static inline void 1411 pci_unlock_rescan_remove(void) 1412 { 1413 } 1414 1415 static __inline void 1416 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1417 { 1418 } 1419 1420 static inline int 1421 pci_rescan_bus(struct pci_bus *pbus) 1422 { 1423 device_t *devlist, parent; 1424 int devcount, error; 1425 1426 if (!device_is_attached(pbus->self->dev.bsddev)) 1427 return (0); 1428 /* pci_rescan_method() will work on the pcib (parent). */ 1429 error = BUS_RESCAN(pbus->self->dev.bsddev); 1430 if (error != 0) 1431 return (0); 1432 1433 parent = device_get_parent(pbus->self->dev.bsddev); 1434 error = device_get_children(parent, &devlist, &devcount); 1435 if (error != 0) 1436 return (0); 1437 if (devcount != 0) 1438 free(devlist, M_TEMP); 1439 1440 return (devcount); 1441 } 1442 1443 /* 1444 * The following functions can be used to attach/detach the LinuxKPI's 1445 * PCI device runtime. The pci_driver and pci_device_id pointer is 1446 * allowed to be NULL. Other pointers must be all valid. 1447 * The pci_dev structure should be zero-initialized before passed 1448 * to the linux_pci_attach_device function. 1449 */ 1450 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1451 const struct pci_device_id *, struct pci_dev *); 1452 extern int linux_pci_detach_device(struct pci_dev *); 1453 1454 static inline int 1455 pci_dev_present(const struct pci_device_id *cur) 1456 { 1457 while (cur != NULL && (cur->vendor || cur->device)) { 1458 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1459 return (1); 1460 } 1461 cur++; 1462 } 1463 return (0); 1464 } 1465 1466 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1467 unsigned int bus, unsigned int devfn); 1468 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1469 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1470 1471 static inline int 1472 pci_domain_nr(struct pci_bus *pbus) 1473 { 1474 1475 return (pbus->domain); 1476 } 1477 1478 static inline int 1479 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1480 int pos, uint32_t *val, int len) 1481 { 1482 1483 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1484 return (0); 1485 } 1486 1487 static inline int 1488 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1489 { 1490 uint32_t tmp; 1491 int ret; 1492 1493 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1494 *val = (u16)tmp; 1495 return (ret); 1496 } 1497 1498 static inline int 1499 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1500 { 1501 uint32_t tmp; 1502 int ret; 1503 1504 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1505 *val = (u8)tmp; 1506 return (ret); 1507 } 1508 1509 static inline int 1510 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1511 uint32_t val, int size) 1512 { 1513 1514 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1515 return (0); 1516 } 1517 1518 static inline int 1519 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1520 uint8_t val) 1521 { 1522 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1523 } 1524 1525 static inline int 1526 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1527 uint16_t val) 1528 { 1529 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1530 } 1531 1532 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1533 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1534 1535 /* -------------------------------------------------------------------------- */ 1536 1537 static inline int 1538 pcim_enable_device(struct pci_dev *pdev) 1539 { 1540 struct pci_devres *dr; 1541 int error; 1542 1543 /* Here we cannot run through the pdev->managed check. */ 1544 dr = lkpi_pci_devres_get_alloc(pdev); 1545 if (dr == NULL) 1546 return (-ENOMEM); 1547 1548 /* If resources were enabled before do not do it again. */ 1549 if (dr->enable_io) 1550 return (0); 1551 1552 error = pci_enable_device(pdev); 1553 if (error == 0) 1554 dr->enable_io = true; 1555 1556 /* This device is not managed. */ 1557 pdev->managed = true; 1558 1559 return (error); 1560 } 1561 1562 static inline void __iomem ** 1563 pcim_iomap_table(struct pci_dev *pdev) 1564 { 1565 struct pcim_iomap_devres *dr; 1566 1567 dr = lkpi_pcim_iomap_devres_find(pdev); 1568 if (dr == NULL) 1569 return (NULL); 1570 1571 /* 1572 * If the driver has manually set a flag to be able to request the 1573 * resource to use bus_read/write_<n>, return the shadow table. 1574 */ 1575 if (pdev->want_iomap_res) 1576 return ((void **)dr->res_table); 1577 1578 /* This is the Linux default. */ 1579 return (dr->mmio_table); 1580 } 1581 1582 static inline int 1583 pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, const char *name) 1584 { 1585 struct pcim_iomap_devres *dr; 1586 void *res; 1587 uint32_t mappings; 1588 int bar; 1589 1590 dr = lkpi_pcim_iomap_devres_find(pdev); 1591 if (dr == NULL) 1592 return (-ENOMEM); 1593 1594 /* Now iomap all the requested (by "mask") ones. */ 1595 for (bar = mappings = 0; mappings != mask; bar++) { 1596 if ((mask & (1 << bar)) == 0) 1597 continue; 1598 1599 /* Request double is not allowed. */ 1600 if (dr->mmio_table[bar] != NULL) { 1601 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1602 __func__, bar, dr->mmio_table[bar]); 1603 goto err; 1604 } 1605 1606 res = _lkpi_pci_iomap(pdev, bar, 0); 1607 if (res == NULL) 1608 goto err; 1609 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1610 dr->res_table[bar] = res; 1611 1612 mappings |= (1 << bar); 1613 } 1614 1615 return (0); 1616 err: 1617 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1618 if ((mappings & (1 << bar)) != 0) { 1619 res = dr->mmio_table[bar]; 1620 if (res == NULL) 1621 continue; 1622 pci_iounmap(pdev, res); 1623 } 1624 } 1625 1626 return (-EINVAL); 1627 } 1628 1629 static inline int 1630 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1631 { 1632 uint32_t requests, req_mask; 1633 int bar, error; 1634 1635 /* Request all the BARs ("regions") we do not iomap. */ 1636 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1637 for (bar = requests = 0; requests != req_mask; bar++) { 1638 if ((req_mask & (1 << bar)) == 0) 1639 continue; 1640 error = pci_request_region(pdev, bar, name); 1641 if (error != 0 && error != -ENODEV) 1642 goto err; 1643 requests |= (1 << bar); 1644 } 1645 1646 error = pcim_iomap_regions(pdev, mask, name); 1647 if (error != 0) 1648 goto err; 1649 1650 return (0); 1651 1652 err: 1653 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1654 if ((requests & (1 << bar)) != 0) 1655 pci_release_region(pdev, bar); 1656 } 1657 1658 return (-EINVAL); 1659 } 1660 1661 /* 1662 * We cannot simply re-define pci_get_device() as we would normally do 1663 * and then hide it in linux_pci.c as too many semi-native drivers still 1664 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1665 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1666 */ 1667 static inline struct pci_dev * 1668 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1669 { 1670 1671 return (lkpi_pci_get_device(vendor, device, odev)); 1672 } 1673 1674 /* This is a FreeBSD extension so we can use bus_*(). */ 1675 static inline void 1676 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1677 { 1678 pdev->want_iomap_res = true; 1679 } 1680 1681 static inline bool 1682 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1683 { 1684 1685 return (false); 1686 } 1687 1688 static inline void * 1689 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1690 { 1691 1692 return (NULL); 1693 } 1694 1695 static inline void 1696 pci_ignore_hotplug(struct pci_dev *pdev) 1697 { 1698 } 1699 1700 static inline const char * 1701 pci_power_name(pci_power_t state) 1702 { 1703 int pstate = state + 1; 1704 1705 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1706 return (pci_power_names[pstate]); 1707 else 1708 return (pci_power_names[0]); 1709 } 1710 1711 static inline int 1712 pcie_get_readrq(struct pci_dev *dev) 1713 { 1714 u16 ctl; 1715 1716 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1717 return (-EINVAL); 1718 1719 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1720 } 1721 1722 static inline bool 1723 pci_is_enabled(struct pci_dev *pdev) 1724 { 1725 1726 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1727 PCIM_CMD_BUSMASTEREN) != 0); 1728 } 1729 1730 static inline int 1731 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1732 { 1733 1734 return (0); 1735 } 1736 1737 static inline int 1738 pci_assign_resource(struct pci_dev *pdev, int bar) 1739 { 1740 1741 return (0); 1742 } 1743 1744 static inline int 1745 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1746 { 1747 1748 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1749 if (vector != 0) 1750 return (-EINVAL); 1751 return (pdev->irq); 1752 } 1753 1754 if (pdev->msix_enabled || pdev->msi_enabled) { 1755 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1756 return (-EINVAL); 1757 return (pdev->dev.irq_start + vector); 1758 } 1759 1760 return (-ENXIO); 1761 } 1762 1763 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1764