1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/nv.h> 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 #include <linux/pm.h> 63 64 struct pci_device_id { 65 uint32_t vendor; 66 uint32_t device; 67 uint32_t subvendor; 68 uint32_t subdevice; 69 uint32_t class; 70 uint32_t class_mask; 71 uintptr_t driver_data; 72 }; 73 74 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 75 #define MODULE_DEVICE_TABLE(_bus, _table) \ 76 \ 77 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 78 DEVMETHOD_END \ 79 }; \ 80 \ 81 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 82 "lkpi_" #_bus #_table, \ 83 _ ## _bus ## _ ## _table ## _methods, \ 84 0 \ 85 }; \ 86 \ 87 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 88 0, 0); \ 89 \ 90 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 91 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 92 93 #define PCI_ANY_ID -1U 94 95 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 96 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 97 #define PCI_FUNC(devfn) ((devfn) & 0x07) 98 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 99 100 #define PCI_VDEVICE(_vendor, _device) \ 101 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 102 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 103 #define PCI_DEVICE(_vendor, _device) \ 104 .vendor = (_vendor), .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 107 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 108 109 #define PCI_STD_NUM_BARS 6 110 #define PCI_VENDOR_ID PCIR_VENDOR 111 #define PCI_DEVICE_ID PCIR_DEVICE 112 #define PCI_COMMAND PCIR_COMMAND 113 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 114 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 115 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 116 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 117 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 118 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 119 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 120 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 121 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 122 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 123 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 124 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 125 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 126 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 127 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 128 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 129 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 130 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 131 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 132 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 133 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 134 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 135 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 136 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 137 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 138 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 139 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 140 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 141 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 142 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 143 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 144 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 145 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 146 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 147 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 148 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 149 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 150 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 151 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 152 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 153 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 154 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 155 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 156 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 157 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 158 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 159 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 160 #define PCI_EXP_LNKCTL2_TLS 0x000f 161 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 162 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 163 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 164 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 165 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 166 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 167 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 168 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 169 170 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 171 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 172 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 173 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 174 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 175 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 176 177 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 178 #define PCI_EXP_DEVSTA_TRPND 0x0020 179 180 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 181 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 182 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 183 184 enum pci_bus_speed { 185 PCI_SPEED_UNKNOWN = -1, 186 PCIE_SPEED_2_5GT, 187 PCIE_SPEED_5_0GT, 188 PCIE_SPEED_8_0GT, 189 PCIE_SPEED_16_0GT, 190 PCIE_SPEED_32_0GT, 191 PCIE_SPEED_64_0GT, 192 }; 193 194 enum pcie_link_width { 195 PCIE_LNK_WIDTH_RESRV = 0x00, 196 PCIE_LNK_X1 = 0x01, 197 PCIE_LNK_X2 = 0x02, 198 PCIE_LNK_X4 = 0x04, 199 PCIE_LNK_X8 = 0x08, 200 PCIE_LNK_X12 = 0x0c, 201 PCIE_LNK_X16 = 0x10, 202 PCIE_LNK_X32 = 0x20, 203 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 204 }; 205 206 #define PCIE_LINK_STATE_L0S 0x00000001 207 #define PCIE_LINK_STATE_L1 0x00000002 208 #define PCIE_LINK_STATE_CLKPM 0x00000004 209 210 typedef int pci_power_t; 211 212 #define PCI_D0 PCI_POWERSTATE_D0 213 #define PCI_D1 PCI_POWERSTATE_D1 214 #define PCI_D2 PCI_POWERSTATE_D2 215 #define PCI_D3hot PCI_POWERSTATE_D3 216 #define PCI_D3cold 4 217 218 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 219 220 extern const char *pci_power_names[6]; 221 222 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 223 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 224 225 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 226 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 227 228 #define PCI_L1SS_CTL1 0x8 229 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 230 231 #define PCI_IRQ_LEGACY 0x01 232 #define PCI_IRQ_MSI 0x02 233 #define PCI_IRQ_MSIX 0x04 234 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 235 236 struct pci_dev; 237 238 struct pci_driver { 239 struct list_head node; 240 char *name; 241 const struct pci_device_id *id_table; 242 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 243 void (*remove)(struct pci_dev *dev); 244 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 245 int (*resume) (struct pci_dev *dev); /* Device woken up */ 246 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 247 driver_t bsddriver; 248 devclass_t bsdclass; 249 struct device_driver driver; 250 const struct pci_error_handlers *err_handler; 251 bool isdrm; 252 int bsd_probe_return; 253 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 254 const nvlist_t *pf_config); 255 void (*bsd_iov_uninit)(device_t dev); 256 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 257 const nvlist_t *vf_config); 258 }; 259 260 struct pci_bus { 261 struct pci_dev *self; 262 int domain; 263 int number; 264 }; 265 266 extern struct list_head pci_drivers; 267 extern struct list_head pci_devices; 268 extern spinlock_t pci_lock; 269 270 #define __devexit_p(x) x 271 272 #define module_pci_driver(_driver) \ 273 \ 274 static inline int \ 275 _pci_init(void) \ 276 { \ 277 \ 278 return (linux_pci_register_driver(&_driver)); \ 279 } \ 280 \ 281 static inline void \ 282 _pci_exit(void) \ 283 { \ 284 \ 285 linux_pci_unregister_driver(&_driver); \ 286 } \ 287 \ 288 module_init(_pci_init); \ 289 module_exit(_pci_exit) 290 291 struct msi_msg { 292 uint32_t data; 293 }; 294 295 struct msi_desc { 296 struct msi_msg msg; 297 struct { 298 bool is_64; 299 } msi_attrib; 300 }; 301 302 /* 303 * If we find drivers accessing this from multiple KPIs we may have to 304 * refcount objects of this structure. 305 */ 306 struct pci_mmio_region { 307 TAILQ_ENTRY(pci_mmio_region) next; 308 struct resource *res; 309 int rid; 310 int type; 311 }; 312 313 struct pci_dev { 314 struct device dev; 315 struct list_head links; 316 struct pci_driver *pdrv; 317 struct pci_bus *bus; 318 struct pci_dev *root; 319 pci_power_t current_state; 320 uint16_t device; 321 uint16_t vendor; 322 uint16_t subsystem_vendor; 323 uint16_t subsystem_device; 324 unsigned int irq; 325 unsigned int devfn; 326 uint32_t class; 327 uint8_t revision; 328 uint8_t msi_cap; 329 uint8_t msix_cap; 330 bool managed; /* devres "pcim_*(). */ 331 bool want_iomap_res; 332 bool msi_enabled; 333 bool msix_enabled; 334 phys_addr_t rom; 335 size_t romlen; 336 struct msi_desc **msi_desc; 337 char *path_name; 338 339 TAILQ_HEAD(, pci_mmio_region) mmio; 340 }; 341 342 /* We need some meta-struct to keep track of these for devres. */ 343 struct pci_devres { 344 bool enable_io; 345 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 346 uint8_t region_mask; 347 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 348 }; 349 struct pcim_iomap_devres { 350 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 351 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 352 }; 353 354 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 355 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 356 unsigned int flags); 357 bool pci_device_is_present(struct pci_dev *pdev); 358 359 /* Internal helper function(s). */ 360 struct pci_dev *lkpinew_pci_dev(device_t); 361 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev); 362 void lkpi_pci_devres_release(struct device *, void *); 363 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size); 364 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev); 365 void lkpi_pcim_iomap_table_release(struct device *, void *); 366 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 367 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 368 369 static inline bool 370 dev_is_pci(struct device *dev) 371 { 372 373 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 374 } 375 376 static inline int 377 pci_resource_type(struct pci_dev *pdev, int bar) 378 { 379 struct pci_map *pm; 380 381 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 382 if (!pm) 383 return (-1); 384 385 if (PCI_BAR_IO(pm->pm_value)) 386 return (SYS_RES_IOPORT); 387 else 388 return (SYS_RES_MEMORY); 389 } 390 391 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 392 struct resource_list *rl, int type, int rid); 393 394 static inline struct resource_list_entry * 395 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 396 { 397 struct pci_devinfo *dinfo; 398 struct resource_list *rl; 399 struct resource_list_entry *rle; 400 401 dinfo = device_get_ivars(pdev->dev.bsddev); 402 rl = &dinfo->resources; 403 rle = resource_list_find(rl, type, rid); 404 /* Reserve resources for this BAR if needed. */ 405 if (rle == NULL && reserve_bar) 406 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 407 return (rle); 408 } 409 410 static inline struct resource_list_entry * 411 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 412 { 413 int type; 414 415 type = pci_resource_type(pdev, bar); 416 if (type < 0) 417 return (NULL); 418 bar = PCIR_BAR(bar); 419 return (linux_pci_get_rle(pdev, type, bar, reserve)); 420 } 421 422 static inline struct device * 423 linux_pci_find_irq_dev(unsigned int irq) 424 { 425 struct pci_dev *pdev; 426 struct device *found; 427 428 found = NULL; 429 spin_lock(&pci_lock); 430 list_for_each_entry(pdev, &pci_devices, links) { 431 if (irq == pdev->dev.irq || 432 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 433 found = &pdev->dev; 434 break; 435 } 436 } 437 spin_unlock(&pci_lock); 438 return (found); 439 } 440 441 /* 442 * All drivers just seem to want to inspect the type not flags. 443 */ 444 static inline int 445 pci_resource_flags(struct pci_dev *pdev, int bar) 446 { 447 int type; 448 449 type = pci_resource_type(pdev, bar); 450 if (type < 0) 451 return (0); 452 return (1 << type); 453 } 454 455 static inline const char * 456 pci_name(struct pci_dev *d) 457 { 458 return d->path_name; 459 } 460 461 static inline void * 462 pci_get_drvdata(struct pci_dev *pdev) 463 { 464 465 return dev_get_drvdata(&pdev->dev); 466 } 467 468 static inline void 469 pci_set_drvdata(struct pci_dev *pdev, void *data) 470 { 471 472 dev_set_drvdata(&pdev->dev, data); 473 } 474 475 static inline struct pci_dev * 476 pci_dev_get(struct pci_dev *pdev) 477 { 478 479 if (pdev != NULL) 480 get_device(&pdev->dev); 481 return (pdev); 482 } 483 484 static __inline void 485 pci_dev_put(struct pci_dev *pdev) 486 { 487 488 if (pdev != NULL) 489 put_device(&pdev->dev); 490 } 491 492 static inline int 493 pci_enable_device(struct pci_dev *pdev) 494 { 495 496 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 497 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 498 return (0); 499 } 500 501 static inline void 502 pci_disable_device(struct pci_dev *pdev) 503 { 504 505 pci_disable_busmaster(pdev->dev.bsddev); 506 } 507 508 static inline int 509 pci_set_master(struct pci_dev *pdev) 510 { 511 512 pci_enable_busmaster(pdev->dev.bsddev); 513 return (0); 514 } 515 516 static inline int 517 pci_set_power_state(struct pci_dev *pdev, int state) 518 { 519 520 pci_set_powerstate(pdev->dev.bsddev, state); 521 return (0); 522 } 523 524 static inline int 525 pci_clear_master(struct pci_dev *pdev) 526 { 527 528 pci_disable_busmaster(pdev->dev.bsddev); 529 return (0); 530 } 531 532 static inline bool 533 pci_is_root_bus(struct pci_bus *pbus) 534 { 535 536 return (pbus->self == NULL); 537 } 538 539 static inline struct pci_dev * 540 pci_upstream_bridge(struct pci_dev *pdev) 541 { 542 543 if (pci_is_root_bus(pdev->bus)) 544 return (NULL); 545 546 /* 547 * If we do not have a (proper) "upstream bridge" set, e.g., we point 548 * to ourselves, try to handle this case on the fly like we do 549 * for pcie_find_root_port(). 550 */ 551 if (pdev == pdev->bus->self) { 552 device_t bridge; 553 554 bridge = device_get_parent(pdev->dev.bsddev); 555 if (bridge == NULL) 556 goto done; 557 bridge = device_get_parent(bridge); 558 if (bridge == NULL) 559 goto done; 560 if (device_get_devclass(device_get_parent(bridge)) != 561 devclass_find("pci")) 562 goto done; 563 564 /* 565 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 566 * for it so it can be returned. 567 */ 568 pdev->bus->self = lkpinew_pci_dev(bridge); 569 } 570 done: 571 return (pdev->bus->self); 572 } 573 574 static inline struct pci_devres * 575 lkpi_pci_devres_find(struct pci_dev *pdev) 576 { 577 578 if (!pdev->managed) 579 return (NULL); 580 581 return (lkpi_pci_devres_get_alloc(pdev)); 582 } 583 584 static inline void 585 pci_release_region(struct pci_dev *pdev, int bar) 586 { 587 struct resource_list_entry *rle; 588 struct pci_devres *dr; 589 struct pci_mmio_region *mmio, *p; 590 591 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 592 return; 593 594 /* 595 * As we implicitly track the requests we also need to clear them on 596 * release. Do clear before resource release. 597 */ 598 dr = lkpi_pci_devres_find(pdev); 599 if (dr != NULL) { 600 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 601 " region_table res %p != rel->res %p\n", __func__, pdev, 602 bar, dr->region_table[bar], rle->res)); 603 dr->region_table[bar] = NULL; 604 dr->region_mask &= ~(1 << bar); 605 } 606 607 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 608 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 609 continue; 610 TAILQ_REMOVE(&pdev->mmio, mmio, next); 611 free(mmio, M_DEVBUF); 612 } 613 614 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 615 } 616 617 static inline void 618 pci_release_regions(struct pci_dev *pdev) 619 { 620 int i; 621 622 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 623 pci_release_region(pdev, i); 624 } 625 626 static inline int 627 pci_request_regions(struct pci_dev *pdev, const char *res_name) 628 { 629 int error; 630 int i; 631 632 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 633 error = pci_request_region(pdev, i, res_name); 634 if (error && error != -ENODEV) { 635 pci_release_regions(pdev); 636 return (error); 637 } 638 } 639 return (0); 640 } 641 642 static inline void 643 lkpi_pci_disable_msix(struct pci_dev *pdev) 644 { 645 646 pci_release_msi(pdev->dev.bsddev); 647 648 /* 649 * The MSIX IRQ numbers associated with this PCI device are no 650 * longer valid and might be re-assigned. Make sure 651 * linux_pci_find_irq_dev() does no longer see them by 652 * resetting their references to zero: 653 */ 654 pdev->dev.irq_start = 0; 655 pdev->dev.irq_end = 0; 656 pdev->msix_enabled = false; 657 } 658 /* Only for consistency. No conflict on that one. */ 659 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 660 661 static inline void 662 lkpi_pci_disable_msi(struct pci_dev *pdev) 663 { 664 665 pci_release_msi(pdev->dev.bsddev); 666 667 pdev->dev.irq_start = 0; 668 pdev->dev.irq_end = 0; 669 pdev->irq = pdev->dev.irq; 670 pdev->msi_enabled = false; 671 } 672 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 673 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 674 675 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 676 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 677 678 static inline bus_addr_t 679 pci_bus_address(struct pci_dev *pdev, int bar) 680 { 681 682 return (pci_resource_start(pdev, bar)); 683 } 684 685 #define PCI_CAP_ID_EXP PCIY_EXPRESS 686 #define PCI_CAP_ID_PCIX PCIY_PCIX 687 #define PCI_CAP_ID_AGP PCIY_AGP 688 #define PCI_CAP_ID_PM PCIY_PMG 689 690 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 691 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 692 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 693 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 694 #define PCI_EXP_LNKSTA PCIER_LINK_STA 695 696 static inline int 697 pci_find_capability(struct pci_dev *pdev, int capid) 698 { 699 int reg; 700 701 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 702 return (0); 703 return (reg); 704 } 705 706 static inline int pci_pcie_cap(struct pci_dev *dev) 707 { 708 return pci_find_capability(dev, PCI_CAP_ID_EXP); 709 } 710 711 static inline int 712 pci_find_ext_capability(struct pci_dev *pdev, int capid) 713 { 714 int reg; 715 716 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 717 return (0); 718 return (reg); 719 } 720 721 #define PCIM_PCAP_PME_SHIFT 11 722 static __inline bool 723 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 724 { 725 struct pci_devinfo *dinfo; 726 pcicfgregs *cfg; 727 728 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 729 return (false); 730 731 dinfo = device_get_ivars(pdev->dev.bsddev); 732 cfg = &dinfo->cfg; 733 734 if (cfg->pp.pp_cap == 0) 735 return (false); 736 737 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 738 return (true); 739 740 return (false); 741 } 742 743 static inline int 744 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 745 { 746 747 if (!pci_enable_aspm) 748 return (-EPERM); 749 750 return (-ENXIO); 751 } 752 753 static inline int 754 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 755 { 756 757 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 758 return (0); 759 } 760 761 static inline int 762 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 763 { 764 765 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 766 return (0); 767 } 768 769 static inline int 770 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 771 { 772 773 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 774 return (0); 775 } 776 777 static inline int 778 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 779 { 780 781 pci_write_config(pdev->dev.bsddev, where, val, 1); 782 return (0); 783 } 784 785 static inline int 786 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 787 { 788 789 pci_write_config(pdev->dev.bsddev, where, val, 2); 790 return (0); 791 } 792 793 static inline int 794 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 795 { 796 797 pci_write_config(pdev->dev.bsddev, where, val, 4); 798 return (0); 799 } 800 801 int linux_pci_register_driver(struct pci_driver *pdrv); 802 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 803 void linux_pci_unregister_driver(struct pci_driver *pdrv); 804 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 805 806 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 807 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 808 809 struct msix_entry { 810 int entry; 811 int vector; 812 }; 813 814 /* 815 * Enable msix, positive errors indicate actual number of available 816 * vectors. Negative errors are failures. 817 * 818 * NB: define added to prevent this definition of pci_enable_msix from 819 * clashing with the native FreeBSD version. 820 */ 821 #define pci_enable_msix(...) \ 822 linux_pci_enable_msix(__VA_ARGS__) 823 824 static inline int 825 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 826 { 827 struct resource_list_entry *rle; 828 int error; 829 int avail; 830 int i; 831 832 avail = pci_msix_count(pdev->dev.bsddev); 833 if (avail < nreq) { 834 if (avail == 0) 835 return -EINVAL; 836 return avail; 837 } 838 avail = nreq; 839 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 840 return error; 841 /* 842 * Handle case where "pci_alloc_msix()" may allocate less 843 * interrupts than available and return with no error: 844 */ 845 if (avail < nreq) { 846 pci_release_msi(pdev->dev.bsddev); 847 return avail; 848 } 849 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 850 pdev->dev.irq_start = rle->start; 851 pdev->dev.irq_end = rle->start + avail; 852 for (i = 0; i < nreq; i++) 853 entries[i].vector = pdev->dev.irq_start + i; 854 pdev->msix_enabled = true; 855 return (0); 856 } 857 858 #define pci_enable_msix_range(...) \ 859 linux_pci_enable_msix_range(__VA_ARGS__) 860 861 static inline int 862 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 863 int minvec, int maxvec) 864 { 865 int nvec = maxvec; 866 int rc; 867 868 if (maxvec < minvec) 869 return (-ERANGE); 870 871 do { 872 rc = pci_enable_msix(dev, entries, nvec); 873 if (rc < 0) { 874 return (rc); 875 } else if (rc > 0) { 876 if (rc < minvec) 877 return (-ENOSPC); 878 nvec = rc; 879 } 880 } while (rc); 881 return (nvec); 882 } 883 884 #define pci_enable_msi(pdev) \ 885 linux_pci_enable_msi(pdev) 886 887 static inline int 888 _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec) 889 { 890 struct resource_list_entry *rle; 891 int error; 892 int nvec; 893 894 if (maxvec < minvec) 895 return (-EINVAL); 896 897 nvec = pci_msi_count(pdev->dev.bsddev); 898 if (nvec < 1 || nvec < minvec) 899 return (-ENOSPC); 900 901 nvec = min(nvec, maxvec); 902 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &nvec)) != 0) 903 return error; 904 905 /* Native PCI might only ever ask for 32 vectors. */ 906 if (nvec < minvec) { 907 pci_release_msi(pdev->dev.bsddev); 908 return (-ENOSPC); 909 } 910 911 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 912 pdev->dev.irq_start = rle->start; 913 pdev->dev.irq_end = rle->start + nvec; 914 pdev->irq = rle->start; 915 pdev->msi_enabled = true; 916 return (0); 917 } 918 919 static inline int 920 pci_enable_msi(struct pci_dev *pdev) 921 { 922 923 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 924 } 925 926 static inline int 927 pci_channel_offline(struct pci_dev *pdev) 928 { 929 930 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 931 } 932 933 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 934 { 935 return -ENODEV; 936 } 937 938 static inline void pci_disable_sriov(struct pci_dev *dev) 939 { 940 } 941 942 static inline void * 943 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 944 { 945 struct resource *res; 946 947 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 948 if (res == NULL) 949 return (NULL); 950 /* This is a FreeBSD extension so we can use bus_*(). */ 951 if (pdev->want_iomap_res) 952 return (res); 953 return ((void *)rman_get_bushandle(res)); 954 } 955 956 static inline void 957 pci_iounmap(struct pci_dev *pdev, void *res) 958 { 959 struct pci_mmio_region *mmio, *p; 960 961 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 962 if (res != (void *)rman_get_bushandle(mmio->res)) 963 continue; 964 bus_release_resource(pdev->dev.bsddev, 965 mmio->type, mmio->rid, mmio->res); 966 TAILQ_REMOVE(&pdev->mmio, mmio, next); 967 free(mmio, M_DEVBUF); 968 return; 969 } 970 } 971 972 static inline void 973 lkpi_pci_save_state(struct pci_dev *pdev) 974 { 975 976 pci_save_state(pdev->dev.bsddev); 977 } 978 979 static inline void 980 lkpi_pci_restore_state(struct pci_dev *pdev) 981 { 982 983 pci_restore_state(pdev->dev.bsddev); 984 } 985 986 #define pci_save_state(dev) lkpi_pci_save_state(dev) 987 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 988 989 static inline int 990 pci_reset_function(struct pci_dev *pdev) 991 { 992 993 return (-ENOSYS); 994 } 995 996 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 997 const struct pci_device_id _table[] __devinitdata 998 999 /* XXX This should not be necessary. */ 1000 #define pcix_set_mmrbc(d, v) 0 1001 #define pcix_get_max_mmrbc(d) 0 1002 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 1003 1004 #define PCI_DMA_BIDIRECTIONAL 0 1005 #define PCI_DMA_TODEVICE 1 1006 #define PCI_DMA_FROMDEVICE 2 1007 #define PCI_DMA_NONE 3 1008 1009 #define pci_pool dma_pool 1010 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 1011 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 1012 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 1013 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 1014 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 1015 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 1016 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1017 _size, _vaddr, _dma_handle) 1018 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 1019 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1020 _sg, _nents, (enum dma_data_direction)_dir) 1021 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 1022 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1023 (_ptr), (_size), (enum dma_data_direction)_dir) 1024 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 1025 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1026 _addr, _size, (enum dma_data_direction)_dir) 1027 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 1028 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1029 _sg, _nents, (enum dma_data_direction)_dir) 1030 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 1031 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 1032 _offset, _size, (enum dma_data_direction)_dir) 1033 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 1034 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1035 _dma_address, _size, (enum dma_data_direction)_dir) 1036 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1037 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1038 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1039 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1040 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1041 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1042 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1043 #define pci_unmap_addr dma_unmap_addr 1044 #define pci_unmap_addr_set dma_unmap_addr_set 1045 #define pci_unmap_len dma_unmap_len 1046 #define pci_unmap_len_set dma_unmap_len_set 1047 1048 typedef unsigned int __bitwise pci_channel_state_t; 1049 typedef unsigned int __bitwise pci_ers_result_t; 1050 1051 enum pci_channel_state { 1052 pci_channel_io_normal = 1, 1053 pci_channel_io_frozen = 2, 1054 pci_channel_io_perm_failure = 3, 1055 }; 1056 1057 enum pci_ers_result { 1058 PCI_ERS_RESULT_NONE = 1, 1059 PCI_ERS_RESULT_CAN_RECOVER = 2, 1060 PCI_ERS_RESULT_NEED_RESET = 3, 1061 PCI_ERS_RESULT_DISCONNECT = 4, 1062 PCI_ERS_RESULT_RECOVERED = 5, 1063 }; 1064 1065 /* PCI bus error event callbacks */ 1066 struct pci_error_handlers { 1067 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1068 enum pci_channel_state error); 1069 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1070 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1071 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1072 void (*resume)(struct pci_dev *dev); 1073 }; 1074 1075 /* FreeBSD does not support SRIOV - yet */ 1076 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1077 { 1078 return dev; 1079 } 1080 1081 static inline bool pci_is_pcie(struct pci_dev *dev) 1082 { 1083 return !!pci_pcie_cap(dev); 1084 } 1085 1086 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1087 { 1088 int pos; 1089 u16 reg16; 1090 1091 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1092 if (!pos) 1093 return 0; 1094 1095 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1096 1097 return reg16; 1098 } 1099 1100 static inline int pci_pcie_type(struct pci_dev *dev) 1101 { 1102 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1103 } 1104 1105 static inline int pcie_cap_version(struct pci_dev *dev) 1106 { 1107 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1108 } 1109 1110 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1111 { 1112 int type = pci_pcie_type(dev); 1113 1114 return pcie_cap_version(dev) > 1 || 1115 type == PCI_EXP_TYPE_ROOT_PORT || 1116 type == PCI_EXP_TYPE_ENDPOINT || 1117 type == PCI_EXP_TYPE_LEG_END; 1118 } 1119 1120 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1121 { 1122 return true; 1123 } 1124 1125 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1126 { 1127 int type = pci_pcie_type(dev); 1128 1129 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1130 (type == PCI_EXP_TYPE_DOWNSTREAM && 1131 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1132 } 1133 1134 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1135 { 1136 int type = pci_pcie_type(dev); 1137 1138 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1139 type == PCI_EXP_TYPE_RC_EC; 1140 } 1141 1142 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1143 { 1144 if (!pci_is_pcie(dev)) 1145 return false; 1146 1147 switch (pos) { 1148 case PCI_EXP_FLAGS_TYPE: 1149 return true; 1150 case PCI_EXP_DEVCAP: 1151 case PCI_EXP_DEVCTL: 1152 case PCI_EXP_DEVSTA: 1153 return pcie_cap_has_devctl(dev); 1154 case PCI_EXP_LNKCAP: 1155 case PCI_EXP_LNKCTL: 1156 case PCI_EXP_LNKSTA: 1157 return pcie_cap_has_lnkctl(dev); 1158 case PCI_EXP_SLTCAP: 1159 case PCI_EXP_SLTCTL: 1160 case PCI_EXP_SLTSTA: 1161 return pcie_cap_has_sltctl(dev); 1162 case PCI_EXP_RTCTL: 1163 case PCI_EXP_RTCAP: 1164 case PCI_EXP_RTSTA: 1165 return pcie_cap_has_rtctl(dev); 1166 case PCI_EXP_DEVCAP2: 1167 case PCI_EXP_DEVCTL2: 1168 case PCI_EXP_LNKCAP2: 1169 case PCI_EXP_LNKCTL2: 1170 case PCI_EXP_LNKSTA2: 1171 return pcie_cap_version(dev) > 1; 1172 default: 1173 return false; 1174 } 1175 } 1176 1177 static inline int 1178 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1179 { 1180 if (pos & 3) 1181 return -EINVAL; 1182 1183 if (!pcie_capability_reg_implemented(dev, pos)) 1184 return -EINVAL; 1185 1186 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1187 } 1188 1189 static inline int 1190 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1191 { 1192 if (pos & 3) 1193 return -EINVAL; 1194 1195 if (!pcie_capability_reg_implemented(dev, pos)) 1196 return -EINVAL; 1197 1198 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1199 } 1200 1201 static inline int 1202 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1203 { 1204 if (pos & 1) 1205 return -EINVAL; 1206 1207 if (!pcie_capability_reg_implemented(dev, pos)) 1208 return 0; 1209 1210 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1211 } 1212 1213 static inline int 1214 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1215 { 1216 int error; 1217 uint16_t v; 1218 1219 error = pcie_capability_read_word(dev, pos, &v); 1220 if (error != 0) 1221 return (error); 1222 1223 v |= val; 1224 1225 error = pcie_capability_write_word(dev, pos, v); 1226 return (error); 1227 } 1228 1229 static inline int 1230 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1231 { 1232 int error; 1233 uint16_t v; 1234 1235 error = pcie_capability_read_word(dev, pos, &v); 1236 if (error != 0) 1237 return (error); 1238 1239 v &= ~val; 1240 1241 error = pcie_capability_write_word(dev, pos, v); 1242 return (error); 1243 } 1244 1245 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1246 enum pci_bus_speed *speed, enum pcie_link_width *width) 1247 { 1248 *speed = PCI_SPEED_UNKNOWN; 1249 *width = PCIE_LNK_WIDTH_UNKNOWN; 1250 return (0); 1251 } 1252 1253 static inline int 1254 pci_num_vf(struct pci_dev *dev) 1255 { 1256 return (0); 1257 } 1258 1259 static inline enum pci_bus_speed 1260 pcie_get_speed_cap(struct pci_dev *dev) 1261 { 1262 device_t root; 1263 uint32_t lnkcap, lnkcap2; 1264 int error, pos; 1265 1266 root = device_get_parent(dev->dev.bsddev); 1267 if (root == NULL) 1268 return (PCI_SPEED_UNKNOWN); 1269 root = device_get_parent(root); 1270 if (root == NULL) 1271 return (PCI_SPEED_UNKNOWN); 1272 root = device_get_parent(root); 1273 if (root == NULL) 1274 return (PCI_SPEED_UNKNOWN); 1275 1276 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1277 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1278 return (PCI_SPEED_UNKNOWN); 1279 1280 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1281 return (PCI_SPEED_UNKNOWN); 1282 1283 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1284 1285 if (lnkcap2) { /* PCIe r3.0-compliant */ 1286 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1287 return (PCIE_SPEED_2_5GT); 1288 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1289 return (PCIE_SPEED_5_0GT); 1290 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1291 return (PCIE_SPEED_8_0GT); 1292 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1293 return (PCIE_SPEED_16_0GT); 1294 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1295 return (PCIE_SPEED_32_0GT); 1296 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1297 return (PCIE_SPEED_64_0GT); 1298 } else { /* pre-r3.0 */ 1299 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1300 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1301 return (PCIE_SPEED_2_5GT); 1302 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1303 return (PCIE_SPEED_5_0GT); 1304 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1305 return (PCIE_SPEED_8_0GT); 1306 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1307 return (PCIE_SPEED_16_0GT); 1308 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1309 return (PCIE_SPEED_32_0GT); 1310 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1311 return (PCIE_SPEED_64_0GT); 1312 } 1313 return (PCI_SPEED_UNKNOWN); 1314 } 1315 1316 static inline enum pcie_link_width 1317 pcie_get_width_cap(struct pci_dev *dev) 1318 { 1319 uint32_t lnkcap; 1320 1321 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1322 if (lnkcap) 1323 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1324 1325 return (PCIE_LNK_WIDTH_UNKNOWN); 1326 } 1327 1328 static inline int 1329 pcie_get_mps(struct pci_dev *dev) 1330 { 1331 return (pci_get_max_payload(dev->dev.bsddev)); 1332 } 1333 1334 static inline uint32_t 1335 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1336 { 1337 1338 switch(spd) { 1339 case PCIE_SPEED_64_0GT: 1340 return (64000 * 128 / 130); 1341 case PCIE_SPEED_32_0GT: 1342 return (32000 * 128 / 130); 1343 case PCIE_SPEED_16_0GT: 1344 return (16000 * 128 / 130); 1345 case PCIE_SPEED_8_0GT: 1346 return (8000 * 128 / 130); 1347 case PCIE_SPEED_5_0GT: 1348 return (5000 * 8 / 10); 1349 case PCIE_SPEED_2_5GT: 1350 return (2500 * 8 / 10); 1351 default: 1352 return (0); 1353 } 1354 } 1355 1356 static inline uint32_t 1357 pcie_bandwidth_available(struct pci_dev *pdev, 1358 struct pci_dev **limiting, 1359 enum pci_bus_speed *speed, 1360 enum pcie_link_width *width) 1361 { 1362 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1363 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1364 1365 if (speed) 1366 *speed = nspeed; 1367 if (width) 1368 *width = nwidth; 1369 1370 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1371 } 1372 1373 static inline struct pci_dev * 1374 pcie_find_root_port(struct pci_dev *pdev) 1375 { 1376 device_t root; 1377 1378 if (pdev->root != NULL) 1379 return (pdev->root); 1380 1381 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1382 if (root == NULL) 1383 return (NULL); 1384 1385 pdev->root = lkpinew_pci_dev(root); 1386 return (pdev->root); 1387 } 1388 1389 /* This is needed when people rip out the device "HotPlug". */ 1390 static inline void 1391 pci_lock_rescan_remove(void) 1392 { 1393 } 1394 1395 static inline void 1396 pci_unlock_rescan_remove(void) 1397 { 1398 } 1399 1400 static __inline void 1401 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1402 { 1403 } 1404 1405 /* 1406 * The following functions can be used to attach/detach the LinuxKPI's 1407 * PCI device runtime. The pci_driver and pci_device_id pointer is 1408 * allowed to be NULL. Other pointers must be all valid. 1409 * The pci_dev structure should be zero-initialized before passed 1410 * to the linux_pci_attach_device function. 1411 */ 1412 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1413 const struct pci_device_id *, struct pci_dev *); 1414 extern int linux_pci_detach_device(struct pci_dev *); 1415 1416 static inline int 1417 pci_dev_present(const struct pci_device_id *cur) 1418 { 1419 while (cur != NULL && (cur->vendor || cur->device)) { 1420 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1421 return (1); 1422 } 1423 cur++; 1424 } 1425 return (0); 1426 } 1427 1428 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1429 unsigned int bus, unsigned int devfn); 1430 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1431 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1432 1433 static inline int 1434 pci_domain_nr(struct pci_bus *pbus) 1435 { 1436 1437 return (pbus->domain); 1438 } 1439 1440 static inline int 1441 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1442 int pos, uint32_t *val, int len) 1443 { 1444 1445 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1446 return (0); 1447 } 1448 1449 static inline int 1450 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1451 { 1452 uint32_t tmp; 1453 int ret; 1454 1455 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1456 *val = (u16)tmp; 1457 return (ret); 1458 } 1459 1460 static inline int 1461 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1462 { 1463 uint32_t tmp; 1464 int ret; 1465 1466 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1467 *val = (u8)tmp; 1468 return (ret); 1469 } 1470 1471 static inline int 1472 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1473 uint32_t val, int size) 1474 { 1475 1476 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1477 return (0); 1478 } 1479 1480 static inline int 1481 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1482 uint8_t val) 1483 { 1484 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1485 } 1486 1487 static inline int 1488 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1489 uint16_t val) 1490 { 1491 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1492 } 1493 1494 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1495 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1496 1497 /* -------------------------------------------------------------------------- */ 1498 1499 static inline int 1500 pcim_enable_device(struct pci_dev *pdev) 1501 { 1502 struct pci_devres *dr; 1503 int error; 1504 1505 /* Here we cannot run through the pdev->managed check. */ 1506 dr = lkpi_pci_devres_get_alloc(pdev); 1507 if (dr == NULL) 1508 return (-ENOMEM); 1509 1510 /* If resources were enabled before do not do it again. */ 1511 if (dr->enable_io) 1512 return (0); 1513 1514 error = pci_enable_device(pdev); 1515 if (error == 0) 1516 dr->enable_io = true; 1517 1518 /* This device is not managed. */ 1519 pdev->managed = true; 1520 1521 return (error); 1522 } 1523 1524 static inline void __iomem ** 1525 pcim_iomap_table(struct pci_dev *pdev) 1526 { 1527 struct pcim_iomap_devres *dr; 1528 1529 dr = lkpi_pcim_iomap_devres_find(pdev); 1530 if (dr == NULL) 1531 return (NULL); 1532 1533 /* 1534 * If the driver has manually set a flag to be able to request the 1535 * resource to use bus_read/write_<n>, return the shadow table. 1536 */ 1537 if (pdev->want_iomap_res) 1538 return ((void **)dr->res_table); 1539 1540 /* This is the Linux default. */ 1541 return (dr->mmio_table); 1542 } 1543 1544 static inline int 1545 pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, const char *name) 1546 { 1547 struct pcim_iomap_devres *dr; 1548 void *res; 1549 uint32_t mappings; 1550 int bar; 1551 1552 dr = lkpi_pcim_iomap_devres_find(pdev); 1553 if (dr == NULL) 1554 return (-ENOMEM); 1555 1556 /* Now iomap all the requested (by "mask") ones. */ 1557 for (bar = mappings = 0; mappings != mask; bar++) { 1558 if ((mask & (1 << bar)) == 0) 1559 continue; 1560 1561 /* Request double is not allowed. */ 1562 if (dr->mmio_table[bar] != NULL) { 1563 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1564 __func__, bar, dr->mmio_table[bar]); 1565 goto err; 1566 } 1567 1568 res = _lkpi_pci_iomap(pdev, bar, 0); 1569 if (res == NULL) 1570 goto err; 1571 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1572 dr->res_table[bar] = res; 1573 1574 mappings |= (1 << bar); 1575 } 1576 1577 return (0); 1578 err: 1579 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1580 if ((mappings & (1 << bar)) != 0) { 1581 res = dr->mmio_table[bar]; 1582 if (res == NULL) 1583 continue; 1584 pci_iounmap(pdev, res); 1585 } 1586 } 1587 1588 return (-EINVAL); 1589 } 1590 1591 static inline int 1592 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1593 { 1594 uint32_t requests, req_mask; 1595 int bar, error; 1596 1597 /* Request all the BARs ("regions") we do not iomap. */ 1598 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1599 for (bar = requests = 0; requests != req_mask; bar++) { 1600 if ((req_mask & (1 << bar)) == 0) 1601 continue; 1602 error = pci_request_region(pdev, bar, name); 1603 if (error != 0 && error != -ENODEV) 1604 goto err; 1605 requests |= (1 << bar); 1606 } 1607 1608 error = pcim_iomap_regions(pdev, mask, name); 1609 if (error != 0) 1610 goto err; 1611 1612 return (0); 1613 1614 err: 1615 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1616 if ((requests & (1 << bar)) != 0) 1617 pci_release_region(pdev, bar); 1618 } 1619 1620 return (-EINVAL); 1621 } 1622 1623 /* 1624 * We cannot simply re-define pci_get_device() as we would normally do 1625 * and then hide it in linux_pci.c as too many semi-native drivers still 1626 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1627 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1628 */ 1629 static inline struct pci_dev * 1630 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1631 { 1632 1633 return (lkpi_pci_get_device(vendor, device, odev)); 1634 } 1635 1636 /* This is a FreeBSD extension so we can use bus_*(). */ 1637 static inline void 1638 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1639 { 1640 pdev->want_iomap_res = true; 1641 } 1642 1643 static inline bool 1644 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1645 { 1646 1647 return (false); 1648 } 1649 1650 static inline void * 1651 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1652 { 1653 1654 return (NULL); 1655 } 1656 1657 static inline void 1658 pci_ignore_hotplug(struct pci_dev *pdev) 1659 { 1660 } 1661 1662 static inline const char * 1663 pci_power_name(pci_power_t state) 1664 { 1665 int pstate = state + 1; 1666 1667 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1668 return (pci_power_names[pstate]); 1669 else 1670 return (pci_power_names[0]); 1671 } 1672 1673 static inline int 1674 pcie_get_readrq(struct pci_dev *dev) 1675 { 1676 u16 ctl; 1677 1678 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1679 return (-EINVAL); 1680 1681 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1682 } 1683 1684 static inline bool 1685 pci_is_enabled(struct pci_dev *pdev) 1686 { 1687 1688 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1689 PCIM_CMD_BUSMASTEREN) != 0); 1690 } 1691 1692 static inline int 1693 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1694 { 1695 1696 return (0); 1697 } 1698 1699 static inline int 1700 pci_assign_resource(struct pci_dev *pdev, int bar) 1701 { 1702 1703 return (0); 1704 } 1705 1706 static inline int 1707 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1708 { 1709 1710 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1711 if (vector != 0) 1712 return (-EINVAL); 1713 return (pdev->irq); 1714 } 1715 1716 if (pdev->msix_enabled || pdev->msi_enabled) { 1717 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1718 return (-EINVAL); 1719 return (pdev->dev.irq_start + vector); 1720 } 1721 1722 return (-ENXIO); 1723 } 1724 1725 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1726