1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/pciio.h> 41 #include <sys/rman.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pci_private.h> 45 46 #include <machine/resource.h> 47 48 #include <linux/list.h> 49 #include <linux/dmapool.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/compiler.h> 52 #include <linux/errno.h> 53 #include <asm/atomic.h> 54 #include <linux/device.h> 55 56 struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class; 62 uint32_t class_mask; 63 uintptr_t driver_data; 64 }; 65 66 #define MODULE_DEVICE_TABLE(bus, table) 67 68 #define PCI_BASE_CLASS_DISPLAY 0x03 69 #define PCI_CLASS_DISPLAY_VGA 0x0300 70 #define PCI_CLASS_DISPLAY_OTHER 0x0380 71 #define PCI_BASE_CLASS_BRIDGE 0x06 72 #define PCI_CLASS_BRIDGE_ISA 0x0601 73 74 #define PCI_ANY_ID (-1) 75 #define PCI_VENDOR_ID_APPLE 0x106b 76 #define PCI_VENDOR_ID_ASUSTEK 0x1043 77 #define PCI_VENDOR_ID_ATI 0x1002 78 #define PCI_VENDOR_ID_DELL 0x1028 79 #define PCI_VENDOR_ID_HP 0x103c 80 #define PCI_VENDOR_ID_IBM 0x1014 81 #define PCI_VENDOR_ID_INTEL 0x8086 82 #define PCI_VENDOR_ID_MELLANOX 0x15b3 83 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 84 #define PCI_VENDOR_ID_SERVERWORKS 0x1166 85 #define PCI_VENDOR_ID_SONY 0x104d 86 #define PCI_VENDOR_ID_TOPSPIN 0x1867 87 #define PCI_VENDOR_ID_VIA 0x1106 88 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 89 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 90 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 91 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 92 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 93 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 94 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 95 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 96 #define PCI_SUBDEVICE_ID_QEMU 0x1100 97 98 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 99 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 100 #define PCI_FUNC(devfn) ((devfn) & 0x07) 101 102 #define PCI_VDEVICE(_vendor, _device) \ 103 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 104 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 105 #define PCI_DEVICE(_vendor, _device) \ 106 .vendor = (_vendor), .device = (_device), \ 107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 108 109 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 110 111 #define PCI_VENDOR_ID PCIR_DEVVENDOR 112 #define PCI_COMMAND PCIR_COMMAND 113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 115 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 116 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 117 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 118 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 119 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 120 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 121 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 122 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 123 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 124 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 125 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 126 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 127 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 128 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 129 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 130 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 131 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 132 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 133 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 134 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 135 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 136 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 137 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 138 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 139 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 140 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 141 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 142 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 143 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 144 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 145 146 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 147 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 148 #define PCI_EXP_DEVSTA_TRPND 0x0020 149 150 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 151 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 152 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 153 154 enum pci_bus_speed { 155 PCI_SPEED_UNKNOWN = -1, 156 PCIE_SPEED_2_5GT, 157 PCIE_SPEED_5_0GT, 158 PCIE_SPEED_8_0GT, 159 }; 160 161 enum pcie_link_width { 162 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 163 }; 164 165 typedef int pci_power_t; 166 167 #define PCI_D0 PCI_POWERSTATE_D0 168 #define PCI_D1 PCI_POWERSTATE_D1 169 #define PCI_D2 PCI_POWERSTATE_D2 170 #define PCI_D3hot PCI_POWERSTATE_D3 171 #define PCI_D3cold 4 172 173 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 174 175 struct pci_dev; 176 177 struct pci_driver { 178 struct list_head links; 179 char *name; 180 const struct pci_device_id *id_table; 181 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 182 void (*remove)(struct pci_dev *dev); 183 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 184 int (*resume) (struct pci_dev *dev); /* Device woken up */ 185 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 186 driver_t bsddriver; 187 devclass_t bsdclass; 188 struct device_driver driver; 189 const struct pci_error_handlers *err_handler; 190 }; 191 192 extern struct list_head pci_drivers; 193 extern struct list_head pci_devices; 194 extern spinlock_t pci_lock; 195 196 #define __devexit_p(x) x 197 198 struct pci_dev { 199 struct device dev; 200 struct list_head links; 201 struct pci_driver *pdrv; 202 uint64_t dma_mask; 203 uint16_t device; 204 uint16_t vendor; 205 unsigned int irq; 206 unsigned int devfn; 207 uint32_t class; 208 uint8_t revision; 209 }; 210 211 static inline struct resource_list_entry * 212 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 213 { 214 struct pci_devinfo *dinfo; 215 struct resource_list *rl; 216 217 dinfo = device_get_ivars(pdev->dev.bsddev); 218 rl = &dinfo->resources; 219 return resource_list_find(rl, type, rid); 220 } 221 222 static inline struct resource_list_entry * 223 linux_pci_get_bar(struct pci_dev *pdev, int bar) 224 { 225 struct resource_list_entry *rle; 226 227 bar = PCIR_BAR(bar); 228 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 229 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 230 return (rle); 231 } 232 233 static inline struct device * 234 linux_pci_find_irq_dev(unsigned int irq) 235 { 236 struct pci_dev *pdev; 237 struct device *found; 238 239 found = NULL; 240 spin_lock(&pci_lock); 241 list_for_each_entry(pdev, &pci_devices, links) { 242 if (irq == pdev->dev.irq || 243 (irq >= pdev->dev.msix && irq < pdev->dev.msix_max)) { 244 found = &pdev->dev; 245 break; 246 } 247 } 248 spin_unlock(&pci_lock); 249 return (found); 250 } 251 252 static inline unsigned long 253 pci_resource_start(struct pci_dev *pdev, int bar) 254 { 255 struct resource_list_entry *rle; 256 257 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 258 return (0); 259 return rle->start; 260 } 261 262 static inline unsigned long 263 pci_resource_len(struct pci_dev *pdev, int bar) 264 { 265 struct resource_list_entry *rle; 266 267 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 268 return (0); 269 return rle->count; 270 } 271 272 static inline int 273 pci_resource_type(struct pci_dev *pdev, int bar) 274 { 275 struct pci_map *pm; 276 277 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 278 if (!pm) 279 return (-1); 280 281 if (PCI_BAR_IO(pm->pm_value)) 282 return (SYS_RES_IOPORT); 283 else 284 return (SYS_RES_MEMORY); 285 } 286 287 /* 288 * All drivers just seem to want to inspect the type not flags. 289 */ 290 static inline int 291 pci_resource_flags(struct pci_dev *pdev, int bar) 292 { 293 int type; 294 295 type = pci_resource_type(pdev, bar); 296 if (type < 0) 297 return (0); 298 return (1 << type); 299 } 300 301 static inline const char * 302 pci_name(struct pci_dev *d) 303 { 304 305 return device_get_desc(d->dev.bsddev); 306 } 307 308 static inline void * 309 pci_get_drvdata(struct pci_dev *pdev) 310 { 311 312 return dev_get_drvdata(&pdev->dev); 313 } 314 315 static inline void 316 pci_set_drvdata(struct pci_dev *pdev, void *data) 317 { 318 319 dev_set_drvdata(&pdev->dev, data); 320 } 321 322 static inline int 323 pci_enable_device(struct pci_dev *pdev) 324 { 325 326 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 327 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 328 return (0); 329 } 330 331 static inline void 332 pci_disable_device(struct pci_dev *pdev) 333 { 334 335 pci_disable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 336 pci_disable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 337 } 338 339 static inline int 340 pci_set_master(struct pci_dev *pdev) 341 { 342 343 pci_enable_busmaster(pdev->dev.bsddev); 344 return (0); 345 } 346 347 static inline int 348 pci_set_power_state(struct pci_dev *pdev, int state) 349 { 350 351 pci_set_powerstate(pdev->dev.bsddev, state); 352 return (0); 353 } 354 355 static inline int 356 pci_clear_master(struct pci_dev *pdev) 357 { 358 359 pci_disable_busmaster(pdev->dev.bsddev); 360 return (0); 361 } 362 363 static inline int 364 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 365 { 366 int rid; 367 int type; 368 369 type = pci_resource_type(pdev, bar); 370 if (type < 0) 371 return (-ENODEV); 372 rid = PCIR_BAR(bar); 373 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 374 RF_ACTIVE) == NULL) 375 return (-EINVAL); 376 return (0); 377 } 378 379 static inline void 380 pci_release_region(struct pci_dev *pdev, int bar) 381 { 382 struct resource_list_entry *rle; 383 384 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 385 return; 386 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 387 } 388 389 static inline void 390 pci_release_regions(struct pci_dev *pdev) 391 { 392 int i; 393 394 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 395 pci_release_region(pdev, i); 396 } 397 398 static inline int 399 pci_request_regions(struct pci_dev *pdev, const char *res_name) 400 { 401 int error; 402 int i; 403 404 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 405 error = pci_request_region(pdev, i, res_name); 406 if (error && error != -ENODEV) { 407 pci_release_regions(pdev); 408 return (error); 409 } 410 } 411 return (0); 412 } 413 414 static inline void 415 pci_disable_msix(struct pci_dev *pdev) 416 { 417 418 pci_release_msi(pdev->dev.bsddev); 419 } 420 421 static inline bus_addr_t 422 pci_bus_address(struct pci_dev *pdev, int bar) 423 { 424 425 return (pci_resource_start(pdev, bar)); 426 } 427 428 #define PCI_CAP_ID_EXP PCIY_EXPRESS 429 #define PCI_CAP_ID_PCIX PCIY_PCIX 430 #define PCI_CAP_ID_AGP PCIY_AGP 431 #define PCI_CAP_ID_PM PCIY_PMG 432 433 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 434 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 435 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 436 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 437 #define PCI_EXP_LNKSTA PCIER_LINK_STA 438 439 static inline int 440 pci_find_capability(struct pci_dev *pdev, int capid) 441 { 442 int reg; 443 444 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 445 return (0); 446 return (reg); 447 } 448 449 static inline int pci_pcie_cap(struct pci_dev *dev) 450 { 451 return pci_find_capability(dev, PCI_CAP_ID_EXP); 452 } 453 454 455 static inline int 456 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 457 { 458 459 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 460 return (0); 461 } 462 463 static inline int 464 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 465 { 466 467 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 468 return (0); 469 } 470 471 static inline int 472 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 473 { 474 475 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 476 return (0); 477 } 478 479 static inline int 480 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 481 { 482 483 pci_write_config(pdev->dev.bsddev, where, val, 1); 484 return (0); 485 } 486 487 static inline int 488 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 489 { 490 491 pci_write_config(pdev->dev.bsddev, where, val, 2); 492 return (0); 493 } 494 495 static inline int 496 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 497 { 498 499 pci_write_config(pdev->dev.bsddev, where, val, 4); 500 return (0); 501 } 502 503 extern int pci_register_driver(struct pci_driver *pdrv); 504 extern void pci_unregister_driver(struct pci_driver *pdrv); 505 506 struct msix_entry { 507 int entry; 508 int vector; 509 }; 510 511 /* 512 * Enable msix, positive errors indicate actual number of available 513 * vectors. Negative errors are failures. 514 * 515 * NB: define added to prevent this definition of pci_enable_msix from 516 * clashing with the native FreeBSD version. 517 */ 518 #define pci_enable_msix linux_pci_enable_msix 519 static inline int 520 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 521 { 522 struct resource_list_entry *rle; 523 int error; 524 int avail; 525 int i; 526 527 avail = pci_msix_count(pdev->dev.bsddev); 528 if (avail < nreq) { 529 if (avail == 0) 530 return -EINVAL; 531 return avail; 532 } 533 avail = nreq; 534 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 535 return error; 536 /* 537 * Handle case where "pci_alloc_msix()" may allocate less 538 * interrupts than available and return with no error: 539 */ 540 if (avail < nreq) { 541 pci_release_msi(pdev->dev.bsddev); 542 return avail; 543 } 544 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 545 pdev->dev.msix = rle->start; 546 pdev->dev.msix_max = rle->start + avail; 547 for (i = 0; i < nreq; i++) 548 entries[i].vector = pdev->dev.msix + i; 549 return (0); 550 } 551 552 #define pci_enable_msix_range linux_pci_enable_msix_range 553 static inline int 554 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 555 int minvec, int maxvec) 556 { 557 int nvec = maxvec; 558 int rc; 559 560 if (maxvec < minvec) 561 return (-ERANGE); 562 563 do { 564 rc = pci_enable_msix(dev, entries, nvec); 565 if (rc < 0) { 566 return (rc); 567 } else if (rc > 0) { 568 if (rc < minvec) 569 return (-ENOSPC); 570 nvec = rc; 571 } 572 } while (rc); 573 return (nvec); 574 } 575 576 static inline int pci_channel_offline(struct pci_dev *pdev) 577 { 578 return false; 579 } 580 581 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 582 { 583 return -ENODEV; 584 } 585 static inline void pci_disable_sriov(struct pci_dev *dev) 586 { 587 } 588 589 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 590 const struct pci_device_id _table[] __devinitdata 591 592 593 /* XXX This should not be necessary. */ 594 #define pcix_set_mmrbc(d, v) 0 595 #define pcix_get_max_mmrbc(d) 0 596 #define pcie_set_readrq(d, v) 0 597 598 #define PCI_DMA_BIDIRECTIONAL 0 599 #define PCI_DMA_TODEVICE 1 600 #define PCI_DMA_FROMDEVICE 2 601 #define PCI_DMA_NONE 3 602 603 #define pci_pool dma_pool 604 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 605 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 606 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 607 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 608 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 609 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 610 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 611 _size, _vaddr, _dma_handle) 612 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 613 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 614 _sg, _nents, (enum dma_data_direction)_dir) 615 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 616 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 617 (_ptr), (_size), (enum dma_data_direction)_dir) 618 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 619 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 620 _addr, _size, (enum dma_data_direction)_dir) 621 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 622 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 623 _sg, _nents, (enum dma_data_direction)_dir) 624 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 625 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 626 _offset, _size, (enum dma_data_direction)_dir) 627 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 628 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 629 _dma_address, _size, (enum dma_data_direction)_dir) 630 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 631 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 632 dma_mapping_error(&(_pdev)->dev, _dma_addr) 633 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 634 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 635 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 636 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 637 #define pci_unmap_addr dma_unmap_addr 638 #define pci_unmap_addr_set dma_unmap_addr_set 639 #define pci_unmap_len dma_unmap_len 640 #define pci_unmap_len_set dma_unmap_len_set 641 642 typedef unsigned int __bitwise pci_channel_state_t; 643 typedef unsigned int __bitwise pci_ers_result_t; 644 645 enum pci_channel_state { 646 pci_channel_io_normal = 1, 647 pci_channel_io_frozen = 2, 648 pci_channel_io_perm_failure = 3, 649 }; 650 651 enum pci_ers_result { 652 PCI_ERS_RESULT_NONE = 1, 653 PCI_ERS_RESULT_CAN_RECOVER = 2, 654 PCI_ERS_RESULT_NEED_RESET = 3, 655 PCI_ERS_RESULT_DISCONNECT = 4, 656 PCI_ERS_RESULT_RECOVERED = 5, 657 }; 658 659 660 /* PCI bus error event callbacks */ 661 struct pci_error_handlers { 662 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 663 enum pci_channel_state error); 664 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 665 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 666 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 667 void (*resume)(struct pci_dev *dev); 668 }; 669 670 /* FreeBSD does not support SRIOV - yet */ 671 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 672 { 673 return dev; 674 } 675 676 static inline bool pci_is_pcie(struct pci_dev *dev) 677 { 678 return !!pci_pcie_cap(dev); 679 } 680 681 static inline u16 pcie_flags_reg(struct pci_dev *dev) 682 { 683 int pos; 684 u16 reg16; 685 686 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 687 if (!pos) 688 return 0; 689 690 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 691 692 return reg16; 693 } 694 695 696 static inline int pci_pcie_type(struct pci_dev *dev) 697 { 698 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 699 } 700 701 static inline int pcie_cap_version(struct pci_dev *dev) 702 { 703 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 704 } 705 706 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 707 { 708 int type = pci_pcie_type(dev); 709 710 return pcie_cap_version(dev) > 1 || 711 type == PCI_EXP_TYPE_ROOT_PORT || 712 type == PCI_EXP_TYPE_ENDPOINT || 713 type == PCI_EXP_TYPE_LEG_END; 714 } 715 716 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 717 { 718 return true; 719 } 720 721 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 722 { 723 int type = pci_pcie_type(dev); 724 725 return pcie_cap_version(dev) > 1 || 726 type == PCI_EXP_TYPE_ROOT_PORT || 727 (type == PCI_EXP_TYPE_DOWNSTREAM && 728 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 729 } 730 731 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 732 { 733 int type = pci_pcie_type(dev); 734 735 return pcie_cap_version(dev) > 1 || 736 type == PCI_EXP_TYPE_ROOT_PORT || 737 type == PCI_EXP_TYPE_RC_EC; 738 } 739 740 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 741 { 742 if (!pci_is_pcie(dev)) 743 return false; 744 745 switch (pos) { 746 case PCI_EXP_FLAGS_TYPE: 747 return true; 748 case PCI_EXP_DEVCAP: 749 case PCI_EXP_DEVCTL: 750 case PCI_EXP_DEVSTA: 751 return pcie_cap_has_devctl(dev); 752 case PCI_EXP_LNKCAP: 753 case PCI_EXP_LNKCTL: 754 case PCI_EXP_LNKSTA: 755 return pcie_cap_has_lnkctl(dev); 756 case PCI_EXP_SLTCAP: 757 case PCI_EXP_SLTCTL: 758 case PCI_EXP_SLTSTA: 759 return pcie_cap_has_sltctl(dev); 760 case PCI_EXP_RTCTL: 761 case PCI_EXP_RTCAP: 762 case PCI_EXP_RTSTA: 763 return pcie_cap_has_rtctl(dev); 764 case PCI_EXP_DEVCAP2: 765 case PCI_EXP_DEVCTL2: 766 case PCI_EXP_LNKCAP2: 767 case PCI_EXP_LNKCTL2: 768 case PCI_EXP_LNKSTA2: 769 return pcie_cap_version(dev) > 1; 770 default: 771 return false; 772 } 773 } 774 775 static inline int 776 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 777 { 778 if (pos & 3) 779 return -EINVAL; 780 781 if (!pcie_capability_reg_implemented(dev, pos)) 782 return -EINVAL; 783 784 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 785 } 786 787 static inline int 788 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 789 { 790 if (pos & 3) 791 return -EINVAL; 792 793 if (!pcie_capability_reg_implemented(dev, pos)) 794 return -EINVAL; 795 796 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 797 } 798 799 static inline int 800 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 801 { 802 if (pos & 1) 803 return -EINVAL; 804 805 if (!pcie_capability_reg_implemented(dev, pos)) 806 return 0; 807 808 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 809 } 810 811 static inline int pcie_get_minimum_link(struct pci_dev *dev, 812 enum pci_bus_speed *speed, enum pcie_link_width *width) 813 { 814 *speed = PCI_SPEED_UNKNOWN; 815 *width = PCIE_LNK_WIDTH_UNKNOWN; 816 return (0); 817 } 818 819 static inline int 820 pci_num_vf(struct pci_dev *dev) 821 { 822 return (0); 823 } 824 825 #endif /* _LINUX_PCI_H_ */ 826