1f4b37ed0SZbigniew Bodek /*_ 2f4b37ed0SZbigniew Bodek ******************************************************************************** 3f4b37ed0SZbigniew Bodek Copyright (C) 2015 Annapurna Labs Ltd. 4f4b37ed0SZbigniew Bodek 5f4b37ed0SZbigniew Bodek This file may be licensed under the terms of the Annapurna Labs Commercial 6f4b37ed0SZbigniew Bodek License Agreement. 7f4b37ed0SZbigniew Bodek 8f4b37ed0SZbigniew Bodek Alternatively, this file can be distributed under the terms of the GNU General 9f4b37ed0SZbigniew Bodek Public License V2 as published by the Free Software Foundation and can be 10f4b37ed0SZbigniew Bodek found at http://www.gnu.org/licenses/gpl-2.0.html 11f4b37ed0SZbigniew Bodek 12f4b37ed0SZbigniew Bodek Alternatively, redistribution and use in source and binary forms, with or 13f4b37ed0SZbigniew Bodek without modification, are permitted provided that the following conditions are 14f4b37ed0SZbigniew Bodek met: 15f4b37ed0SZbigniew Bodek 16f4b37ed0SZbigniew Bodek * Redistributions of source code must retain the above copyright notice, 17f4b37ed0SZbigniew Bodek this list of conditions and the following disclaimer. 18f4b37ed0SZbigniew Bodek 19f4b37ed0SZbigniew Bodek * Redistributions in binary form must reproduce the above copyright 20f4b37ed0SZbigniew Bodek notice, this list of conditions and the following disclaimer in 21f4b37ed0SZbigniew Bodek the documentation and/or other materials provided with the 22f4b37ed0SZbigniew Bodek distribution. 23f4b37ed0SZbigniew Bodek 24f4b37ed0SZbigniew Bodek THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25f4b37ed0SZbigniew Bodek ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26f4b37ed0SZbigniew Bodek WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27f4b37ed0SZbigniew Bodek DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28f4b37ed0SZbigniew Bodek ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29f4b37ed0SZbigniew Bodek (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30f4b37ed0SZbigniew Bodek LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31f4b37ed0SZbigniew Bodek ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32f4b37ed0SZbigniew Bodek (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33f4b37ed0SZbigniew Bodek SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34f4b37ed0SZbigniew Bodek 35f4b37ed0SZbigniew Bodek *******************************************************************************/ 36f4b37ed0SZbigniew Bodek 37f4b37ed0SZbigniew Bodek 38f4b37ed0SZbigniew Bodek #ifndef __AL_HAL_IOFIC_REG_H 39f4b37ed0SZbigniew Bodek #define __AL_HAL_IOFIC_REG_H 40f4b37ed0SZbigniew Bodek 41f4b37ed0SZbigniew Bodek #ifdef __cplusplus 42f4b37ed0SZbigniew Bodek extern "C" { 43f4b37ed0SZbigniew Bodek #endif 44f4b37ed0SZbigniew Bodek /* 45f4b37ed0SZbigniew Bodek * Unit Registers 46f4b37ed0SZbigniew Bodek */ 47f4b37ed0SZbigniew Bodek 48f4b37ed0SZbigniew Bodek struct al_iofic_grp_ctrl { 49f4b37ed0SZbigniew Bodek uint32_t int_cause_grp; /* Interrupt Cause RegisterSet by hardware */ 50f4b37ed0SZbigniew Bodek uint32_t rsrvd1; 51f4b37ed0SZbigniew Bodek uint32_t int_cause_set_grp; /* Interrupt Cause Set RegisterWriting 1 to a bit in t ... */ 52f4b37ed0SZbigniew Bodek uint32_t rsrvd2; 53f4b37ed0SZbigniew Bodek uint32_t int_mask_grp; /* Interrupt Mask RegisterIf Auto-mask control bit =TR ... */ 54f4b37ed0SZbigniew Bodek uint32_t rsrvd3; 55f4b37ed0SZbigniew Bodek uint32_t int_mask_clear_grp; /* Interrupt Mask Clear RegisterUsed when auto-mask co ... */ 56f4b37ed0SZbigniew Bodek uint32_t rsrvd4; 57f4b37ed0SZbigniew Bodek uint32_t int_status_grp; /* Interrupt status RegisterThis register latch the st ... */ 58f4b37ed0SZbigniew Bodek uint32_t rsrvd5; 59f4b37ed0SZbigniew Bodek uint32_t int_control_grp; /* Interrupt Control Register */ 60f4b37ed0SZbigniew Bodek uint32_t rsrvd6; 61f4b37ed0SZbigniew Bodek uint32_t int_abort_msk_grp; /* Interrupt Mask RegisterEach bit in this register ma ... */ 62f4b37ed0SZbigniew Bodek uint32_t rsrvd7; 63f4b37ed0SZbigniew Bodek uint32_t int_log_msk_grp; /* Interrupt Log RegisterEach bit in this register mas ... */ 64f4b37ed0SZbigniew Bodek uint32_t rsrvd8; 65f4b37ed0SZbigniew Bodek }; 66f4b37ed0SZbigniew Bodek 67f4b37ed0SZbigniew Bodek struct al_iofic_grp_mod { 68f4b37ed0SZbigniew Bodek uint32_t grp_int_mod_reg; /* Interrupt moderation registerDedicated moderation in ... */ 69*3fc36ee0SWojciech Macek uint32_t grp_int_tgtid_reg; 70f4b37ed0SZbigniew Bodek }; 71f4b37ed0SZbigniew Bodek 72f4b37ed0SZbigniew Bodek struct al_iofic_regs { 73f4b37ed0SZbigniew Bodek struct al_iofic_grp_ctrl ctrl[0]; 74f4b37ed0SZbigniew Bodek uint32_t rsrvd1[0x400 >> 2]; 75f4b37ed0SZbigniew Bodek struct al_iofic_grp_mod grp_int_mod[0][32]; 76f4b37ed0SZbigniew Bodek }; 77f4b37ed0SZbigniew Bodek 78f4b37ed0SZbigniew Bodek 79f4b37ed0SZbigniew Bodek /* 80f4b37ed0SZbigniew Bodek * Registers Fields 81f4b37ed0SZbigniew Bodek */ 82f4b37ed0SZbigniew Bodek 83f4b37ed0SZbigniew Bodek 84f4b37ed0SZbigniew Bodek /**** int_control_grp register ****/ 85f4b37ed0SZbigniew Bodek /* When Clear_on_Read =1, All bits of Cause register ... */ 86f4b37ed0SZbigniew Bodek #define INT_CONTROL_GRP_CLEAR_ON_READ (1 << 0) 87f4b37ed0SZbigniew Bodek /* (must be set only when MSIX is enabled)When Auto-Ma ... */ 88f4b37ed0SZbigniew Bodek #define INT_CONTROL_GRP_AUTO_MASK (1 << 1) 89f4b37ed0SZbigniew Bodek /* Auto_Clear (RW)When Auto-Clear =1, the bits in the ... */ 90f4b37ed0SZbigniew Bodek #define INT_CONTROL_GRP_AUTO_CLEAR (1 << 2) 91f4b37ed0SZbigniew Bodek /* When Set_on_Posedge =1, the bits in the interrupt c ... */ 92f4b37ed0SZbigniew Bodek #define INT_CONTROL_GRP_SET_ON_POSEDGE (1 << 3) 93f4b37ed0SZbigniew Bodek /* When Moderation_Reset =1, all Moderation timers ass ... */ 94f4b37ed0SZbigniew Bodek #define INT_CONTROL_GRP_MOD_RST (1 << 4) 95f4b37ed0SZbigniew Bodek /* When mask_msi_x =1, No MSI-X from this group is sen ... */ 96f4b37ed0SZbigniew Bodek #define INT_CONTROL_GRP_MASK_MSI_X (1 << 5) 97f4b37ed0SZbigniew Bodek /* MSI-X AWID value, same ID for all cause bits */ 98f4b37ed0SZbigniew Bodek #define INT_CONTROL_GRP_AWID_MASK 0x00000F00 99f4b37ed0SZbigniew Bodek #define INT_CONTROL_GRP_AWID_SHIFT 8 100f4b37ed0SZbigniew Bodek /* This value determines the interval between interrup ... */ 101f4b37ed0SZbigniew Bodek #define INT_CONTROL_GRP_MOD_INTV_MASK 0x00FF0000 102f4b37ed0SZbigniew Bodek #define INT_CONTROL_GRP_MOD_INTV_SHIFT 16 103f4b37ed0SZbigniew Bodek /* This value determines the Moderation_Timer_Clock sp ... */ 104f4b37ed0SZbigniew Bodek #define INT_CONTROL_GRP_MOD_RES_MASK 0x0F000000 105f4b37ed0SZbigniew Bodek #define INT_CONTROL_GRP_MOD_RES_SHIFT 24 106f4b37ed0SZbigniew Bodek 107f4b37ed0SZbigniew Bodek /**** grp_int_mod_reg register ****/ 108f4b37ed0SZbigniew Bodek /* Interrupt Moderation Interval registerDedicated reg ... */ 109f4b37ed0SZbigniew Bodek #define INT_MOD_INTV_MASK 0x000000FF 110f4b37ed0SZbigniew Bodek #define INT_MOD_INTV_SHIFT 0 111f4b37ed0SZbigniew Bodek 112*3fc36ee0SWojciech Macek /**** grp_int_tgtid_reg register ****/ 113*3fc36ee0SWojciech Macek /* Interrupt tgtid value registerDedicated reg ... */ 114*3fc36ee0SWojciech Macek #define INT_MSIX_TGTID_MASK 0x0000FFFF 115*3fc36ee0SWojciech Macek #define INT_MSIX_TGTID_SHIFT 0 116*3fc36ee0SWojciech Macek /* Interrupt tgtid_en value registerDedicated reg ... */ 117*3fc36ee0SWojciech Macek #define INT_MSIX_TGTID_EN_SHIFT 31 118f4b37ed0SZbigniew Bodek 119f4b37ed0SZbigniew Bodek #ifdef __cplusplus 120f4b37ed0SZbigniew Bodek } 121f4b37ed0SZbigniew Bodek #endif 122f4b37ed0SZbigniew Bodek 123f4b37ed0SZbigniew Bodek #endif /* __AL_HAL_IOFIC_REG_H */ 124f4b37ed0SZbigniew Bodek 125f4b37ed0SZbigniew Bodek 126f4b37ed0SZbigniew Bodek 127f4b37ed0SZbigniew Bodek 128