1*3fc36ee0SWojciech Macek /******************************************************************************* 2*3fc36ee0SWojciech Macek Copyright (C) 2015 Annapurna Labs Ltd. 3*3fc36ee0SWojciech Macek 4*3fc36ee0SWojciech Macek This file may be licensed under the terms of the Annapurna Labs Commercial 5*3fc36ee0SWojciech Macek License Agreement. 6*3fc36ee0SWojciech Macek 7*3fc36ee0SWojciech Macek Alternatively, this file can be distributed under the terms of the GNU General 8*3fc36ee0SWojciech Macek Public License V2 as published by the Free Software Foundation and can be 9*3fc36ee0SWojciech Macek found at http://www.gnu.org/licenses/gpl-2.0.html 10*3fc36ee0SWojciech Macek 11*3fc36ee0SWojciech Macek Alternatively, redistribution and use in source and binary forms, with or 12*3fc36ee0SWojciech Macek without modification, are permitted provided that the following conditions are 13*3fc36ee0SWojciech Macek met: 14*3fc36ee0SWojciech Macek 15*3fc36ee0SWojciech Macek * Redistributions of source code must retain the above copyright notice, 16*3fc36ee0SWojciech Macek this list of conditions and the following disclaimer. 17*3fc36ee0SWojciech Macek 18*3fc36ee0SWojciech Macek * Redistributions in binary form must reproduce the above copyright 19*3fc36ee0SWojciech Macek notice, this list of conditions and the following disclaimer in 20*3fc36ee0SWojciech Macek the documentation and/or other materials provided with the 21*3fc36ee0SWojciech Macek distribution. 22*3fc36ee0SWojciech Macek 23*3fc36ee0SWojciech Macek THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 24*3fc36ee0SWojciech Macek ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25*3fc36ee0SWojciech Macek WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26*3fc36ee0SWojciech Macek DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 27*3fc36ee0SWojciech Macek ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28*3fc36ee0SWojciech Macek (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29*3fc36ee0SWojciech Macek LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30*3fc36ee0SWojciech Macek ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31*3fc36ee0SWojciech Macek (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32*3fc36ee0SWojciech Macek SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33*3fc36ee0SWojciech Macek 34*3fc36ee0SWojciech Macek *******************************************************************************/ 35*3fc36ee0SWojciech Macek #ifndef _AL_SERDES_25G_INTERNAL_REGS_H_ 36*3fc36ee0SWojciech Macek #define _AL_SERDES_25G_INTERNAL_REGS_H_ 37*3fc36ee0SWojciech Macek 38*3fc36ee0SWojciech Macek #ifdef _cplusplus 39*3fc36ee0SWojciech Macek extern "C" { 40*3fc36ee0SWojciech Macek #endif 41*3fc36ee0SWojciech Macek 42*3fc36ee0SWojciech Macek /******************************************************************************* 43*3fc36ee0SWojciech Macek * TOP Registers 44*3fc36ee0SWojciech Macek ******************************************************************************/ 45*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_BASE 0x00 46*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_SIZE 0x200 47*3fc36ee0SWojciech Macek 48*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_PHY_STAT0_ADDR 0x00 49*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_PHY_CTRL0_ADDR 0x08 50*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_PHY_CFG0_ADDR 0x09 51*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL0_ADDR 0x30 52*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL1_ADDR 0x31 53*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_ADDR 0x32 54*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_STATUS0_ADDR 0x33 55*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_ATEST_CTRL0_ADDR 0x38 56*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_ATEST_CTRL1_ADDR 0x39 57*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_CM0_ADDR 0x50 58*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_ADDR 0x54 59*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_ADDR 0x55 60*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_ADDR 0x56 61*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_ADDR 0x57 62*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_ADDR 0x100 63*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_ADDR 0x101 64*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_REFCLK_ADDR 0x102 65*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_ADDR 0x103 66*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_ADDR 0x104 67*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_ADDR 0x105 68*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_ADDR 0x106 69*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL1_ADDR 0x107 70*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_ADDR 0x108 71*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL1_ADDR 0x109 72*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_ADDR 0x10A 73*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_ADDR 0x110 74*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_ADDR 0x111 75*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_ADDR 0x112 76*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_ADDR 0x113 77*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_ADDR 0x118 78*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_ADDR 0x119 79*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_ADDR 0x11A 80*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RXDIV_CORE_ADDR 0x11B 81*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_ADDR 0x120 82*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_ADDR 0x121 83*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_ADDR 0x122 84*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RXDIV_CORE_ADDR 0x123 85*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_ADDR 0x128 86*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_ADDR 0x129 87*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_ADDR 0x12A 88*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RXDIV_CORE_ADDR 0x12B 89*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_LOS_INT_EN_CTRL_ADDR 0x130 90*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_INT0_STATUS_ADDR 0x131 91*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_TIMER_ADDR 0x170 92*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_ERR_CTRL0_ADDR 0x180 93*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_ERR_CTRL1_ADDR 0x181 94*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_ERR_CTRL2_ADDR 0x182 95*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_ERR_STATUS0_ADDR 0x185 96*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_CTRL_ADDR 0x187 97*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_ADDR 0x188 98*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS1_ADDR 0x189 99*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS2_ADDR 0x18A 100*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS3_ADDR 0x18B 101*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS4_ADDR 0x18C 102*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_ADDR_7_0_ADDR 0x1A0 103*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_ADDR_15_8_ADDR 0x1A1 104*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_CTRL0_ADDR 0x1A2 105*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_CTRL1_ADDR 0x1A3 106*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_DATA_7_0_ADDR 0x1B0 107*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_DATA_11_8_ADDR 0x1B1 108*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_SIM_CTRL_ADDR 0x1C0 109*3fc36ee0SWojciech Macek 110*3fc36ee0SWojciech Macek /******************************************************************************* 111*3fc36ee0SWojciech Macek * masks and shifts 112*3fc36ee0SWojciech Macek ******************************************************************************/ 113*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_PHY_STAT0_PHY_CTRL_CFG_MASK 0x0F 114*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_PHY_STAT0_PHY_CTRL_CFG_SHIFT 0 115*3fc36ee0SWojciech Macek 116*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_PHY_CTRL0_PHY_CTRL_CFG_OVR_VAL_MASK 0x0F 117*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_PHY_CTRL0_PHY_CTRL_CFG_OVR_VAL_SHIFT 0 118*3fc36ee0SWojciech Macek 119*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_PHY_CTRL0_OVR_EN_MASK 0x80 120*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_PHY_CTRL0_OVR_EN_SHIFT 7 121*3fc36ee0SWojciech Macek 122*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_PHY_CFG0_CPU_CLK_FREQ_MASK 0xFF 123*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_PHY_CFG0_CPU_CLK_FREQ_SHIFT 0 124*3fc36ee0SWojciech Macek 125*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL0_ACAL_EN_MASK 0x0F 126*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL0_ACAL_EN_SHIFT 0 127*3fc36ee0SWojciech Macek 128*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL1_ACAL_SEL_MASK 0x1F 129*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL1_ACAL_SEL_SHIFT 0 130*3fc36ee0SWojciech Macek 131*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_EN_MASK 0x01 132*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_EN_SHIFT 0 133*3fc36ee0SWojciech Macek 134*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_MUTE_MASK 0x02 135*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_MUTE_SHIFT 1 136*3fc36ee0SWojciech Macek 137*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SEL_MASK 0x04 138*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SEL_SHIFT 2 139*3fc36ee0SWojciech Macek 140*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SPARE_MASK 0xF0 141*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SPARE_SHIFT 4 142*3fc36ee0SWojciech Macek 143*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_STATUS0_CALCOMP_OUT_MASK 0x01 144*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_CALCOMP_STATUS0_CALCOMP_OUT_SHIFT 0 145*3fc36ee0SWojciech Macek 146*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_ATEST_CTRL0_ATEST_EN_MASK 0x0F 147*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_ATEST_CTRL0_ATEST_EN_SHIFT 0 148*3fc36ee0SWojciech Macek 149*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_ATEST_CTRL1_ATEST_SEL_MASK 0x3F 150*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_AFE_ATEST_CTRL1_ATEST_SEL_SHIFT 0 151*3fc36ee0SWojciech Macek 152*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_CM0_CORE_SW_RESET_MASK 0x01 153*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_CM0_CORE_SW_RESET_SHIFT 0 154*3fc36ee0SWojciech Macek 155*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_CM0_REG_SW_RESET_MASK 0x02 156*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_CM0_REG_SW_RESET_SHIFT 1 157*3fc36ee0SWojciech Macek 158*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_CM0_SUBCORE_SW_RESET_MASK 0x04 159*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_CM0_SUBCORE_SW_RESET_SHIFT 2 160*3fc36ee0SWojciech Macek 161*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_CM0_CAL_SW_RESET_MASK 0x40 162*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_CM0_CAL_SW_RESET_SHIFT 6 163*3fc36ee0SWojciech Macek 164*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_CORE_SW_RESET_MASK 0x01 165*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_CORE_SW_RESET_SHIFT 0 166*3fc36ee0SWojciech Macek 167*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_REG_SW_RESET_MASK 0x02 168*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_REG_SW_RESET_SHIFT 1 169*3fc36ee0SWojciech Macek 170*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_SUBCORE_SW_RESET_MASK 0x04 171*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_SUBCORE_SW_RESET_SHIFT 2 172*3fc36ee0SWojciech Macek 173*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_TXDP_SW_RESET_MASK 0x08 174*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_TXDP_SW_RESET_SHIFT 3 175*3fc36ee0SWojciech Macek 176*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_RXDP_SW_RESET_MASK 0x10 177*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_RXDP_SW_RESET_SHIFT 4 178*3fc36ee0SWojciech Macek 179*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_LOS_SW_RESET_MASK 0x20 180*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_LOS_SW_RESET_SHIFT 5 181*3fc36ee0SWojciech Macek 182*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_CAL_SW_RESET_MASK 0x40 183*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN0_CAL_SW_RESET_SHIFT 6 184*3fc36ee0SWojciech Macek 185*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_CORE_SW_RESET_MASK 0x01 186*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_CORE_SW_RESET_SHIFT 0 187*3fc36ee0SWojciech Macek 188*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_REG_SW_RESET_MASK 0x02 189*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_REG_SW_RESET_SHIFT 1 190*3fc36ee0SWojciech Macek 191*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_SUBCORE_SW_RESET_MASK 0x04 192*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_SUBCORE_SW_RESET_SHIFT 2 193*3fc36ee0SWojciech Macek 194*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_TXDP_SW_RESET_MASK 0x08 195*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_TXDP_SW_RESET_SHIFT 3 196*3fc36ee0SWojciech Macek 197*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_RXDP_SW_RESET_MASK 0x10 198*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_RXDP_SW_RESET_SHIFT 4 199*3fc36ee0SWojciech Macek 200*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_LOS_SW_RESET_MASK 0x20 201*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_LOS_SW_RESET_SHIFT 5 202*3fc36ee0SWojciech Macek 203*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_CAL_SW_RESET_MASK 0x40 204*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN1_CAL_SW_RESET_SHIFT 6 205*3fc36ee0SWojciech Macek 206*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_CORE_SW_RESET_MASK 0x01 207*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_CORE_SW_RESET_SHIFT 0 208*3fc36ee0SWojciech Macek 209*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_REG_SW_RESET_MASK 0x02 210*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_REG_SW_RESET_SHIFT 1 211*3fc36ee0SWojciech Macek 212*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_SUBCORE_SW_RESET_MASK 0x04 213*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_SUBCORE_SW_RESET_SHIFT 2 214*3fc36ee0SWojciech Macek 215*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_TXDP_SW_RESET_MASK 0x08 216*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_TXDP_SW_RESET_SHIFT 3 217*3fc36ee0SWojciech Macek 218*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_RXDP_SW_RESET_MASK 0x10 219*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_RXDP_SW_RESET_SHIFT 4 220*3fc36ee0SWojciech Macek 221*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_LOS_SW_RESET_MASK 0x20 222*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_LOS_SW_RESET_SHIFT 5 223*3fc36ee0SWojciech Macek 224*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_CAL_SW_RESET_MASK 0x40 225*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN2_CAL_SW_RESET_SHIFT 6 226*3fc36ee0SWojciech Macek 227*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_CORE_SW_RESET_MASK 0x01 228*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_CORE_SW_RESET_SHIFT 0 229*3fc36ee0SWojciech Macek 230*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_REG_SW_RESET_MASK 0x02 231*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_REG_SW_RESET_SHIFT 1 232*3fc36ee0SWojciech Macek 233*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_SUBCORE_SW_RESET_MASK 0x04 234*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_SUBCORE_SW_RESET_SHIFT 2 235*3fc36ee0SWojciech Macek 236*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_TXDP_SW_RESET_MASK 0x08 237*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_TXDP_SW_RESET_SHIFT 3 238*3fc36ee0SWojciech Macek 239*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_RXDP_SW_RESET_MASK 0x10 240*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_RXDP_SW_RESET_SHIFT 4 241*3fc36ee0SWojciech Macek 242*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_LOS_SW_RESET_MASK 0x20 243*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_LOS_SW_RESET_SHIFT 5 244*3fc36ee0SWojciech Macek 245*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_CAL_SW_RESET_MASK 0x40 246*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RESET_CTRL_LN3_CAL_SW_RESET_SHIFT 6 247*3fc36ee0SWojciech Macek 248*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_SRC_SEL_MASK 0x01 249*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_SRC_SEL_SHIFT 0 250*3fc36ee0SWojciech Macek 251*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_DEFAULT_CLK_EN_MASK 0x02 252*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_DEFAULT_CLK_EN_SHIFT 1 253*3fc36ee0SWojciech Macek 254*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_REF_CLK_EN_MASK 0x04 255*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_REF_CLK_EN_SHIFT 2 256*3fc36ee0SWojciech Macek 257*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_MASK 0x80 258*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_SHIFT 7 259*3fc36ee0SWojciech Macek 260*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_DIV_SEL_MASK 0x01 261*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_DIV_SEL_SHIFT 0 262*3fc36ee0SWojciech Macek 263*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_MASK 0x80 264*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_SHIFT 7 265*3fc36ee0SWojciech Macek 266*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_CG_EN_MASK 0x01 267*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_CG_EN_SHIFT 0 268*3fc36ee0SWojciech Macek 269*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_TBUS_OUT_CG_EN_MASK 0x80 270*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_TBUS_OUT_CG_EN_SHIFT 7 271*3fc36ee0SWojciech Macek 272*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_DIV_SEL_MASK 0x07 273*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_DIV_SEL_SHIFT 0 274*3fc36ee0SWojciech Macek 275*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_TBUS_OUT_CG_EN_MASK 0x80 276*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_TBUS_OUT_CG_EN_SHIFT 7 277*3fc36ee0SWojciech Macek 278*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_DIV_SEL_MASK 0x07 279*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_DIV_SEL_SHIFT 0 280*3fc36ee0SWojciech Macek 281*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_TBUS_OUT_CG_EN_MASK 0x80 282*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_TBUS_OUT_CG_EN_SHIFT 7 283*3fc36ee0SWojciech Macek 284*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_DIV_SEL_MASK 0x01 285*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_DIV_SEL_SHIFT 0 286*3fc36ee0SWojciech Macek 287*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_CG_EN_MASK 0x02 288*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_CG_EN_SHIFT 1 289*3fc36ee0SWojciech Macek 290*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_TBUS_OUT_CG_EN_MASK 0x80 291*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_TBUS_OUT_CG_EN_SHIFT 7 292*3fc36ee0SWojciech Macek 293*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_SRC_SEL_MASK 0x01 294*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_SRC_SEL_SHIFT 0 295*3fc36ee0SWojciech Macek 296*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_DEFAULT_CLK_EN_MASK 0x02 297*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_DEFAULT_CLK_EN_SHIFT 1 298*3fc36ee0SWojciech Macek 299*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_CMU_CLK_EN_MASK 0x04 300*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_CMU_CLK_EN_SHIFT 2 301*3fc36ee0SWojciech Macek 302*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_DIV_SEL_MASK 0xF8 303*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_DIV_SEL_SHIFT 3 304*3fc36ee0SWojciech Macek 305*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN_MASK 0x80 306*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN_SHIFT 7 307*3fc36ee0SWojciech Macek 308*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_SRC_SEL_MASK 0x01 309*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_SRC_SEL_SHIFT 0 310*3fc36ee0SWojciech Macek 311*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_DEFAULT_CLK_EN_MASK 0x02 312*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_DEFAULT_CLK_EN_SHIFT 1 313*3fc36ee0SWojciech Macek 314*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_CMUDIV_CLK_EN_MASK 0x04 315*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_CMUDIV_CLK_EN_SHIFT 2 316*3fc36ee0SWojciech Macek 317*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_DIV_SEL_MASK 0xF8 318*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_DIV_SEL_SHIFT 3 319*3fc36ee0SWojciech Macek 320*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN_MASK 0x80 321*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN_SHIFT 7 322*3fc36ee0SWojciech Macek 323*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_FRCDIV_MODE_EN_MASK 0x01 324*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_FRCDIV_MODE_EN_SHIFT 0 325*3fc36ee0SWojciech Macek 326*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_SRC_SEL_MASK 0x06 327*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_SRC_SEL_SHIFT 1 328*3fc36ee0SWojciech Macek 329*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_DIV_SEL_MASK 0x08 330*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_DIV_SEL_SHIFT 3 331*3fc36ee0SWojciech Macek 332*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_TBUS_OUT_CG_EN_MASK 0x80 333*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_TBUS_OUT_CG_EN_SHIFT 7 334*3fc36ee0SWojciech Macek 335*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_SRC_SEL_MASK 0x03 336*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_SRC_SEL_SHIFT 0 337*3fc36ee0SWojciech Macek 338*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_DIV_SEL_MASK 0x04 339*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_DIV_SEL_SHIFT 2 340*3fc36ee0SWojciech Macek 341*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_MASK 0x10 342*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_SHIFT 4 343*3fc36ee0SWojciech Macek 344*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 345*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 346*3fc36ee0SWojciech Macek 347*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_SRC_SEL_MASK 0x01 348*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_SRC_SEL_SHIFT 0 349*3fc36ee0SWojciech Macek 350*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_DEFAULT_CLK_EN_MASK 0x02 351*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT 1 352*3fc36ee0SWojciech Macek 353*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_RX_CLK_EN_MASK 0x04 354*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_RX_CLK_EN_SHIFT 2 355*3fc36ee0SWojciech Macek 356*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 357*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 358*3fc36ee0SWojciech Macek 359*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_SRC_SEL_MASK 0x03 360*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_SRC_SEL_SHIFT 0 361*3fc36ee0SWojciech Macek 362*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_MASK 0x10 363*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_SHIFT 4 364*3fc36ee0SWojciech Macek 365*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_MASK 0x20 366*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_SHIFT 5 367*3fc36ee0SWojciech Macek 368*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 369*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 370*3fc36ee0SWojciech Macek 371*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_SRC_SEL_MASK 0x01 372*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_SRC_SEL_SHIFT 0 373*3fc36ee0SWojciech Macek 374*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_DEFAULT_CLK_EN_MASK 0x02 375*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_DEFAULT_CLK_EN_SHIFT 1 376*3fc36ee0SWojciech Macek 377*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_RX_CLKDIV_EN_MASK 0x04 378*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_RX_CLKDIV_EN_SHIFT 2 379*3fc36ee0SWojciech Macek 380*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_TBUS_OUT_CG_EN_MASK 0x80 381*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_TBUS_OUT_CG_EN_SHIFT 7 382*3fc36ee0SWojciech Macek 383*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_SRC_SEL_MASK 0x03 384*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_SRC_SEL_SHIFT 0 385*3fc36ee0SWojciech Macek 386*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_DIV_SEL_MASK 0x04 387*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_DIV_SEL_SHIFT 2 388*3fc36ee0SWojciech Macek 389*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_MASK 0x10 390*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_SHIFT 4 391*3fc36ee0SWojciech Macek 392*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 393*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 394*3fc36ee0SWojciech Macek 395*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_SRC_SEL_MASK 0x01 396*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_SRC_SEL_SHIFT 0 397*3fc36ee0SWojciech Macek 398*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_DEFAULT_CLK_EN_MASK 0x02 399*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT 1 400*3fc36ee0SWojciech Macek 401*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_RX_CLK_EN_MASK 0x04 402*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_RX_CLK_EN_SHIFT 2 403*3fc36ee0SWojciech Macek 404*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 405*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 406*3fc36ee0SWojciech Macek 407*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_SRC_SEL_MASK 0x03 408*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_SRC_SEL_SHIFT 0 409*3fc36ee0SWojciech Macek 410*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_MASK 0x10 411*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_SHIFT 4 412*3fc36ee0SWojciech Macek 413*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_MASK 0x20 414*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_SHIFT 5 415*3fc36ee0SWojciech Macek 416*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 417*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 418*3fc36ee0SWojciech Macek 419*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_SRC_SEL_MASK 0x03 420*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_SRC_SEL_SHIFT 0 421*3fc36ee0SWojciech Macek 422*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_DIV_SEL_MASK 0x04 423*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_DIV_SEL_SHIFT 2 424*3fc36ee0SWojciech Macek 425*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_BIST_CG_EN_MASK 0x10 426*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_BIST_CG_EN_SHIFT 4 427*3fc36ee0SWojciech Macek 428*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 429*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 430*3fc36ee0SWojciech Macek 431*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_SRC_SEL_MASK 0x01 432*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_SRC_SEL_SHIFT 0 433*3fc36ee0SWojciech Macek 434*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_DEFAULT_CLK_EN_MASK 0x02 435*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT 1 436*3fc36ee0SWojciech Macek 437*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_RX_CLK_EN_MASK 0x04 438*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_RX_CLK_EN_SHIFT 2 439*3fc36ee0SWojciech Macek 440*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 441*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 442*3fc36ee0SWojciech Macek 443*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_SRC_SEL_MASK 0x03 444*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_SRC_SEL_SHIFT 0 445*3fc36ee0SWojciech Macek 446*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_CG_EN_MASK 0x10 447*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_CG_EN_SHIFT 4 448*3fc36ee0SWojciech Macek 449*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_BIST_CG_EN_MASK 0x20 450*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_BIST_CG_EN_SHIFT 5 451*3fc36ee0SWojciech Macek 452*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 453*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 454*3fc36ee0SWojciech Macek 455*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_SRC_SEL_MASK 0x03 456*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_SRC_SEL_SHIFT 0 457*3fc36ee0SWojciech Macek 458*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_DIV_SEL_MASK 0x04 459*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_DIV_SEL_SHIFT 2 460*3fc36ee0SWojciech Macek 461*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_BIST_CG_EN_MASK 0x10 462*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_BIST_CG_EN_SHIFT 4 463*3fc36ee0SWojciech Macek 464*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 465*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 466*3fc36ee0SWojciech Macek 467*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_SRC_SEL_MASK 0x01 468*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_SRC_SEL_SHIFT 0 469*3fc36ee0SWojciech Macek 470*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_DEFAULT_CLK_EN_MASK 0x02 471*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT 1 472*3fc36ee0SWojciech Macek 473*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_RX_CLK_EN_MASK 0x04 474*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_RX_CLK_EN_SHIFT 2 475*3fc36ee0SWojciech Macek 476*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 477*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 478*3fc36ee0SWojciech Macek 479*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_SRC_SEL_MASK 0x03 480*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_SRC_SEL_SHIFT 0 481*3fc36ee0SWojciech Macek 482*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_CG_EN_MASK 0x10 483*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_CG_EN_SHIFT 4 484*3fc36ee0SWojciech Macek 485*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_BIST_CG_EN_MASK 0x20 486*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_BIST_CG_EN_SHIFT 5 487*3fc36ee0SWojciech Macek 488*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 489*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 490*3fc36ee0SWojciech Macek 491*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN0_MASK 0x01 492*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN0_SHIFT 0 493*3fc36ee0SWojciech Macek 494*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN1_MASK 0x02 495*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN1_SHIFT 1 496*3fc36ee0SWojciech Macek 497*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN2_MASK 0x04 498*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN2_SHIFT 2 499*3fc36ee0SWojciech Macek 500*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN3_MASK 0x08 501*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN3_SHIFT 3 502*3fc36ee0SWojciech Macek 503*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_TIMER_LOAD_VAL_MASK 0xFF 504*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_TIMER_LOAD_VAL_SHIFT 0 505*3fc36ee0SWojciech Macek 506*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_ERR_CTRL0_ERR_MASK 0x01 507*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_ERR_CTRL0_ERR_SHIFT 0 508*3fc36ee0SWojciech Macek 509*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK 0xFF 510*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT 0 511*3fc36ee0SWojciech Macek 512*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK 0xFF 513*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT 0 514*3fc36ee0SWojciech Macek 515*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_ERR_STATUS0_REGBUS_ERR_MASK 0x01 516*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_ERR_STATUS0_REGBUS_ERR_SHIFT 0 517*3fc36ee0SWojciech Macek 518*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_CTRL_CLR_MASK 0x01 519*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_CTRL_CLR_SHIFT 0 520*3fc36ee0SWojciech Macek 521*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_ERR_TYPE_MASK 0x03 522*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_ERR_TYPE_SHIFT 0 523*3fc36ee0SWojciech Macek 524*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_TRANSFER_RW_MASK 0x04 525*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_TRANSFER_RW_SHIFT 2 526*3fc36ee0SWojciech Macek 527*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS1_TRANSFER_ADDR_LSB_MASK 0xFF 528*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS1_TRANSFER_ADDR_LSB_SHIFT 0 529*3fc36ee0SWojciech Macek 530*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS2_TRANSFER_ADDR_MSB_MASK 0x7F 531*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS2_TRANSFER_ADDR_MSB_SHIFT 0 532*3fc36ee0SWojciech Macek 533*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS3_TRANSFER_WD_MASK 0xFF 534*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS3_TRANSFER_WD_SHIFT 0 535*3fc36ee0SWojciech Macek 536*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS4_TRANSFER_WR_BIT_EN_MASK 0xFF 537*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS4_TRANSFER_WR_BIT_EN_SHIFT 0 538*3fc36ee0SWojciech Macek 539*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_ADDR_7_0_MASK 0xFF 540*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_ADDR_7_0_SHIFT 0 541*3fc36ee0SWojciech Macek 542*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_ADDR_15_8_MASK 0xFF 543*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_ADDR_15_8_SHIFT 0 544*3fc36ee0SWojciech Macek 545*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_CTRL0_CLOCK_GATE0_MASK 0xFF 546*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_CTRL0_CLOCK_GATE0_SHIFT 0 547*3fc36ee0SWojciech Macek 548*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_CTRL1_CLOCK_GATE1_MASK 0xFF 549*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_CTRL1_CLOCK_GATE1_SHIFT 0 550*3fc36ee0SWojciech Macek 551*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_DATA_7_0_MASK 0xFF 552*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_DATA_7_0_SHIFT 0 553*3fc36ee0SWojciech Macek 554*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_DATA_11_8_MASK 0x0F 555*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_TBUS_DATA_11_8_SHIFT 0 556*3fc36ee0SWojciech Macek 557*3fc36ee0SWojciech Macek /*********************************** Mailbox **********************************/ 558*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_MB_BASE 0x200 559*3fc36ee0SWojciech Macek 560*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_ADDR (SERDES_25G_TOP_MB_BASE + 0x00) 561*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_FLAG_ADDR (SERDES_25G_TOP_MB_BASE + 0x02) 562*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA0_ADDR (SERDES_25G_TOP_MB_BASE + 0x03) 563*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA1_ADDR (SERDES_25G_TOP_MB_BASE + 0x04) 564*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA2_ADDR (SERDES_25G_TOP_MB_BASE + 0x05) 565*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA3_ADDR (SERDES_25G_TOP_MB_BASE + 0x06) 566*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA4_ADDR (SERDES_25G_TOP_MB_BASE + 0x07) 567*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA5_ADDR (SERDES_25G_TOP_MB_BASE + 0x08) 568*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA6_ADDR (SERDES_25G_TOP_MB_BASE + 0x09) 569*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA7_ADDR (SERDES_25G_TOP_MB_BASE + 0x0A) 570*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_ADDR (SERDES_25G_TOP_MB_BASE + 0x10) 571*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_FLAG_ADDR (SERDES_25G_TOP_MB_BASE + 0x12) 572*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA0_ADDR (SERDES_25G_TOP_MB_BASE + 0x13) 573*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA1_ADDR (SERDES_25G_TOP_MB_BASE + 0x14) 574*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA2_ADDR (SERDES_25G_TOP_MB_BASE + 0x15) 575*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA3_ADDR (SERDES_25G_TOP_MB_BASE + 0x16) 576*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA4_ADDR (SERDES_25G_TOP_MB_BASE + 0x17) 577*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA5_ADDR (SERDES_25G_TOP_MB_BASE + 0x18) 578*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA6_ADDR (SERDES_25G_TOP_MB_BASE + 0x19) 579*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA7_ADDR (SERDES_25G_TOP_MB_BASE + 0x1A) 580*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA8_ADDR (SERDES_25G_TOP_MB_BASE + 0x1B) 581*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA9_ADDR (SERDES_25G_TOP_MB_BASE + 0x1C) 582*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA10_ADDR (SERDES_25G_TOP_MB_BASE + 0x1D) 583*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA11_ADDR (SERDES_25G_TOP_MB_BASE + 0x1E) 584*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA12_ADDR (SERDES_25G_TOP_MB_BASE + 0x1F) 585*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA13_ADDR (SERDES_25G_TOP_MB_BASE + 0x20) 586*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA14_ADDR (SERDES_25G_TOP_MB_BASE + 0x21) 587*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA15_ADDR (SERDES_25G_TOP_MB_BASE + 0x22) 588*3fc36ee0SWojciech Macek /******************************************************************************* 589*3fc36ee0SWojciech Macek * masks and shifts 590*3fc36ee0SWojciech Macek ******************************************************************************/ 591*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_MASK 0xFF 592*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_SHIFT 0 593*3fc36ee0SWojciech Macek 594*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_FLAG_MASK 0x01 595*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_FLAG_SHIFT 0 596*3fc36ee0SWojciech Macek 597*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA0_MASK 0xFF 598*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA0_SHIFT 0 599*3fc36ee0SWojciech Macek 600*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA1_MASK 0xFF 601*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA1_SHIFT 0 602*3fc36ee0SWojciech Macek 603*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA2_MASK 0xFF 604*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA2_SHIFT 0 605*3fc36ee0SWojciech Macek 606*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA3_MASK 0xFF 607*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA3_SHIFT 0 608*3fc36ee0SWojciech Macek 609*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA4_MASK 0xFF 610*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA4_SHIFT 0 611*3fc36ee0SWojciech Macek 612*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA5_MASK 0xFF 613*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA5_SHIFT 0 614*3fc36ee0SWojciech Macek 615*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA6_MASK 0xFF 616*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA6_SHIFT 0 617*3fc36ee0SWojciech Macek 618*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA7_MASK 0xFF 619*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_CMD_DATA7_SHIFT 0 620*3fc36ee0SWojciech Macek 621*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_MASK 0xFF 622*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_SHIFT 0 623*3fc36ee0SWojciech Macek 624*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_FLAG_MASK 0x01 625*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_FLAG_SHIFT 0 626*3fc36ee0SWojciech Macek 627*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA0_MASK 0xFF 628*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA0_SHIFT 0 629*3fc36ee0SWojciech Macek 630*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA1_MASK 0xFF 631*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA1_SHIFT 0 632*3fc36ee0SWojciech Macek 633*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA2_MASK 0xFF 634*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA2_SHIFT 0 635*3fc36ee0SWojciech Macek 636*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA3_MASK 0xFF 637*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA3_SHIFT 0 638*3fc36ee0SWojciech Macek 639*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA4_MASK 0xFF 640*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA4_SHIFT 0 641*3fc36ee0SWojciech Macek 642*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA5_MASK 0xFF 643*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA5_SHIFT 0 644*3fc36ee0SWojciech Macek 645*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA6_MASK 0xFF 646*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA6_SHIFT 0 647*3fc36ee0SWojciech Macek 648*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA7_MASK 0xFF 649*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA7_SHIFT 0 650*3fc36ee0SWojciech Macek 651*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA8_MASK 0xFF 652*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA8_SHIFT 0 653*3fc36ee0SWojciech Macek 654*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA9_MASK 0xFF 655*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA9_SHIFT 0 656*3fc36ee0SWojciech Macek 657*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA10_MASK 0xFF 658*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA10_SHIFT 0 659*3fc36ee0SWojciech Macek 660*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA11_MASK 0xFF 661*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA11_SHIFT 0 662*3fc36ee0SWojciech Macek 663*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA12_MASK 0xFF 664*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA12_SHIFT 0 665*3fc36ee0SWojciech Macek 666*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA13_MASK 0xFF 667*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA13_SHIFT 0 668*3fc36ee0SWojciech Macek 669*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA14_MASK 0xFF 670*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA14_SHIFT 0 671*3fc36ee0SWojciech Macek 672*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA15_MASK 0xFF 673*3fc36ee0SWojciech Macek #define SERDES_25G_TOP_RSP_DATA15_SHIFT 0 674*3fc36ee0SWojciech Macek 675*3fc36ee0SWojciech Macek /******************************************************************************* 676*3fc36ee0SWojciech Macek * Common Registers 677*3fc36ee0SWojciech Macek ******************************************************************************/ 678*3fc36ee0SWojciech Macek #define SERDES_25G_CM_BASE 0xC00 679*3fc36ee0SWojciech Macek #define SERDES_25G_CM_SIZE 0x400 680*3fc36ee0SWojciech Macek 681*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_PD_CTRL0_ADDR 0x00 682*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_PD_CTRL1_ADDR 0x01 683*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_RST_CTRL0_ADDR 0x03 684*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_BIAS_CTRL0_ADDR 0x05 685*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_BIAS_CTRL1_ADDR 0x06 686*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_BIAS_CTRL2_ADDR 0x07 687*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_BIAS_CTRL3_ADDR 0x08 688*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_BIAS_CTRL4_ADDR 0x09 689*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_BIAS_CTRL5_ADDR 0x0A 690*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_REG_CTRL0_ADDR 0x0C 691*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_REFCLK_CTRL0_ADDR 0x1A 692*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_REFCLK_CTRL1_ADDR 0x1B 693*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_REFCLK_CTRL2_ADDR 0x1F 694*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_CMCP_CTRL0_ADDR 0x20 695*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_CMCP_CTRL1_ADDR 0x21 696*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_CMCP_CTRL2_ADDR 0x22 697*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_MISC_CTRL0_ADDR 0x23 698*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_CMCP_STATUS_ADDR 0x24 699*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_TOGGLE_CTRL0_ADDR 0x25 700*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_TSTCLK_CTRL0_ADDR 0x28 701*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_TXTC_CTRL0_ADDR 0x30 702*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_TXTC_CTRL1_ADDR 0x31 703*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_TXTC_CTRL2_ADDR 0x32 704*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_TXTC_CTRL3_ADDR 0x33 705*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_AFE_TXTC_CTRL4_ADDR 0x34 706*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_PWR_STATE_REQ_STATUS_ADDR 0x50 707*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_PWR_STATE_ACK_CTRL_ADDR 0x51 708*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_PHY_IF_STATUS_ADDR 0x52 709*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_CMU_TOP_SPARE0_ADDR 0x58 710*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_CMU_TOP_SPARE1_ADDR 0x59 711*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_ERR_CTRL1_ADDR 0x80 712*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_ERR_CTRL2_ADDR 0x81 713*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_ERR_CTRL3_ADDR 0x82 714*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_CMU_IF_OVR_CTRL0_ADDR 0x8A 715*3fc36ee0SWojciech Macek #define SERDES_25G_CM_TOP_CMU_IF_OVR_CTRL1_ADDR 0x8B 716*3fc36ee0SWojciech Macek /******************************************************************************* 717*3fc36ee0SWojciech Macek * masks and shifts 718*3fc36ee0SWojciech Macek ******************************************************************************/ 719*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_MASK 0x01 720*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_SHIFT 0 721*3fc36ee0SWojciech Macek 722*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICV_MASK 0x02 723*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICV_SHIFT 1 724*3fc36ee0SWojciech Macek 725*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICC_MASK 0x04 726*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICC_SHIFT 2 727*3fc36ee0SWojciech Macek 728*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_IPTAT_MASK 0x08 729*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_IPTAT_SHIFT 3 730*3fc36ee0SWojciech Macek 731*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_SLAVE_MASK 0x10 732*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_SLAVE_SHIFT 4 733*3fc36ee0SWojciech Macek 734*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REG_REF_MASK 0x20 735*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REG_REF_SHIFT 5 736*3fc36ee0SWojciech Macek 737*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REFCLK_MASK 0x40 738*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REFCLK_SHIFT 6 739*3fc36ee0SWojciech Macek 740*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_MASK 0x01 741*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_SHIFT 0 742*3fc36ee0SWojciech Macek 743*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_LEFT_MASK 0x02 744*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_LEFT_SHIFT 1 745*3fc36ee0SWojciech Macek 746*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_RIGHT_MASK 0x04 747*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_RIGHT_SHIFT 2 748*3fc36ee0SWojciech Macek 749*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMU_N_MASK 0x01 750*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMU_N_SHIFT 0 751*3fc36ee0SWojciech Macek 752*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMUDIV_N_MASK 0x02 753*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMUDIV_N_SHIFT 1 754*3fc36ee0SWojciech Macek 755*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICV_TRIM_MASK 0x0F 756*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICV_TRIM_SHIFT 0 757*3fc36ee0SWojciech Macek 758*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICC_TRIM_MASK 0xF0 759*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICC_TRIM_SHIFT 4 760*3fc36ee0SWojciech Macek 761*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL1_BIAS_IPTAT_TRIM_MASK 0x0F 762*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL1_BIAS_IPTAT_TRIM_SHIFT 0 763*3fc36ee0SWojciech Macek 764*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_BGSTART_BYP_MASK 0x01 765*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_BGSTART_BYP_SHIFT 0 766*3fc36ee0SWojciech Macek 767*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_IPTATSTART_BYP_MASK 0x02 768*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_IPTATSTART_BYP_SHIFT 1 769*3fc36ee0SWojciech Macek 770*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_TERMCAL_EN_MASK 0x04 771*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_TERMCAL_EN_SHIFT 2 772*3fc36ee0SWojciech Macek 773*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_PTRIM_MASK 0x0F 774*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_PTRIM_SHIFT 0 775*3fc36ee0SWojciech Macek 776*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_NTRIM_MASK 0xF0 777*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_NTRIM_SHIFT 4 778*3fc36ee0SWojciech Macek 779*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL4_BIAS_SPARE_MASK 0x0F 780*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL4_BIAS_SPARE_SHIFT 0 781*3fc36ee0SWojciech Macek 782*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL5_BIAS_CALREF_TRIM_MASK 0x0F 783*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL5_BIAS_CALREF_TRIM_SHIFT 0 784*3fc36ee0SWojciech Macek 785*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_PASS_EN_MASK 0x01 786*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_PASS_EN_SHIFT 0 787*3fc36ee0SWojciech Macek 788*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRIM_MASK 0x0E 789*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRIM_SHIFT 1 790*3fc36ee0SWojciech Macek 791*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRICKLE_MASK 0x30 792*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRICKLE_SHIFT 4 793*3fc36ee0SWojciech Macek 794*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DIV_MASK 0x03 795*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DIV_SHIFT 0 796*3fc36ee0SWojciech Macek 797*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DPL_DIV_MASK 0x0C 798*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DPL_DIV_SHIFT 2 799*3fc36ee0SWojciech Macek 800*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DEGLITCH_OVR_MASK 0x10 801*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DEGLITCH_OVR_SHIFT 4 802*3fc36ee0SWojciech Macek 803*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL1_REFCLK_TERM_MASK 0x1F 804*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL1_REFCLK_TERM_SHIFT 0 805*3fc36ee0SWojciech Macek 806*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL2_REFCLK_SPARE_MASK 0x0F 807*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL2_REFCLK_SPARE_SHIFT 0 808*3fc36ee0SWojciech Macek 809*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_QSAMPLE_EN_MASK 0x01 810*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_QSAMPLE_EN_SHIFT 0 811*3fc36ee0SWojciech Macek 812*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_DCD_RANGE_MASK 0x02 813*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_DCD_RANGE_SHIFT 1 814*3fc36ee0SWojciech Macek 815*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUCLK_DIV_MASK 0x1C 816*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUCLK_DIV_SHIFT 2 817*3fc36ee0SWojciech Macek 818*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUDIVCLK_DIV_MASK 0xE0 819*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUDIVCLK_DIV_SHIFT 5 820*3fc36ee0SWojciech Macek 821*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CLKDIV_SWING_MASK 0x03 822*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CLKDIV_SWING_SHIFT 0 823*3fc36ee0SWojciech Macek 824*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_TXCLK_SWING_MASK 0x0C 825*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_TXCLK_SWING_SHIFT 2 826*3fc36ee0SWojciech Macek 827*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CMUCLK_DIV2_BYPASS_MASK 0x10 828*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CMUCLK_DIV2_BYPASS_SHIFT 4 829*3fc36ee0SWojciech Macek 830*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_CLKDIV_OVR_MASK 0x03 831*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_CLKDIV_OVR_SHIFT 0 832*3fc36ee0SWojciech Macek 833*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_BIASI_MASK 0x0C 834*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_BIASI_SHIFT 2 835*3fc36ee0SWojciech Macek 836*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_DIV_MASK 0x70 837*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_DIV_SHIFT 4 838*3fc36ee0SWojciech Macek 839*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_DIV1P5_DUMMY_EN_MASK 0x80 840*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_DIV1P5_DUMMY_EN_SHIFT 7 841*3fc36ee0SWojciech Macek 842*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_MISC_CTRL0_CMCP_SPARE_MASK 0xFF 843*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_MISC_CTRL0_CMCP_SPARE_SHIFT 0 844*3fc36ee0SWojciech Macek 845*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_STATUS_CMCP_DIV1P5_QSAMPLE_MASK 0x0F 846*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_CMCP_STATUS_CMCP_DIV1P5_QSAMPLE_SHIFT 0 847*3fc36ee0SWojciech Macek 848*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CLK_TOGGLE_EN_MASK 0x01 849*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CLK_TOGGLE_EN_SHIFT 0 850*3fc36ee0SWojciech Macek 851*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CMCP_TOGGLE_EN_MASK 0x02 852*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CMCP_TOGGLE_EN_SHIFT 1 853*3fc36ee0SWojciech Macek 854*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_MUX_MASK 0x03 855*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_MUX_SHIFT 0 856*3fc36ee0SWojciech Macek 857*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV_MASK 0x1C 858*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV_SHIFT 2 859*3fc36ee0SWojciech Macek 860*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_SWING_MASK 0x60 861*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_SWING_SHIFT 5 862*3fc36ee0SWojciech Macek 863*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_MASK 0x07 864*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_SHIFT 0 865*3fc36ee0SWojciech Macek 866*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_MASK 0x18 867*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_SHIFT 3 868*3fc36ee0SWojciech Macek 869*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_MASK 0x1F 870*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_SHIFT 0 871*3fc36ee0SWojciech Macek 872*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_MASK 0x60 873*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_SHIFT 5 874*3fc36ee0SWojciech Macek 875*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_MASK 0x07 876*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_SHIFT 0 877*3fc36ee0SWojciech Macek 878*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_MASK 0x18 879*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_SHIFT 3 880*3fc36ee0SWojciech Macek 881*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_MASK 0x1F 882*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_SHIFT 0 883*3fc36ee0SWojciech Macek 884*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_MASK 0x60 885*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_SHIFT 5 886*3fc36ee0SWojciech Macek 887*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_NEG_MASK 0x07 888*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_NEG_SHIFT 0 889*3fc36ee0SWojciech Macek 890*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_POS_MASK 0x70 891*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_POS_SHIFT 4 892*3fc36ee0SWojciech Macek 893*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_STATE_MASK 0x07 894*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_STATE_SHIFT 0 895*3fc36ee0SWojciech Macek 896*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_REQ_MASK 0x08 897*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_REQ_SHIFT 3 898*3fc36ee0SWojciech Macek 899*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_STATE_MASK 0x07 900*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_STATE_SHIFT 0 901*3fc36ee0SWojciech Macek 902*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_ACK_MASK 0x08 903*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_ACK_SHIFT 3 904*3fc36ee0SWojciech Macek 905*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_MASK 0x70 906*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_SHIFT 4 907*3fc36ee0SWojciech Macek 908*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_PHY_IF_STATUS_CMU_OK_MASK 0x01 909*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_PHY_IF_STATUS_CMU_OK_SHIFT 0 910*3fc36ee0SWojciech Macek 911*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_CMU_TOP_SPARE0_MASK 0xFF 912*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_CMU_TOP_SPARE0_SHIFT 0 913*3fc36ee0SWojciech Macek 914*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_CMU_TOP_SPARE1_MASK 0xFF 915*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_CMU_TOP_SPARE1_SHIFT 0 916*3fc36ee0SWojciech Macek 917*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK 0xFF 918*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT 0 919*3fc36ee0SWojciech Macek 920*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK 0xFF 921*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT 0 922*3fc36ee0SWojciech Macek 923*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_ERR_CTRL3_CMU_ERR__MASK 0x01 924*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_ERR_CTRL3_CMU_ERR__SHIFT 0 925*3fc36ee0SWojciech Macek 926*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_EN_MASK 0x01 927*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_EN_SHIFT 0 928*3fc36ee0SWojciech Macek 929*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_VAL_MASK 0x06 930*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_VAL_SHIFT 1 931*3fc36ee0SWojciech Macek 932*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_EN_MASK 0x01 933*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_EN_SHIFT 0 934*3fc36ee0SWojciech Macek 935*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_VAL_MASK 0x02 936*3fc36ee0SWojciech Macek #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_VAL_SHIFT 1 937*3fc36ee0SWojciech Macek 938*3fc36ee0SWojciech Macek 939*3fc36ee0SWojciech Macek /******************************************************************************* 940*3fc36ee0SWojciech Macek * Lane Registers 941*3fc36ee0SWojciech Macek ******************************************************************************/ 942*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_BASE 0x1800 943*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_SIZE 0x800 944*3fc36ee0SWojciech Macek 945*3fc36ee0SWojciech Macek /********************************** LANE_TOP **********************************/ 946*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_ADDR 0x00 947*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_ADDR 0x01 948*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_ADDR 0x02 949*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_ADDR 0x03 950*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_ADDR 0x04 951*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_ADDR 0x05 952*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_ADDR 0x06 953*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_ADDR 0x10 954*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_ADDR 0x12 955*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_ADDR 0x13 956*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_ADDR 0x14 957*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_ADDR 0x16 958*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_ADDR 0x19 959*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_ADDR 0x1B 960*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_ADDR 0x1C 961*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_ADDR 0x22 962*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_ADDR 0x24 963*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_ADDR 0x25 964*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ADDR 0x26 965*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PHY_IF_STATUS_ADDR 0x27 966*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL0_ADDR 0x30 967*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL1_ADDR 0x31 968*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_ADDR 0x38 969*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_ADDR 0x39 970*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_ADDR 0x3A 971*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_ADDR 0x3B 972*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_ADDR 0x3C 973*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_ADDR 0x3D 974*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_ERR_CTRL1_ADDR 0x40 975*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_ERR_CTRL2_ADDR 0x41 976*3fc36ee0SWojciech Macek /******************************************************************************* 977*3fc36ee0SWojciech Macek * masks and shifts 978*3fc36ee0SWojciech Macek ******************************************************************************/ 979*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_MASK 0x01 980*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_SHIFT 0 981*3fc36ee0SWojciech Macek 982*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_MASK 0x02 983*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_SHIFT 1 984*3fc36ee0SWojciech Macek 985*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_MASK 0x04 986*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_SHIFT 2 987*3fc36ee0SWojciech Macek 988*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_MASK 0x08 989*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_SHIFT 3 990*3fc36ee0SWojciech Macek 991*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_MASK 0x01 992*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_SHIFT 0 993*3fc36ee0SWojciech Macek 994*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_MASK 0x02 995*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_SHIFT 1 996*3fc36ee0SWojciech Macek 997*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_MASK 0x01 998*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_SHIFT 0 999*3fc36ee0SWojciech Macek 1000*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_MASK 0x02 1001*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_SHIFT 1 1002*3fc36ee0SWojciech Macek 1003*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_MASK 0x01 1004*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_SHIFT 0 1005*3fc36ee0SWojciech Macek 1006*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_MASK 0x01 1007*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_SHIFT 0 1008*3fc36ee0SWojciech Macek 1009*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_MASK 0x04 1010*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_SHIFT 2 1011*3fc36ee0SWojciech Macek 1012*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_MASK 0x0F 1013*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_SHIFT 0 1014*3fc36ee0SWojciech Macek 1015*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_MASK 0x0F 1016*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_SHIFT 0 1017*3fc36ee0SWojciech Macek 1018*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_MASK 0x30 1019*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_SHIFT 4 1020*3fc36ee0SWojciech Macek 1021*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_MASK 0x40 1022*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_SHIFT 6 1023*3fc36ee0SWojciech Macek 1024*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_MASK 0x01 1025*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_SHIFT 0 1026*3fc36ee0SWojciech Macek 1027*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_MASK 0x06 1028*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_SHIFT 1 1029*3fc36ee0SWojciech Macek 1030*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_MASK 0x0F 1031*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_SHIFT 0 1032*3fc36ee0SWojciech Macek 1033*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_MASK 0x03 1034*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_SHIFT 0 1035*3fc36ee0SWojciech Macek 1036*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_MASK 0x04 1037*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_SHIFT 2 1038*3fc36ee0SWojciech Macek 1039*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_MASK 0xF0 1040*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_SHIFT 4 1041*3fc36ee0SWojciech Macek 1042*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_MASK 0x07 1043*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_SHIFT 0 1044*3fc36ee0SWojciech Macek 1045*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_MASK 0xF0 1046*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_SHIFT 4 1047*3fc36ee0SWojciech Macek 1048*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_MASK 0x07 1049*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_SHIFT 0 1050*3fc36ee0SWojciech Macek 1051*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_MASK 0x08 1052*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_SHIFT 3 1053*3fc36ee0SWojciech Macek 1054*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_MASK 0x10 1055*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_SHIFT 4 1056*3fc36ee0SWojciech Macek 1057*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_MASK 0x1F 1058*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_SHIFT 0 1059*3fc36ee0SWojciech Macek 1060*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_MASK 0x03 1061*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_SHIFT 0 1062*3fc36ee0SWojciech Macek 1063*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_MASK 0x04 1064*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_SHIFT 2 1065*3fc36ee0SWojciech Macek 1066*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_MASK 0x10 1067*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_SHIFT 4 1068*3fc36ee0SWojciech Macek 1069*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_MASK 0x01 1070*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_SHIFT 0 1071*3fc36ee0SWojciech Macek 1072*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_MASK 0x07 1073*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_SHIFT 0 1074*3fc36ee0SWojciech Macek 1075*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_MASK 0x08 1076*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_SHIFT 3 1077*3fc36ee0SWojciech Macek 1078*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_MASK 0x07 1079*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_SHIFT 0 1080*3fc36ee0SWojciech Macek 1081*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_MASK 0x08 1082*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_SHIFT 3 1083*3fc36ee0SWojciech Macek 1084*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_MASK 0x70 1085*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_SHIFT 4 1086*3fc36ee0SWojciech Macek 1087*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_MASK 0x01 1088*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_SHIFT 0 1089*3fc36ee0SWojciech Macek 1090*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_MASK 0x07 1091*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_SHIFT 0 1092*3fc36ee0SWojciech Macek 1093*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_MASK 0x38 1094*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_SHIFT 3 1095*3fc36ee0SWojciech Macek 1096*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_MASK 0x07 1097*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_SHIFT 0 1098*3fc36ee0SWojciech Macek 1099*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_MASK 0x38 1100*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_SHIFT 3 1101*3fc36ee0SWojciech Macek 1102*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_MASK 0x01 1103*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_SHIFT 0 1104*3fc36ee0SWojciech Macek 1105*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_MASK 0x01 1106*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_SHIFT 0 1107*3fc36ee0SWojciech Macek 1108*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_MASK 0x02 1109*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_SHIFT 1 1110*3fc36ee0SWojciech Macek 1111*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_MASK 0x01 1112*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_SHIFT 0 1113*3fc36ee0SWojciech Macek 1114*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_MASK 0x01 1115*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_SHIFT 0 1116*3fc36ee0SWojciech Macek 1117*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_MASK 0x02 1118*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_SHIFT 1 1119*3fc36ee0SWojciech Macek 1120*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_MASK 0x04 1121*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_SHIFT 2 1122*3fc36ee0SWojciech Macek 1123*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_MASK 0x08 1124*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_SHIFT 3 1125*3fc36ee0SWojciech Macek 1126*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_MASK 0x10 1127*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_SHIFT 4 1128*3fc36ee0SWojciech Macek 1129*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_MASK 0x20 1130*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_SHIFT 5 1131*3fc36ee0SWojciech Macek 1132*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_MASK 0x40 1133*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_SHIFT 6 1134*3fc36ee0SWojciech Macek 1135*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_MASK 0x01 1136*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_SHIFT 0 1137*3fc36ee0SWojciech Macek 1138*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_MASK 0x06 1139*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_SHIFT 1 1140*3fc36ee0SWojciech Macek 1141*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_MASK 0x08 1142*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_SHIFT 3 1143*3fc36ee0SWojciech Macek 1144*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_MASK 0x01 1145*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_SHIFT 0 1146*3fc36ee0SWojciech Macek 1147*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_MASK 0x02 1148*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_SHIFT 1 1149*3fc36ee0SWojciech Macek 1150*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK 0xFF 1151*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT 0 1152*3fc36ee0SWojciech Macek 1153*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK 0xFF 1154*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT 0 1155*3fc36ee0SWojciech Macek 1156*3fc36ee0SWojciech Macek /********************************* Lane CDR RXCLK ***************************/ 1157*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_BASE 0x80 1158*3fc36ee0SWojciech Macek 1159*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x10) 1160*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x11) 1161*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x21) 1162*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x22) 1163*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x26) 1164*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x27) 1165*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x28) 1166*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x29) 1167*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x2A) 1168*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x2B) 1169*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x2D) 1170*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x30) 1171*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x31) 1172*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x32) 1173*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x34) 1174*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL4_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x36) 1175*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL5_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x37) 1176*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL6_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x39) 1177*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3A) 1178*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL8_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3B) 1179*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3C) 1180*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3D) 1181*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3E) 1182*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3F) 1183*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x40) 1184*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x41) 1185*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x44) 1186*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x45) 1187*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x46) 1188*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x48) 1189*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x49) 1190*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4A) 1191*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4B) 1192*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4C) 1193*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4D) 1194*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4E) 1195*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4F) 1196*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x60) 1197*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x61) 1198*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x62) 1199*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x63) 1200*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x68) 1201*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x69) 1202*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6A) 1203*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6B) 1204*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6C) 1205*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6D) 1206*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6E) 1207*3fc36ee0SWojciech Macek /******************************************************************************* 1208*3fc36ee0SWojciech Macek * masks and shifts 1209*3fc36ee0SWojciech Macek ******************************************************************************/ 1210*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL0_DLPF_SRC_SEL_MASK 0x01 1211*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL0_DLPF_SRC_SEL_SHIFT 0 1212*3fc36ee0SWojciech Macek 1213*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL1_CFG_DOSC_MIN_MASK 0x07 1214*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL1_CFG_DOSC_MIN_SHIFT 0 1215*3fc36ee0SWojciech Macek 1216*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DECIMATION_MODE_MASK 0x0F 1217*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DECIMATION_MODE_SHIFT 0 1218*3fc36ee0SWojciech Macek 1219*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DLPF_MODE_MASK 0x30 1220*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DLPF_MODE_SHIFT 4 1221*3fc36ee0SWojciech Macek 1222*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL1_PD_OUT_MASK_MASK 0x03 1223*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL1_PD_OUT_MASK_SHIFT 0 1224*3fc36ee0SWojciech Macek 1225*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_DLPF_VAL_7_0_MASK 0xFF 1226*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_DLPF_VAL_7_0_SHIFT 0 1227*3fc36ee0SWojciech Macek 1228*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_DLPF_VAL_8_MASK 0x01 1229*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_DLPF_VAL_8_SHIFT 0 1230*3fc36ee0SWojciech Macek 1231*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL2_DLPF_DITHER_VAL_7_0_MASK 0xFF 1232*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL2_DLPF_DITHER_VAL_7_0_SHIFT 0 1233*3fc36ee0SWojciech Macek 1234*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL3_DLPF_DITHER_VAL_10_8_MASK 0x07 1235*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL3_DLPF_DITHER_VAL_10_8_SHIFT 0 1236*3fc36ee0SWojciech Macek 1237*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL0_DLPF_VAL_7_0_MASK 0xFF 1238*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL0_DLPF_VAL_7_0_SHIFT 0 1239*3fc36ee0SWojciech Macek 1240*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL1_DLPF_VAL_8_MASK 0x01 1241*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL1_DLPF_VAL_8_SHIFT 0 1242*3fc36ee0SWojciech Macek 1243*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL2_EN_MASK 0x01 1244*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL2_EN_SHIFT 0 1245*3fc36ee0SWojciech Macek 1246*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL0_NUM_DITHER_BITS_MASK 0x0F 1247*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL0_NUM_DITHER_BITS_SHIFT 0 1248*3fc36ee0SWojciech Macek 1249*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL1_HIGH_THRESHOLD_7_0_MASK 0xFF 1250*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL1_HIGH_THRESHOLD_7_0_SHIFT 0 1251*3fc36ee0SWojciech Macek 1252*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL2_HIGH_THRESHOLD_8_MASK 0x01 1253*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL2_HIGH_THRESHOLD_8_SHIFT 0 1254*3fc36ee0SWojciech Macek 1255*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL3_HIGH_COUNT_MASK 0x0F 1256*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL3_HIGH_COUNT_SHIFT 0 1257*3fc36ee0SWojciech Macek 1258*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL4_LOW_THRESHOLD_7_0_MASK 0xFF 1259*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL4_LOW_THRESHOLD_7_0_SHIFT 0 1260*3fc36ee0SWojciech Macek 1261*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL5_LOW_THRESHOLD_8_MASK 0x01 1262*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL5_LOW_THRESHOLD_8_SHIFT 0 1263*3fc36ee0SWojciech Macek 1264*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL6_LOW_COUNT_MASK 0x0F 1265*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL6_LOW_COUNT_SHIFT 0 1266*3fc36ee0SWojciech Macek 1267*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCK_EN_MASK 0x01 1268*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCK_EN_SHIFT 0 1269*3fc36ee0SWojciech Macek 1270*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCKL_EN_MASK 0x02 1271*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCKL_EN_SHIFT 1 1272*3fc36ee0SWojciech Macek 1273*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_HIGH_EN_MASK 0x04 1274*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_HIGH_EN_SHIFT 2 1275*3fc36ee0SWojciech Macek 1276*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOW_EN_MASK 0x08 1277*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOW_EN_SHIFT 3 1278*3fc36ee0SWojciech Macek 1279*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL8_OUTPUT_SAMPLE_PERIOD_MASK 0x3F 1280*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL8_OUTPUT_SAMPLE_PERIOD_SHIFT 0 1281*3fc36ee0SWojciech Macek 1282*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS0_GREY_VAL_7_0_MASK 0xFF 1283*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS0_GREY_VAL_7_0_SHIFT 0 1284*3fc36ee0SWojciech Macek 1285*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS1_GREY_VAL_8_MASK 0x01 1286*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS1_GREY_VAL_8_SHIFT 0 1287*3fc36ee0SWojciech Macek 1288*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS2_BINARY_VAL_7_0_MASK 0xFF 1289*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS2_BINARY_VAL_7_0_SHIFT 0 1290*3fc36ee0SWojciech Macek 1291*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_MASK 0x01 1292*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_SHIFT 0 1293*3fc36ee0SWojciech Macek 1294*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_MASK 0x01 1295*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_SHIFT 0 1296*3fc36ee0SWojciech Macek 1297*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_MASK 0x02 1298*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_SHIFT 1 1299*3fc36ee0SWojciech Macek 1300*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_MASK 0x04 1301*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_SHIFT 2 1302*3fc36ee0SWojciech Macek 1303*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_MASK 0x01 1304*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_SHIFT 0 1305*3fc36ee0SWojciech Macek 1306*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS0_ACCUMULATOR_7_0_MASK 0xFF 1307*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS0_ACCUMULATOR_7_0_SHIFT 0 1308*3fc36ee0SWojciech Macek 1309*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS1_ACCUMULATOR_15_8_MASK 0xFF 1310*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS1_ACCUMULATOR_15_8_SHIFT 0 1311*3fc36ee0SWojciech Macek 1312*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_MASK 0x0F 1313*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_SHIFT 0 1314*3fc36ee0SWojciech Macek 1315*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_DITHER_BITS_MASK 0x0F 1316*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_DITHER_BITS_SHIFT 0 1317*3fc36ee0SWojciech Macek 1318*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_SAMPLE_PERIOD_MASK 0xF0 1319*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_SAMPLE_PERIOD_SHIFT 4 1320*3fc36ee0SWojciech Macek 1321*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL1_NUM_SAMPLES_MASK 0xFF 1322*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL1_NUM_SAMPLES_SHIFT 0 1323*3fc36ee0SWojciech Macek 1324*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL2_SLOPE_THRESHOLD_MASK 0xFF 1325*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL2_SLOPE_THRESHOLD_SHIFT 0 1326*3fc36ee0SWojciech Macek 1327*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL3_RANGE_THRESHOLD_MASK 0xFF 1328*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL3_RANGE_THRESHOLD_SHIFT 0 1329*3fc36ee0SWojciech Macek 1330*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_DITHER_BITS_MASK 0x0F 1331*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_DITHER_BITS_SHIFT 0 1332*3fc36ee0SWojciech Macek 1333*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_SAMPLE_PERIOD_MASK 0xF0 1334*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_SAMPLE_PERIOD_SHIFT 4 1335*3fc36ee0SWojciech Macek 1336*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL1_NUM_SAMPLES_MASK 0xFF 1337*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL1_NUM_SAMPLES_SHIFT 0 1338*3fc36ee0SWojciech Macek 1339*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL2_SLOPE_THRESHOLD_MASK 0xFF 1340*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL2_SLOPE_THRESHOLD_SHIFT 0 1341*3fc36ee0SWojciech Macek 1342*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL3_RANGE_THRESHOLD_MASK 0xFF 1343*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL3_RANGE_THRESHOLD_SHIFT 0 1344*3fc36ee0SWojciech Macek 1345*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL0_EN_MASK 0x01 1346*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL0_EN_SHIFT 0 1347*3fc36ee0SWojciech Macek 1348*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_SAMPLE_DROP_BITS_MASK 0x07 1349*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_SAMPLE_DROP_BITS_SHIFT 0 1350*3fc36ee0SWojciech Macek 1351*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_NUM_PEAKS_MASK 0xF0 1352*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_NUM_PEAKS_SHIFT 4 1353*3fc36ee0SWojciech Macek 1354*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL2_PEAK2PEAK_PERIOD_MIN_MASK 0xFF 1355*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL2_PEAK2PEAK_PERIOD_MIN_SHIFT 0 1356*3fc36ee0SWojciech Macek 1357*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL3_PEAK2PEAK_PERIOD_MAX_MASK 0xFF 1358*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL3_PEAK2PEAK_PERIOD_MAX_SHIFT 0 1359*3fc36ee0SWojciech Macek 1360*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_DONE_MASK 0x01 1361*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_DONE_SHIFT 0 1362*3fc36ee0SWojciech Macek 1363*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_NOISY_MASK 0x02 1364*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_NOISY_SHIFT 1 1365*3fc36ee0SWojciech Macek 1366*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_SLOW_MASK 0x04 1367*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_SLOW_SHIFT 2 1368*3fc36ee0SWojciech Macek 1369*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS0_VAL_7_0_MASK 0xFF 1370*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS0_VAL_7_0_SHIFT 0 1371*3fc36ee0SWojciech Macek 1372*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS1_VAL_15_8_MASK 0xFF 1373*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS1_VAL_15_8_SHIFT 0 1374*3fc36ee0SWojciech Macek 1375*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS2_VAL_19_16_MASK 0x0F 1376*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS2_VAL_19_16_SHIFT 0 1377*3fc36ee0SWojciech Macek 1378*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS0_VAL_7_0_MASK 0xFF 1379*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS0_VAL_7_0_SHIFT 0 1380*3fc36ee0SWojciech Macek 1381*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS1_VAL_15_8_MASK 0xFF 1382*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS1_VAL_15_8_SHIFT 0 1383*3fc36ee0SWojciech Macek 1384*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS2_VAL_19_16_MASK 0x0F 1385*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS2_VAL_19_16_SHIFT 0 1386*3fc36ee0SWojciech Macek 1387*3fc36ee0SWojciech Macek /********************************* Lane CDR_REFCLK ***************************/ 1388*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_BASE 0x180 1389*3fc36ee0SWojciech Macek 1390*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x00) 1391*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x01) 1392*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x06) 1393*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x0A) 1394*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x0B) 1395*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x0C) 1396*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x10) 1397*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x11) 1398*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x18) 1399*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x19) 1400*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x1A) 1401*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x1B) 1402*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x20) 1403*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x21) 1404*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL2_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x22) 1405*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCOCAL_STATUS0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x24) 1406*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_RXCDR_HSCAN_EYE_CFG_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x30) 1407*3fc36ee0SWojciech Macek /******************************************************************************* 1408*3fc36ee0SWojciech Macek * masks and shifts 1409*3fc36ee0SWojciech Macek ******************************************************************************/ 1410*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_MASK 0x01 1411*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_SHIFT 0 1412*3fc36ee0SWojciech Macek 1413*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_EYE_MASK 0x02 1414*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_EYE_SHIFT 1 1415*3fc36ee0SWojciech Macek 1416*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_RXCDR_TOGGLE_EN_MASK 0x04 1417*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_RXCDR_TOGGLE_EN_SHIFT 2 1418*3fc36ee0SWojciech Macek 1419*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL1_RXCDR_PHD_EN_MASK 0xFF 1420*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL1_RXCDR_PHD_EN_SHIFT 0 1421*3fc36ee0SWojciech Macek 1422*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_PHD_N_MASK 0x01 1423*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_PHD_N_SHIFT 0 1424*3fc36ee0SWojciech Macek 1425*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_CLKDIV_N_MASK 0x02 1426*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_CLKDIV_N_SHIFT 1 1427*3fc36ee0SWojciech Macek 1428*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL0_RXCDR_VCO_KICK_MASK 0x01 1429*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL0_RXCDR_VCO_KICK_SHIFT 0 1430*3fc36ee0SWojciech Macek 1431*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REGDAC_BANDWIDTH_MASK 0x01 1432*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REGDAC_BANDWIDTH_SHIFT 0 1433*3fc36ee0SWojciech Macek 1434*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_SHORT_VOSC_PRP_MASK 0x02 1435*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_SHORT_VOSC_PRP_SHIFT 1 1436*3fc36ee0SWojciech Macek 1437*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REFDAC_GAIN_MASK 0x0C 1438*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REFDAC_GAIN_SHIFT 2 1439*3fc36ee0SWojciech Macek 1440*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_MASK 0x07 1441*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_SHIFT 0 1442*3fc36ee0SWojciech Macek 1443*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_BBSTEP_MASK 0x1F 1444*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_BBSTEP_SHIFT 0 1445*3fc36ee0SWojciech Macek 1446*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_CLKDIV_MASK 0x60 1447*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_CLKDIV_SHIFT 5 1448*3fc36ee0SWojciech Macek 1449*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_CLKDIV_SWING_MASK 0x03 1450*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_CLKDIV_SWING_SHIFT 0 1451*3fc36ee0SWojciech Macek 1452*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_SPARE_MASK 0x3C 1453*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_SPARE_SHIFT 2 1454*3fc36ee0SWojciech Macek 1455*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_MASK 0x7F 1456*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_SHIFT 0 1457*3fc36ee0SWojciech Macek 1458*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_SRC_SEL_MASK 0x80 1459*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_SRC_SEL_SHIFT 7 1460*3fc36ee0SWojciech Macek 1461*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_MASK 0x7F 1462*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_SHIFT 0 1463*3fc36ee0SWojciech Macek 1464*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_SRC_SEL_MASK 0x80 1465*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_SRC_SEL_SHIFT 7 1466*3fc36ee0SWojciech Macek 1467*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_MASK 0x7F 1468*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_SHIFT 0 1469*3fc36ee0SWojciech Macek 1470*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_CAP_MASK 0x07 1471*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_CAP_SHIFT 0 1472*3fc36ee0SWojciech Macek 1473*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_SWING_MASK 0x18 1474*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_SWING_SHIFT 3 1475*3fc36ee0SWojciech Macek 1476*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_CAL_EN_MASK 0x01 1477*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_CAL_EN_SHIFT 0 1478*3fc36ee0SWojciech Macek 1479*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_VCOCAL_DIV4_MASK 0x02 1480*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_VCOCAL_DIV4_SHIFT 1 1481*3fc36ee0SWojciech Macek 1482*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL1_RXCDR_VCOCAL_LOAD_VAL_11_8_MASK 0x0F 1483*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL1_RXCDR_VCOCAL_LOAD_VAL_11_8_SHIFT 0 1484*3fc36ee0SWojciech Macek 1485*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL2_RXCDR_VCOCAL_LOAD_VAL_7_0_MASK 0xFF 1486*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL2_RXCDR_VCOCAL_LOAD_VAL_7_0_SHIFT 0 1487*3fc36ee0SWojciech Macek 1488*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCOCAL_STATUS0_RXCDR_VCOCAL_UP_MASK 0x01 1489*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCOCAL_STATUS0_RXCDR_VCOCAL_UP_SHIFT 0 1490*3fc36ee0SWojciech Macek 1491*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_RXCDR_HSCAN_EYE_CFG_ZERO_PHASE_MASK 0x7F 1492*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_CDR_REFCLK_RXCDR_HSCAN_EYE_CFG_ZERO_PHASE_SHIFT 0 1493*3fc36ee0SWojciech Macek 1494*3fc36ee0SWojciech Macek /********************************* Lane BIST *********************************/ 1495*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_ADDR 0x00 1496*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_ADDR 0x01 1497*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_ADDR 0x02 1498*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_ADDR 0x03 1499*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_ADDR 0x04 1500*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_ADDR 0x05 1501*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_ADDR 0x06 1502*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_ADDR 0x10 1503*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_ADDR 0x12 1504*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_ADDR 0x13 1505*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_ADDR 0x14 1506*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_ADDR 0x16 1507*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_ADDR 0x19 1508*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_ADDR 0x1B 1509*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_ADDR 0x1C 1510*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_ADDR 0x22 1511*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_ADDR 0x24 1512*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_ADDR 0x25 1513*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ADDR 0x26 1514*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PHY_IF_STATUS_ADDR 0x27 1515*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL0_ADDR 0x30 1516*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL1_ADDR 0x31 1517*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_ADDR 0x38 1518*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_ADDR 0x39 1519*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_ADDR 0x3A 1520*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_ADDR 0x3B 1521*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_ADDR 0x3C 1522*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_ADDR 0x3D 1523*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_ERR_CTRL1_ADDR 0x40 1524*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_ERR_CTRL2_ADDR 0x41 1525*3fc36ee0SWojciech Macek /******************************************************************************* 1526*3fc36ee0SWojciech Macek * masks and shifts 1527*3fc36ee0SWojciech Macek ******************************************************************************/ 1528*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_MASK 0x01 1529*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_SHIFT 0 1530*3fc36ee0SWojciech Macek 1531*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_MASK 0x02 1532*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_SHIFT 1 1533*3fc36ee0SWojciech Macek 1534*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_MASK 0x04 1535*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_SHIFT 2 1536*3fc36ee0SWojciech Macek 1537*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_MASK 0x08 1538*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_SHIFT 3 1539*3fc36ee0SWojciech Macek 1540*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_MASK 0x01 1541*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_SHIFT 0 1542*3fc36ee0SWojciech Macek 1543*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_MASK 0x02 1544*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_SHIFT 1 1545*3fc36ee0SWojciech Macek 1546*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_MASK 0x01 1547*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_SHIFT 0 1548*3fc36ee0SWojciech Macek 1549*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_MASK 0x02 1550*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_SHIFT 1 1551*3fc36ee0SWojciech Macek 1552*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_MASK 0x01 1553*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_SHIFT 0 1554*3fc36ee0SWojciech Macek 1555*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_MASK 0x01 1556*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_SHIFT 0 1557*3fc36ee0SWojciech Macek 1558*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_MASK 0x04 1559*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_SHIFT 2 1560*3fc36ee0SWojciech Macek 1561*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_MASK 0x0F 1562*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_SHIFT 0 1563*3fc36ee0SWojciech Macek 1564*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_MASK 0x0F 1565*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_SHIFT 0 1566*3fc36ee0SWojciech Macek 1567*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_MASK 0x30 1568*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_SHIFT 4 1569*3fc36ee0SWojciech Macek 1570*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_MASK 0x40 1571*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_SHIFT 6 1572*3fc36ee0SWojciech Macek 1573*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_MASK 0x01 1574*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_SHIFT 0 1575*3fc36ee0SWojciech Macek 1576*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_MASK 0x06 1577*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_SHIFT 1 1578*3fc36ee0SWojciech Macek 1579*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_MASK 0x0F 1580*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_SHIFT 0 1581*3fc36ee0SWojciech Macek 1582*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_MASK 0x03 1583*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_SHIFT 0 1584*3fc36ee0SWojciech Macek 1585*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_MASK 0x04 1586*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_SHIFT 2 1587*3fc36ee0SWojciech Macek 1588*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_MASK 0xF0 1589*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_SHIFT 4 1590*3fc36ee0SWojciech Macek 1591*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_MASK 0x07 1592*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_SHIFT 0 1593*3fc36ee0SWojciech Macek 1594*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_MASK 0xF0 1595*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_SHIFT 4 1596*3fc36ee0SWojciech Macek 1597*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_MASK 0x07 1598*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_SHIFT 0 1599*3fc36ee0SWojciech Macek 1600*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_MASK 0x08 1601*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_SHIFT 3 1602*3fc36ee0SWojciech Macek 1603*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_MASK 0x10 1604*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_SHIFT 4 1605*3fc36ee0SWojciech Macek 1606*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_MASK 0x1F 1607*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_SHIFT 0 1608*3fc36ee0SWojciech Macek 1609*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_MASK 0x03 1610*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_SHIFT 0 1611*3fc36ee0SWojciech Macek 1612*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_MASK 0x04 1613*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_SHIFT 2 1614*3fc36ee0SWojciech Macek 1615*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_MASK 0x10 1616*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_SHIFT 4 1617*3fc36ee0SWojciech Macek 1618*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_MASK 0x01 1619*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_SHIFT 0 1620*3fc36ee0SWojciech Macek 1621*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_MASK 0x07 1622*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_SHIFT 0 1623*3fc36ee0SWojciech Macek 1624*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_MASK 0x08 1625*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_SHIFT 3 1626*3fc36ee0SWojciech Macek 1627*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_MASK 0x07 1628*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_SHIFT 0 1629*3fc36ee0SWojciech Macek 1630*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_MASK 0x08 1631*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_SHIFT 3 1632*3fc36ee0SWojciech Macek 1633*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_MASK 0x70 1634*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_SHIFT 4 1635*3fc36ee0SWojciech Macek 1636*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_MASK 0x01 1637*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_SHIFT 0 1638*3fc36ee0SWojciech Macek 1639*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_MASK 0x07 1640*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_SHIFT 0 1641*3fc36ee0SWojciech Macek 1642*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_MASK 0x38 1643*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_SHIFT 3 1644*3fc36ee0SWojciech Macek 1645*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_MASK 0x07 1646*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_SHIFT 0 1647*3fc36ee0SWojciech Macek 1648*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_MASK 0x38 1649*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_SHIFT 3 1650*3fc36ee0SWojciech Macek 1651*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_MASK 0x01 1652*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_SHIFT 0 1653*3fc36ee0SWojciech Macek 1654*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_MASK 0x01 1655*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_SHIFT 0 1656*3fc36ee0SWojciech Macek 1657*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_MASK 0x02 1658*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_SHIFT 1 1659*3fc36ee0SWojciech Macek 1660*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_MASK 0x01 1661*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_SHIFT 0 1662*3fc36ee0SWojciech Macek 1663*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_MASK 0x01 1664*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_SHIFT 0 1665*3fc36ee0SWojciech Macek 1666*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_MASK 0x02 1667*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_SHIFT 1 1668*3fc36ee0SWojciech Macek 1669*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_MASK 0x04 1670*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_SHIFT 2 1671*3fc36ee0SWojciech Macek 1672*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_MASK 0x08 1673*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_SHIFT 3 1674*3fc36ee0SWojciech Macek 1675*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_MASK 0x10 1676*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_SHIFT 4 1677*3fc36ee0SWojciech Macek 1678*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_MASK 0x20 1679*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_SHIFT 5 1680*3fc36ee0SWojciech Macek 1681*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_MASK 0x40 1682*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_SHIFT 6 1683*3fc36ee0SWojciech Macek 1684*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_MASK 0x01 1685*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_SHIFT 0 1686*3fc36ee0SWojciech Macek 1687*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_MASK 0x06 1688*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_SHIFT 1 1689*3fc36ee0SWojciech Macek 1690*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_MASK 0x08 1691*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_SHIFT 3 1692*3fc36ee0SWojciech Macek 1693*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_MASK 0x01 1694*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_SHIFT 0 1695*3fc36ee0SWojciech Macek 1696*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_MASK 0x02 1697*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_SHIFT 1 1698*3fc36ee0SWojciech Macek 1699*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK 0xFF 1700*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT 0 1701*3fc36ee0SWojciech Macek 1702*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK 0xFF 1703*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT 0 1704*3fc36ee0SWojciech Macek 1705*3fc36ee0SWojciech Macek /********************************* LEQ_REFCLK *********************************/ 1706*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_BASE 0x200 1707*3fc36ee0SWojciech Macek 1708*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x00) 1709*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x02) 1710*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x03) 1711*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x05) 1712*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_EQ_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x07) 1713*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_MISC_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x09) 1714*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0A) 1715*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0B) 1716*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0C) 1717*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0E) 1718*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0F) 1719*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x10) 1720*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x11) 1721*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x20) 1722*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x21) 1723*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x22) 1724*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x23) 1725*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x24) 1726*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x25) 1727*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x26) 1728*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x27) 1729*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x28) 1730*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x29) 1731*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2A) 1732*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2B) 1733*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2C) 1734*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_OUTINTF_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2E) 1735*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x30) 1736*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x31) 1737*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x32) 1738*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x33) 1739*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x34) 1740*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x35) 1741*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x36) 1742*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL7_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x37) 1743*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL8_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x38) 1744*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL9_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x39) 1745*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL10_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x3A) 1746*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x3D) 1747*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x3E) 1748*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x40) 1749*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x41) 1750*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x42) 1751*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x43) 1752*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x44) 1753*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x45) 1754*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x46) 1755*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x50) 1756*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x51) 1757*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x52) 1758*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x53) 1759*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x54) 1760*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x55) 1761*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x56) 1762*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x57) 1763*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x58) 1764*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x59) 1765*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5A) 1766*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5B) 1767*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5C) 1768*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5D) 1769*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5E) 1770*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5F) 1771*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x60) 1772*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x61) 1773*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x62) 1774*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x63) 1775*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x64) 1776*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x65) 1777*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x66) 1778*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x67) 1779*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x68) 1780*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x70) 1781*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x71) 1782*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x72) 1783*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x73) 1784*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x74) 1785*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x75) 1786*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x76) 1787*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x80) 1788*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x81) 1789*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x82) 1790*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x83) 1791*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x84) 1792*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x85) 1793*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x86) 1794*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL7_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x87) 1795*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL8_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x88) 1796*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x90) 1797*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x91) 1798*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x92) 1799*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x93) 1800*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x94) 1801*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x95) 1802*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x96) 1803*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x98) 1804*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x99) 1805*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9A) 1806*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9B) 1807*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9C) 1808*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9D) 1809*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA0) 1810*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA1) 1811*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA2) 1812*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA3) 1813*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA6) 1814*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA7) 1815*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA8) 1816*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA9) 1817*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAB) 1818*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAC) 1819*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAE) 1820*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYEINTF_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAF) 1821*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xB8) 1822*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xB9) 1823*3fc36ee0SWojciech Macek 1824*3fc36ee0SWojciech Macek /******************************************************************************* 1825*3fc36ee0SWojciech Macek * masks and shifts 1826*3fc36ee0SWojciech Macek ******************************************************************************/ 1827*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_MASK 0x3F 1828*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_SHIFT 0 1829*3fc36ee0SWojciech Macek 1830*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_BIASGEN_MASK 0x40 1831*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_BIASGEN_SHIFT 6 1832*3fc36ee0SWojciech Macek 1833*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL0_RXLEQ_BIAS_MASK 0xFF 1834*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL0_RXLEQ_BIAS_SHIFT 0 1835*3fc36ee0SWojciech Macek 1836*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_VGSW_SEL_MASK 0x07 1837*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_VGSW_SEL_SHIFT 0 1838*3fc36ee0SWojciech Macek 1839*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_MASK 0x18 1840*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_SHIFT 3 1841*3fc36ee0SWojciech Macek 1842*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_MUTE_MASK 0x01 1843*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_MUTE_SHIFT 0 1844*3fc36ee0SWojciech Macek 1845*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_MASK 0x06 1846*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_SHIFT 1 1847*3fc36ee0SWojciech Macek 1848*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_PRECH_MASK 0x08 1849*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_PRECH_SHIFT 3 1850*3fc36ee0SWojciech Macek 1851*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_EQ_CTRL0_RXLEQ_EQ_SQL_DIR_MASK 0x01 1852*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_EQ_CTRL0_RXLEQ_EQ_SQL_DIR_SHIFT 0 1853*3fc36ee0SWojciech Macek 1854*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_MISC_CTRL0_RXLEQ_SPARE_MASK 0x0F 1855*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AFE_MISC_CTRL0_RXLEQ_SPARE_SHIFT 0 1856*3fc36ee0SWojciech Macek 1857*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START0_MASK 0x07 1858*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START0_SHIFT 0 1859*3fc36ee0SWojciech Macek 1860*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START1_MASK 0x38 1861*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START1_SHIFT 3 1862*3fc36ee0SWojciech Macek 1863*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START2_MASK 0x07 1864*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START2_SHIFT 0 1865*3fc36ee0SWojciech Macek 1866*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START3_MASK 0x38 1867*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START3_SHIFT 3 1868*3fc36ee0SWojciech Macek 1869*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE0_MASK 0x03 1870*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE0_SHIFT 0 1871*3fc36ee0SWojciech Macek 1872*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE1_MASK 0x0C 1873*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE1_SHIFT 2 1874*3fc36ee0SWojciech Macek 1875*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE2_MASK 0x30 1876*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE2_SHIFT 4 1877*3fc36ee0SWojciech Macek 1878*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE3_MASK 0xC0 1879*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE3_SHIFT 6 1880*3fc36ee0SWojciech Macek 1881*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START0_MASK 0x07 1882*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START0_SHIFT 0 1883*3fc36ee0SWojciech Macek 1884*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START1_MASK 0x38 1885*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START1_SHIFT 3 1886*3fc36ee0SWojciech Macek 1887*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START2_MASK 0x07 1888*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START2_SHIFT 0 1889*3fc36ee0SWojciech Macek 1890*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START3_MASK 0x38 1891*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START3_SHIFT 3 1892*3fc36ee0SWojciech Macek 1893*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START0_MASK 0x07 1894*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START0_SHIFT 0 1895*3fc36ee0SWojciech Macek 1896*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START1_MASK 0x38 1897*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START1_SHIFT 3 1898*3fc36ee0SWojciech Macek 1899*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START2_MASK 0x07 1900*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START2_SHIFT 0 1901*3fc36ee0SWojciech Macek 1902*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START3_MASK 0x38 1903*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START3_SHIFT 3 1904*3fc36ee0SWojciech Macek 1905*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_MASK 0x01 1906*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_SHIFT 0 1907*3fc36ee0SWojciech Macek 1908*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_STATE_RESET_MASK 0x04 1909*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_STATE_RESET_SHIFT 2 1910*3fc36ee0SWojciech Macek 1911*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_OPCODE_MASK 0x0F 1912*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_OPCODE_SHIFT 0 1913*3fc36ee0SWojciech Macek 1914*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_TARGET_MASK 0xF0 1915*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_TARGET_SHIFT 4 1916*3fc36ee0SWojciech Macek 1917*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_LEQ_FSM_CMD_SCRATCHPAD_MASK 0xFF 1918*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_LEQ_FSM_CMD_SCRATCHPAD_SHIFT 0 1919*3fc36ee0SWojciech Macek 1920*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_LEQ_FSM_CMD_MISC_OPTION_MASK 0xFF 1921*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_LEQ_FSM_CMD_MISC_OPTION_SHIFT 0 1922*3fc36ee0SWojciech Macek 1923*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_MASK 0x07 1924*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_SHIFT 0 1925*3fc36ee0SWojciech Macek 1926*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_MASK 0x38 1927*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_SHIFT 3 1928*3fc36ee0SWojciech Macek 1929*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MAX_CLAMP_MASK 0x40 1930*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MAX_CLAMP_SHIFT 6 1931*3fc36ee0SWojciech Macek 1932*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MIN_CLAMP_MASK 0x80 1933*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MIN_CLAMP_SHIFT 7 1934*3fc36ee0SWojciech Macek 1935*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_STATE_MASK 0x0F 1936*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_STATE_SHIFT 0 1937*3fc36ee0SWojciech Macek 1938*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_LAST_RESULT_MASK 0xF0 1939*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_LAST_RESULT_SHIFT 4 1940*3fc36ee0SWojciech Macek 1941*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS2_LEQ_FSM_LAST_STEP_MASK 0xFF 1942*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS2_LEQ_FSM_LAST_STEP_SHIFT 0 1943*3fc36ee0SWojciech Macek 1944*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_LEQ_FSM_LAST_VALUE_MASK 0xFF 1945*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_LEQ_FSM_LAST_VALUE_SHIFT 0 1946*3fc36ee0SWojciech Macek 1947*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_OPCODE_MASK 0x0F 1948*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_OPCODE_SHIFT 0 1949*3fc36ee0SWojciech Macek 1950*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_TARGET_MASK 0xF0 1951*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_TARGET_SHIFT 4 1952*3fc36ee0SWojciech Macek 1953*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL1_LEQ_FSM_TIMEOUT_LIMIT_7_0_MASK 0xFF 1954*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL1_LEQ_FSM_TIMEOUT_LIMIT_7_0_SHIFT 0 1955*3fc36ee0SWojciech Macek 1956*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL2_LEQ_FSM_TIMEOUT_LIMIT_15_8_MASK 0xFF 1957*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL2_LEQ_FSM_TIMEOUT_LIMIT_15_8_SHIFT 0 1958*3fc36ee0SWojciech Macek 1959*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_MASK 0x02 1960*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_SHIFT 1 1961*3fc36ee0SWojciech Macek 1962*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS6_LEQ_FSM_2LST_VALUE_MASK 0xFF 1963*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS6_LEQ_FSM_2LST_VALUE_SHIFT 0 1964*3fc36ee0SWojciech Macek 1965*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_OUTINTF_CTRL0_LEQ_OUTINTF_RDY_WAIT_MASK 0xFF 1966*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_OUTINTF_CTRL0_LEQ_OUTINTF_RDY_WAIT_SHIFT 0 1967*3fc36ee0SWojciech Macek 1968*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_MASK 0x0F 1969*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_SHIFT 0 1970*3fc36ee0SWojciech Macek 1971*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL1_AGCLOS_VALUE_MAX_MASK 0x0F 1972*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL1_AGCLOS_VALUE_MAX_SHIFT 0 1973*3fc36ee0SWojciech Macek 1974*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL2_AGCLOS_VALUE_MIN_MASK 0x0F 1975*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL2_AGCLOS_VALUE_MIN_SHIFT 0 1976*3fc36ee0SWojciech Macek 1977*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_WRWAIT_TIME_MASK 0x0F 1978*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_WRWAIT_TIME_SHIFT 0 1979*3fc36ee0SWojciech Macek 1980*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_INIT_TIMEOUT_DISABLE_MASK 0x40 1981*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_INIT_TIMEOUT_DISABLE_SHIFT 6 1982*3fc36ee0SWojciech Macek 1983*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_MEASURE_TIMEOUT_DISABLE_MASK 0x80 1984*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_MEASURE_TIMEOUT_DISABLE_SHIFT 7 1985*3fc36ee0SWojciech Macek 1986*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_BY1_MASK 0x01 1987*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_BY1_SHIFT 0 1988*3fc36ee0SWojciech Macek 1989*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_ERROR_SIGN_MASK 0x02 1990*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_ERROR_SIGN_SHIFT 1 1991*3fc36ee0SWojciech Macek 1992*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_SIZE_MASK 0x1C 1993*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_SIZE_SHIFT 2 1994*3fc36ee0SWojciech Macek 1995*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_BOUNCE_LIMIT_MASK 0x0F 1996*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_BOUNCE_LIMIT_SHIFT 0 1997*3fc36ee0SWojciech Macek 1998*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_AVG_MASK 0x30 1999*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_AVG_SHIFT 4 2000*3fc36ee0SWojciech Macek 2001*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_FLOOR_MASK 0x40 2002*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_FLOOR_SHIFT 6 2003*3fc36ee0SWojciech Macek 2004*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL6_AGCLOS_LASTWR_ADJUST_MASK 0x0F 2005*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL6_AGCLOS_LASTWR_ADJUST_SHIFT 0 2006*3fc36ee0SWojciech Macek 2007*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL7_AGCLOS_PEAK_ACQ_TIME_7_0_MASK 0xFF 2008*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL7_AGCLOS_PEAK_ACQ_TIME_7_0_SHIFT 0 2009*3fc36ee0SWojciech Macek 2010*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL8_AGCLOS_PEAK_ACQ_TIME_15_8_MASK 0xFF 2011*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL8_AGCLOS_PEAK_ACQ_TIME_15_8_SHIFT 0 2012*3fc36ee0SWojciech Macek 2013*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL9_AGCLOS_PEAK_ACQ_TIME_23_16_MASK 0xFF 2014*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL9_AGCLOS_PEAK_ACQ_TIME_23_16_SHIFT 0 2015*3fc36ee0SWojciech Macek 2016*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL10_AGCLOS_PEAK_ACQ_TIME_25_24_MASK 0x03 2017*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL10_AGCLOS_PEAK_ACQ_TIME_25_24_SHIFT 0 2018*3fc36ee0SWojciech Macek 2019*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_WRWAIT_TIME_MASK 0x0F 2020*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_WRWAIT_TIME_SHIFT 0 2021*3fc36ee0SWojciech Macek 2022*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_STEP_BY1_MASK 0x10 2023*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_STEP_BY1_SHIFT 4 2024*3fc36ee0SWojciech Macek 2025*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL1_PLE_LFG_START_MASK 0x07 2026*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL1_PLE_LFG_START_SHIFT 0 2027*3fc36ee0SWojciech Macek 2028*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_MASK 0x1F 2029*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_SHIFT 0 2030*3fc36ee0SWojciech Macek 2031*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL1_EQ_HFG_SQL_VALUE_MAX_MASK 0x1F 2032*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL1_EQ_HFG_SQL_VALUE_MAX_SHIFT 0 2033*3fc36ee0SWojciech Macek 2034*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL2_EQ_HFG_SQL_VALUE_MIN_MASK 0x1F 2035*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL2_EQ_HFG_SQL_VALUE_MIN_SHIFT 0 2036*3fc36ee0SWojciech Macek 2037*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_WRWAIT_TIME_MASK 0x0F 2038*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_WRWAIT_TIME_SHIFT 0 2039*3fc36ee0SWojciech Macek 2040*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_MEASURE_TIMEOUT_DISABLE_MASK 0x80 2041*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_MEASURE_TIMEOUT_DISABLE_SHIFT 7 2042*3fc36ee0SWojciech Macek 2043*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_BY1_MASK 0x01 2044*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_BY1_SHIFT 0 2045*3fc36ee0SWojciech Macek 2046*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_ERROR_SIGN_MASK 0x02 2047*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_ERROR_SIGN_SHIFT 1 2048*3fc36ee0SWojciech Macek 2049*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_SIZE_MASK 0x1C 2050*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_SIZE_SHIFT 2 2051*3fc36ee0SWojciech Macek 2052*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_BOUNCE_LIMIT_MASK 0x0F 2053*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_BOUNCE_LIMIT_SHIFT 0 2054*3fc36ee0SWojciech Macek 2055*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_AVG_MASK 0x30 2056*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_AVG_SHIFT 4 2057*3fc36ee0SWojciech Macek 2058*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_FLOOR_MASK 0x40 2059*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_FLOOR_SHIFT 6 2060*3fc36ee0SWojciech Macek 2061*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL6_EQ_HFG_SQL_LASTWR_ADJUST_MASK 0x1F 2062*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL6_EQ_HFG_SQL_LASTWR_ADJUST_SHIFT 0 2063*3fc36ee0SWojciech Macek 2064*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE0_MASK 0x01 2065*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE0_SHIFT 0 2066*3fc36ee0SWojciech Macek 2067*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE1_MASK 0x02 2068*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE1_SHIFT 1 2069*3fc36ee0SWojciech Macek 2070*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE2_MASK 0x04 2071*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE2_SHIFT 2 2072*3fc36ee0SWojciech Macek 2073*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE3_MASK 0x08 2074*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE3_SHIFT 3 2075*3fc36ee0SWojciech Macek 2076*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP0_RATE0_MASK 0x07 2077*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP0_RATE0_SHIFT 0 2078*3fc36ee0SWojciech Macek 2079*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP1_RATE0_MASK 0x70 2080*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP1_RATE0_SHIFT 4 2081*3fc36ee0SWojciech Macek 2082*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP2_RATE0_MASK 0x07 2083*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP2_RATE0_SHIFT 0 2084*3fc36ee0SWojciech Macek 2085*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP3_RATE0_MASK 0x70 2086*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP3_RATE0_SHIFT 4 2087*3fc36ee0SWojciech Macek 2088*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP4_RATE0_MASK 0x07 2089*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP4_RATE0_SHIFT 0 2090*3fc36ee0SWojciech Macek 2091*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP5_RATE0_MASK 0x70 2092*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP5_RATE0_SHIFT 4 2093*3fc36ee0SWojciech Macek 2094*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP6_RATE0_MASK 0x07 2095*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP6_RATE0_SHIFT 0 2096*3fc36ee0SWojciech Macek 2097*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP7_RATE0_MASK 0x70 2098*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP7_RATE0_SHIFT 4 2099*3fc36ee0SWojciech Macek 2100*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP8_RATE0_MASK 0x07 2101*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP8_RATE0_SHIFT 0 2102*3fc36ee0SWojciech Macek 2103*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP9_RATE0_MASK 0x70 2104*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP9_RATE0_SHIFT 4 2105*3fc36ee0SWojciech Macek 2106*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP10_RATE0_MASK 0x07 2107*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP10_RATE0_SHIFT 0 2108*3fc36ee0SWojciech Macek 2109*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP11_RATE0_MASK 0x70 2110*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP11_RATE0_SHIFT 4 2111*3fc36ee0SWojciech Macek 2112*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP0_RATE1_MASK 0x07 2113*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP0_RATE1_SHIFT 0 2114*3fc36ee0SWojciech Macek 2115*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP1_RATE1_MASK 0x70 2116*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP1_RATE1_SHIFT 4 2117*3fc36ee0SWojciech Macek 2118*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP2_RATE1_MASK 0x07 2119*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP2_RATE1_SHIFT 0 2120*3fc36ee0SWojciech Macek 2121*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP3_RATE1_MASK 0x70 2122*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP3_RATE1_SHIFT 4 2123*3fc36ee0SWojciech Macek 2124*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP4_RATE1_MASK 0x07 2125*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP4_RATE1_SHIFT 0 2126*3fc36ee0SWojciech Macek 2127*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP5_RATE1_MASK 0x70 2128*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP5_RATE1_SHIFT 4 2129*3fc36ee0SWojciech Macek 2130*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP6_RATE1_MASK 0x07 2131*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP6_RATE1_SHIFT 0 2132*3fc36ee0SWojciech Macek 2133*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP7_RATE1_MASK 0x70 2134*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP7_RATE1_SHIFT 4 2135*3fc36ee0SWojciech Macek 2136*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP8_RATE1_MASK 0x07 2137*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP8_RATE1_SHIFT 0 2138*3fc36ee0SWojciech Macek 2139*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP9_RATE1_MASK 0x70 2140*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP9_RATE1_SHIFT 4 2141*3fc36ee0SWojciech Macek 2142*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP10_RATE1_MASK 0x07 2143*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP10_RATE1_SHIFT 0 2144*3fc36ee0SWojciech Macek 2145*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP11_RATE1_MASK 0x70 2146*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP11_RATE1_SHIFT 4 2147*3fc36ee0SWojciech Macek 2148*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP0_RATE2_MASK 0x07 2149*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP0_RATE2_SHIFT 0 2150*3fc36ee0SWojciech Macek 2151*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP1_RATE2_MASK 0x70 2152*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP1_RATE2_SHIFT 4 2153*3fc36ee0SWojciech Macek 2154*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP2_RATE2_MASK 0x07 2155*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP2_RATE2_SHIFT 0 2156*3fc36ee0SWojciech Macek 2157*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP3_RATE2_MASK 0x70 2158*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP3_RATE2_SHIFT 4 2159*3fc36ee0SWojciech Macek 2160*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP4_RATE2_MASK 0x07 2161*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP4_RATE2_SHIFT 0 2162*3fc36ee0SWojciech Macek 2163*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP5_RATE2_MASK 0x70 2164*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP5_RATE2_SHIFT 4 2165*3fc36ee0SWojciech Macek 2166*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP6_RATE2_MASK 0x07 2167*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP6_RATE2_SHIFT 0 2168*3fc36ee0SWojciech Macek 2169*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP7_RATE2_MASK 0x70 2170*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP7_RATE2_SHIFT 4 2171*3fc36ee0SWojciech Macek 2172*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP8_RATE2_MASK 0x07 2173*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP8_RATE2_SHIFT 0 2174*3fc36ee0SWojciech Macek 2175*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP9_RATE2_MASK 0x70 2176*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP9_RATE2_SHIFT 4 2177*3fc36ee0SWojciech Macek 2178*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP10_RATE2_MASK 0x07 2179*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP10_RATE2_SHIFT 0 2180*3fc36ee0SWojciech Macek 2181*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP11_RATE2_MASK 0x70 2182*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP11_RATE2_SHIFT 4 2183*3fc36ee0SWojciech Macek 2184*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP0_RATE3_MASK 0x07 2185*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP0_RATE3_SHIFT 0 2186*3fc36ee0SWojciech Macek 2187*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP1_RATE3_MASK 0x70 2188*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP1_RATE3_SHIFT 4 2189*3fc36ee0SWojciech Macek 2190*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP2_RATE3_MASK 0x07 2191*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP2_RATE3_SHIFT 0 2192*3fc36ee0SWojciech Macek 2193*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP3_RATE3_MASK 0x70 2194*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP3_RATE3_SHIFT 4 2195*3fc36ee0SWojciech Macek 2196*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP4_RATE3_MASK 0x07 2197*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP4_RATE3_SHIFT 0 2198*3fc36ee0SWojciech Macek 2199*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP5_RATE3_MASK 0x70 2200*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP5_RATE3_SHIFT 4 2201*3fc36ee0SWojciech Macek 2202*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP6_RATE3_MASK 0x07 2203*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP6_RATE3_SHIFT 0 2204*3fc36ee0SWojciech Macek 2205*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP7_RATE3_MASK 0x70 2206*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP7_RATE3_SHIFT 4 2207*3fc36ee0SWojciech Macek 2208*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP8_RATE3_MASK 0x07 2209*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP8_RATE3_SHIFT 0 2210*3fc36ee0SWojciech Macek 2211*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP9_RATE3_MASK 0x70 2212*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP9_RATE3_SHIFT 4 2213*3fc36ee0SWojciech Macek 2214*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP10_RATE3_MASK 0x07 2215*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP10_RATE3_SHIFT 0 2216*3fc36ee0SWojciech Macek 2217*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP11_RATE3_MASK 0x70 2218*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP11_RATE3_SHIFT 4 2219*3fc36ee0SWojciech Macek 2220*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_MASK 0x03 2221*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_SHIFT 0 2222*3fc36ee0SWojciech Macek 2223*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MAX_MASK 0x03 2224*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MAX_SHIFT 0 2225*3fc36ee0SWojciech Macek 2226*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MIN_MASK 0x0C 2227*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MIN_SHIFT 2 2228*3fc36ee0SWojciech Macek 2229*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_WRWAIT_TIME_MASK 0x0F 2230*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_WRWAIT_TIME_SHIFT 0 2231*3fc36ee0SWojciech Macek 2232*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_MEASURE_TIMEOUT_DISABLE_MASK 0x80 2233*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_MEASURE_TIMEOUT_DISABLE_SHIFT 7 2234*3fc36ee0SWojciech Macek 2235*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_BY1_MASK 0x01 2236*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_BY1_SHIFT 0 2237*3fc36ee0SWojciech Macek 2238*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_ERROR_SIGN_MASK 0x02 2239*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_ERROR_SIGN_SHIFT 1 2240*3fc36ee0SWojciech Macek 2241*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_SIZE_MASK 0x0C 2242*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_SIZE_SHIFT 2 2243*3fc36ee0SWojciech Macek 2244*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_BOUNCE_LIMIT_MASK 0x0F 2245*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_BOUNCE_LIMIT_SHIFT 0 2246*3fc36ee0SWojciech Macek 2247*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_AVG_MASK 0x30 2248*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_AVG_SHIFT 4 2249*3fc36ee0SWojciech Macek 2250*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_FLOOR_MASK 0x40 2251*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_FLOOR_SHIFT 6 2252*3fc36ee0SWojciech Macek 2253*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL5_GN_APG_LASTWR_ADJUST_MASK 0x03 2254*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL5_GN_APG_LASTWR_ADJUST_SHIFT 0 2255*3fc36ee0SWojciech Macek 2256*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_DELTA_MASK 0x03 2257*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_DELTA_SHIFT 0 2258*3fc36ee0SWojciech Macek 2259*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_MAX_MASK 0x0C 2260*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_MAX_SHIFT 2 2261*3fc36ee0SWojciech Macek 2262*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_MASK 0x1F 2263*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_SHIFT 0 2264*3fc36ee0SWojciech Macek 2265*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_MASK 0x1F 2266*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_SHIFT 0 2267*3fc36ee0SWojciech Macek 2268*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_MASK 0x1F 2269*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_SHIFT 0 2270*3fc36ee0SWojciech Macek 2271*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_WRWAIT_TIME_MASK 0x0F 2272*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_WRWAIT_TIME_SHIFT 0 2273*3fc36ee0SWojciech Macek 2274*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_MEASURE_TIMEOUT_DISABLE_MASK 0x80 2275*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_MEASURE_TIMEOUT_DISABLE_SHIFT 7 2276*3fc36ee0SWojciech Macek 2277*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_BY1_MASK 0x01 2278*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_BY1_SHIFT 0 2279*3fc36ee0SWojciech Macek 2280*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_ERROR_SIGN_MASK 0x02 2281*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_ERROR_SIGN_SHIFT 1 2282*3fc36ee0SWojciech Macek 2283*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_SIZE_MASK 0x1C 2284*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_SIZE_SHIFT 2 2285*3fc36ee0SWojciech Macek 2286*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_BOUNCE_LIMIT_MASK 0x0F 2287*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_BOUNCE_LIMIT_SHIFT 0 2288*3fc36ee0SWojciech Macek 2289*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_AVG_MASK 0x30 2290*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_AVG_SHIFT 4 2291*3fc36ee0SWojciech Macek 2292*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_FLOOR_MASK 0x40 2293*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_FLOOR_SHIFT 6 2294*3fc36ee0SWojciech Macek 2295*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL6_EQ_LFG_LASTWR_ADJUST_MASK 0x1F 2296*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL6_EQ_LFG_LASTWR_ADJUST_SHIFT 0 2297*3fc36ee0SWojciech Macek 2298*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL7_EQ_LFG_CCL_DELTA_MASK 0x1F 2299*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL7_EQ_LFG_CCL_DELTA_SHIFT 0 2300*3fc36ee0SWojciech Macek 2301*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL8_EQ_LFG_CCL_MAX_MASK 0x1F 2302*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL8_EQ_LFG_CCL_MAX_SHIFT 0 2303*3fc36ee0SWojciech Macek 2304*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL0_GNEQ_CCL_LFG_START_MASK 0x1F 2305*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL0_GNEQ_CCL_LFG_START_SHIFT 0 2306*3fc36ee0SWojciech Macek 2307*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL1_GNEQ_CCL_LFG_VALUE_MAX_MASK 0x1F 2308*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL1_GNEQ_CCL_LFG_VALUE_MAX_SHIFT 0 2309*3fc36ee0SWojciech Macek 2310*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL2_GNEQ_CCL_LFG_VALUE_MIN_MASK 0x1F 2311*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL2_GNEQ_CCL_LFG_VALUE_MIN_SHIFT 0 2312*3fc36ee0SWojciech Macek 2313*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_WRWAIT_TIME_MASK 0x0F 2314*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_WRWAIT_TIME_SHIFT 0 2315*3fc36ee0SWojciech Macek 2316*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_MEASURE_TIMEOUT_DISABLE_MASK 0x80 2317*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_MEASURE_TIMEOUT_DISABLE_SHIFT 7 2318*3fc36ee0SWojciech Macek 2319*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_BY1_MASK 0x01 2320*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_BY1_SHIFT 0 2321*3fc36ee0SWojciech Macek 2322*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_ERROR_SIGN_MASK 0x02 2323*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_ERROR_SIGN_SHIFT 1 2324*3fc36ee0SWojciech Macek 2325*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_SIZE_MASK 0x1C 2326*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_SIZE_SHIFT 2 2327*3fc36ee0SWojciech Macek 2328*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_BOUNCE_LIMIT_MASK 0x0F 2329*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_BOUNCE_LIMIT_SHIFT 0 2330*3fc36ee0SWojciech Macek 2331*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_AVG_MASK 0x30 2332*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_AVG_SHIFT 4 2333*3fc36ee0SWojciech Macek 2334*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_FLOOR_MASK 0x40 2335*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_FLOOR_SHIFT 6 2336*3fc36ee0SWojciech Macek 2337*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL6_GNEQ_CCL_LFG_LASTWR_ADJUST_MASK 0x1F 2338*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL6_GNEQ_CCL_LFG_LASTWR_ADJUST_SHIFT 0 2339*3fc36ee0SWojciech Macek 2340*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_WRWAIT_TIME_MASK 0x0F 2341*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_WRWAIT_TIME_SHIFT 0 2342*3fc36ee0SWojciech Macek 2343*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_STEP_BY1_MASK 0x10 2344*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_STEP_BY1_SHIFT 4 2345*3fc36ee0SWojciech Macek 2346*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_MASK 0x0F 2347*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_SHIFT 0 2348*3fc36ee0SWojciech Macek 2349*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_MASK 0xF0 2350*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_SHIFT 4 2351*3fc36ee0SWojciech Macek 2352*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL0_VSCAN_VALUE_MAX_MASK 0xFF 2353*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL0_VSCAN_VALUE_MAX_SHIFT 0 2354*3fc36ee0SWojciech Macek 2355*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL1_VSCAN_VALUE_MIN_MASK 0xFF 2356*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL1_VSCAN_VALUE_MIN_SHIFT 0 2357*3fc36ee0SWojciech Macek 2358*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_BY1_MASK 0x01 2359*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_BY1_SHIFT 0 2360*3fc36ee0SWojciech Macek 2361*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_ERROR_SIGN_MASK 0x02 2362*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_ERROR_SIGN_SHIFT 1 2363*3fc36ee0SWojciech Macek 2364*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_SIZE_MASK 0x3C 2365*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_SIZE_SHIFT 2 2366*3fc36ee0SWojciech Macek 2367*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_BOUNCE_LIMIT_MASK 0x0F 2368*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_BOUNCE_LIMIT_SHIFT 0 2369*3fc36ee0SWojciech Macek 2370*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_AVG_MASK 0x30 2371*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_AVG_SHIFT 4 2372*3fc36ee0SWojciech Macek 2373*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_FLOOR_MASK 0x40 2374*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_FLOOR_SHIFT 6 2375*3fc36ee0SWojciech Macek 2376*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL0_HSCAN_VALUE_MAX_MASK 0xFF 2377*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL0_HSCAN_VALUE_MAX_SHIFT 0 2378*3fc36ee0SWojciech Macek 2379*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL1_HSCAN_VALUE_MIN_MASK 0xFF 2380*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL1_HSCAN_VALUE_MIN_SHIFT 0 2381*3fc36ee0SWojciech Macek 2382*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_BY1_MASK 0x01 2383*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_BY1_SHIFT 0 2384*3fc36ee0SWojciech Macek 2385*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_ERROR_SIGN_MASK 0x02 2386*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_ERROR_SIGN_SHIFT 1 2387*3fc36ee0SWojciech Macek 2388*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_SIZE_MASK 0x3C 2389*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_SIZE_SHIFT 2 2390*3fc36ee0SWojciech Macek 2391*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_BOUNCE_LIMIT_MASK 0x0F 2392*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_BOUNCE_LIMIT_SHIFT 0 2393*3fc36ee0SWojciech Macek 2394*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_AVG_MASK 0x30 2395*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_AVG_SHIFT 4 2396*3fc36ee0SWojciech Macek 2397*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_FLOOR_MASK 0x40 2398*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_FLOOR_SHIFT 6 2399*3fc36ee0SWojciech Macek 2400*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD0_GN_APG_REF_N_MASK 0xFF 2401*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD0_GN_APG_REF_N_SHIFT 0 2402*3fc36ee0SWojciech Macek 2403*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD1_GN_APG_REF_P_MASK 0xFF 2404*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD1_GN_APG_REF_P_SHIFT 0 2405*3fc36ee0SWojciech Macek 2406*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD2_EQ_LFG_REF_N_MASK 0xFF 2407*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD2_EQ_LFG_REF_N_SHIFT 0 2408*3fc36ee0SWojciech Macek 2409*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD3_EQ_LFG_REF_P_MASK 0xFF 2410*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD3_EQ_LFG_REF_P_SHIFT 0 2411*3fc36ee0SWojciech Macek 2412*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE0_EYE_PHASE_7_0_MASK 0xFF 2413*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE0_EYE_PHASE_7_0_SHIFT 0 2414*3fc36ee0SWojciech Macek 2415*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_8_MASK 0x01 2416*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_8_SHIFT 0 2417*3fc36ee0SWojciech Macek 2418*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_VALID_MASK 0x02 2419*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_VALID_SHIFT 1 2420*3fc36ee0SWojciech Macek 2421*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_ODDEYE_MASK 0x01 2422*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_ODDEYE_SHIFT 0 2423*3fc36ee0SWojciech Macek 2424*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_PATH1_MASK 0x02 2425*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_PATH1_SHIFT 1 2426*3fc36ee0SWojciech Macek 2427*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYEINTF_CTRL0_EYEINTF_INIT_TIMEOUT_DISABLE_MASK 0x40 2428*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_EYEINTF_CTRL0_EYEINTF_INIT_TIMEOUT_DISABLE_SHIFT 6 2429*3fc36ee0SWojciech Macek 2430*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE0_MASK 0xFF 2431*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE0_SHIFT 0 2432*3fc36ee0SWojciech Macek 2433*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE1_MASK 0xFF 2434*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE1_SHIFT 0 2435*3fc36ee0SWojciech Macek 2436*3fc36ee0SWojciech Macek /********************************* DRV_REFCLK *********************************/ 2437*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_REFCLK_BASE 0x380 2438*3fc36ee0SWojciech Macek 2439*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x00) 2440*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_RST_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x01) 2441*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CTRL1_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x03) 2442*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CTRL2_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x04) 2443*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CTRL3_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x05) 2444*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x06) 2445*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x08) 2446*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x09) 2447*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0A) 2448*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0B) 2449*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0C) 2450*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0D) 2451*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x10) 2452*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_STATUS0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x11) 2453*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL1_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x12) 2454*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL2_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x13) 2455*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL3_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x14) 2456*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL4_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x15) 2457*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL5_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x16) 2458*3fc36ee0SWojciech Macek /******************************************************************************* 2459*3fc36ee0SWojciech Macek * masks and shifts 2460*3fc36ee0SWojciech Macek ******************************************************************************/ 2461*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_PD_TXDRV_MASK 0x01 2462*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_PD_TXDRV_SHIFT 0 2463*3fc36ee0SWojciech Macek 2464*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_TXDRV_LP_IDLE_MASK 0x02 2465*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_TXDRV_LP_IDLE_SHIFT 1 2466*3fc36ee0SWojciech Macek 2467*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_RST_CTRL0_RST_TXDRV_DIV2_N_MASK 0x01 2468*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_RST_CTRL0_RST_TXDRV_DIV2_N_SHIFT 0 2469*3fc36ee0SWojciech Macek 2470*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CTRL1_TXDRV_SPARE_MASK 0xFF 2471*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CTRL1_TXDRV_SPARE_SHIFT 0 2472*3fc36ee0SWojciech Macek 2473*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_TOGGLE_EN_MASK 0x01 2474*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_TOGGLE_EN_SHIFT 0 2475*3fc36ee0SWojciech Macek 2476*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_CLK_DELAY_MASK 0x3E 2477*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_CLK_DELAY_SHIFT 1 2478*3fc36ee0SWojciech Macek 2479*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CTRL3_TXDRV_CO_POL_MASK 0x07 2480*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CTRL3_TXDRV_CO_POL_SHIFT 0 2481*3fc36ee0SWojciech Macek 2482*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_P5_MASK 0x01 2483*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_P5_SHIFT 0 2484*3fc36ee0SWojciech Macek 2485*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X1_MASK 0x02 2486*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X1_SHIFT 1 2487*3fc36ee0SWojciech Macek 2488*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X2_MASK 0x1C 2489*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X2_SHIFT 2 2490*3fc36ee0SWojciech Macek 2491*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X1_MASK 0x20 2492*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X1_SHIFT 5 2493*3fc36ee0SWojciech Macek 2494*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X2_MASK 0xC0 2495*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X2_SHIFT 6 2496*3fc36ee0SWojciech Macek 2497*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_P5_MASK 0x01 2498*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_P5_SHIFT 0 2499*3fc36ee0SWojciech Macek 2500*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X1_MASK 0x02 2501*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X1_SHIFT 1 2502*3fc36ee0SWojciech Macek 2503*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X2_MASK 0x0C 2504*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X2_SHIFT 2 2505*3fc36ee0SWojciech Macek 2506*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CXCM1_X2_MASK 0x10 2507*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CXCM1_X2_SHIFT 4 2508*3fc36ee0SWojciech Macek 2509*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X1_MASK 0x07 2510*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X1_SHIFT 0 2511*3fc36ee0SWojciech Macek 2512*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X2_MASK 0xF8 2513*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X2_SHIFT 3 2514*3fc36ee0SWojciech Macek 2515*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_CXN_X1_MASK 0x07 2516*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_CXN_X1_SHIFT 0 2517*3fc36ee0SWojciech Macek 2518*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_FIXEDCXN_X1_MASK 0x18 2519*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_FIXEDCXN_X1_SHIFT 3 2520*3fc36ee0SWojciech Macek 2521*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_CXN_X2_MASK 0x1F 2522*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_CXN_X2_SHIFT 0 2523*3fc36ee0SWojciech Macek 2524*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_FIXEDCXN_XP5_MASK 0x60 2525*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_FIXEDCXN_XP5_SHIFT 5 2526*3fc36ee0SWojciech Macek 2527*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_CXP_X1_MASK 0x07 2528*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_CXP_X1_SHIFT 0 2529*3fc36ee0SWojciech Macek 2530*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_FIXEDCXP_X1_MASK 0x18 2531*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_FIXEDCXP_X1_SHIFT 3 2532*3fc36ee0SWojciech Macek 2533*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_CXP_X2_MASK 0x1F 2534*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_CXP_X2_SHIFT 0 2535*3fc36ee0SWojciech Macek 2536*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_FIXEDCXP_XP5_MASK 0x60 2537*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_FIXEDCXP_XP5_SHIFT 5 2538*3fc36ee0SWojciech Macek 2539*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_MASK 0x01 2540*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_SHIFT 0 2541*3fc36ee0SWojciech Macek 2542*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_MASK 0x01 2543*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_SHIFT 0 2544*3fc36ee0SWojciech Macek 2545*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_MASK 0x1F 2546*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_SHIFT 0 2547*3fc36ee0SWojciech Macek 2548*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL2_TXEQ_C2_MASK 0x03 2549*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL2_TXEQ_C2_SHIFT 0 2550*3fc36ee0SWojciech Macek 2551*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_MASK 0x0F 2552*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_SHIFT 0 2553*3fc36ee0SWojciech Macek 2554*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL4_TXEQ_1LSB_MODE_MASK 0x01 2555*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL4_TXEQ_1LSB_MODE_SHIFT 0 2556*3fc36ee0SWojciech Macek 2557*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL4_SWING_1LSB_MODE_MASK 0x02 2558*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL4_SWING_1LSB_MODE_SHIFT 1 2559*3fc36ee0SWojciech Macek 2560*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_MASK 0x0F 2561*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_SHIFT 0 2562*3fc36ee0SWojciech Macek 2563*3fc36ee0SWojciech Macek /********************************* DFE REFCLK *********************************/ 2564*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_BASE 0x400 2565*3fc36ee0SWojciech Macek 2566*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x00) 2567*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x01) 2568*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x02) 2569*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_RST_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x04) 2570*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_TOGGLE_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x06) 2571*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x0A) 2572*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x0C) 2573*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x0E) 2574*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x10) 2575*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x12) 2576*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_SPARE_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x14) 2577*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x16) 2578*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x18) 2579*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x19) 2580*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x1B) 2581*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x20) 2582*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x21) 2583*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x22) 2584*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x23) 2585*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x24) 2586*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x25) 2587*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x26) 2588*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x27) 2589*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x28) 2590*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2A) 2591*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2B) 2592*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2C) 2593*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2D) 2594*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2E) 2595*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2F) 2596*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x30) 2597*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x31) 2598*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x32) 2599*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x33) 2600*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x34) 2601*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x35) 2602*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x36) 2603*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x37) 2604*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x38) 2605*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x39) 2606*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3A) 2607*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3B) 2608*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3C) 2609*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3D) 2610*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3E) 2611*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3F) 2612*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x40) 2613*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x41) 2614*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x42) 2615*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x50) 2616*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x51) 2617*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x52) 2618*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x53) 2619*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x54) 2620*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x55) 2621*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x56) 2622*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x57) 2623*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x58) 2624*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x59) 2625*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5A) 2626*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5B) 2627*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5C) 2628*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5D) 2629*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5E) 2630*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5F) 2631*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x60) 2632*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x61) 2633*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x62) 2634*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x63) 2635*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x64) 2636*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x65) 2637*3fc36ee0SWojciech Macek /******************************************************************************* 2638*3fc36ee0SWojciech Macek * masks and shifts 2639*3fc36ee0SWojciech Macek ******************************************************************************/ 2640*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_MASK 0x01 2641*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_SHIFT 0 2642*3fc36ee0SWojciech Macek 2643*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_TAP_MASK 0x3E 2644*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_TAP_SHIFT 1 2645*3fc36ee0SWojciech Macek 2646*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_EVEN_PATH_MASK 0x03 2647*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_EVEN_PATH_SHIFT 0 2648*3fc36ee0SWojciech Macek 2649*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_ODD_PATH_MASK 0x0C 2650*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_ODD_PATH_SHIFT 2 2651*3fc36ee0SWojciech Macek 2652*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_EVEN_MASK 0x07 2653*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_EVEN_SHIFT 0 2654*3fc36ee0SWojciech Macek 2655*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_ODD_MASK 0x38 2656*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_ODD_SHIFT 3 2657*3fc36ee0SWojciech Macek 2658*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_RST_CTRL0_RST_RXDFE_N_MASK 0x01 2659*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_RST_CTRL0_RST_RXDFE_N_SHIFT 0 2660*3fc36ee0SWojciech Macek 2661*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_TOGGLE_CTRL0_RXDFE_TOGGLE_EN_MASK 0x01 2662*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_TOGGLE_CTRL0_RXDFE_TOGGLE_EN_SHIFT 0 2663*3fc36ee0SWojciech Macek 2664*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_EVEN_MASK 0x01 2665*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_EVEN_SHIFT 0 2666*3fc36ee0SWojciech Macek 2667*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_ODD_MASK 0x02 2668*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_ODD_SHIFT 1 2669*3fc36ee0SWojciech Macek 2670*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_EDGE_MUTE_MASK 0x0C 2671*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_EDGE_MUTE_SHIFT 2 2672*3fc36ee0SWojciech Macek 2673*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLK_DELAY_MASK 0x0F 2674*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLK_DELAY_SHIFT 0 2675*3fc36ee0SWojciech Macek 2676*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLKDIV_OVR_MASK 0x30 2677*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLKDIV_OVR_SHIFT 4 2678*3fc36ee0SWojciech Macek 2679*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYECLK_DELAY_MASK 0x0F 2680*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYECLK_DELAY_SHIFT 0 2681*3fc36ee0SWojciech Macek 2682*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_CLKDIVEYE_OVR_MASK 0x30 2683*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_CLKDIVEYE_OVR_SHIFT 4 2684*3fc36ee0SWojciech Macek 2685*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYERESAMP_ADJ_MASK 0xC0 2686*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYERESAMP_ADJ_SHIFT 6 2687*3fc36ee0SWojciech Macek 2688*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLI_MASK 0x0F 2689*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLI_SHIFT 0 2690*3fc36ee0SWojciech Macek 2691*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_MASK 0x30 2692*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_SHIFT 4 2693*3fc36ee0SWojciech Macek 2694*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_LTCH_MASK 0x40 2695*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_LTCH_SHIFT 6 2696*3fc36ee0SWojciech Macek 2697*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_SUMGAIN_MASK 0x01 2698*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_SUMGAIN_SHIFT 0 2699*3fc36ee0SWojciech Macek 2700*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_LDR_MASK 0x06 2701*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_LDR_SHIFT 1 2702*3fc36ee0SWojciech Macek 2703*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_SPARE_RXDFE_SPARE_MASK 0xFF 2704*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_SPARE_RXDFE_SPARE_SHIFT 0 2705*3fc36ee0SWojciech Macek 2706*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIV_QSAMPLE_MASK 0x01 2707*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIV_QSAMPLE_SHIFT 0 2708*3fc36ee0SWojciech Macek 2709*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIVEYE_QSAMPLE_MASK 0x1E 2710*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIVEYE_QSAMPLE_SHIFT 1 2711*3fc36ee0SWojciech Macek 2712*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL0_MAG_MASK 0xFF 2713*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL0_MAG_SHIFT 0 2714*3fc36ee0SWojciech Macek 2715*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL1_POL_MASK 0x01 2716*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL1_POL_SHIFT 0 2717*3fc36ee0SWojciech Macek 2718*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_MAG_MASK 0x1F 2719*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_MAG_SHIFT 0 2720*3fc36ee0SWojciech Macek 2721*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_POL_MASK 0x80 2722*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_POL_SHIFT 7 2723*3fc36ee0SWojciech Macek 2724*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_REQ_MASK 0x01 2725*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_REQ_SHIFT 0 2726*3fc36ee0SWojciech Macek 2727*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_CMD_MASK 0x3E 2728*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_CMD_SHIFT 1 2729*3fc36ee0SWojciech Macek 2730*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_FINISH_MASK 0x40 2731*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_FINISH_SHIFT 6 2732*3fc36ee0SWojciech Macek 2733*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_MASK 0x80 2734*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_SHIFT 7 2735*3fc36ee0SWojciech Macek 2736*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_NEXT_STATE_MASK 0x0F 2737*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_NEXT_STATE_SHIFT 0 2738*3fc36ee0SWojciech Macek 2739*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_CTRL_EN_MASK 0x10 2740*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_CTRL_EN_SHIFT 4 2741*3fc36ee0SWojciech Macek 2742*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL2_WAIT_1_TIMER7_0_MASK 0xFF 2743*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL2_WAIT_1_TIMER7_0_SHIFT 0 2744*3fc36ee0SWojciech Macek 2745*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL3_WAIT_1_TIMER9_8_MASK 0x03 2746*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL3_WAIT_1_TIMER9_8_SHIFT 0 2747*3fc36ee0SWojciech Macek 2748*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL4_WAIT_2_TIMER7_0_MASK 0xFF 2749*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL4_WAIT_2_TIMER7_0_SHIFT 0 2750*3fc36ee0SWojciech Macek 2751*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL5_WAIT_2_TIMER9_8_MASK 0x03 2752*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL5_WAIT_2_TIMER9_8_SHIFT 0 2753*3fc36ee0SWojciech Macek 2754*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL6_TAP_DELAY_7_0_MASK 0xFF 2755*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL6_TAP_DELAY_7_0_SHIFT 0 2756*3fc36ee0SWojciech Macek 2757*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL7_TAP_DELAY_9_8_MASK 0x03 2758*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL7_TAP_DELAY_9_8_SHIFT 0 2759*3fc36ee0SWojciech Macek 2760*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ACK_MASK 0x01 2761*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ACK_SHIFT 0 2762*3fc36ee0SWojciech Macek 2763*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_SLICER_OFST_ACK_MASK 0x02 2764*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_SLICER_OFST_ACK_SHIFT 1 2765*3fc36ee0SWojciech Macek 2766*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ERR_FUNC_ACK_MASK 0x04 2767*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ERR_FUNC_ACK_SHIFT 2 2768*3fc36ee0SWojciech Macek 2769*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_AFE_DRV_ACK_MASK 0x08 2770*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_AFE_DRV_ACK_SHIFT 3 2771*3fc36ee0SWojciech Macek 2772*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_MASK 0x01 2773*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_SHIFT 0 2774*3fc36ee0SWojciech Macek 2775*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_MASK 0x02 2776*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_SHIFT 1 2777*3fc36ee0SWojciech Macek 2778*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_MASK 0x04 2779*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_SHIFT 2 2780*3fc36ee0SWojciech Macek 2781*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_MASK 0x08 2782*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_SHIFT 3 2783*3fc36ee0SWojciech Macek 2784*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP2_EN_MASK 0x10 2785*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP2_EN_SHIFT 4 2786*3fc36ee0SWojciech Macek 2787*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP3_EN_MASK 0x20 2788*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP3_EN_SHIFT 5 2789*3fc36ee0SWojciech Macek 2790*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP4_EN_MASK 0x40 2791*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP4_EN_SHIFT 6 2792*3fc36ee0SWojciech Macek 2793*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP5_EN_MASK 0x80 2794*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP5_EN_SHIFT 7 2795*3fc36ee0SWojciech Macek 2796*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_MASK 0x1F 2797*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_SHIFT 0 2798*3fc36ee0SWojciech Macek 2799*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_MASK 0x80 2800*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT 7 2801*3fc36ee0SWojciech Macek 2802*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_MASK 0x1F 2803*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_SHIFT 0 2804*3fc36ee0SWojciech Macek 2805*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_MASK 0x80 2806*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT 7 2807*3fc36ee0SWojciech Macek 2808*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_MASK 0x1F 2809*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_SHIFT 0 2810*3fc36ee0SWojciech Macek 2811*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_MASK 0x80 2812*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT 7 2813*3fc36ee0SWojciech Macek 2814*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_MASK 0x1F 2815*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_SHIFT 0 2816*3fc36ee0SWojciech Macek 2817*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_MASK 0x80 2818*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT 7 2819*3fc36ee0SWojciech Macek 2820*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_MASK 0x0F 2821*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_SHIFT 0 2822*3fc36ee0SWojciech Macek 2823*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_MASK 0x80 2824*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_SHIFT 7 2825*3fc36ee0SWojciech Macek 2826*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_MASK 0x07 2827*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_SHIFT 0 2828*3fc36ee0SWojciech Macek 2829*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_MASK 0x80 2830*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_SHIFT 7 2831*3fc36ee0SWojciech Macek 2832*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_MASK 0x07 2833*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_SHIFT 0 2834*3fc36ee0SWojciech Macek 2835*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_MASK 0x80 2836*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_SHIFT 7 2837*3fc36ee0SWojciech Macek 2838*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_MASK 0x07 2839*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_SHIFT 0 2840*3fc36ee0SWojciech Macek 2841*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_MASK 0x80 2842*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_SHIFT 7 2843*3fc36ee0SWojciech Macek 2844*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_MASK 0x1F 2845*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_SHIFT 0 2846*3fc36ee0SWojciech Macek 2847*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_MASK 0x80 2848*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT 7 2849*3fc36ee0SWojciech Macek 2850*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_MASK 0x1F 2851*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_SHIFT 0 2852*3fc36ee0SWojciech Macek 2853*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_MASK 0x80 2854*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT 7 2855*3fc36ee0SWojciech Macek 2856*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_MASK 0x1F 2857*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_SHIFT 0 2858*3fc36ee0SWojciech Macek 2859*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_MASK 0x80 2860*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT 7 2861*3fc36ee0SWojciech Macek 2862*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_MASK 0x1F 2863*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_SHIFT 0 2864*3fc36ee0SWojciech Macek 2865*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_MASK 0x80 2866*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT 7 2867*3fc36ee0SWojciech Macek 2868*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_MASK 0x0F 2869*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_SHIFT 0 2870*3fc36ee0SWojciech Macek 2871*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_MASK 0x80 2872*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_SHIFT 7 2873*3fc36ee0SWojciech Macek 2874*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_MASK 0x07 2875*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_SHIFT 0 2876*3fc36ee0SWojciech Macek 2877*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_MASK 0x80 2878*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_SHIFT 7 2879*3fc36ee0SWojciech Macek 2880*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_MASK 0x07 2881*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_SHIFT 0 2882*3fc36ee0SWojciech Macek 2883*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_MASK 0x80 2884*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_SHIFT 7 2885*3fc36ee0SWojciech Macek 2886*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_MASK 0x07 2887*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_SHIFT 0 2888*3fc36ee0SWojciech Macek 2889*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_MASK 0x80 2890*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_SHIFT 7 2891*3fc36ee0SWojciech Macek 2892*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_MASK 0x1F 2893*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_SHIFT 0 2894*3fc36ee0SWojciech Macek 2895*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_MASK 0x80 2896*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_SHIFT 7 2897*3fc36ee0SWojciech Macek 2898*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_MASK 0x1F 2899*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_SHIFT 0 2900*3fc36ee0SWojciech Macek 2901*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_MASK 0x80 2902*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_SHIFT 7 2903*3fc36ee0SWojciech Macek 2904*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_MASK 0x1F 2905*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_SHIFT 0 2906*3fc36ee0SWojciech Macek 2907*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_MASK 0x80 2908*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_SHIFT 7 2909*3fc36ee0SWojciech Macek 2910*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_MASK 0x1F 2911*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_SHIFT 0 2912*3fc36ee0SWojciech Macek 2913*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_MASK 0x80 2914*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_SHIFT 7 2915*3fc36ee0SWojciech Macek 2916*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_MASK 0x0F 2917*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_SHIFT 0 2918*3fc36ee0SWojciech Macek 2919*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_MASK 0x80 2920*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_SHIFT 7 2921*3fc36ee0SWojciech Macek 2922*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_MASK 0x07 2923*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_SHIFT 0 2924*3fc36ee0SWojciech Macek 2925*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_MASK 0x80 2926*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_SHIFT 7 2927*3fc36ee0SWojciech Macek 2928*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_MASK 0x07 2929*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_SHIFT 0 2930*3fc36ee0SWojciech Macek 2931*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_MASK 0x80 2932*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_SHIFT 7 2933*3fc36ee0SWojciech Macek 2934*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_MASK 0x07 2935*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_SHIFT 0 2936*3fc36ee0SWojciech Macek 2937*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_MASK 0x80 2938*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_SHIFT 7 2939*3fc36ee0SWojciech Macek 2940*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN0_DATA_EN_MASK 0x01 2941*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN0_DATA_EN_SHIFT 0 2942*3fc36ee0SWojciech Macek 2943*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN1_DATA_EN_MASK 0x02 2944*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN1_DATA_EN_SHIFT 1 2945*3fc36ee0SWojciech Macek 2946*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD0_DATA_EN_MASK 0x04 2947*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD0_DATA_EN_SHIFT 2 2948*3fc36ee0SWojciech Macek 2949*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD1_DATA_EN_MASK 0x08 2950*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD1_DATA_EN_SHIFT 3 2951*3fc36ee0SWojciech Macek 2952*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EDGE_EN_MASK 0x10 2953*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EDGE_EN_SHIFT 4 2954*3fc36ee0SWojciech Macek 2955*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EDGE_EN_MASK 0x20 2956*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EDGE_EN_SHIFT 5 2957*3fc36ee0SWojciech Macek 2958*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EYE_EN_MASK 0x40 2959*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EYE_EN_SHIFT 6 2960*3fc36ee0SWojciech Macek 2961*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EYE_EN_MASK 0x80 2962*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EYE_EN_SHIFT 7 2963*3fc36ee0SWojciech Macek 2964*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL1_LIMIT_MASK 0x1F 2965*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL1_LIMIT_SHIFT 0 2966*3fc36ee0SWojciech Macek 2967*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL2_MAX_BOUNCES_MASK 0x0F 2968*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL2_MAX_BOUNCES_SHIFT 0 2969*3fc36ee0SWojciech Macek 2970*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL0_EVEN0_DATA_MASK 0x3F 2971*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL0_EVEN0_DATA_SHIFT 0 2972*3fc36ee0SWojciech Macek 2973*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL1_EVEN1_DATA_MASK 0x3F 2974*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL1_EVEN1_DATA_SHIFT 0 2975*3fc36ee0SWojciech Macek 2976*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL2_ODD0_DATA_MASK 0x3F 2977*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL2_ODD0_DATA_SHIFT 0 2978*3fc36ee0SWojciech Macek 2979*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL3_ODD1_DATA_MASK 0x3F 2980*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL3_ODD1_DATA_SHIFT 0 2981*3fc36ee0SWojciech Macek 2982*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL4_EVEN_EDGE_MASK 0x3F 2983*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL4_EVEN_EDGE_SHIFT 0 2984*3fc36ee0SWojciech Macek 2985*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL5_ODD_EDGE_MASK 0x3F 2986*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL5_ODD_EDGE_SHIFT 0 2987*3fc36ee0SWojciech Macek 2988*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL6_EVEN_EYE_MASK 0x3F 2989*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL6_EVEN_EYE_SHIFT 0 2990*3fc36ee0SWojciech Macek 2991*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL7_ODD_EYE_MASK 0x3F 2992*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL7_ODD_EYE_SHIFT 0 2993*3fc36ee0SWojciech Macek 2994*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS0_EVEN0_DATA_MASK 0x3F 2995*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS0_EVEN0_DATA_SHIFT 0 2996*3fc36ee0SWojciech Macek 2997*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS1_EVEN1_DATA_MASK 0x3F 2998*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS1_EVEN1_DATA_SHIFT 0 2999*3fc36ee0SWojciech Macek 3000*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS2_ODD0_DATA_MASK 0x3F 3001*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS2_ODD0_DATA_SHIFT 0 3002*3fc36ee0SWojciech Macek 3003*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS3_ODD1_DATA_MASK 0x3F 3004*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS3_ODD1_DATA_SHIFT 0 3005*3fc36ee0SWojciech Macek 3006*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS4_EVEN_EDGE_MASK 0x3F 3007*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS4_EVEN_EDGE_SHIFT 0 3008*3fc36ee0SWojciech Macek 3009*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS5_ODD_EDGE_MASK 0x3F 3010*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS5_ODD_EDGE_SHIFT 0 3011*3fc36ee0SWojciech Macek 3012*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS6_EVEN_EYE_MASK 0x3F 3013*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS6_EVEN_EYE_SHIFT 0 3014*3fc36ee0SWojciech Macek 3015*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS7_ODD_EYE_MASK 0x3F 3016*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS7_ODD_EYE_SHIFT 0 3017*3fc36ee0SWojciech Macek 3018*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN0_DATA_MASK 0x01 3019*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN0_DATA_SHIFT 0 3020*3fc36ee0SWojciech Macek 3021*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN1_DATA_MASK 0x02 3022*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN1_DATA_SHIFT 1 3023*3fc36ee0SWojciech Macek 3024*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD0_DATA_MASK 0x04 3025*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD0_DATA_SHIFT 2 3026*3fc36ee0SWojciech Macek 3027*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD1_DATA_MASK 0x08 3028*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD1_DATA_SHIFT 3 3029*3fc36ee0SWojciech Macek 3030*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EDGE_MASK 0x10 3031*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EDGE_SHIFT 4 3032*3fc36ee0SWojciech Macek 3033*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EDGE_MASK 0x20 3034*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EDGE_SHIFT 5 3035*3fc36ee0SWojciech Macek 3036*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EYE_MASK 0x40 3037*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EYE_SHIFT 6 3038*3fc36ee0SWojciech Macek 3039*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EYE_MASK 0x80 3040*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EYE_SHIFT 7 3041*3fc36ee0SWojciech Macek 3042*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_ERR_MASK 0x01 3043*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_ERR_SHIFT 0 3044*3fc36ee0SWojciech Macek 3045*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_INC_MASK 0x02 3046*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_INC_SHIFT 1 3047*3fc36ee0SWojciech Macek 3048*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_DEC_MASK 0x04 3049*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_DEC_SHIFT 2 3050*3fc36ee0SWojciech Macek 3051*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN0_DATA_MASK 0x01 3052*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN0_DATA_SHIFT 0 3053*3fc36ee0SWojciech Macek 3054*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN1_DATA_MASK 0x02 3055*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN1_DATA_SHIFT 1 3056*3fc36ee0SWojciech Macek 3057*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD0_DATA_MASK 0x04 3058*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD0_DATA_SHIFT 2 3059*3fc36ee0SWojciech Macek 3060*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD1_DATA_MASK 0x08 3061*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD1_DATA_SHIFT 3 3062*3fc36ee0SWojciech Macek 3063*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EDGE_MASK 0x10 3064*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EDGE_SHIFT 4 3065*3fc36ee0SWojciech Macek 3066*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EDGE_MASK 0x20 3067*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EDGE_SHIFT 5 3068*3fc36ee0SWojciech Macek 3069*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EYE_MASK 0x40 3070*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EYE_SHIFT 6 3071*3fc36ee0SWojciech Macek 3072*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EYE_MASK 0x80 3073*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EYE_SHIFT 7 3074*3fc36ee0SWojciech Macek 3075*3fc36ee0SWojciech Macek /********************************** LOS REFCLK **********************************/ 3076*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_BASE 0x500 3077*3fc36ee0SWojciech Macek 3078*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x00) 3079*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x01) 3080*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x02) 3081*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x10) 3082*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x11) 3083*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL2_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x12) 3084*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL3_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x13) 3085*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL4_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x14) 3086*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL5_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x15) 3087*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL6_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x16) 3088*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x20) 3089*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x21) 3090*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL2_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x22) 3091*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL3_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x23) 3092*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL4_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x24) 3093*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x30) 3094*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x31) 3095*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x32) 3096*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x33) 3097*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x40) 3098*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x41) 3099*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL2_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x42) 3100*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL3_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x43) 3101*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_EYE_CTRL_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x46) 3102*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x51) 3103*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x59) 3104*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x60) 3105*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x70) 3106*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x71) 3107*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_AFE_SPARE_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x72) 3108*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x73) 3109*3fc36ee0SWojciech Macek /******************************************************************************* 3110*3fc36ee0SWojciech Macek * masks and shifts 3111*3fc36ee0SWojciech Macek ******************************************************************************/ 3112*3fc36ee0SWojciech Macek 3113*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_MASK 0x01 3114*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_SHIFT 0 3115*3fc36ee0SWojciech Macek 3116*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL1_ASSERT_THRESHOLD_MASK 0xFF 3117*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL1_ASSERT_THRESHOLD_SHIFT 0 3118*3fc36ee0SWojciech Macek 3119*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_MASK 0x01 3120*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_SHIFT 0 3121*3fc36ee0SWojciech Macek 3122*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_MASK 0x02 3123*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_SHIFT 1 3124*3fc36ee0SWojciech Macek 3125*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL0_ASSERT_THRESHOLD_7_0_MASK 0xFF 3126*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL0_ASSERT_THRESHOLD_7_0_SHIFT 0 3127*3fc36ee0SWojciech Macek 3128*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL1_ASSERT_THRESHOLD_15_8_MASK 0xFF 3129*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL1_ASSERT_THRESHOLD_15_8_SHIFT 0 3130*3fc36ee0SWojciech Macek 3131*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL2_DEASSERT_THRESHOLD_7_0_MASK 0xFF 3132*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL2_DEASSERT_THRESHOLD_7_0_SHIFT 0 3133*3fc36ee0SWojciech Macek 3134*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL3_DEASSERT_THRESHOLD_15_8_MASK 0xFF 3135*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL3_DEASSERT_THRESHOLD_15_8_SHIFT 0 3136*3fc36ee0SWojciech Macek 3137*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL4_DEASSERT_THRESHOLD_23_16_MASK 0xFF 3138*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL4_DEASSERT_THRESHOLD_23_16_SHIFT 0 3139*3fc36ee0SWojciech Macek 3140*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_MASK 0x03 3141*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_SHIFT 0 3142*3fc36ee0SWojciech Macek 3143*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL6_EN_MASK 0x01 3144*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL6_EN_SHIFT 0 3145*3fc36ee0SWojciech Macek 3146*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL0_EN_MASK 0x01 3147*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL0_EN_SHIFT 0 3148*3fc36ee0SWojciech Macek 3149*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL1_PERIOD_7_0_MASK 0xFF 3150*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL1_PERIOD_7_0_SHIFT 0 3151*3fc36ee0SWojciech Macek 3152*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL2_PERIOD_15_8_MASK 0xFF 3153*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL2_PERIOD_15_8_SHIFT 0 3154*3fc36ee0SWojciech Macek 3155*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL3_PERIOD_23_16_MASK 0xFF 3156*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL3_PERIOD_23_16_SHIFT 0 3157*3fc36ee0SWojciech Macek 3158*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL4_PERIOD_25_24_MASK 0x03 3159*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL4_PERIOD_25_24_SHIFT 0 3160*3fc36ee0SWojciech Macek 3161*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_MASK 0x01 3162*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_SHIFT 0 3163*3fc36ee0SWojciech Macek 3164*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_MASK 0x10 3165*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_SHIFT 4 3166*3fc36ee0SWojciech Macek 3167*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_EN_MASK 0x01 3168*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_EN_SHIFT 0 3169*3fc36ee0SWojciech Macek 3170*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_VALUE_MASK 0x10 3171*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_VALUE_SHIFT 4 3172*3fc36ee0SWojciech Macek 3173*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_VALUE_MASK 0x3F 3174*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_VALUE_SHIFT 0 3175*3fc36ee0SWojciech Macek 3176*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_EN_MASK 0x40 3177*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_EN_SHIFT 6 3178*3fc36ee0SWojciech Macek 3179*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_VALUE_MASK 0x3F 3180*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_VALUE_SHIFT 0 3181*3fc36ee0SWojciech Macek 3182*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_EN_MASK 0x40 3183*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_EN_SHIFT 6 3184*3fc36ee0SWojciech Macek 3185*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_BANDWIDTH_MASK 0x01 3186*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_BANDWIDTH_SHIFT 0 3187*3fc36ee0SWojciech Macek 3188*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_HYSTERESIS_MASK 0x0E 3189*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_HYSTERESIS_SHIFT 1 3190*3fc36ee0SWojciech Macek 3191*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_ENVDET_BYP_MASK 0x10 3192*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_ENVDET_BYP_SHIFT 4 3193*3fc36ee0SWojciech Macek 3194*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_GAIN_MASK 0x01 3195*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_GAIN_SHIFT 0 3196*3fc36ee0SWojciech Macek 3197*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_LOS_INVERT_MASK 0x02 3198*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_LOS_INVERT_SHIFT 1 3199*3fc36ee0SWojciech Macek 3200*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_AGC_INVERT_MASK 0x04 3201*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_AGC_INVERT_SHIFT 2 3202*3fc36ee0SWojciech Macek 3203*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_THRESHOLD_MASK 0x78 3204*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_THRESHOLD_SHIFT 3 3205*3fc36ee0SWojciech Macek 3206*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL2_MODE_SWITCH_WAIT_7_0_MASK 0xFF 3207*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL2_MODE_SWITCH_WAIT_7_0_SHIFT 0 3208*3fc36ee0SWojciech Macek 3209*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL3_MODE_SWITCH_WAIT_15_8_MASK 0xFF 3210*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL3_MODE_SWITCH_WAIT_15_8_SHIFT 0 3211*3fc36ee0SWojciech Macek 3212*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_EYE_CTRL_EYE_DATA_PARITY_MASK 0x01 3213*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_EYE_CTRL_EYE_DATA_PARITY_SHIFT 0 3214*3fc36ee0SWojciech Macek 3215*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_EN_MASK 0x01 3216*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_EN_SHIFT 0 3217*3fc36ee0SWojciech Macek 3218*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_MODE_MASK 0x02 3219*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_MODE_SHIFT 1 3220*3fc36ee0SWojciech Macek 3221*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_LOS_OFFSET_MASK 0x3F 3222*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_LOS_OFFSET_SHIFT 0 3223*3fc36ee0SWojciech Macek 3224*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_AGC_CALIB_DONE_MASK 0x40 3225*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_AGC_CALIB_DONE_SHIFT 6 3226*3fc36ee0SWojciech Macek 3227*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CTRL0_EN_MASK 0x01 3228*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CTRL0_EN_SHIFT 0 3229*3fc36ee0SWojciech Macek 3230*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTRL0_SRC_SELECT_MASK 0x02 3231*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTRL0_SRC_SELECT_SHIFT 1 3232*3fc36ee0SWojciech Macek 3233*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_READY_MASK 0x01 3234*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_READY_SHIFT 0 3235*3fc36ee0SWojciech Macek 3236*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_READY_MASK 0x02 3237*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_READY_SHIFT 1 3238*3fc36ee0SWojciech Macek 3239*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_MASK 0x04 3240*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_SHIFT 2 3241*3fc36ee0SWojciech Macek 3242*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_RAW_MASK 0x08 3243*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_RAW_SHIFT 3 3244*3fc36ee0SWojciech Macek 3245*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_MASK 0x10 3246*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_SHIFT 4 3247*3fc36ee0SWojciech Macek 3248*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_AFE_SPARE_CTRL0_RXLOS_SPARE_MASK 0x0F 3249*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_AFE_SPARE_CTRL0_RXLOS_SPARE_SHIFT 0 3250*3fc36ee0SWojciech Macek 3251*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_AFE_PD_CTRL0_PD_RXLOS_MASK 0x01 3252*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_AFE_PD_CTRL0_PD_RXLOS_SHIFT 0 3253*3fc36ee0SWojciech Macek 3254*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL6_REQ_MASK 0x01 3255*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL6_REQ_SHIFT 0 3256*3fc36ee0SWojciech Macek 3257*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS2_ACK_MASK 0x01 3258*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS2_ACK_SHIFT 0 3259*3fc36ee0SWojciech Macek 3260*3fc36ee0SWojciech Macek /********************************** GCFSM2 **********************************/ 3261*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_BASE 0x580 3262*3fc36ee0SWojciech Macek 3263*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x00) 3264*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x01) 3265*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x02) 3266*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_STATUS_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x03) 3267*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x10) 3268*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x11) 3269*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x12) 3270*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x13) 3271*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x20) 3272*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x21) 3273*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL2_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x22) 3274*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL3_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x23) 3275*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL4_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x24) 3276*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL5_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x25) 3277*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL6_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x26) 3278*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x30) 3279*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x31) 3280*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL2_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x32) 3281*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x40) 3282*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x41) 3283*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL2_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x42) 3284*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL3_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x43) 3285*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL4_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x44) 3286*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL5_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x45) 3287*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL6_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x46) 3288*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL7_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x47) 3289*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL8_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x48) 3290*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x50) 3291*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x51) 3292*3fc36ee0SWojciech Macek /******************************************************************************* 3293*3fc36ee0SWojciech Macek * masks and shifts 3294*3fc36ee0SWojciech Macek ******************************************************************************/ 3295*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_MASK 0x01 3296*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_SHIFT 0 3297*3fc36ee0SWojciech Macek 3298*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_MASK 0x07 3299*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_SHIFT 0 3300*3fc36ee0SWojciech Macek 3301*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR_MASK 0xFF 3302*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR_SHIFT 0 3303*3fc36ee0SWojciech Macek 3304*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_MASK 0x01 3305*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_SHIFT 0 3306*3fc36ee0SWojciech Macek 3307*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_STATUS_CODE_MASK 0x1E 3308*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_CMD_STATUS_CODE_SHIFT 1 3309*3fc36ee0SWojciech Macek 3310*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_7_0_MASK 0xFF 3311*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_7_0_SHIFT 0 3312*3fc36ee0SWojciech Macek 3313*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_MASK 0x0F 3314*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_SHIFT 0 3315*3fc36ee0SWojciech Macek 3316*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS0_7_0_MASK 0xFF 3317*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS0_7_0_SHIFT 0 3318*3fc36ee0SWojciech Macek 3319*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS1_8_8_MASK 0x01 3320*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS1_8_8_SHIFT 0 3321*3fc36ee0SWojciech Macek 3322*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_TYPE_MASK 0x03 3323*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_TYPE_SHIFT 0 3324*3fc36ee0SWojciech Macek 3325*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_WIDTH_MASK 0x3C 3326*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_WIDTH_SHIFT 2 3327*3fc36ee0SWojciech Macek 3328*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL1_START_7_0_MASK 0xFF 3329*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL1_START_7_0_SHIFT 0 3330*3fc36ee0SWojciech Macek 3331*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL2_START_11_8_MASK 0x0F 3332*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL2_START_11_8_SHIFT 0 3333*3fc36ee0SWojciech Macek 3334*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL3_MIN_7_0_MASK 0xFF 3335*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL3_MIN_7_0_SHIFT 0 3336*3fc36ee0SWojciech Macek 3337*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL4_MIN_11_8_MASK 0x0F 3338*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL4_MIN_11_8_SHIFT 0 3339*3fc36ee0SWojciech Macek 3340*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL5_MAX_7_0_MASK 0xFF 3341*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL5_MAX_7_0_SHIFT 0 3342*3fc36ee0SWojciech Macek 3343*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL6_MAX_11_8_MASK 0x0F 3344*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_DATA_CTRL6_MAX_11_8_SHIFT 0 3345*3fc36ee0SWojciech Macek 3346*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL0_STEP_SIZE_MASK 0x1F 3347*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL0_STEP_SIZE_SHIFT 0 3348*3fc36ee0SWojciech Macek 3349*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_BOUNCE_NUM_MASK 0x0F 3350*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_BOUNCE_NUM_SHIFT 0 3351*3fc36ee0SWojciech Macek 3352*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_COARSE_BOUNCE_NUM_MASK 0xF0 3353*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_COARSE_BOUNCE_NUM_SHIFT 4 3354*3fc36ee0SWojciech Macek 3355*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL2_SETTLE_ON_LOWEST_AVG_EN_MASK 0x01 3356*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL2_SETTLE_ON_LOWEST_AVG_EN_SHIFT 0 3357*3fc36ee0SWojciech Macek 3358*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL0_LEN_DELAY_AFE_EN_MASK 0x03 3359*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL0_LEN_DELAY_AFE_EN_SHIFT 0 3360*3fc36ee0SWojciech Macek 3361*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL1_LEN_AFE_1ST_LATCH_SETTLE_7_0_MASK 0xFF 3362*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL1_LEN_AFE_1ST_LATCH_SETTLE_7_0_SHIFT 0 3363*3fc36ee0SWojciech Macek 3364*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL2_LEN_AFE_1ST_LATCH_SETTLE_15_8_MASK 0xFF 3365*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL2_LEN_AFE_1ST_LATCH_SETTLE_15_8_SHIFT 0 3366*3fc36ee0SWojciech Macek 3367*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL3_LEN_AFE_LATCH_SETTLE_MASK 0xFF 3368*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL3_LEN_AFE_LATCH_SETTLE_SHIFT 0 3369*3fc36ee0SWojciech Macek 3370*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL4_LEN_AFE_CMP_7_0_MASK 0xFF 3371*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL4_LEN_AFE_CMP_7_0_SHIFT 0 3372*3fc36ee0SWojciech Macek 3373*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL5_LEN_AFE_CMP_15_8_MASK 0xFF 3374*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL5_LEN_AFE_CMP_15_8_SHIFT 0 3375*3fc36ee0SWojciech Macek 3376*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL6_LEN_COARSE_BOUNCE_AFE_CMP_7_0_MASK 0xFF 3377*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL6_LEN_COARSE_BOUNCE_AFE_CMP_7_0_SHIFT 0 3378*3fc36ee0SWojciech Macek 3379*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL7_LEN_COARSE_BOUNCE_AFE_CMP_15_8_MASK 0xFF 3380*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL7_LEN_COARSE_BOUNCE_AFE_CMP_15_8_SHIFT 0 3381*3fc36ee0SWojciech Macek 3382*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL8_WAIT_MODE_MASK 0x01 3383*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL8_WAIT_MODE_SHIFT 0 3384*3fc36ee0SWojciech Macek 3385*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_INVERT_AFE_UP_MASK 0x01 3386*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_INVERT_AFE_UP_SHIFT 0 3387*3fc36ee0SWojciech Macek 3388*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_LEN_WAIT_AFE_UP_MASK 0x1E 3389*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_LEN_WAIT_AFE_UP_SHIFT 1 3390*3fc36ee0SWojciech Macek 3391*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL1_LEN_AVG_AFE_UP_MASK 0xFF 3392*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL1_LEN_AVG_AFE_UP_SHIFT 0 3393*3fc36ee0SWojciech Macek 3394*3fc36ee0SWojciech Macek /********************************** TX BIST **********************************/ 3395*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BASE 0x600 3396*3fc36ee0SWojciech Macek 3397*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_CTRL_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x00) 3398*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL0_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x04) 3399*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL1_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x05) 3400*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL2_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x06) 3401*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL3_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x07) 3402*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL4_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x08) 3403*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL5_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x09) 3404*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL6_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x0A) 3405*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL7_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x0B) 3406*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_SHIFT_AMOUNT_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x20) 3407*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_ADDR(byte_num) \ 3408*3fc36ee0SWojciech Macek ((SERDES_25G_LANE_TX_BIST_BASE + 0x24) + byte_num) 3409*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_NUM_BYTES 20 3410*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_7_0_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x24) 3411*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_15_8_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x25) 3412*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_23_16_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x26) 3413*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_31_24_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x27) 3414*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_39_32_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x28) 3415*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_47_40_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x29) 3416*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_55_48_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2A) 3417*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_63_56_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2B) 3418*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_71_64_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2C) 3419*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_79_72_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2D) 3420*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_87_80_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2E) 3421*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_95_88_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2F) 3422*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_103_96_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x30) 3423*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_111_104_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x31) 3424*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_119_112_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x32) 3425*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_127_120_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x33) 3426*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_135_128_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x34) 3427*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_143_136_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x35) 3428*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_151_144_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x36) 3429*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_159_152_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x37) 3430*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_167_160_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x38) 3431*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_175_168_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x39) 3432*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_183_176_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x3A) 3433*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_191_184_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x3B) 3434*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_199_192_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x3C) 3435*3fc36ee0SWojciech Macek 3436*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_CTRL_EN_MASK 0x01 3437*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_CTRL_EN_SHIFT 0 3438*3fc36ee0SWojciech Macek 3439*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_MASK 0x1E 3440*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_SHIFT 1 3441*3fc36ee0SWojciech Macek 3442*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS7 1 3443*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS9 2 3444*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS11 3 3445*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS15 4 3446*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS23 5 3447*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS31 6 3448*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS_USER 7 3449*3fc36ee0SWojciech Macek 3450*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL0_MODE_MASK 0x03 3451*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL0_MODE_SHIFT 0 3452*3fc36ee0SWojciech Macek 3453*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL1_TIMER_7_0_MASK 0xFF 3454*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL1_TIMER_7_0_SHIFT 0 3455*3fc36ee0SWojciech Macek 3456*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL2_TIMER_15_8_MASK 0xFF 3457*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL2_TIMER_15_8_SHIFT 0 3458*3fc36ee0SWojciech Macek 3459*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL3_BIT_ERROR_FIELD_7_0_MASK 0xFF 3460*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL3_BIT_ERROR_FIELD_7_0_SHIFT 0 3461*3fc36ee0SWojciech Macek 3462*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL4_BIT_ERROR_FIELD_15_8_MASK 0xFF 3463*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL4_BIT_ERROR_FIELD_15_8_SHIFT 0 3464*3fc36ee0SWojciech Macek 3465*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL5_BIT_ERROR_FIELD_23_16_MASK 0xFF 3466*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL5_BIT_ERROR_FIELD_23_16_SHIFT 0 3467*3fc36ee0SWojciech Macek 3468*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL6_BIT_ERROR_FIELD_31_24_MASK 0xFF 3469*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL6_BIT_ERROR_FIELD_31_24_SHIFT 0 3470*3fc36ee0SWojciech Macek 3471*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL7_BIT_ERROR_FIELD_39_32_MASK 0xFF 3472*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_BER_CTRL7_BIT_ERROR_FIELD_39_32_SHIFT 0 3473*3fc36ee0SWojciech Macek 3474*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_SHIFT_AMOUNT_MASK 0xFF 3475*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_SHIFT_AMOUNT_SHIFT 0 3476*3fc36ee0SWojciech Macek 3477*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_7_0_MASK 0xFF 3478*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_7_0_SHIFT 0 3479*3fc36ee0SWojciech Macek 3480*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_15_8_MASK 0xFF 3481*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_15_8_SHIFT 0 3482*3fc36ee0SWojciech Macek 3483*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_23_16_MASK 0xFF 3484*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_23_16_SHIFT 0 3485*3fc36ee0SWojciech Macek 3486*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_31_24_MASK 0xFF 3487*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_31_24_SHIFT 0 3488*3fc36ee0SWojciech Macek 3489*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_39_32_MASK 0xFF 3490*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_39_32_SHIFT 0 3491*3fc36ee0SWojciech Macek 3492*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_47_40_MASK 0xFF 3493*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_47_40_SHIFT 0 3494*3fc36ee0SWojciech Macek 3495*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_55_48_MASK 0xFF 3496*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_55_48_SHIFT 0 3497*3fc36ee0SWojciech Macek 3498*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_63_56_MASK 0xFF 3499*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_63_56_SHIFT 0 3500*3fc36ee0SWojciech Macek 3501*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_71_64_MASK 0xFF 3502*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_71_64_SHIFT 0 3503*3fc36ee0SWojciech Macek 3504*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_79_72_MASK 0xFF 3505*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_79_72_SHIFT 0 3506*3fc36ee0SWojciech Macek 3507*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_87_80_MASK 0xFF 3508*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_87_80_SHIFT 0 3509*3fc36ee0SWojciech Macek 3510*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_95_88_MASK 0xFF 3511*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_95_88_SHIFT 0 3512*3fc36ee0SWojciech Macek 3513*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_103_96_MASK 0xFF 3514*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_103_96_SHIFT 0 3515*3fc36ee0SWojciech Macek 3516*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_111_104_MASK 0xFF 3517*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_111_104_SHIFT 0 3518*3fc36ee0SWojciech Macek 3519*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_119_112_MASK 0xFF 3520*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_119_112_SHIFT 0 3521*3fc36ee0SWojciech Macek 3522*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_127_120_MASK 0xFF 3523*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_127_120_SHIFT 0 3524*3fc36ee0SWojciech Macek 3525*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_135_128_MASK 0xFF 3526*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_135_128_SHIFT 0 3527*3fc36ee0SWojciech Macek 3528*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_143_136_MASK 0xFF 3529*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_143_136_SHIFT 0 3530*3fc36ee0SWojciech Macek 3531*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_151_144_MASK 0xFF 3532*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_151_144_SHIFT 0 3533*3fc36ee0SWojciech Macek 3534*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_159_152_MASK 0xFF 3535*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_159_152_SHIFT 0 3536*3fc36ee0SWojciech Macek 3537*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_167_160_MASK 0xFF 3538*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_167_160_SHIFT 0 3539*3fc36ee0SWojciech Macek 3540*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_175_168_MASK 0xFF 3541*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_175_168_SHIFT 0 3542*3fc36ee0SWojciech Macek 3543*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_183_176_MASK 0xFF 3544*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_183_176_SHIFT 0 3545*3fc36ee0SWojciech Macek 3546*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_191_184_MASK 0xFF 3547*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_191_184_SHIFT 0 3548*3fc36ee0SWojciech Macek 3549*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_199_192_MASK 0xFF 3550*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_TX_BIST_UDP_199_192_SHIFT 0 3551*3fc36ee0SWojciech Macek 3552*3fc36ee0SWojciech Macek /********************************** RX BIST **********************************/ 3553*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BASE 0x680 3554*3fc36ee0SWojciech Macek 3555*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_CTRL_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x00) 3556*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_STATUS_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x04) 3557*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS0_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x08) 3558*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS1_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x09) 3559*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS2_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x0A) 3560*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS4_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x0C) 3561*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS5_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x0D) 3562*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS6_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x0E) 3563*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL0_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x14) 3564*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL1_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x15) 3565*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL2_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x16) 3566*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL3_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x17) 3567*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL0_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x20) 3568*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL1_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x21) 3569*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL2_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x22) 3570*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL3_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x23) 3571*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x24) 3572*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_SHIFT_AMOUNT_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x30) 3573*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_7_0_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x34) 3574*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_15_8_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x35) 3575*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_23_16_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x36) 3576*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_31_24_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x37) 3577*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_39_32_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x38) 3578*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_47_40_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x39) 3579*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_55_48_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3A) 3580*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_63_56_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3B) 3581*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_71_64_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3C) 3582*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_79_72_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3D) 3583*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_87_80_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3E) 3584*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_95_88_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3F) 3585*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_103_96_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x40) 3586*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_111_104_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x41) 3587*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_119_112_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x42) 3588*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_127_120_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x43) 3589*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_135_128_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x44) 3590*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_143_136_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x45) 3591*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_151_144_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x46) 3592*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_159_152_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x47) 3593*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_167_160_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x48) 3594*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_175_168_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x49) 3595*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_183_176_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x4A) 3596*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_191_184_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x4B) 3597*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_199_192_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x4C) 3598*3fc36ee0SWojciech Macek 3599*3fc36ee0SWojciech Macek /******************************************************************************* 3600*3fc36ee0SWojciech Macek * masks and shifts 3601*3fc36ee0SWojciech Macek ******************************************************************************/ 3602*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_CTRL_EN_MASK 0x01 3603*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_CTRL_EN_SHIFT 0 3604*3fc36ee0SWojciech Macek 3605*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_MASK 0x1E 3606*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_SHIFT 1 3607*3fc36ee0SWojciech Macek 3608*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_MASK 0x20 3609*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_SHIFT 5 3610*3fc36ee0SWojciech Macek 3611*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_CTRL_STOP_ERROR_COUNT_MASK 0x40 3612*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_CTRL_STOP_ERROR_COUNT_SHIFT 6 3613*3fc36ee0SWojciech Macek 3614*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_CTRL_FORCE_LFSR_WITH_RXDATA_MASK 0x80 3615*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_CTRL_FORCE_LFSR_WITH_RXDATA_SHIFT 7 3616*3fc36ee0SWojciech Macek 3617*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_STATUS_STATE_MASK 0x07 3618*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_STATUS_STATE_SHIFT 0 3619*3fc36ee0SWojciech Macek 3620*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_STATUS_PATTERN_DET_MASK 0x78 3621*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_STATUS_PATTERN_DET_SHIFT 3 3622*3fc36ee0SWojciech Macek 3623*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_MASK 0xFF 3624*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_SHIFT 0 3625*3fc36ee0SWojciech Macek 3626*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_MASK 0xFF 3627*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_SHIFT 0 3628*3fc36ee0SWojciech Macek 3629*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_MASK 0xFF 3630*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_SHIFT 0 3631*3fc36ee0SWojciech Macek 3632*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS4_CYCLE_COUNT_7_0_MASK 0xFF 3633*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS4_CYCLE_COUNT_7_0_SHIFT 0 3634*3fc36ee0SWojciech Macek 3635*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS5_CYCLE_COUNT_15_8_MASK 0xFF 3636*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS5_CYCLE_COUNT_15_8_SHIFT 0 3637*3fc36ee0SWojciech Macek 3638*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS6_CYCLE_COUNT_23_16_MASK 0xFF 3639*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_BER_STATUS6_CYCLE_COUNT_23_16_SHIFT 0 3640*3fc36ee0SWojciech Macek 3641*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL0_NUM_CYCLES_7_0_MASK 0xFF 3642*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL0_NUM_CYCLES_7_0_SHIFT 0 3643*3fc36ee0SWojciech Macek 3644*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL1_NUM_CYCLES_15_8_MASK 0xFF 3645*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL1_NUM_CYCLES_15_8_SHIFT 0 3646*3fc36ee0SWojciech Macek 3647*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL2_MAX_ERRORS_7_0_MASK 0xFF 3648*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL2_MAX_ERRORS_7_0_SHIFT 0 3649*3fc36ee0SWojciech Macek 3650*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL3_MAX_ERRORS_15_8_MASK 0xFF 3651*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL3_MAX_ERRORS_15_8_SHIFT 0 3652*3fc36ee0SWojciech Macek 3653*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL0_NUM_CYCLES_7_0_MASK 0xFF 3654*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL0_NUM_CYCLES_7_0_SHIFT 0 3655*3fc36ee0SWojciech Macek 3656*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL1_NUM_CYCLES_15_8_MASK 0xFF 3657*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL1_NUM_CYCLES_15_8_SHIFT 0 3658*3fc36ee0SWojciech Macek 3659*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL2_MIN_ERRORS_7_0_MASK 0xFF 3660*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL2_MIN_ERRORS_7_0_SHIFT 0 3661*3fc36ee0SWojciech Macek 3662*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL3_MIN_ERRORS_15_8_MASK 0xFF 3663*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL3_MIN_ERRORS_15_8_SHIFT 0 3664*3fc36ee0SWojciech Macek 3665*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_MASK 0x01 3666*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_SHIFT 0 3667*3fc36ee0SWojciech Macek 3668*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_SHIFT_AMOUNT_MASK 0xFF 3669*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_SHIFT_AMOUNT_SHIFT 0 3670*3fc36ee0SWojciech Macek 3671*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_7_0_MASK 0xFF 3672*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_7_0_SHIFT 0 3673*3fc36ee0SWojciech Macek 3674*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_15_8_MASK 0xFF 3675*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_15_8_SHIFT 0 3676*3fc36ee0SWojciech Macek 3677*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_23_16_MASK 0xFF 3678*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_23_16_SHIFT 0 3679*3fc36ee0SWojciech Macek 3680*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_31_24_MASK 0xFF 3681*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_31_24_SHIFT 0 3682*3fc36ee0SWojciech Macek 3683*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_39_32_MASK 0xFF 3684*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_39_32_SHIFT 0 3685*3fc36ee0SWojciech Macek 3686*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_47_40_MASK 0xFF 3687*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_47_40_SHIFT 0 3688*3fc36ee0SWojciech Macek 3689*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_55_48_MASK 0xFF 3690*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_55_48_SHIFT 0 3691*3fc36ee0SWojciech Macek 3692*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_63_56_MASK 0xFF 3693*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_63_56_SHIFT 0 3694*3fc36ee0SWojciech Macek 3695*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_71_64_MASK 0xFF 3696*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_71_64_SHIFT 0 3697*3fc36ee0SWojciech Macek 3698*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_79_72_MASK 0xFF 3699*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_79_72_SHIFT 0 3700*3fc36ee0SWojciech Macek 3701*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_87_80_MASK 0xFF 3702*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_87_80_SHIFT 0 3703*3fc36ee0SWojciech Macek 3704*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_95_88_MASK 0xFF 3705*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_95_88_SHIFT 0 3706*3fc36ee0SWojciech Macek 3707*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_103_96_MASK 0xFF 3708*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_103_96_SHIFT 0 3709*3fc36ee0SWojciech Macek 3710*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_111_104_MASK 0xFF 3711*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_111_104_SHIFT 0 3712*3fc36ee0SWojciech Macek 3713*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_119_112_MASK 0xFF 3714*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_119_112_SHIFT 0 3715*3fc36ee0SWojciech Macek 3716*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_127_120_MASK 0xFF 3717*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_127_120_SHIFT 0 3718*3fc36ee0SWojciech Macek 3719*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_135_128_MASK 0xFF 3720*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_135_128_SHIFT 0 3721*3fc36ee0SWojciech Macek 3722*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_143_136_MASK 0xFF 3723*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_143_136_SHIFT 0 3724*3fc36ee0SWojciech Macek 3725*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_151_144_MASK 0xFF 3726*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_151_144_SHIFT 0 3727*3fc36ee0SWojciech Macek 3728*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_159_152_MASK 0xFF 3729*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_159_152_SHIFT 0 3730*3fc36ee0SWojciech Macek 3731*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_167_160_MASK 0xFF 3732*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_167_160_SHIFT 0 3733*3fc36ee0SWojciech Macek 3734*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_175_168_MASK 0xFF 3735*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_175_168_SHIFT 0 3736*3fc36ee0SWojciech Macek 3737*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_183_176_MASK 0xFF 3738*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_183_176_SHIFT 0 3739*3fc36ee0SWojciech Macek 3740*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_191_184_MASK 0xFF 3741*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_191_184_SHIFT 0 3742*3fc36ee0SWojciech Macek 3743*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_199_192_MASK 0xFF 3744*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_RX_BIST_UDP_199_192_SHIFT 0 3745*3fc36ee0SWojciech Macek 3746*3fc36ee0SWojciech Macek /*********************************** FEATURE **********************************/ 3747*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_BASE 0x700 3748*3fc36ee0SWojciech Macek 3749*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RXTERM_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x00) 3750*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x04) 3751*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x05) 3752*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x06) 3753*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x07) 3754*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x08) 3755*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x09) 3756*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_ADAPT_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x0C) 3757*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x10) 3758*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x11) 3759*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x12) 3760*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x13) 3761*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x14) 3762*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x15) 3763*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x16) 3764*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x17) 3765*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x18) 3766*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x19) 3767*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x1A) 3768*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x1B) 3769*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x1F) 3770*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x20) 3771*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x21) 3772*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x22) 3773*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x23) 3774*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x24) 3775*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x25) 3776*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x26) 3777*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x27) 3778*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x28) 3779*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x30) 3780*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x31) 3781*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x32) 3782*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x33) 3783*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x40) 3784*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x41) 3785*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x42) 3786*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG3_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x43) 3787*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG4_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x44) 3788*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG5_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x45) 3789*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG6_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x46) 3790*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x47) 3791*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x48) 3792*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x49) 3793*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_TEST_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x50) 3794*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x58) 3795*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x59) 3796*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5A) 3797*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG3_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5B) 3798*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG4_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5C) 3799*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG5_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5D) 3800*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG6_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5E) 3801*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG7_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5F) 3802*3fc36ee0SWojciech Macek /******************************************************************************* 3803*3fc36ee0SWojciech Macek * masks and shifts 3804*3fc36ee0SWojciech Macek ******************************************************************************/ 3805*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RXTERM_CFG0_AC_COUPLED_MASK 0x01 3806*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RXTERM_CFG0_AC_COUPLED_SHIFT 0 3807*3fc36ee0SWojciech Macek 3808*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_LOS_COMP_EN_MASK 0x01 3809*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_LOS_COMP_EN_SHIFT 0 3810*3fc36ee0SWojciech Macek 3811*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_AGC_COMP_EN_MASK 0x02 3812*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_AGC_COMP_EN_SHIFT 1 3813*3fc36ee0SWojciech Macek 3814*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_GN_EN_MASK 0x01 3815*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_GN_EN_SHIFT 0 3816*3fc36ee0SWojciech Macek 3817*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ1_EN_MASK 0x02 3818*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ1_EN_SHIFT 1 3819*3fc36ee0SWojciech Macek 3820*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ2_EN_MASK 0x04 3821*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ2_EN_SHIFT 2 3822*3fc36ee0SWojciech Macek 3823*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ3_EN_MASK 0x08 3824*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ3_EN_SHIFT 3 3825*3fc36ee0SWojciech Macek 3826*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ4_EN_MASK 0x10 3827*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ4_EN_SHIFT 4 3828*3fc36ee0SWojciech Macek 3829*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ5_EN_MASK 0x20 3830*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ5_EN_SHIFT 5 3831*3fc36ee0SWojciech Macek 3832*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMODD_EN_MASK 0x01 3833*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMODD_EN_SHIFT 0 3834*3fc36ee0SWojciech Macek 3835*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMEVEN_EN_MASK 0x02 3836*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMEVEN_EN_SHIFT 1 3837*3fc36ee0SWojciech Macek 3838*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANODD_EN_MASK 0x04 3839*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANODD_EN_SHIFT 2 3840*3fc36ee0SWojciech Macek 3841*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANEVEN_EN_MASK 0x08 3842*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANEVEN_EN_SHIFT 3 3843*3fc36ee0SWojciech Macek 3844*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN1_EN_MASK 0x01 3845*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN1_EN_SHIFT 0 3846*3fc36ee0SWojciech Macek 3847*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN0_EN_MASK 0x02 3848*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN0_EN_SHIFT 1 3849*3fc36ee0SWojciech Macek 3850*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD1_EN_MASK 0x04 3851*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD1_EN_SHIFT 2 3852*3fc36ee0SWojciech Macek 3853*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD0_EN_MASK 0x08 3854*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD0_EN_SHIFT 3 3855*3fc36ee0SWojciech Macek 3856*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICEREVEN_EN_MASK 0x10 3857*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICEREVEN_EN_SHIFT 4 3858*3fc36ee0SWojciech Macek 3859*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICERODD_EN_MASK 0x20 3860*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICERODD_EN_SHIFT 5 3861*3fc36ee0SWojciech Macek 3862*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICEREVEN_EN_MASK 0x40 3863*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICEREVEN_EN_SHIFT 6 3864*3fc36ee0SWojciech Macek 3865*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICERODD_EN_MASK 0x80 3866*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICERODD_EN_SHIFT 7 3867*3fc36ee0SWojciech Macek 3868*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_VCO_FREQ_EN_MASK 0x01 3869*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_VCO_FREQ_EN_SHIFT 0 3870*3fc36ee0SWojciech Macek 3871*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL1_EN_MASK 0x02 3872*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL1_EN_SHIFT 1 3873*3fc36ee0SWojciech Macek 3874*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL2_EN_MASK 0x04 3875*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL2_EN_SHIFT 2 3876*3fc36ee0SWojciech Macek 3877*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL3_EN_MASK 0x08 3878*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL3_EN_SHIFT 3 3879*3fc36ee0SWojciech Macek 3880*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL_RESULT_SEL_MASK 0x30 3881*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL_RESULT_SEL_SHIFT 4 3882*3fc36ee0SWojciech Macek 3883*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_REG_EN_MASK 0x01 3884*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_REG_EN_SHIFT 0 3885*3fc36ee0SWojciech Macek 3886*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_DCD_EN_MASK 0x02 3887*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_DCD_EN_SHIFT 1 3888*3fc36ee0SWojciech Macek 3889*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TXDP_CLOCK_PHASE_EN_MASK 0x04 3890*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TXDP_CLOCK_PHASE_EN_SHIFT 2 3891*3fc36ee0SWojciech Macek 3892*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_ADAPT_CFG_EYE_MON_MASK 0x01 3893*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_ADAPT_CFG_EYE_MON_SHIFT 0 3894*3fc36ee0SWojciech Macek 3895*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_MASK 0x03 3896*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_SHIFT 0 3897*3fc36ee0SWojciech Macek 3898*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_MASK 0x0C 3899*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_SHIFT 2 3900*3fc36ee0SWojciech Macek 3901*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE0_MASK 0x30 3902*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE0_SHIFT 4 3903*3fc36ee0SWojciech Macek 3904*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE1_MASK 0xC0 3905*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE1_SHIFT 6 3906*3fc36ee0SWojciech Macek 3907*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG0_INTERVAL_7_0_MASK 0xFF 3908*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG0_INTERVAL_7_0_SHIFT 0 3909*3fc36ee0SWojciech Macek 3910*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG1_INTERVAL_15_8_MASK 0xFF 3911*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG1_INTERVAL_15_8_SHIFT 0 3912*3fc36ee0SWojciech Macek 3913*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG2_INTERVAL_23_16_MASK 0xFF 3914*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG2_INTERVAL_23_16_SHIFT 0 3915*3fc36ee0SWojciech Macek 3916*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_MASK 0x01 3917*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_SHIFT 0 3918*3fc36ee0SWojciech Macek 3919*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_EIE0_EN_MASK 0x04 3920*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_EIE0_EN_SHIFT 2 3921*3fc36ee0SWojciech Macek 3922*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_MASK 0x01 3923*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_SHIFT 0 3924*3fc36ee0SWojciech Macek 3925*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_EIE0_EN_MASK 0x04 3926*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_EIE0_EN_SHIFT 2 3927*3fc36ee0SWojciech Macek 3928*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_MASK 0x03 3929*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_SHIFT 0 3930*3fc36ee0SWojciech Macek 3931*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_MASK 0x0C 3932*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_SHIFT 2 3933*3fc36ee0SWojciech Macek 3934*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE0_SEL_MASK 0x30 3935*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE0_SEL_SHIFT 4 3936*3fc36ee0SWojciech Macek 3937*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE1_SEL_MASK 0xC0 3938*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE1_SEL_SHIFT 6 3939*3fc36ee0SWojciech Macek 3940*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_MASK 0x01 3941*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_SHIFT 0 3942*3fc36ee0SWojciech Macek 3943*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_MASK 0x02 3944*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_SHIFT 1 3945*3fc36ee0SWojciech Macek 3946*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_MASK 0x04 3947*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_SHIFT 2 3948*3fc36ee0SWojciech Macek 3949*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_MASK 0x08 3950*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_SHIFT 3 3951*3fc36ee0SWojciech Macek 3952*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_EDGE_EN_MASK 0x10 3953*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_EDGE_EN_SHIFT 4 3954*3fc36ee0SWojciech Macek 3955*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_DATA_EN_MASK 0x20 3956*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_DATA_EN_SHIFT 5 3957*3fc36ee0SWojciech Macek 3958*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_EDGE_EN_MASK 0x40 3959*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_EDGE_EN_SHIFT 6 3960*3fc36ee0SWojciech Macek 3961*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_DATA_EN_MASK 0x80 3962*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_DATA_EN_SHIFT 7 3963*3fc36ee0SWojciech Macek 3964*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_MASK 0x03 3965*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_SHIFT 0 3966*3fc36ee0SWojciech Macek 3967*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_MASK 0x0C 3968*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_SHIFT 2 3969*3fc36ee0SWojciech Macek 3970*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE0_RESULT_SEL_MASK 0x30 3971*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE0_RESULT_SEL_SHIFT 4 3972*3fc36ee0SWojciech Macek 3973*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE1_RESULT_SEL_MASK 0xC0 3974*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE1_RESULT_SEL_SHIFT 6 3975*3fc36ee0SWojciech Macek 3976*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_EDGE_EN_MASK 0x01 3977*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_EDGE_EN_SHIFT 0 3978*3fc36ee0SWojciech Macek 3979*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_DATA_EN_MASK 0x02 3980*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_DATA_EN_SHIFT 1 3981*3fc36ee0SWojciech Macek 3982*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_RESULT_SEL_MASK 0x0C 3983*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_RESULT_SEL_SHIFT 2 3984*3fc36ee0SWojciech Macek 3985*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_MASK 0x01 3986*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_SHIFT 0 3987*3fc36ee0SWojciech Macek 3988*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_MASK 0x02 3989*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_SHIFT 1 3990*3fc36ee0SWojciech Macek 3991*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE0_EN_MASK 0x04 3992*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE0_EN_SHIFT 2 3993*3fc36ee0SWojciech Macek 3994*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE1_EN_MASK 0x08 3995*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE1_EN_SHIFT 3 3996*3fc36ee0SWojciech Macek 3997*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_CONT_EN_MASK 0x10 3998*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_CONT_EN_SHIFT 4 3999*3fc36ee0SWojciech Macek 4000*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_AGCLOS_START_VAL_SEL_MASK 0x01 4001*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_AGCLOS_START_VAL_SEL_SHIFT 0 4002*3fc36ee0SWojciech Macek 4003*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_PLE_ATT_START_VAL_SEL_MASK 0x02 4004*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_PLE_ATT_START_VAL_SEL_SHIFT 1 4005*3fc36ee0SWojciech Macek 4006*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GN_APG_START_VAL_SEL_MASK 0x04 4007*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GN_APG_START_VAL_SEL_SHIFT 2 4008*3fc36ee0SWojciech Macek 4009*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_LFG_START_VAL_SEL_MASK 0x08 4010*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_LFG_START_VAL_SEL_SHIFT 3 4011*3fc36ee0SWojciech Macek 4012*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GNEQ_CCL_LFG_START_VAL_SEL_MASK 0x10 4013*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GNEQ_CCL_LFG_START_VAL_SEL_SHIFT 4 4014*3fc36ee0SWojciech Macek 4015*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_HFG_SQL_START_VAL_SEL_MASK 0x20 4016*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_HFG_SQL_START_VAL_SEL_SHIFT 5 4017*3fc36ee0SWojciech Macek 4018*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBF_START_VAL_SEL_MASK 0x40 4019*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBF_START_VAL_SEL_SHIFT 6 4020*3fc36ee0SWojciech Macek 4021*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBG_START_VAL_SEL_MASK 0x80 4022*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBG_START_VAL_SEL_SHIFT 7 4023*3fc36ee0SWojciech Macek 4024*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP1_EN_MASK 0x01 4025*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP1_EN_SHIFT 0 4026*3fc36ee0SWojciech Macek 4027*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP2_EN_MASK 0x02 4028*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP2_EN_SHIFT 1 4029*3fc36ee0SWojciech Macek 4030*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP3_EN_MASK 0x04 4031*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP3_EN_SHIFT 2 4032*3fc36ee0SWojciech Macek 4033*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP4_EN_MASK 0x08 4034*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP4_EN_SHIFT 3 4035*3fc36ee0SWojciech Macek 4036*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP5_EN_MASK 0x10 4037*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP5_EN_SHIFT 4 4038*3fc36ee0SWojciech Macek 4039*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_MASK 0x01 4040*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_SHIFT 0 4041*3fc36ee0SWojciech Macek 4042*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG0_INTERVAL_7_0_MASK 0xFF 4043*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG0_INTERVAL_7_0_SHIFT 0 4044*3fc36ee0SWojciech Macek 4045*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG1_INTERVAL_15_8_MASK 0xFF 4046*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG1_INTERVAL_15_8_SHIFT 0 4047*3fc36ee0SWojciech Macek 4048*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG2_INTERVAL_23_16_MASK 0xFF 4049*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG2_INTERVAL_23_16_SHIFT 0 4050*3fc36ee0SWojciech Macek 4051*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_MASK 0x01 4052*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_SHIFT 0 4053*3fc36ee0SWojciech Macek 4054*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_EIE_EN_MASK 0x02 4055*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_EIE_EN_SHIFT 1 4056*3fc36ee0SWojciech Macek 4057*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_CONT_EN_MASK 0x04 4058*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_CONT_EN_SHIFT 2 4059*3fc36ee0SWojciech Macek 4060*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_START_VAL_SEL_MASK 0x08 4061*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_START_VAL_SEL_SHIFT 3 4062*3fc36ee0SWojciech Macek 4063*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_MASK 0x01 4064*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_SHIFT 0 4065*3fc36ee0SWojciech Macek 4066*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_EIE_EN_MASK 0x02 4067*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_EIE_EN_SHIFT 1 4068*3fc36ee0SWojciech Macek 4069*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_CONT_EN_MASK 0x04 4070*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_CONT_EN_SHIFT 2 4071*3fc36ee0SWojciech Macek 4072*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_START_VAL_SEL_MASK 0x08 4073*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_START_VAL_SEL_SHIFT 3 4074*3fc36ee0SWojciech Macek 4075*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_MASK 0x01 4076*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_SHIFT 0 4077*3fc36ee0SWojciech Macek 4078*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_EIE_EN_MASK 0x02 4079*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_EIE_EN_SHIFT 1 4080*3fc36ee0SWojciech Macek 4081*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_CONT_EN_MASK 0x04 4082*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_CONT_EN_SHIFT 2 4083*3fc36ee0SWojciech Macek 4084*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_START_VAL_SEL_MASK 0x08 4085*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_START_VAL_SEL_SHIFT 3 4086*3fc36ee0SWojciech Macek 4087*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_MASK 0x01 4088*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_SHIFT 0 4089*3fc36ee0SWojciech Macek 4090*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_EIE_EN_MASK 0x02 4091*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_EIE_EN_SHIFT 1 4092*3fc36ee0SWojciech Macek 4093*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_CONT_EN_MASK 0x04 4094*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_CONT_EN_SHIFT 2 4095*3fc36ee0SWojciech Macek 4096*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_START_VAL_SEL_MASK 0x08 4097*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_START_VAL_SEL_SHIFT 3 4098*3fc36ee0SWojciech Macek 4099*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_MASK 0x01 4100*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_SHIFT 0 4101*3fc36ee0SWojciech Macek 4102*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_EIE_EN_MASK 0x02 4103*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_EIE_EN_SHIFT 1 4104*3fc36ee0SWojciech Macek 4105*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_CONT_EN_MASK 0x04 4106*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_CONT_EN_SHIFT 2 4107*3fc36ee0SWojciech Macek 4108*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_START_VAL_SEL_MASK 0x08 4109*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_START_VAL_SEL_SHIFT 3 4110*3fc36ee0SWojciech Macek 4111*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_EN_MASK 0x01 4112*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_EN_SHIFT 0 4113*3fc36ee0SWojciech Macek 4114*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_TIMEOUT_US_MASK 0xFE 4115*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_TIMEOUT_US_SHIFT 1 4116*3fc36ee0SWojciech Macek 4117*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG1_CDR_LOCK_WAIT_TIME_US_MASK 0xFF 4118*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG1_CDR_LOCK_WAIT_TIME_US_SHIFT 0 4119*3fc36ee0SWojciech Macek 4120*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG2_CDR_FREQ_MEASURE_EN_MASK 0x01 4121*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG2_CDR_FREQ_MEASURE_EN_SHIFT 0 4122*3fc36ee0SWojciech Macek 4123*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_RXCLKDIV_EN_MASK 0x01 4124*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_RXCLKDIV_EN_SHIFT 0 4125*3fc36ee0SWojciech Macek 4126*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_BIST_HANDSHAKE_EN_MASK 0x02 4127*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_BIST_HANDSHAKE_EN_SHIFT 1 4128*3fc36ee0SWojciech Macek 4129*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_SIG_DET_MODE_MASK 0x03 4130*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_SIG_DET_MODE_SHIFT 0 4131*3fc36ee0SWojciech Macek 4132*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_LOS_DET_MODE_MASK 0x0C 4133*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_LOS_DET_MODE_SHIFT 2 4134*3fc36ee0SWojciech Macek 4135*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG1_SIG_DET_THRESHOLD_MASK 0xFF 4136*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG1_SIG_DET_THRESHOLD_SHIFT 0 4137*3fc36ee0SWojciech Macek 4138*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG2_LOS_DET_THRESHOLD_MASK 0xFF 4139*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG2_LOS_DET_THRESHOLD_SHIFT 0 4140*3fc36ee0SWojciech Macek 4141*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG3_INTERVAL_7_0_MASK 0xFF 4142*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG3_INTERVAL_7_0_SHIFT 0 4143*3fc36ee0SWojciech Macek 4144*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG4_INTERVAL_15_8_MASK 0xFF 4145*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG4_INTERVAL_15_8_SHIFT 0 4146*3fc36ee0SWojciech Macek 4147*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG5_SAMPLE_LEN_7_0_MASK 0xFF 4148*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG5_SAMPLE_LEN_7_0_SHIFT 0 4149*3fc36ee0SWojciech Macek 4150*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG6_SAMPLE_LEN_11_8_MASK 0x0F 4151*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG6_SAMPLE_LEN_11_8_SHIFT 0 4152*3fc36ee0SWojciech Macek 4153*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_PLE_ATT_MASK 0x07 4154*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_PLE_ATT_SHIFT 0 4155*3fc36ee0SWojciech Macek 4156*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_EQ_LFG_MASK 0xF8 4157*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_EQ_LFG_SHIFT 3 4158*3fc36ee0SWojciech Macek 4159*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_GN_APG_MASK 0x03 4160*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_GN_APG_SHIFT 0 4161*3fc36ee0SWojciech Macek 4162*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_HFG_SQL_MASK 0x7C 4163*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_HFG_SQL_SHIFT 2 4164*3fc36ee0SWojciech Macek 4165*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBF_MASK 0x0F 4166*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBF_SHIFT 0 4167*3fc36ee0SWojciech Macek 4168*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBG_MASK 0xF0 4169*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBG_SHIFT 4 4170*3fc36ee0SWojciech Macek 4171*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_TEST_CFG0_LANE_MSM_DIS_MASK 0x01 4172*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_TEST_CFG0_LANE_MSM_DIS_SHIFT 0 4173*3fc36ee0SWojciech Macek 4174*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_TEST_CFG0_RX_CTRL_DIS_MASK 0x02 4175*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_TEST_CFG0_RX_CTRL_DIS_SHIFT 1 4176*3fc36ee0SWojciech Macek 4177*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG0_MASK 0xFF 4178*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG0_SHIFT 0 4179*3fc36ee0SWojciech Macek 4180*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG1_MASK 0xFF 4181*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG1_SHIFT 0 4182*3fc36ee0SWojciech Macek 4183*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG2_MASK 0xFF 4184*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG2_SHIFT 0 4185*3fc36ee0SWojciech Macek 4186*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG3_MASK 0xFF 4187*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG3_SHIFT 0 4188*3fc36ee0SWojciech Macek 4189*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG4_MASK 0xFF 4190*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG4_SHIFT 0 4191*3fc36ee0SWojciech Macek 4192*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG5_MASK 0xFF 4193*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG5_SHIFT 0 4194*3fc36ee0SWojciech Macek 4195*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG6_MASK 0xFF 4196*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG6_SHIFT 0 4197*3fc36ee0SWojciech Macek 4198*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG7_MASK 0xFF 4199*3fc36ee0SWojciech Macek #define SERDES_25G_LANE_FEATURE_SPARE_CFG7_SHIFT 0 4200*3fc36ee0SWojciech Macek 4201*3fc36ee0SWojciech Macek #ifdef _cplusplus 4202*3fc36ee0SWojciech Macek } 4203*3fc36ee0SWojciech Macek #endif 4204*3fc36ee0SWojciech Macek 4205*3fc36ee0SWojciech Macek #endif 4206