149b49cdaSZbigniew Bodek /*- 249b49cdaSZbigniew Bodek ******************************************************************************* 349b49cdaSZbigniew Bodek Copyright (C) 2015 Annapurna Labs Ltd. 449b49cdaSZbigniew Bodek 549b49cdaSZbigniew Bodek This file may be licensed under the terms of the Annapurna Labs Commercial 649b49cdaSZbigniew Bodek License Agreement. 749b49cdaSZbigniew Bodek 849b49cdaSZbigniew Bodek Alternatively, this file can be distributed under the terms of the GNU General 949b49cdaSZbigniew Bodek Public License V2 as published by the Free Software Foundation and can be 1049b49cdaSZbigniew Bodek found at http://www.gnu.org/licenses/gpl-2.0.html 1149b49cdaSZbigniew Bodek 1249b49cdaSZbigniew Bodek Alternatively, redistribution and use in source and binary forms, with or 1349b49cdaSZbigniew Bodek without modification, are permitted provided that the following conditions are 1449b49cdaSZbigniew Bodek met: 1549b49cdaSZbigniew Bodek 1649b49cdaSZbigniew Bodek * Redistributions of source code must retain the above copyright notice, 1749b49cdaSZbigniew Bodek this list of conditions and the following disclaimer. 1849b49cdaSZbigniew Bodek 1949b49cdaSZbigniew Bodek * Redistributions in binary form must reproduce the above copyright 2049b49cdaSZbigniew Bodek notice, this list of conditions and the following disclaimer in 2149b49cdaSZbigniew Bodek the documentation and/or other materials provided with the 2249b49cdaSZbigniew Bodek distribution. 2349b49cdaSZbigniew Bodek 2449b49cdaSZbigniew Bodek THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 2549b49cdaSZbigniew Bodek ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 2649b49cdaSZbigniew Bodek WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 2749b49cdaSZbigniew Bodek DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 2849b49cdaSZbigniew Bodek ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 2949b49cdaSZbigniew Bodek (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 3049b49cdaSZbigniew Bodek LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 3149b49cdaSZbigniew Bodek ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3249b49cdaSZbigniew Bodek (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 3349b49cdaSZbigniew Bodek SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3449b49cdaSZbigniew Bodek 3549b49cdaSZbigniew Bodek *******************************************************************************/ 3649b49cdaSZbigniew Bodek #ifndef __AL_SERDES_INTERNAL_REGS_H__ 3749b49cdaSZbigniew Bodek #define __AL_SERDES_INTERNAL_REGS_H__ 3849b49cdaSZbigniew Bodek 3949b49cdaSZbigniew Bodek #ifdef __cplusplus 4049b49cdaSZbigniew Bodek extern "C" { 4149b49cdaSZbigniew Bodek #endif 4249b49cdaSZbigniew Bodek 4349b49cdaSZbigniew Bodek /******************************************************************************* 4449b49cdaSZbigniew Bodek * Per lane register fields 4549b49cdaSZbigniew Bodek ******************************************************************************/ 4649b49cdaSZbigniew Bodek /* 4749b49cdaSZbigniew Bodek * RX and TX lane hard reset 4849b49cdaSZbigniew Bodek * 0 - Hard reset is asserted 4949b49cdaSZbigniew Bodek * 1 - Hard reset is de-asserted 5049b49cdaSZbigniew Bodek */ 5149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM 2 5249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_MASK 0x01 5349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_ASSERT 0x00 5449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_DEASSERT 0x01 5549b49cdaSZbigniew Bodek 5649b49cdaSZbigniew Bodek /* 5749b49cdaSZbigniew Bodek * RX and TX lane hard reset control 5849b49cdaSZbigniew Bodek * 0 - Hard reset is taken from the interface pins 5949b49cdaSZbigniew Bodek * 1 - Hard reset is taken from registers 6049b49cdaSZbigniew Bodek */ 6149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM 2 6249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_MASK 0x02 6349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_IFACE 0x00 6449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_REGS 0x02 6549b49cdaSZbigniew Bodek 6649b49cdaSZbigniew Bodek /* RX lane power state control */ 6749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM 3 6849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_MASK 0x1f 6949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_PD 0x01 7049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P2 0x02 7149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P1 0x04 7249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0S 0x08 7349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0 0x10 7449b49cdaSZbigniew Bodek 7549b49cdaSZbigniew Bodek /* TX lane power state control */ 7649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_REG_NUM 4 7749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_MASK 0x1f 7849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_PD 0x01 7949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P2 0x02 8049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P1 0x04 8149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0S 0x08 8249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0 0x10 8349b49cdaSZbigniew Bodek 8449b49cdaSZbigniew Bodek /* RX lane word width */ 8549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM 5 8649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_MASK 0x07 8749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_8 0x00 8849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_10 0x01 8949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_16 0x02 9049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_20 0x03 9149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_32 0x04 9249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_40 0x05 9349b49cdaSZbigniew Bodek 9449b49cdaSZbigniew Bodek /* TX lane word width */ 9549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_REG_NUM 5 9649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_MASK 0x70 9749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_8 0x00 9849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_10 0x10 9949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_16 0x20 10049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_20 0x30 10149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_32 0x40 10249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_40 0x50 10349b49cdaSZbigniew Bodek 10449b49cdaSZbigniew Bodek /* RX lane rate select */ 10549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM 6 10649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DIVRATE_MASK 0x07 10749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_8 0x00 10849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_4 0x01 10949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_2 0x02 11049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1 0x03 11149b49cdaSZbigniew Bodek 11249b49cdaSZbigniew Bodek /* TX lane rate select */ 11349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DIVRATE_REG_NUM 6 11449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DIVRATE_MASK 0x70 11549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_8 0x00 11649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_4 0x10 11749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_2 0x20 11849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_1 0x30 11949b49cdaSZbigniew Bodek 12049b49cdaSZbigniew Bodek /* 12149b49cdaSZbigniew Bodek * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive 12249b49cdaSZbigniew Bodek * to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed, 12349b49cdaSZbigniew Bodek * partial equalized RX signal out the transmit IO pins 12449b49cdaSZbigniew Bodek */ 12549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN_REG_NUM 7 12649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN 0x10 12749b49cdaSZbigniew Bodek 12849b49cdaSZbigniew Bodek /* 12949b49cdaSZbigniew Bodek * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial 13049b49cdaSZbigniew Bodek * transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back 13149b49cdaSZbigniew Bodek * the TX serializer output into the CDR 13249b49cdaSZbigniew Bodek */ 13349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN_REG_NUM 7 13449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN 0x20 13549b49cdaSZbigniew Bodek 13649b49cdaSZbigniew Bodek /* 13749b49cdaSZbigniew Bodek * PMA TX-to-RX I/O serial loop-back enable (loop back done directly from TX to 13849b49cdaSZbigniew Bodek * RX pads). Serial IO loopback from the transmit lane IO pins to the receive 13949b49cdaSZbigniew Bodek * lane IO pins: 0 - Disables loopback 1 - Loops back the driver IO signal to 14049b49cdaSZbigniew Bodek * the RX IO pins 14149b49cdaSZbigniew Bodek */ 14249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN_REG_NUM 7 14349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN 0x40 14449b49cdaSZbigniew Bodek 14549b49cdaSZbigniew Bodek /* 14649b49cdaSZbigniew Bodek * PMA Parallel RX-to-TX loop-back enable. Parallel loopback from the PMA 14749b49cdaSZbigniew Bodek * receive lane 20-bit data ports, to the transmit lane 20-bit data ports 0 - 14849b49cdaSZbigniew Bodek * Disables loopback 1 - Loops back the 20-bit receive data port to the 14949b49cdaSZbigniew Bodek * transmitter 15049b49cdaSZbigniew Bodek */ 15149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN_REG_NUM 7 15249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN 0x80 15349b49cdaSZbigniew Bodek 15449b49cdaSZbigniew Bodek /* 15549b49cdaSZbigniew Bodek * PMA CDR recovered-clock loopback enable; asserted when PARRX2TXTIMEDEN is 1. 15649b49cdaSZbigniew Bodek * Transmit bit clock select: 0 - Selects synthesizer bit clock for transmit 1 15749b49cdaSZbigniew Bodek * - Selects CDR clock for transmit 15849b49cdaSZbigniew Bodek */ 15949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LB_CDRCLK2TXEN_REG_NUM 7 16049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LB_CDRCLK2TXEN 0x01 16149b49cdaSZbigniew Bodek 16249b49cdaSZbigniew Bodek /* Receive lane BIST enable. Active High */ 16349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRXBIST_EN_REG_NUM 8 16449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRXBIST_EN 0x01 16549b49cdaSZbigniew Bodek 16649b49cdaSZbigniew Bodek /* TX lane BIST enable. Active High */ 16749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTXBIST_EN_REG_NUM 8 16849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTXBIST_EN 0x02 16949b49cdaSZbigniew Bodek 17049b49cdaSZbigniew Bodek /* 17149b49cdaSZbigniew Bodek * RX BIST completion signal 0 - Indicates test is not completed 1 - Indicates 17249b49cdaSZbigniew Bodek * the test has completed, and will remain high until a new test is initiated 17349b49cdaSZbigniew Bodek */ 17449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXBIST_DONE_REG_NUM 8 17549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXBIST_DONE 0x04 17649b49cdaSZbigniew Bodek 17749b49cdaSZbigniew Bodek /* 17849b49cdaSZbigniew Bodek * RX BIST error count overflow indicator. Indicates an overflow in the number 17949b49cdaSZbigniew Bodek * of byte errors identified during the course of the test. This word is stable 18049b49cdaSZbigniew Bodek * to sample when *_DONE_* signal has asserted 18149b49cdaSZbigniew Bodek */ 18249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW_REG_NUM 8 18349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW 0x08 18449b49cdaSZbigniew Bodek 18549b49cdaSZbigniew Bodek /* 18649b49cdaSZbigniew Bodek * RX BIST locked indicator 0 - Indicates BIST is not word locked and error 18749b49cdaSZbigniew Bodek * comparisons have not begun yet 1 - Indicates BIST is word locked and error 18849b49cdaSZbigniew Bodek * comparisons have begun 18949b49cdaSZbigniew Bodek */ 19049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXBIST_RXLOCKED_REG_NUM 8 19149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXBIST_RXLOCKED 0x10 19249b49cdaSZbigniew Bodek 19349b49cdaSZbigniew Bodek /* 19449b49cdaSZbigniew Bodek * RX BIST error count word. Indicates the number of byte errors identified 19549b49cdaSZbigniew Bodek * during the course of the test. This word is stable to sample when *_DONE_* 19649b49cdaSZbigniew Bodek * signal has asserted 19749b49cdaSZbigniew Bodek */ 19849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXBIST_ERRCOUNT_MSB_REG_NUM 9 19949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXBIST_ERRCOUNT_LSB_REG_NUM 10 20049b49cdaSZbigniew Bodek 20149b49cdaSZbigniew Bodek /* Tx params */ 20249b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_1_REG_NUM 21 20349b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_1_HLEV_MASK 0x7 20449b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_1_HLEV_SHIFT 0 20549b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_1_LEVN_MASK 0xf8 20649b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_1_LEVN_SHIFT 3 20749b49cdaSZbigniew Bodek 20849b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_2_REG_NUM 22 20949b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_2_LEVNM1_MASK 0xf 21049b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT 0 21149b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_2_LEVNM2_MASK 0x30 21249b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT 4 21349b49cdaSZbigniew Bodek 21449b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_3_REG_NUM 23 21549b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_3_LEVNP1_MASK 0x7 21649b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT 0 21749b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_3_SLEW_MASK 0x18 21849b49cdaSZbigniew Bodek #define SERDES_IREG_TX_DRV_3_SLEW_SHIFT 3 21949b49cdaSZbigniew Bodek 22049b49cdaSZbigniew Bodek /* Rx params */ 22149b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_1_REG_NUM 24 22249b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK 0x7 22349b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_1_DCGAIN_SHIFT 0 22449b49cdaSZbigniew Bodek /* DFE post-shaping tap 3dB frequency */ 22549b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_MASK 0x38 22649b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT 3 22749b49cdaSZbigniew Bodek 22849b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_2_REG_NUM 25 22949b49cdaSZbigniew Bodek /* DFE post-shaping tap gain */ 23049b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_MASK 0x7 23149b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_SHIFT 0 23249b49cdaSZbigniew Bodek /* DFE first tap gain control */ 23349b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_MASK 0x78 23449b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT 3 23549b49cdaSZbigniew Bodek 23649b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_3_REG_NUM 26 23749b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_MASK 0xf 23849b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_SHIFT 0 23949b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_MASK 0xf0 24049b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT 4 24149b49cdaSZbigniew Bodek 24249b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_4_REG_NUM 27 24349b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_MASK 0xf 24449b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_SHIFT 0 24549b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_MASK 0x70 24649b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT 4 24749b49cdaSZbigniew Bodek 24849b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_5_REG_NUM 28 24949b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_MASK 0x7 25049b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_SHIFT 0 25149b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_MASK 0xf8 25249b49cdaSZbigniew Bodek #define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT 3 25349b49cdaSZbigniew Bodek 25449b49cdaSZbigniew Bodek /* RX lane best eye point measurement result */ 25549b49cdaSZbigniew Bodek #define SERDES_IREG_RXEQ_BEST_EYE_MSB_VAL_REG_NUM 29 25649b49cdaSZbigniew Bodek #define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_REG_NUM 30 25749b49cdaSZbigniew Bodek #define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_MASK 0x3F 25849b49cdaSZbigniew Bodek 25949b49cdaSZbigniew Bodek /* 26049b49cdaSZbigniew Bodek * Adaptive RX Equalization enable 26149b49cdaSZbigniew Bodek * 0 - Disables adaptive RX equalization. 26249b49cdaSZbigniew Bodek * 1 - Enables adaptive RX equalization. 26349b49cdaSZbigniew Bodek */ 26449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM 31 26549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRXEQ_START (1 << 0) 26649b49cdaSZbigniew Bodek 26749b49cdaSZbigniew Bodek /* 26849b49cdaSZbigniew Bodek * Enables an eye diagram measurement 26949b49cdaSZbigniew Bodek * within the PHY. 27049b49cdaSZbigniew Bodek * 0 - Disables eye diagram measurement 27149b49cdaSZbigniew Bodek * 1 - Enables eye diagram measurement 27249b49cdaSZbigniew Bodek */ 27349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM 31 27449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START (1 << 1) 27549b49cdaSZbigniew Bodek 27649b49cdaSZbigniew Bodek 27749b49cdaSZbigniew Bodek /* 27849b49cdaSZbigniew Bodek * RX lane single roam eye point measurement start signal. 27949b49cdaSZbigniew Bodek * If asserted, single measurement at fix XADJUST and YADJUST is started. 28049b49cdaSZbigniew Bodek */ 28149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM 31 28249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START (1 << 2) 28349b49cdaSZbigniew Bodek 28449b49cdaSZbigniew Bodek 28549b49cdaSZbigniew Bodek /* 28649b49cdaSZbigniew Bodek * PHY Eye diagram measurement status 28749b49cdaSZbigniew Bodek * signal 28849b49cdaSZbigniew Bodek * 0 - Indicates eye diagram results are not 28949b49cdaSZbigniew Bodek * valid for sampling 29049b49cdaSZbigniew Bodek * 1 - Indicates eye diagram is complete and 29149b49cdaSZbigniew Bodek * results are valid for sampling 29249b49cdaSZbigniew Bodek */ 29349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM 32 29449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE (1 << 0) 29549b49cdaSZbigniew Bodek 29649b49cdaSZbigniew Bodek /* 29749b49cdaSZbigniew Bodek * Eye diagram error signal. Indicates if the 29849b49cdaSZbigniew Bodek * measurement was invalid because the eye 29949b49cdaSZbigniew Bodek * diagram was interrupted by the link entering 30049b49cdaSZbigniew Bodek * electrical idle. 30149b49cdaSZbigniew Bodek * 0 - Indicates eye diagram is valid 30249b49cdaSZbigniew Bodek * 1- Indicates an error occurred, and the eye 30349b49cdaSZbigniew Bodek * diagram measurement should be re-run 30449b49cdaSZbigniew Bodek */ 30549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR_REG_NUM 32 30649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR (1 << 1) 30749b49cdaSZbigniew Bodek 30849b49cdaSZbigniew Bodek /* 30949b49cdaSZbigniew Bodek * PHY Adaptive Equalization status 31049b49cdaSZbigniew Bodek * 0 - Indicates Adaptive Equalization results are not valid for sampling 31149b49cdaSZbigniew Bodek * 1 - Indicates Adaptive Equalization is complete and results are valid for 31249b49cdaSZbigniew Bodek * sampling 31349b49cdaSZbigniew Bodek */ 31449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM 32 31549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE (1 << 2) 31649b49cdaSZbigniew Bodek 31749b49cdaSZbigniew Bodek /* 31849b49cdaSZbigniew Bodek * 31949b49cdaSZbigniew Bodek * PHY Adaptive Equalization Status Signal 32049b49cdaSZbigniew Bodek * 0 – Indicates adaptive equalization results 32149b49cdaSZbigniew Bodek * are not valid for sampling 32249b49cdaSZbigniew Bodek * 1 – Indicates adaptive equalization is 32349b49cdaSZbigniew Bodek * complete and results are valid for sampling. 32449b49cdaSZbigniew Bodek */ 32549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_DONE_REG_NUM 32 32649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_DONE (1 << 3) 32749b49cdaSZbigniew Bodek 32849b49cdaSZbigniew Bodek 32949b49cdaSZbigniew Bodek /* 33049b49cdaSZbigniew Bodek * 7-bit eye diagram time adjust control 33149b49cdaSZbigniew Bodek * - 6-bits per UI 33249b49cdaSZbigniew Bodek * - spans 2 UI 33349b49cdaSZbigniew Bodek */ 33449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMXADJUST_REG_NUM 33 33549b49cdaSZbigniew Bodek 33649b49cdaSZbigniew Bodek /* 6-bit eye diagram voltage adjust control - spans +/-300mVdiff */ 33749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMYADJUST_REG_NUM 34 33849b49cdaSZbigniew Bodek 33949b49cdaSZbigniew Bodek /* 34049b49cdaSZbigniew Bodek * Eye diagram status signal. Safe for 34149b49cdaSZbigniew Bodek * sampling when *DONE* signal has 34249b49cdaSZbigniew Bodek * asserted 34349b49cdaSZbigniew Bodek * 14'h0000 - Completely Closed Eye 34449b49cdaSZbigniew Bodek * 14'hFFFF - Completely Open Eye 34549b49cdaSZbigniew Bodek */ 34649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM 35 34749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_MAKE 0xFF 34849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_SHIFT 0 34949b49cdaSZbigniew Bodek 35049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM 36 35149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE 0x3F 35249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_SHIFT 0 35349b49cdaSZbigniew Bodek 35449b49cdaSZbigniew Bodek /* 35549b49cdaSZbigniew Bodek * RX lane single roam eye point measurement result. 35649b49cdaSZbigniew Bodek * If 0, eye is open at current XADJUST and YADJUST settings. 35749b49cdaSZbigniew Bodek */ 35849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_MSB_REG_NUM 37 35949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_LSB_REG_NUM 38 36049b49cdaSZbigniew Bodek 36149b49cdaSZbigniew Bodek /* 36249b49cdaSZbigniew Bodek * Override enable for CDR lock to reference clock 36349b49cdaSZbigniew Bodek * 0 - CDR is always locked to reference 36449b49cdaSZbigniew Bodek * 1 - CDR operation mode (Lock2Reference or Lock2data are controlled internally 36549b49cdaSZbigniew Bodek * depending on the incoming signal and ppm status) 36649b49cdaSZbigniew Bodek */ 36749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM 39 36849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXLOCK2REF_OVREN (1 << 1) 36949b49cdaSZbigniew Bodek 37049b49cdaSZbigniew Bodek /* 37149b49cdaSZbigniew Bodek * Selects Eye to capture based on edge 37249b49cdaSZbigniew Bodek * 0 - Capture 1st Eye in Eye Diagram 37349b49cdaSZbigniew Bodek * 1 - Capture 2nd Eye in Eye Diagram measurement 37449b49cdaSZbigniew Bodek */ 37549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM 39 37649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXROAM_XORBITSEL (1 << 2) 37749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXROAM_XORBITSEL_1ST 0 37849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXROAM_XORBITSEL_2ND (1 << 2) 37949b49cdaSZbigniew Bodek 38049b49cdaSZbigniew Bodek /* 38149b49cdaSZbigniew Bodek * RX Signal detect. 0 indicates no signal, 1 indicates signal detected. 38249b49cdaSZbigniew Bodek */ 38349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXRANDET_REG_NUM 41 38449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXRANDET_STAT 0x20 38549b49cdaSZbigniew Bodek 38649b49cdaSZbigniew Bodek /* 38749b49cdaSZbigniew Bodek * RX data polarity inversion control: 38849b49cdaSZbigniew Bodek * 1'b0: no inversion 38949b49cdaSZbigniew Bodek * 1'b1: invert polarity 39049b49cdaSZbigniew Bodek */ 39149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_POLARITY_RX_REG_NUM 46 39249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_POLARITY_RX_INV (1 << 0) 39349b49cdaSZbigniew Bodek 39449b49cdaSZbigniew Bodek /* 39549b49cdaSZbigniew Bodek * TX data polarity inversion control: 39649b49cdaSZbigniew Bodek * 1'b0: no inversion 39749b49cdaSZbigniew Bodek * 1'b1: invert polarity 39849b49cdaSZbigniew Bodek */ 39949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_POLARITY_TX_REG_NUM 46 40049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_POLARITY_TX_INV (1 << 1) 40149b49cdaSZbigniew Bodek 40249b49cdaSZbigniew Bodek /* LANEPCSPSTATE* override enable (Active low) */ 40349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM 85 40449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN (1 << 0) 40549b49cdaSZbigniew Bodek 40649b49cdaSZbigniew Bodek /* LB* override enable (Active low) */ 40749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LB_LOCWREN_REG_NUM 85 40849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_LB_LOCWREN (1 << 1) 40949b49cdaSZbigniew Bodek 41049b49cdaSZbigniew Bodek /* PCSRX* override enable (Active low) */ 41149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_LOCWREN_REG_NUM 85 41249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRX_LOCWREN (1 << 4) 41349b49cdaSZbigniew Bodek 41449b49cdaSZbigniew Bodek /* PCSRXBIST* override enable (Active low) */ 41549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRXBIST_LOCWREN_REG_NUM 85 41649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRXBIST_LOCWREN (1 << 5) 41749b49cdaSZbigniew Bodek 41849b49cdaSZbigniew Bodek /* PCSRXEQ* override enable (Active low) */ 41949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM 85 42049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSRXEQ_LOCWREN (1 << 6) 42149b49cdaSZbigniew Bodek 42249b49cdaSZbigniew Bodek /* PCSTX* override enable (Active low) */ 42349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_LOCWREN_REG_NUM 85 42449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTX_LOCWREN (1 << 7) 42549b49cdaSZbigniew Bodek 42649b49cdaSZbigniew Bodek /* 42749b49cdaSZbigniew Bodek * group registers: 42849b49cdaSZbigniew Bodek * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN, 42949b49cdaSZbigniew Bodek * SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN 43049b49cdaSZbigniew Bodek * SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN 43149b49cdaSZbigniew Bodek */ 43249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM 86 43349b49cdaSZbigniew Bodek 43449b49cdaSZbigniew Bodek /* PCSTXBIST* override enable (Active low) */ 43549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM 86 43649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCSTXBIST_LOCWREN (1 << 0) 43749b49cdaSZbigniew Bodek 43849b49cdaSZbigniew Bodek /* Override RX_CALCEQ through the internal registers (Active low) */ 43949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM 86 44049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN (1 << 3) 44149b49cdaSZbigniew Bodek 44249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM 86 44349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN (1 << 4) 44449b49cdaSZbigniew Bodek 44549b49cdaSZbigniew Bodek 44649b49cdaSZbigniew Bodek /* RXCALROAMEYEMEASIN* override enable - Active Low */ 44749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM 86 44849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN (1 << 6) 44949b49cdaSZbigniew Bodek 45049b49cdaSZbigniew Bodek /* RXCALROAMXADJUST* override enable - Active Low */ 45149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM 86 45249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN (1 << 7) 45349b49cdaSZbigniew Bodek 45449b49cdaSZbigniew Bodek /* RXCALROAMYADJUST* override enable - Active Low */ 45549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM 87 45649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN (1 << 0) 45749b49cdaSZbigniew Bodek 45849b49cdaSZbigniew Bodek /* RXCDRCALFOSC* override enable. Active Low */ 45949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN_REG_NUM 87 46049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN (1 << 1) 46149b49cdaSZbigniew Bodek 46249b49cdaSZbigniew Bodek /* Over-write enable for RXEYEDIAGFSM_INITXVAL */ 46349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN_REG_NUM 87 46449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN (1 << 2) 46549b49cdaSZbigniew Bodek 46649b49cdaSZbigniew Bodek /* Over-write enable for CMNCLKGENMUXSEL_TXINTERNAL */ 46749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN_REG_NUM 87 46849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN (1 << 3) 46949b49cdaSZbigniew Bodek 47049b49cdaSZbigniew Bodek /* TXCALTCLKDUTY* override enable. Active Low */ 47149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN_REG_NUM 87 47249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN (1 << 4) 47349b49cdaSZbigniew Bodek 47449b49cdaSZbigniew Bodek /* Override TX_DRV through the internal registers (Active low) */ 47549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM 87 47649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN (1 << 5) 47749b49cdaSZbigniew Bodek 47849b49cdaSZbigniew Bodek /******************************************************************************* 47949b49cdaSZbigniew Bodek * Common lane register fields - PMA 48049b49cdaSZbigniew Bodek ******************************************************************************/ 48149b49cdaSZbigniew Bodek /* 48249b49cdaSZbigniew Bodek * Common lane hard reset control 48349b49cdaSZbigniew Bodek * 0 - Hard reset is taken from the interface pins 48449b49cdaSZbigniew Bodek * 1 - Hard reset is taken from registers 48549b49cdaSZbigniew Bodek */ 48649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM 2 48749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_MASK 0x01 48849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_IFACE 0x00 48949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_REGS 0x01 49049b49cdaSZbigniew Bodek 49149b49cdaSZbigniew Bodek /* 49249b49cdaSZbigniew Bodek * Common lane hard reset 49349b49cdaSZbigniew Bodek * 0 - Hard reset is asserted 49449b49cdaSZbigniew Bodek * 1 - Hard reset is de-asserted 49549b49cdaSZbigniew Bodek */ 49649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM 2 49749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_MASK 0x02 49849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_ASSERT 0x00 49949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_DEASSERT 0x02 50049b49cdaSZbigniew Bodek 50149b49cdaSZbigniew Bodek /* Synth power state control */ 50249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM 3 50349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_MASK 0x1f 50449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_PD 0x01 50549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P2 0x02 50649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P1 0x04 50749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0S 0x08 50849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0 0x10 50949b49cdaSZbigniew Bodek 51049b49cdaSZbigniew Bodek /* Transmit datapath FIFO enable (Active High) */ 51149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCS_TXENABLE_REG_NUM 8 51249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCS_TXENABLE (1 << 2) 51349b49cdaSZbigniew Bodek 51449b49cdaSZbigniew Bodek /* 51549b49cdaSZbigniew Bodek * RX lost of signal detector enable 51649b49cdaSZbigniew Bodek * - 0 - disable 51749b49cdaSZbigniew Bodek * - 1 - enable 51849b49cdaSZbigniew Bodek */ 51949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXLOSDET_ENABLE_REG_NUM 13 52049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXLOSDET_ENABLE AL_BIT(4) 52149b49cdaSZbigniew Bodek 52249b49cdaSZbigniew Bodek /* Signal Detect Threshold Level */ 52349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_REG_NUM 15 52449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_MASK AL_FIELD_MASK(2, 0) 52549b49cdaSZbigniew Bodek 52649b49cdaSZbigniew Bodek /* LOS Detect Threshold Level */ 52749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXLOSDET_THRESH_REG_NUM 15 52849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXLOSDET_THRESH_MASK AL_FIELD_MASK(4, 3) 52949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXLOSDET_THRESH_SHIFT 3 53049b49cdaSZbigniew Bodek 53149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_REG_NUM 30 53249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_MASK 0x7f 53349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_SHIFT 0 53449b49cdaSZbigniew Bodek 53549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_REG_NUM 31 53649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_MASK 0x7f 53749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_SHIFT 0 53849b49cdaSZbigniew Bodek 53949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_REG_NUM 32 54049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_MASK 0xff 54149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_SHIFT 0 54249b49cdaSZbigniew Bodek 54349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_REG_NUM 33 54449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_MASK 0x1 54549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_SHIFT 0 54649b49cdaSZbigniew Bodek 54749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_COARSE_STEP_REG_NUM 33 54849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_COARSE_STEP_MASK 0x3e 54949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_COARSE_STEP_SHIFT 1 55049b49cdaSZbigniew Bodek 55149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_REG_NUM 34 55249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_MASK 0xff 55349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_SHIFT 0 55449b49cdaSZbigniew Bodek 55549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_REG_NUM 35 55649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_MASK 0x1 55749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_SHIFT 0 55849b49cdaSZbigniew Bodek 55949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_FINE_STEP_REG_NUM 35 56049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_FINE_STEP_MASK 0x3e 56149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_FINE_STEP_SHIFT 1 56249b49cdaSZbigniew Bodek 56349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_REG_NUM 36 56449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_MASK 0xff 56549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_SHIFT 0 56649b49cdaSZbigniew Bodek 56749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_REG_NUM 37 56849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_MASK 0x7 56949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_SHIFT 0 57049b49cdaSZbigniew Bodek 57149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_REG_NUM 43 57249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_MASK 0x7 57349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_SHIFT 0 57449b49cdaSZbigniew Bodek 57549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_TX_BIST_PAT_REG_NUM(byte_num) (56 + (byte_num)) 57649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_TX_BIST_PAT_NUM_BYTES 10 57749b49cdaSZbigniew Bodek 57849b49cdaSZbigniew Bodek /* 57949b49cdaSZbigniew Bodek * Selects the transmit BIST mode: 58049b49cdaSZbigniew Bodek * 0 - Uses the 80-bit internal memory pattern (w/ OOB) 58149b49cdaSZbigniew Bodek * 1 - Uses a 27 PRBS pattern 58249b49cdaSZbigniew Bodek * 2 - Uses a 223 PRBS pattern 58349b49cdaSZbigniew Bodek * 3 - Uses a 231 PRBS pattern 58449b49cdaSZbigniew Bodek * 4 - Uses a 1010 clock pattern 58549b49cdaSZbigniew Bodek * 5 and above - Reserved 58649b49cdaSZbigniew Bodek */ 58749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_REG_NUM 80 58849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_MASK 0x07 58949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_USER 0x00 59049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS7 0x01 59149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS23 0x02 59249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS31 0x03 59349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_CLK1010 0x04 59449b49cdaSZbigniew Bodek 59549b49cdaSZbigniew Bodek /* Single-Bit error injection enable (on posedge) */ 59649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM 80 59749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_TXBIST_BITERROR_EN 0x20 59849b49cdaSZbigniew Bodek 59949b49cdaSZbigniew Bodek /* CMNPCIEGEN3* override enable (Active Low) */ 60049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM 95 60149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN (1 << 2) 60249b49cdaSZbigniew Bodek 60349b49cdaSZbigniew Bodek /* CMNPCS* override enable (Active Low) */ 60449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCS_LOCWREN_REG_NUM 95 60549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCS_LOCWREN (1 << 3) 60649b49cdaSZbigniew Bodek 60749b49cdaSZbigniew Bodek /* CMNPCSBIST* override enable (Active Low) */ 60849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN_REG_NUM 95 60949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN (1 << 4) 61049b49cdaSZbigniew Bodek 61149b49cdaSZbigniew Bodek /* CMNPCSPSTATE* override enable (Active Low) */ 61249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN_REG_NUM 95 61349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN (1 << 5) 61449b49cdaSZbigniew Bodek 61549b49cdaSZbigniew Bodek /* PCS_EN* override enable (Active Low) */ 61649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_LOCWREN_REG_NUM 96 61749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_LOCWREN (1 << 3) 61849b49cdaSZbigniew Bodek 61949b49cdaSZbigniew Bodek /* Eye diagram sample count */ 62049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM 150 62149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_MASK 0xff 62249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_SHIFT 0 62349b49cdaSZbigniew Bodek 62449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM 151 62549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_MASK 0xff 62649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_SHIFT 0 62749b49cdaSZbigniew Bodek 62849b49cdaSZbigniew Bodek /* override control */ 62949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM 230 63049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN 1 << 0 63149b49cdaSZbigniew Bodek 63249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_REG_NUM 623 63349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_MASK 0xff 63449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_SHIFT 0 63549b49cdaSZbigniew Bodek 63649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_REG_NUM 624 63749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_MASK 0xff 63849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_SHIFT 0 63949b49cdaSZbigniew Bodek 64049b49cdaSZbigniew Bodek /* X and Y coefficient return value */ 64149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM 626 64249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_MASK 0x0F 64349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_SHIFT 0 64449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_MASK 0xF0 64549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_SHIFT 4 64649b49cdaSZbigniew Bodek 64749b49cdaSZbigniew Bodek /* X coarse scan step */ 64849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM 627 64949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_MASK 0x7F 65049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_SHIFT 0 65149b49cdaSZbigniew Bodek 65249b49cdaSZbigniew Bodek /* X fine scan step */ 65349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM 628 65449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_MASK 0x7F 65549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_SHIFT 0 65649b49cdaSZbigniew Bodek 65749b49cdaSZbigniew Bodek /* Y coarse scan step */ 65849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM 629 65949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_MASK 0x0F 66049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_SHIFT 0 66149b49cdaSZbigniew Bodek 66249b49cdaSZbigniew Bodek /* Y fine scan step */ 66349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM 630 66449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_MASK 0x0F 66549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_SHIFT 0 66649b49cdaSZbigniew Bodek 66749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PPMDRIFTCOUNT1_REG_NUM 157 66849b49cdaSZbigniew Bodek 66949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PPMDRIFTCOUNT2_REG_NUM 158 67049b49cdaSZbigniew Bodek 67149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PPMDRIFTMAX1_REG_NUM 159 67249b49cdaSZbigniew Bodek 67349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PPMDRIFTMAX2_REG_NUM 160 67449b49cdaSZbigniew Bodek 67549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX1_REG_NUM 163 67649b49cdaSZbigniew Bodek 67749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX2_REG_NUM 164 67849b49cdaSZbigniew Bodek 67949b49cdaSZbigniew Bodek /******************************************************************************* 68049b49cdaSZbigniew Bodek * Common lane register fields - PCS 68149b49cdaSZbigniew Bodek ******************************************************************************/ 68249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM 3 68349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK AL_FIELD_MASK(5, 4) 68449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_SHIFT 4 68549b49cdaSZbigniew Bodek 68649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM 6 68749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA AL_BIT(2) 68849b49cdaSZbigniew Bodek 68949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_NUM 18 69049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_MASK 0x1F 69149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_SHIFT 0 69249b49cdaSZbigniew Bodek 69349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_NUM 19 69449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_MASK 0x7C 69549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_SHIFT 2 69649b49cdaSZbigniew Bodek 69749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_NUM 20 69849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_MASK 0x1F 69949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_SHIFT 0 70049b49cdaSZbigniew Bodek 70149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_NUM 21 70249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_MASK 0x7C 70349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_SHIFT 2 70449b49cdaSZbigniew Bodek 70549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_REG_NUM 22 70649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_MASK 0x7f 70749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_SHIFT 0 70849b49cdaSZbigniew Bodek 70949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_REG_NUM 34 71049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_MASK 0x7f 71149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_SHIFT 0 71249b49cdaSZbigniew Bodek 71349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_REG_NUM 23 71449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_MASK 0xff 71549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_SHIFT 0 71649b49cdaSZbigniew Bodek 71749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_REG_NUM 22 71849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_MASK 0x80 71949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_SHIFT 7 72049b49cdaSZbigniew Bodek 72149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_REG_NUM 24 72249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_MASK 0x3e 72349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_SHIFT 1 72449b49cdaSZbigniew Bodek 72549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_REG_NUM 35 72649b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_MASK 0xff 72749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_SHIFT 0 72849b49cdaSZbigniew Bodek 72949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_REG_NUM 34 73049b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_MASK 0x80 73149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_SHIFT 7 73249b49cdaSZbigniew Bodek 73349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_REG_NUM 36 73449b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_MASK 0x1f 73549b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_SHIFT 0 73649b49cdaSZbigniew Bodek 73749b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_REG_NUM 37 73849b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_MASK 0xff 73949b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_SHIFT 0 74049b49cdaSZbigniew Bodek 74149b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_REG_NUM 36 74249b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_MASK 0xe0 74349b49cdaSZbigniew Bodek #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_SHIFT 5 74449b49cdaSZbigniew Bodek 74549b49cdaSZbigniew Bodek #ifdef __cplusplus 74649b49cdaSZbigniew Bodek } 74749b49cdaSZbigniew Bodek #endif 74849b49cdaSZbigniew Bodek 74949b49cdaSZbigniew Bodek #endif /* __AL_serdes_REG_H */ 75049b49cdaSZbigniew Bodek 751