1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "opt_ah.h" 18 19 #include "ah.h" 20 #include "ah_desc.h" 21 #include "ah_internal.h" 22 23 #include "ar9300/ar9300desc.h" 24 #include "ar9300/ar9300.h" 25 #include "ar9300/ar9300reg.h" 26 #include "ar9300/ar9300phy.h" 27 #include "ah_devid.h" 28 29 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 30 static void ar9300_swap_tx_desc(void *ds); 31 #endif 32 33 void 34 ar9300_tx_req_intr_desc(struct ath_hal *ah, void *ds) 35 { 36 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, 37 "%s:Desc Interrupt not supported\n", __func__); 38 } 39 40 static inline u_int16_t 41 ar9300_calc_ptr_chk_sum(struct ar9300_txc *ads) 42 { 43 u_int checksum; 44 u_int16_t ptrchecksum; 45 46 /* checksum = __bswap32(ads->ds_info) + ads->ds_link */ 47 checksum = ads->ds_info + ads->ds_link 48 + ads->ds_data0 + ads->ds_ctl3 49 + ads->ds_data1 + ads->ds_ctl5 50 + ads->ds_data2 + ads->ds_ctl7 51 + ads->ds_data3 + ads->ds_ctl9; 52 53 ptrchecksum = ((checksum & 0xffff) + (checksum >> 16)) & AR_tx_ptr_chk_sum; 54 return ptrchecksum; 55 } 56 57 HAL_BOOL 58 ar9300_fill_tx_desc( 59 struct ath_hal *ah, 60 void *ds, 61 HAL_DMA_ADDR *buf_addr, 62 u_int32_t *seg_len, 63 u_int desc_id, 64 u_int qcu, 65 HAL_KEY_TYPE key_type, 66 HAL_BOOL first_seg, 67 HAL_BOOL last_seg, 68 const void *ds0) 69 { 70 struct ar9300_txc *ads = AR9300TXC(ds); 71 short desclen; 72 73 /* Fill TXC info field */ 74 desclen = (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) ? 0x18 : 0x17; 75 ads->ds_info = TXC_INFO(qcu, desclen); 76 77 /* Set the buffer addresses */ 78 ads->ds_data0 = buf_addr[0]; 79 ads->ds_data1 = buf_addr[1]; 80 ads->ds_data2 = buf_addr[2]; 81 ads->ds_data3 = buf_addr[3]; 82 83 /* Set the buffer lengths */ 84 ads->ds_ctl3 = (seg_len[0] << AR_buf_len_S) & AR_buf_len; 85 ads->ds_ctl5 = (seg_len[1] << AR_buf_len_S) & AR_buf_len; 86 ads->ds_ctl7 = (seg_len[2] << AR_buf_len_S) & AR_buf_len; 87 ads->ds_ctl9 = (seg_len[3] << AR_buf_len_S) & AR_buf_len; 88 89 /* Fill in pointer checksum and descriptor id */ 90 ads->ds_ctl10 = (desc_id << AR_tx_desc_id_S) | ar9300_calc_ptr_chk_sum(ads); 91 92 if (first_seg) { 93 /* 94 * First descriptor, don't clobber xmit control data 95 * setup by ar9300_set_11n_tx_desc. 96 * 97 * Note: AR_encr_type is already setup in the first descriptor by 98 * set_11n_tx_desc(). 99 */ 100 ads->ds_ctl12 |= (last_seg ? 0 : AR_tx_more); 101 } else if (last_seg) { /* !first_seg && last_seg */ 102 /* 103 * Last descriptor in a multi-descriptor frame, 104 * copy the multi-rate transmit parameters from 105 * the first frame for processing on completion. 106 */ 107 ads->ds_ctl11 = 0; 108 ads->ds_ctl12 = 0; 109 #ifdef AH_NEED_DESC_SWAP 110 ads->ds_ctl13 = __bswap32(AR9300TXC_CONST(ds0)->ds_ctl13); 111 ads->ds_ctl14 = __bswap32(AR9300TXC_CONST(ds0)->ds_ctl14); 112 ads->ds_ctl17 = __bswap32(SM(key_type, AR_encr_type)); 113 #else 114 ads->ds_ctl13 = AR9300TXC_CONST(ds0)->ds_ctl13; 115 ads->ds_ctl14 = AR9300TXC_CONST(ds0)->ds_ctl14; 116 ads->ds_ctl17 = SM(key_type, AR_encr_type); 117 #endif 118 } else { /* !first_seg && !last_seg */ 119 /* 120 * XXX Intermediate descriptor in a multi-descriptor frame. 121 */ 122 ads->ds_ctl11 = 0; 123 ads->ds_ctl12 = AR_tx_more; 124 ads->ds_ctl13 = 0; 125 ads->ds_ctl14 = 0; 126 ads->ds_ctl17 = SM(key_type, AR_encr_type); 127 } 128 129 /* Only relevant for Jupiter/Aphrodite */ 130 ads->ds_ctl23 = 0; 131 132 return AH_TRUE; 133 } 134 135 void 136 ar9300_set_desc_link(struct ath_hal *ah, void *ds, u_int32_t link) 137 { 138 struct ar9300_txc *ads = AR9300TXC(ds); 139 140 ads->ds_link = link; 141 142 /* TODO - checksum is calculated twice for subframes 143 * Once in filldesc and again when linked. Need to fix. 144 */ 145 /* Fill in pointer checksum. Preserve descriptor id */ 146 ads->ds_ctl10 &= ~AR_tx_ptr_chk_sum; 147 ads->ds_ctl10 |= ar9300_calc_ptr_chk_sum(ads); 148 } 149 150 void 151 ar9300_get_desc_link_ptr(struct ath_hal *ah, void *ds, u_int32_t **link) 152 { 153 struct ar9300_txc *ads = AR9300TXC(ds); 154 155 *link = &ads->ds_link; 156 } 157 158 void 159 ar9300_clear_tx_desc_status(struct ath_hal *ah, void *ds) 160 { 161 struct ar9300_txs *ads = AR9300TXS(ds); 162 ads->status1 = ads->status2 = 0; 163 ads->status3 = ads->status4 = 0; 164 ads->status5 = ads->status6 = 0; 165 ads->status7 = ads->status8 = 0; 166 } 167 168 #ifdef ATH_SWRETRY 169 void 170 ar9300_clear_dest_mask(struct ath_hal *ah, void *ds) 171 { 172 struct ar9300_txc *ads = AR9300TXC(ds); 173 ads->ds_ctl11 |= AR_clr_dest_mask; 174 } 175 #endif 176 177 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 178 /* XXX what words need swapping */ 179 /* Swap transmit descriptor */ 180 static __inline void 181 ar9300_swap_tx_desc(void *dsp) 182 { 183 struct ar9300_txs *ds = (struct ar9300_txs *)dsp; 184 185 ds->ds_info = __bswap32(ds->ds_info); 186 ds->status1 = __bswap32(ds->status1); 187 ds->status2 = __bswap32(ds->status2); 188 ds->status3 = __bswap32(ds->status3); 189 ds->status4 = __bswap32(ds->status4); 190 ds->status5 = __bswap32(ds->status5); 191 ds->status6 = __bswap32(ds->status6); 192 ds->status7 = __bswap32(ds->status7); 193 ds->status8 = __bswap32(ds->status8); 194 } 195 #endif 196 197 198 /* 199 * Extract the transmit rate code. 200 */ 201 void 202 ar9300_get_tx_rate_code(struct ath_hal *ah, void *ds, struct ath_tx_status *ts) 203 { 204 struct ar9300_txc *ads = AR9300TXC(ds); 205 206 switch (ts->ts_finaltsi) { 207 case 0: 208 ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate0); 209 break; 210 case 1: 211 ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate1); 212 break; 213 case 2: 214 ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate2); 215 break; 216 case 3: 217 ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate3); 218 break; 219 } 220 221 ar9300_set_selfgenrate_limit(ah, ts->ts_rate); 222 } 223 224 /* 225 * Get TX Status descriptor contents. 226 */ 227 void 228 ar9300_get_raw_tx_desc(struct ath_hal *ah, u_int32_t *txstatus) 229 { 230 struct ath_hal_9300 *ahp = AH9300(ah); 231 struct ar9300_txs *ads; 232 233 ads = &ahp->ts_ring[ahp->ts_tail]; 234 235 OS_MEMCPY(txstatus, ads, sizeof(struct ar9300_txs)); 236 } 237 238 /* 239 * Processing of HW TX descriptor. 240 */ 241 HAL_STATUS 242 ar9300_proc_tx_desc(struct ath_hal *ah, void *txstatus) 243 { 244 struct ath_hal_9300 *ahp = AH9300(ah); 245 struct ar9300_txs *ads; 246 struct ath_tx_status *ts = (struct ath_tx_status *)txstatus; 247 u_int32_t dsinfo; 248 249 ads = &ahp->ts_ring[ahp->ts_tail]; 250 251 if ((ads->status8 & AR_tx_done) == 0) { 252 return HAL_EINPROGRESS; 253 } 254 255 /* 256 * Sanity check 257 */ 258 259 #if 0 260 ath_hal_printf(ah, 261 "CHH: tail=%d\n", ahp->ts_tail); 262 ath_hal_printf(ah, 263 "CHH: ds_info 0x%x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 264 ads->ds_info, 265 ads->status1, 266 ads->status2, 267 ads->status3, 268 ads->status4, 269 ads->status5, 270 ads->status6, 271 ads->status7, 272 ads->status8); 273 #endif 274 275 276 /* Increment the tail to point to the next status element. */ 277 ahp->ts_tail = (ahp->ts_tail + 1) & (ahp->ts_size-1); 278 279 /* 280 ** For big endian systems, ds_info is not swapped as the other 281 ** registers are. Ensure we use the bswap32 version (which is 282 ** defined to "nothing" in little endian systems 283 */ 284 285 dsinfo = ads->ds_info; 286 287 if ((MS(dsinfo, AR_desc_id) != ATHEROS_VENDOR_ID) || 288 (MS(dsinfo, AR_tx_rx_desc) != 1)) 289 { 290 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "%s: Tx Descriptor error %x\n", 291 __func__, dsinfo); 292 HALASSERT(0); 293 /* Zero out the status for reuse */ 294 OS_MEMZERO(ads, sizeof(struct ar9300_txs)); 295 return HAL_EIO; 296 } 297 298 /* Update software copies of the HW status */ 299 ts->ts_queue_id = MS(dsinfo, AR_tx_qcu_num); 300 ts->ts_desc_id = MS(ads->status1, AR_tx_desc_id); 301 ts->ts_seqnum = MS(ads->status8, AR_seq_num); 302 ts->ts_tstamp = ads->status4; 303 ts->ts_status = 0; 304 ts->ts_flags = 0; 305 306 if (ads->status3 & AR_excessive_retries) { 307 ts->ts_status |= HAL_TXERR_XRETRY; 308 } 309 if (ads->status3 & AR_filtered) { 310 ts->ts_status |= HAL_TXERR_FILT; 311 } 312 if (ads->status3 & AR_fifounderrun) { 313 ts->ts_status |= HAL_TXERR_FIFO; 314 ar9300_update_tx_trig_level(ah, AH_TRUE); 315 } 316 if (ads->status8 & AR_tx_op_exceeded) { 317 ts->ts_status |= HAL_TXERR_XTXOP; 318 } 319 if (ads->status3 & AR_tx_timer_expired) { 320 ts->ts_status |= HAL_TXERR_TIMER_EXPIRED; 321 } 322 if (ads->status3 & AR_desc_cfg_err) { 323 ts->ts_flags |= HAL_TX_DESC_CFG_ERR; 324 } 325 if (ads->status3 & AR_tx_data_underrun) { 326 ts->ts_flags |= HAL_TX_DATA_UNDERRUN; 327 ar9300_update_tx_trig_level(ah, AH_TRUE); 328 } 329 if (ads->status3 & AR_tx_delim_underrun) { 330 ts->ts_flags |= HAL_TX_DELIM_UNDERRUN; 331 ar9300_update_tx_trig_level(ah, AH_TRUE); 332 } 333 if (ads->status2 & AR_tx_ba_status) { 334 ts->ts_flags |= HAL_TX_BA; 335 ts->ts_ba_low = ads->status5; 336 ts->ts_ba_high = ads->status6; 337 } 338 if (ads->status8 & AR_tx_fast_ts) { 339 ts->ts_flags |= HAL_TX_FAST_TS; 340 } 341 342 /* 343 * Extract the transmit rate. 344 */ 345 ts->ts_finaltsi = MS(ads->status8, AR_final_tx_idx); 346 347 ts->ts_rssi = MS(ads->status7, AR_tx_rssi_combined); 348 ts->ts_rssi_ctl[0] = MS(ads->status2, AR_tx_rssi_ant00); 349 ts->ts_rssi_ctl[1] = MS(ads->status2, AR_tx_rssi_ant01); 350 ts->ts_rssi_ctl[2] = MS(ads->status2, AR_tx_rssi_ant02); 351 ts->ts_rssi_ext[0] = MS(ads->status7, AR_tx_rssi_ant10); 352 ts->ts_rssi_ext[1] = MS(ads->status7, AR_tx_rssi_ant11); 353 ts->ts_rssi_ext[2] = MS(ads->status7, AR_tx_rssi_ant12); 354 ts->ts_shortretry = MS(ads->status3, AR_rts_fail_cnt); 355 ts->ts_longretry = MS(ads->status3, AR_data_fail_cnt); 356 ts->ts_virtcol = MS(ads->status3, AR_virt_retry_cnt); 357 ts->ts_antenna = 0; 358 359 /* extract TID from block ack */ 360 ts->ts_tid = MS(ads->status8, AR_tx_tid); 361 362 /* Zero out the status for reuse */ 363 OS_MEMZERO(ads, sizeof(struct ar9300_txs)); 364 365 return HAL_OK; 366 } 367 368 /* 369 * Calculate air time of a transmit packet 370 * if comp_wastedt is 1, calculate air time only for failed subframes 371 * this is required for VOW_DCS ( dynamic channel selection ) 372 */ 373 u_int32_t 374 ar9300_calc_tx_airtime(struct ath_hal *ah, void *ds, struct ath_tx_status *ts, 375 HAL_BOOL comp_wastedt, u_int8_t nbad, u_int8_t nframes ) 376 { 377 struct ar9300_txc *ads = AR9300TXC(ds); 378 int finalindex_tries; 379 u_int32_t airtime, lastrate_dur; 380 381 382 /* 383 * Number of attempts made on the final index 384 * Note: If no BA was recv, then the data_fail_cnt is the number of tries 385 * made on the final index. If BA was recv, then add 1 to account for the 386 * successful attempt. 387 */ 388 if ( !comp_wastedt ){ 389 finalindex_tries = ts->ts_longretry + (ts->ts_flags & HAL_TX_BA)? 1 : 0; 390 } else { 391 finalindex_tries = ts->ts_longretry ; 392 } 393 394 /* 395 * Calculate time of transmit on air for packet including retries 396 * at different rates. 397 */ 398 switch (ts->ts_finaltsi) { 399 case 0: 400 lastrate_dur = MS(ads->ds_ctl15, AR_packet_dur0); 401 airtime = (lastrate_dur * finalindex_tries); 402 break; 403 case 1: 404 lastrate_dur = MS(ads->ds_ctl15, AR_packet_dur1); 405 airtime = (lastrate_dur * finalindex_tries) + 406 (MS(ads->ds_ctl13, AR_xmit_data_tries0) * 407 MS(ads->ds_ctl15, AR_packet_dur0)); 408 break; 409 case 2: 410 lastrate_dur = MS(ads->ds_ctl16, AR_packet_dur2); 411 airtime = (lastrate_dur * finalindex_tries) + 412 (MS(ads->ds_ctl13, AR_xmit_data_tries1) * 413 MS(ads->ds_ctl15, AR_packet_dur1)) + 414 (MS(ads->ds_ctl13, AR_xmit_data_tries0) * 415 MS(ads->ds_ctl15, AR_packet_dur0)); 416 break; 417 case 3: 418 lastrate_dur = MS(ads->ds_ctl16, AR_packet_dur3); 419 airtime = (lastrate_dur * finalindex_tries) + 420 (MS(ads->ds_ctl13, AR_xmit_data_tries2) * 421 MS(ads->ds_ctl16, AR_packet_dur2)) + 422 (MS(ads->ds_ctl13, AR_xmit_data_tries1) * 423 MS(ads->ds_ctl15, AR_packet_dur1)) + 424 (MS(ads->ds_ctl13, AR_xmit_data_tries0) * 425 MS(ads->ds_ctl15, AR_packet_dur0)); 426 break; 427 default: 428 HALASSERT(0); 429 return 0; 430 } 431 432 if ( comp_wastedt && (ts->ts_flags & HAL_TX_BA)){ 433 airtime += nbad?((lastrate_dur*nbad) / nframes):0; 434 } 435 return airtime; 436 437 } 438 439 #ifdef AH_PRIVATE_DIAG 440 void 441 ar9300__cont_tx_mode(struct ath_hal *ah, void *ds, int mode) 442 { 443 #if 0 444 static int qnum = 0; 445 int i; 446 unsigned int qbits, val, val1, val2; 447 int prefetch; 448 struct ar9300_txs *ads = AR9300TXS(ds); 449 450 if (mode == 10) { 451 return; 452 } 453 454 if (mode == 7) { /* print status from the cont tx desc */ 455 if (ads) { 456 val1 = ads->ds_txstatus1; 457 val2 = ads->ds_txstatus2; 458 HALDEBUG(ah, HAL_DEBUG_TXDESC, "s0(%x) s1(%x)\n", 459 (unsigned)val1, (unsigned)val2); 460 } 461 HALDEBUG(ah, HAL_DEBUG_TXDESC, "txe(%x) txd(%x)\n", 462 OS_REG_READ(ah, AR_Q_TXE), 463 OS_REG_READ(ah, AR_Q_TXD) 464 ); 465 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 466 val = OS_REG_READ(ah, AR_QTXDP(i)); 467 val2 = OS_REG_READ(ah, AR_QSTS(i)) & AR_Q_STS_PEND_FR_CNT; 468 HALDEBUG(ah, HAL_DEBUG_TXDESC, "[%d] %x %d\n", i, val, val2); 469 } 470 return; 471 } 472 if (mode == 8) { /* set TXE for qnum */ 473 OS_REG_WRITE(ah, AR_Q_TXE, 1 << qnum); 474 return; 475 } 476 if (mode == 9) { 477 prefetch = (int)ds; 478 return; 479 } 480 481 if (mode >= 1) { /* initiate cont tx operation */ 482 /* Disable AGC to A2 */ 483 qnum = (int) ds; 484 485 OS_REG_WRITE(ah, AR_PHY_TEST, 486 (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) ); 487 488 OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000); 489 OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe); 490 OS_REG_WRITE(ah, AR_DIAG_SW, 491 (OS_REG_READ(ah, AR_DIAG_SW) | 492 (AR_DIAG_FORCE_RX_CLEAR + AR_DIAG_IGNORE_VIRT_CS)) ); 493 494 495 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ 496 497 if (mode == 3 || mode == 4) { 498 int txcfg; 499 500 if (mode == 3) { 501 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 502 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 503 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 100); 504 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 100); 505 OS_REG_WRITE(ah, AR_TIME_OUT, 2); 506 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 100); 507 } 508 509 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 510 /* enable prefetch on qnum */ 511 OS_REG_WRITE(ah, AR_D_FPCTL, 0x10 | qnum); 512 txcfg = 5 | (6 << AR_FTRIG_S); 513 OS_REG_WRITE(ah, AR_TXCFG, txcfg); 514 515 OS_REG_WRITE(ah, AR_QMISC(qnum), /* set QCU modes */ 516 AR_Q_MISC_DCU_EARLY_TERM_REQ 517 + AR_Q_MISC_FSP_ASAP 518 + AR_Q_MISC_CBR_INCR_DIS1 519 + AR_Q_MISC_CBR_INCR_DIS0 520 ); 521 522 /* stop tx dma all all except qnum */ 523 qbits = 0x3ff; 524 qbits &= ~(1 << qnum); 525 for (i = 0; i < 10; i++) { 526 if (i == qnum) { 527 continue; 528 } 529 OS_REG_WRITE(ah, AR_Q_TXD, 1 << i); 530 } 531 532 OS_REG_WRITE(ah, AR_Q_TXD, qbits); 533 534 /* clear and freeze MIB counters */ 535 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); 536 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); 537 538 OS_REG_WRITE(ah, AR_DMISC(qnum), 539 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 540 AR_D_MISC_ARB_LOCKOUT_CNTRL_S) 541 + (AR_D_MISC_ARB_LOCKOUT_IGNORE) 542 + (AR_D_MISC_POST_FR_BKOFF_DIS) 543 + (AR_D_MISC_VIR_COL_HANDLING_IGNORE << 544 AR_D_MISC_VIR_COL_HANDLING_S)); 545 546 for (i = 0; i < HAL_NUM_TX_QUEUES + 2; i++) { /* disconnect QCUs */ 547 if (i == qnum) { 548 continue; 549 } 550 OS_REG_WRITE(ah, AR_DQCUMASK(i), 0); 551 } 552 } 553 } 554 if (mode == 0) { 555 OS_REG_WRITE(ah, AR_PHY_TEST, 556 (OS_REG_READ(ah, AR_PHY_TEST) & ~PHY_AGC_CLR)); 557 OS_REG_WRITE(ah, AR_DIAG_SW, 558 (OS_REG_READ(ah, AR_DIAG_SW) & 559 ~(AR_DIAG_FORCE_RX_CLEAR + AR_DIAG_IGNORE_VIRT_CS))); 560 } 561 #endif 562 } 563 #endif 564 565 void 566 ar9300_set_paprd_tx_desc(struct ath_hal *ah, void *ds, int chain_num) 567 { 568 struct ar9300_txc *ads = AR9300TXC(ds); 569 570 ads->ds_ctl12 |= SM((1 << chain_num), AR_paprd_chain_mask); 571 } 572 HAL_STATUS 573 ar9300_is_tx_done(struct ath_hal *ah) 574 { 575 struct ath_hal_9300 *ahp = AH9300(ah); 576 struct ar9300_txs *ads; 577 578 ads = &ahp->ts_ring[ahp->ts_tail]; 579 580 if (ads->status8 & AR_tx_done) { 581 return HAL_OK; 582 } 583 return HAL_EINPROGRESS; 584 } 585 586 void 587 ar9300_set_11n_tx_desc( 588 struct ath_hal *ah, 589 void *ds, 590 u_int pkt_len, 591 HAL_PKT_TYPE type, 592 u_int tx_power, 593 u_int key_ix, 594 HAL_KEY_TYPE key_type, 595 u_int flags) 596 { 597 struct ar9300_txc *ads = AR9300TXC(ds); 598 struct ath_hal_9300 *ahp = AH9300(ah); 599 600 HALASSERT(is_valid_pkt_type(type)); 601 HALASSERT(is_valid_key_type(key_type)); 602 603 tx_power += ahp->ah_tx_power_index_offset; 604 if (tx_power > 63) { 605 tx_power = 63; 606 } 607 ads->ds_ctl11 = 608 (pkt_len & AR_frame_len) 609 | (flags & HAL_TXDESC_VMF ? AR_virt_more_frag : 0) 610 | SM(tx_power, AR_xmit_power0) 611 | (flags & HAL_TXDESC_VEOL ? AR_veol : 0) 612 | (flags & HAL_TXDESC_CLRDMASK ? AR_clr_dest_mask : 0) 613 | (key_ix != HAL_TXKEYIX_INVALID ? AR_dest_idx_valid : 0) 614 | (flags & HAL_TXDESC_LOWRXCHAIN ? AR_low_rx_chain : 0); 615 616 ads->ds_ctl12 = 617 (key_ix != HAL_TXKEYIX_INVALID ? SM(key_ix, AR_dest_idx) : 0) 618 | SM(type, AR_frame_type) 619 | (flags & HAL_TXDESC_NOACK ? AR_no_ack : 0) 620 | (flags & HAL_TXDESC_HWTS ? AR_insert_ts : 0) 621 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ext_only : 0) 622 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ext_and_ctl : 0); 623 624 ads->ds_ctl17 = 625 SM(key_type, AR_encr_type) | (flags & HAL_TXDESC_LDPC ? AR_ldpc : 0); 626 627 ads->ds_ctl18 = 0; 628 ads->ds_ctl19 = AR_not_sounding; /* set not sounding for normal frame */ 629 630 /* ToA/ToD positioning */ 631 if (flags & HAL_TXDESC_POS) { 632 ads->ds_ctl12 |= AR_loc_mode; 633 ads->ds_ctl19 &= ~AR_not_sounding; 634 } 635 636 /* 637 * Clear Ness1/2/3 (Number of Extension Spatial Streams) fields. 638 * Ness0 is cleared in ctl19. See EV66059 (BB panic). 639 */ 640 ads->ds_ctl20 = 0; 641 ads->ds_ctl21 = 0; 642 ads->ds_ctl22 = 0; 643 } 644 645 void ar9300_set_rx_chainmask(struct ath_hal *ah, int rxchainmask) 646 { 647 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rxchainmask); 648 } 649 650 void ar9300_update_loc_ctl_reg(struct ath_hal *ah, int pos_bit) 651 { 652 u_int32_t reg_val; 653 reg_val = OS_REG_READ(ah, AR_LOC_CTL_REG); 654 if (pos_bit) { 655 if (!(reg_val & AR_LOC_CTL_REG_FS)) { 656 /* set fast timestamp bit in the regiter */ 657 OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val | AR_LOC_CTL_REG_FS)); 658 OS_REG_WRITE(ah, AR_LOC_TIMER_REG, 0); 659 } 660 } 661 else { 662 OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val & ~AR_LOC_CTL_REG_FS)); 663 } 664 } 665 666 #if 0 667 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) 668 static const u_int8_t ba_duration_delta[] = { 669 24, /* 0: BPSK */ 670 12, /* 1: QPSK 1/2 */ 671 12, /* 2: QPSK 3/4 */ 672 4, /* 3: 16-QAM 1/2 */ 673 4, /* 4: 16-QAM 3/4 */ 674 4, /* 5: 64-QAM 2/3 */ 675 4, /* 6: 64-QAM 3/4 */ 676 4, /* 7: 64-QAM 5/6 */ 677 24, /* 8: BPSK */ 678 12, /* 9: QPSK 1/2 */ 679 12, /* 10: QPSK 3/4 */ 680 4, /* 11: 16-QAM 1/2 */ 681 4, /* 12: 16-QAM 3/4 */ 682 4, /* 13: 64-QAM 2/3 */ 683 4, /* 14: 64-QAM 3/4 */ 684 4, /* 15: 64-QAM 5/6 */ 685 }; 686 #endif 687 688 689 static u_int8_t 690 ar9300_get_tx_mode(u_int rate_flags) 691 { 692 693 /* Check whether STBC is enabled if TxBF is not enabled */ 694 if (rate_flags & HAL_RATESERIES_STBC){ 695 return AR9300_STBC_MODE; 696 } 697 return AR9300_DEF_MODE; 698 } 699 void 700 ar9300_set_11n_rate_scenario( 701 struct ath_hal *ah, 702 void *ds, 703 void *lastds, 704 u_int dur_update_en, 705 u_int rts_cts_rate, 706 u_int rts_cts_duration, 707 HAL_11N_RATE_SERIES series[], 708 u_int nseries, 709 u_int flags, 710 u_int32_t smart_antenna) 711 { 712 struct ath_hal_private *ap = AH_PRIVATE(ah); 713 struct ar9300_txc *ads = AR9300TXC(ds); 714 struct ar9300_txc *last_ads = AR9300TXC(lastds); 715 u_int32_t ds_ctl11; 716 u_int8_t ant, cal_pkt = 0; 717 u_int mode, tx_mode = AR9300_DEF_MODE; 718 719 HALASSERT(nseries == 4); 720 (void)nseries; 721 (void)rts_cts_duration; /* use H/W to calculate RTSCTSDuration */ 722 723 ds_ctl11 = ads->ds_ctl11; 724 /* 725 * Rate control settings override 726 */ 727 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { 728 if (flags & HAL_TXDESC_RTSENA) { 729 ds_ctl11 &= ~AR_cts_enable; 730 ds_ctl11 |= AR_rts_enable; 731 } else { 732 ds_ctl11 &= ~AR_rts_enable; 733 ds_ctl11 |= AR_cts_enable; 734 } 735 } else { 736 ds_ctl11 = (ds_ctl11 & ~(AR_rts_enable | AR_cts_enable)); 737 } 738 739 mode = ath_hal_get_curmode(ah, ap->ah_curchan); 740 cal_pkt = (ads->ds_ctl12 & AR_paprd_chain_mask)?1:0; 741 742 if (ah->ah_config.ath_hal_desc_tpc) { 743 int16_t txpower; 744 745 if (!cal_pkt) { 746 /* Series 0 TxPower */ 747 tx_mode = ar9300_get_tx_mode(series[0].RateFlags); 748 txpower = ar9300_get_rate_txpower(ah, mode, series[0].RateIndex, 749 series[0].ChSel, tx_mode); 750 } else { 751 txpower = AH9300(ah)->paprd_training_power; 752 } 753 ds_ctl11 &= ~AR_xmit_power0; 754 ds_ctl11 |= 755 set_11n_tx_power(0, AH_MIN(txpower, series[0].tx_power_cap)); 756 } 757 758 ads->ds_ctl11 = ds_ctl11; 759 760 761 ads->ds_ctl13 = set_11n_tries(series, 0) 762 | set_11n_tries(series, 1) 763 | set_11n_tries(series, 2) 764 | set_11n_tries(series, 3) 765 | (dur_update_en ? AR_dur_update_ena : 0) 766 | SM(0, AR_burst_dur); 767 768 ads->ds_ctl14 = set_11n_rate(series, 0) 769 | set_11n_rate(series, 1) 770 | set_11n_rate(series, 2) 771 | set_11n_rate(series, 3); 772 773 ads->ds_ctl15 = set_11n_pkt_dur_rts_cts(series, 0) 774 | set_11n_pkt_dur_rts_cts(series, 1); 775 776 ads->ds_ctl16 = set_11n_pkt_dur_rts_cts(series, 2) 777 | set_11n_pkt_dur_rts_cts(series, 3); 778 779 ads->ds_ctl18 = set_11n_rate_flags(series, 0) 780 | set_11n_rate_flags(series, 1) 781 | set_11n_rate_flags(series, 2) 782 | set_11n_rate_flags(series, 3) 783 | SM(rts_cts_rate, AR_rts_cts_rate); 784 /* set not sounding for normal frame */ 785 ads->ds_ctl19 = AR_not_sounding; 786 787 if (ah->ah_config.ath_hal_desc_tpc) { 788 int16_t txpower; 789 790 if (!cal_pkt) { 791 /* Series 1 TxPower */ 792 tx_mode = ar9300_get_tx_mode(series[1].RateFlags); 793 txpower = ar9300_get_rate_txpower( 794 ah, mode, series[1].RateIndex, series[1].ChSel, tx_mode); 795 } else { 796 txpower = AH9300(ah)->paprd_training_power; 797 } 798 ads->ds_ctl20 |= 799 set_11n_tx_power(1, AH_MIN(txpower, series[1].tx_power_cap)); 800 801 802 /* Series 2 TxPower */ 803 if (!cal_pkt) { 804 tx_mode = ar9300_get_tx_mode(series[2].RateFlags); 805 txpower = ar9300_get_rate_txpower( 806 ah, mode, series[2].RateIndex, series[2].ChSel, tx_mode); 807 } else { 808 txpower = AH9300(ah)->paprd_training_power; 809 } 810 ads->ds_ctl21 |= 811 set_11n_tx_power(2, AH_MIN(txpower, series[2].tx_power_cap)); 812 813 /* Series 3 TxPower */ 814 if (!cal_pkt) { 815 tx_mode = ar9300_get_tx_mode(series[3].RateFlags); 816 txpower = ar9300_get_rate_txpower( 817 ah, mode, series[3].RateIndex, series[3].ChSel, tx_mode); 818 } else { 819 txpower = AH9300(ah)->paprd_training_power; 820 } 821 ads->ds_ctl22 |= 822 set_11n_tx_power(3, AH_MIN(txpower, series[3].tx_power_cap)); 823 } 824 825 if (smart_antenna != 0xffffffff) 826 { 827 /* TX DESC dword 19 to 23 are used for smart antenna configuaration 828 * ctl19 for rate series 0 ... ctrl22 for series 3 829 * bits[2:0] used to configure smart anntenna 830 */ 831 ant = (smart_antenna&0x000000ff); 832 ads->ds_ctl19 |= ant; /* rateseries 0 */ 833 834 ant = (smart_antenna&0x0000ff00) >> 8; 835 ads->ds_ctl20 |= ant; /* rateseries 1 */ 836 837 ant = (smart_antenna&0x00ff0000) >> 16; 838 ads->ds_ctl21 |= ant; /* rateseries 2 */ 839 840 ant = (smart_antenna&0xff000000) >> 24; 841 ads->ds_ctl22 |= ant; /* rateseries 3 */ 842 } 843 844 #ifdef AH_NEED_DESC_SWAP 845 last_ads->ds_ctl13 = __bswap32(ads->ds_ctl13); 846 last_ads->ds_ctl14 = __bswap32(ads->ds_ctl14); 847 #else 848 last_ads->ds_ctl13 = ads->ds_ctl13; 849 last_ads->ds_ctl14 = ads->ds_ctl14; 850 #endif 851 } 852 853 void 854 ar9300_set_11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, 855 u_int aggr_len, u_int num_delims) 856 { 857 struct ar9300_txc *ads = AR9300TXC(ds); 858 859 ads->ds_ctl12 |= (AR_is_aggr | AR_more_aggr); 860 861 ads->ds_ctl17 &= ~AR_aggr_len; 862 ads->ds_ctl17 &= ~AR_pad_delim; 863 /* XXX should use a stack variable! */ 864 ads->ds_ctl17 |= SM(aggr_len, AR_aggr_len); 865 ads->ds_ctl17 |= SM(num_delims, AR_pad_delim); 866 } 867 868 void 869 ar9300_set_11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, 870 u_int num_delims) 871 { 872 struct ar9300_txc *ads = AR9300TXC(ds); 873 unsigned int ctl17; 874 875 ads->ds_ctl12 |= (AR_is_aggr | AR_more_aggr); 876 877 /* 878 * We use a stack variable to manipulate ctl6 to reduce uncached 879 * read modify, modfiy, write. 880 */ 881 ctl17 = ads->ds_ctl17; 882 ctl17 &= ~AR_pad_delim; 883 ctl17 |= SM(num_delims, AR_pad_delim); 884 ads->ds_ctl17 = ctl17; 885 } 886 887 void 888 ar9300_set_11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds) 889 { 890 struct ar9300_txc *ads = AR9300TXC(ds); 891 892 ads->ds_ctl12 |= AR_is_aggr; 893 ads->ds_ctl12 &= ~AR_more_aggr; 894 ads->ds_ctl17 &= ~AR_pad_delim; 895 } 896 897 void 898 ar9300_clr_11n_aggr(struct ath_hal *ah, struct ath_desc *ds) 899 { 900 struct ar9300_txc *ads = AR9300TXC(ds); 901 902 ads->ds_ctl12 &= (~AR_is_aggr & ~AR_more_aggr); 903 } 904 905 void 906 ar9300_set_11n_burst_duration(struct ath_hal *ah, struct ath_desc *ds, 907 u_int burst_duration) 908 { 909 struct ar9300_txc *ads = AR9300TXC(ds); 910 911 ads->ds_ctl13 &= ~AR_burst_dur; 912 ads->ds_ctl13 |= SM(burst_duration, AR_burst_dur); 913 } 914 915 void 916 ar9300_set_11n_rifs_burst_middle(struct ath_hal *ah, void *ds) 917 { 918 struct ar9300_txc *ads = AR9300TXC(ds); 919 920 ads->ds_ctl12 |= AR_more_rifs | AR_no_ack; 921 } 922 923 void 924 ar9300_set_11n_rifs_burst_last(struct ath_hal *ah, void *ds) 925 { 926 struct ar9300_txc *ads = AR9300TXC(ds); 927 928 ads->ds_ctl12 &= (~AR_more_aggr & ~AR_more_rifs); 929 } 930 931 void 932 ar9300_clr_11n_rifs_burst(struct ath_hal *ah, void *ds) 933 { 934 struct ar9300_txc *ads = AR9300TXC(ds); 935 936 ads->ds_ctl12 &= (~AR_more_rifs & ~AR_no_ack); 937 } 938 939 void 940 ar9300_set_11n_aggr_rifs_burst(struct ath_hal *ah, void *ds) 941 { 942 struct ar9300_txc *ads = AR9300TXC(ds); 943 944 ads->ds_ctl12 |= AR_no_ack; 945 ads->ds_ctl12 &= ~AR_more_rifs; 946 } 947 948 void 949 ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, struct ath_desc *ds, 950 u_int vmf) 951 { 952 struct ar9300_txc *ads = AR9300TXC(ds); 953 954 if (vmf) { 955 ads->ds_ctl11 |= AR_virt_more_frag; 956 } else { 957 ads->ds_ctl11 &= ~AR_virt_more_frag; 958 } 959 } 960 961 void 962 ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info) 963 { 964 desc_info->txctl_numwords = TXCTL_NUMWORDS(ah); 965 desc_info->txctl_offset = TXCTL_OFFSET(ah); 966 desc_info->txstatus_numwords = TXSTATUS_NUMWORDS(ah); 967 desc_info->txstatus_offset = TXSTATUS_OFFSET(ah); 968 969 desc_info->rxctl_numwords = RXCTL_NUMWORDS(ah); 970 desc_info->rxctl_offset = RXCTL_OFFSET(ah); 971 desc_info->rxstatus_numwords = RXSTATUS_NUMWORDS(ah); 972 desc_info->rxstatus_offset = RXSTATUS_OFFSET(ah); 973 } 974