xref: /freebsd/sys/contrib/dev/athk/ath11k/core.c (revision 28348cae)
1dd4f32aeSBjoern A. Zeeb // SPDX-License-Identifier: BSD-3-Clause-Clear
2dd4f32aeSBjoern A. Zeeb /*
3dd4f32aeSBjoern A. Zeeb  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
428348caeSBjoern A. Zeeb  * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5dd4f32aeSBjoern A. Zeeb  */
6dd4f32aeSBjoern A. Zeeb 
7dd4f32aeSBjoern A. Zeeb #if defined(__FreeBSD__)
8dd4f32aeSBjoern A. Zeeb #define	LINUXKPI_PARAM_PREFIX	ath11k_core_
9dd4f32aeSBjoern A. Zeeb #endif
10dd4f32aeSBjoern A. Zeeb 
11dd4f32aeSBjoern A. Zeeb #include <linux/module.h>
12dd4f32aeSBjoern A. Zeeb #include <linux/slab.h>
13dd4f32aeSBjoern A. Zeeb #include <linux/remoteproc.h>
14dd4f32aeSBjoern A. Zeeb #include <linux/firmware.h>
15dd4f32aeSBjoern A. Zeeb #if defined(CONFIG_OF)
16dd4f32aeSBjoern A. Zeeb #include <linux/of.h>
17dd4f32aeSBjoern A. Zeeb #endif
18dd4f32aeSBjoern A. Zeeb #if defined(__FreeBSD__)
19dd4f32aeSBjoern A. Zeeb #include <linux/delay.h>
20dd4f32aeSBjoern A. Zeeb #endif
2128348caeSBjoern A. Zeeb 
22dd4f32aeSBjoern A. Zeeb #include "core.h"
23dd4f32aeSBjoern A. Zeeb #include "dp_tx.h"
24dd4f32aeSBjoern A. Zeeb #include "dp_rx.h"
25dd4f32aeSBjoern A. Zeeb #include "debug.h"
26dd4f32aeSBjoern A. Zeeb #include "hif.h"
27dd4f32aeSBjoern A. Zeeb #include "wow.h"
28dd4f32aeSBjoern A. Zeeb 
29dd4f32aeSBjoern A. Zeeb unsigned int ath11k_debug_mask;
30dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_debug_mask);
31dd4f32aeSBjoern A. Zeeb module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
32dd4f32aeSBjoern A. Zeeb MODULE_PARM_DESC(debug_mask, "Debugging mask");
33dd4f32aeSBjoern A. Zeeb 
34dd4f32aeSBjoern A. Zeeb static unsigned int ath11k_crypto_mode;
35dd4f32aeSBjoern A. Zeeb module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644);
36dd4f32aeSBjoern A. Zeeb MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
37dd4f32aeSBjoern A. Zeeb 
38dd4f32aeSBjoern A. Zeeb /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */
39dd4f32aeSBjoern A. Zeeb unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI;
40dd4f32aeSBjoern A. Zeeb module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
41dd4f32aeSBjoern A. Zeeb MODULE_PARM_DESC(frame_mode,
42dd4f32aeSBjoern A. Zeeb 		 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
43dd4f32aeSBjoern A. Zeeb 
4428348caeSBjoern A. Zeeb bool ath11k_ftm_mode;
4528348caeSBjoern A. Zeeb module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444);
4628348caeSBjoern A. Zeeb MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode");
4728348caeSBjoern A. Zeeb 
48dd4f32aeSBjoern A. Zeeb static const struct ath11k_hw_params ath11k_hw_params[] = {
49dd4f32aeSBjoern A. Zeeb 	{
50dd4f32aeSBjoern A. Zeeb 		.hw_rev = ATH11K_HW_IPQ8074,
51dd4f32aeSBjoern A. Zeeb 		.name = "ipq8074 hw2.0",
52dd4f32aeSBjoern A. Zeeb 		.fw = {
53dd4f32aeSBjoern A. Zeeb 			.dir = "IPQ8074/hw2.0",
54dd4f32aeSBjoern A. Zeeb 			.board_size = 256 * 1024,
55dd4f32aeSBjoern A. Zeeb 			.cal_offset = 128 * 1024,
56dd4f32aeSBjoern A. Zeeb 		},
57dd4f32aeSBjoern A. Zeeb 		.max_radios = 3,
58dd4f32aeSBjoern A. Zeeb 		.bdf_addr = 0x4B0C0000,
59dd4f32aeSBjoern A. Zeeb 		.hw_ops = &ipq8074_ops,
60dd4f32aeSBjoern A. Zeeb 		.ring_mask = &ath11k_hw_ring_mask_ipq8074,
61dd4f32aeSBjoern A. Zeeb 		.internal_sleep_clock = false,
62dd4f32aeSBjoern A. Zeeb 		.regs = &ipq8074_regs,
63dd4f32aeSBjoern A. Zeeb 		.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
64dd4f32aeSBjoern A. Zeeb 		.host_ce_config = ath11k_host_ce_config_ipq8074,
65dd4f32aeSBjoern A. Zeeb 		.ce_count = 12,
66dd4f32aeSBjoern A. Zeeb 		.target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
67dd4f32aeSBjoern A. Zeeb 		.target_ce_count = 11,
68dd4f32aeSBjoern A. Zeeb 		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
69dd4f32aeSBjoern A. Zeeb 		.svc_to_ce_map_len = 21,
7028348caeSBjoern A. Zeeb 		.ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
71dd4f32aeSBjoern A. Zeeb 		.single_pdev_only = false,
72dd4f32aeSBjoern A. Zeeb 		.rxdma1_enable = true,
73dd4f32aeSBjoern A. Zeeb 		.num_rxmda_per_pdev = 1,
74dd4f32aeSBjoern A. Zeeb 		.rx_mac_buf_ring = false,
75dd4f32aeSBjoern A. Zeeb 		.vdev_start_delay = false,
76dd4f32aeSBjoern A. Zeeb 		.htt_peer_map_v2 = true,
77dd4f32aeSBjoern A. Zeeb 
78dd4f32aeSBjoern A. Zeeb 		.spectral = {
79dd4f32aeSBjoern A. Zeeb 			.fft_sz = 2,
80dd4f32aeSBjoern A. Zeeb 			/* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes.
81dd4f32aeSBjoern A. Zeeb 			 * so added pad size as 2 bytes to compensate the BIN size
82dd4f32aeSBjoern A. Zeeb 			 */
83dd4f32aeSBjoern A. Zeeb 			.fft_pad_sz = 2,
84dd4f32aeSBjoern A. Zeeb 			.summary_pad_sz = 0,
85dd4f32aeSBjoern A. Zeeb 			.fft_hdr_len = 16,
86dd4f32aeSBjoern A. Zeeb 			.max_fft_bins = 512,
8728348caeSBjoern A. Zeeb 			.fragment_160mhz = true,
88dd4f32aeSBjoern A. Zeeb 		},
89dd4f32aeSBjoern A. Zeeb 
90dd4f32aeSBjoern A. Zeeb 		.interface_modes = BIT(NL80211_IFTYPE_STATION) |
91dd4f32aeSBjoern A. Zeeb 					BIT(NL80211_IFTYPE_AP) |
92dd4f32aeSBjoern A. Zeeb 					BIT(NL80211_IFTYPE_MESH_POINT),
93dd4f32aeSBjoern A. Zeeb 		.supports_monitor = true,
94dd4f32aeSBjoern A. Zeeb 		.full_monitor_mode = false,
95dd4f32aeSBjoern A. Zeeb 		.supports_shadow_regs = false,
96dd4f32aeSBjoern A. Zeeb 		.idle_ps = false,
97dd4f32aeSBjoern A. Zeeb 		.supports_sta_ps = false,
9828348caeSBjoern A. Zeeb 		.coldboot_cal_mm = true,
9928348caeSBjoern A. Zeeb 		.coldboot_cal_ftm = true,
10028348caeSBjoern A. Zeeb 		.cbcal_restart_fw = true,
101dd4f32aeSBjoern A. Zeeb 		.fw_mem_mode = 0,
102dd4f32aeSBjoern A. Zeeb 		.num_vdevs = 16 + 1,
103dd4f32aeSBjoern A. Zeeb 		.num_peers = 512,
104dd4f32aeSBjoern A. Zeeb 		.supports_suspend = false,
105dd4f32aeSBjoern A. Zeeb 		.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
106dd4f32aeSBjoern A. Zeeb 		.supports_regdb = false,
107dd4f32aeSBjoern A. Zeeb 		.fix_l1ss = true,
108dd4f32aeSBjoern A. Zeeb 		.credit_flow = false,
109dd4f32aeSBjoern A. Zeeb 		.max_tx_ring = DP_TCL_NUM_RING_MAX,
110dd4f32aeSBjoern A. Zeeb 		.hal_params = &ath11k_hw_hal_params_ipq8074,
111dd4f32aeSBjoern A. Zeeb 		.supports_dynamic_smps_6ghz = false,
112dd4f32aeSBjoern A. Zeeb 		.alloc_cacheable_memory = true,
113dd4f32aeSBjoern A. Zeeb 		.supports_rssi_stats = false,
114dd4f32aeSBjoern A. Zeeb 		.fw_wmi_diag_event = false,
11528348caeSBjoern A. Zeeb 		.current_cc_support = false,
11628348caeSBjoern A. Zeeb 		.dbr_debug_support = true,
11728348caeSBjoern A. Zeeb 		.global_reset = false,
11828348caeSBjoern A. Zeeb 		.bios_sar_capa = NULL,
11928348caeSBjoern A. Zeeb 		.m3_fw_support = false,
12028348caeSBjoern A. Zeeb 		.fixed_bdf_addr = true,
12128348caeSBjoern A. Zeeb 		.fixed_mem_region = true,
12228348caeSBjoern A. Zeeb 		.static_window_map = false,
12328348caeSBjoern A. Zeeb 		.hybrid_bus_type = false,
12428348caeSBjoern A. Zeeb 		.fixed_fw_mem = false,
12528348caeSBjoern A. Zeeb 		.support_off_channel_tx = false,
12628348caeSBjoern A. Zeeb 		.supports_multi_bssid = false,
12728348caeSBjoern A. Zeeb 
12828348caeSBjoern A. Zeeb 		.sram_dump = {},
12928348caeSBjoern A. Zeeb 
13028348caeSBjoern A. Zeeb 		.tcl_ring_retry = true,
13128348caeSBjoern A. Zeeb 		.tx_ring_size = DP_TCL_DATA_RING_SIZE,
13228348caeSBjoern A. Zeeb 		.smp2p_wow_exit = false,
133dd4f32aeSBjoern A. Zeeb 	},
134dd4f32aeSBjoern A. Zeeb 	{
135dd4f32aeSBjoern A. Zeeb 		.hw_rev = ATH11K_HW_IPQ6018_HW10,
136dd4f32aeSBjoern A. Zeeb 		.name = "ipq6018 hw1.0",
137dd4f32aeSBjoern A. Zeeb 		.fw = {
138dd4f32aeSBjoern A. Zeeb 			.dir = "IPQ6018/hw1.0",
139dd4f32aeSBjoern A. Zeeb 			.board_size = 256 * 1024,
140dd4f32aeSBjoern A. Zeeb 			.cal_offset = 128 * 1024,
141dd4f32aeSBjoern A. Zeeb 		},
142dd4f32aeSBjoern A. Zeeb 		.max_radios = 2,
143dd4f32aeSBjoern A. Zeeb 		.bdf_addr = 0x4ABC0000,
144dd4f32aeSBjoern A. Zeeb 		.hw_ops = &ipq6018_ops,
145dd4f32aeSBjoern A. Zeeb 		.ring_mask = &ath11k_hw_ring_mask_ipq8074,
146dd4f32aeSBjoern A. Zeeb 		.internal_sleep_clock = false,
147dd4f32aeSBjoern A. Zeeb 		.regs = &ipq8074_regs,
148dd4f32aeSBjoern A. Zeeb 		.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
149dd4f32aeSBjoern A. Zeeb 		.host_ce_config = ath11k_host_ce_config_ipq8074,
150dd4f32aeSBjoern A. Zeeb 		.ce_count = 12,
151dd4f32aeSBjoern A. Zeeb 		.target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
152dd4f32aeSBjoern A. Zeeb 		.target_ce_count = 11,
153dd4f32aeSBjoern A. Zeeb 		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
154dd4f32aeSBjoern A. Zeeb 		.svc_to_ce_map_len = 19,
15528348caeSBjoern A. Zeeb 		.ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
156dd4f32aeSBjoern A. Zeeb 		.single_pdev_only = false,
157dd4f32aeSBjoern A. Zeeb 		.rxdma1_enable = true,
158dd4f32aeSBjoern A. Zeeb 		.num_rxmda_per_pdev = 1,
159dd4f32aeSBjoern A. Zeeb 		.rx_mac_buf_ring = false,
160dd4f32aeSBjoern A. Zeeb 		.vdev_start_delay = false,
161dd4f32aeSBjoern A. Zeeb 		.htt_peer_map_v2 = true,
162dd4f32aeSBjoern A. Zeeb 
163dd4f32aeSBjoern A. Zeeb 		.spectral = {
164dd4f32aeSBjoern A. Zeeb 			.fft_sz = 4,
165dd4f32aeSBjoern A. Zeeb 			.fft_pad_sz = 0,
166dd4f32aeSBjoern A. Zeeb 			.summary_pad_sz = 0,
167dd4f32aeSBjoern A. Zeeb 			.fft_hdr_len = 16,
168dd4f32aeSBjoern A. Zeeb 			.max_fft_bins = 512,
16928348caeSBjoern A. Zeeb 			.fragment_160mhz = true,
170dd4f32aeSBjoern A. Zeeb 		},
171dd4f32aeSBjoern A. Zeeb 
172dd4f32aeSBjoern A. Zeeb 		.interface_modes = BIT(NL80211_IFTYPE_STATION) |
173dd4f32aeSBjoern A. Zeeb 					BIT(NL80211_IFTYPE_AP) |
174dd4f32aeSBjoern A. Zeeb 					BIT(NL80211_IFTYPE_MESH_POINT),
175dd4f32aeSBjoern A. Zeeb 		.supports_monitor = true,
176dd4f32aeSBjoern A. Zeeb 		.full_monitor_mode = false,
177dd4f32aeSBjoern A. Zeeb 		.supports_shadow_regs = false,
178dd4f32aeSBjoern A. Zeeb 		.idle_ps = false,
179dd4f32aeSBjoern A. Zeeb 		.supports_sta_ps = false,
18028348caeSBjoern A. Zeeb 		.coldboot_cal_mm = true,
18128348caeSBjoern A. Zeeb 		.coldboot_cal_ftm = true,
18228348caeSBjoern A. Zeeb 		.cbcal_restart_fw = true,
183dd4f32aeSBjoern A. Zeeb 		.fw_mem_mode = 0,
184dd4f32aeSBjoern A. Zeeb 		.num_vdevs = 16 + 1,
185dd4f32aeSBjoern A. Zeeb 		.num_peers = 512,
186dd4f32aeSBjoern A. Zeeb 		.supports_suspend = false,
187dd4f32aeSBjoern A. Zeeb 		.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
188dd4f32aeSBjoern A. Zeeb 		.supports_regdb = false,
189dd4f32aeSBjoern A. Zeeb 		.fix_l1ss = true,
190dd4f32aeSBjoern A. Zeeb 		.credit_flow = false,
191dd4f32aeSBjoern A. Zeeb 		.max_tx_ring = DP_TCL_NUM_RING_MAX,
192dd4f32aeSBjoern A. Zeeb 		.hal_params = &ath11k_hw_hal_params_ipq8074,
193dd4f32aeSBjoern A. Zeeb 		.supports_dynamic_smps_6ghz = false,
194dd4f32aeSBjoern A. Zeeb 		.alloc_cacheable_memory = true,
195dd4f32aeSBjoern A. Zeeb 		.supports_rssi_stats = false,
196dd4f32aeSBjoern A. Zeeb 		.fw_wmi_diag_event = false,
19728348caeSBjoern A. Zeeb 		.current_cc_support = false,
19828348caeSBjoern A. Zeeb 		.dbr_debug_support = true,
19928348caeSBjoern A. Zeeb 		.global_reset = false,
20028348caeSBjoern A. Zeeb 		.bios_sar_capa = NULL,
20128348caeSBjoern A. Zeeb 		.m3_fw_support = false,
20228348caeSBjoern A. Zeeb 		.fixed_bdf_addr = true,
20328348caeSBjoern A. Zeeb 		.fixed_mem_region = true,
20428348caeSBjoern A. Zeeb 		.static_window_map = false,
20528348caeSBjoern A. Zeeb 		.hybrid_bus_type = false,
20628348caeSBjoern A. Zeeb 		.fixed_fw_mem = false,
20728348caeSBjoern A. Zeeb 		.support_off_channel_tx = false,
20828348caeSBjoern A. Zeeb 		.supports_multi_bssid = false,
20928348caeSBjoern A. Zeeb 
21028348caeSBjoern A. Zeeb 		.sram_dump = {},
21128348caeSBjoern A. Zeeb 
21228348caeSBjoern A. Zeeb 		.tcl_ring_retry = true,
21328348caeSBjoern A. Zeeb 		.tx_ring_size = DP_TCL_DATA_RING_SIZE,
21428348caeSBjoern A. Zeeb 		.smp2p_wow_exit = false,
21528348caeSBjoern A. Zeeb 		.support_fw_mac_sequence = false,
216dd4f32aeSBjoern A. Zeeb 	},
217dd4f32aeSBjoern A. Zeeb 	{
218dd4f32aeSBjoern A. Zeeb 		.name = "qca6390 hw2.0",
219dd4f32aeSBjoern A. Zeeb 		.hw_rev = ATH11K_HW_QCA6390_HW20,
220dd4f32aeSBjoern A. Zeeb 		.fw = {
221dd4f32aeSBjoern A. Zeeb 			.dir = "QCA6390/hw2.0",
222dd4f32aeSBjoern A. Zeeb 			.board_size = 256 * 1024,
223dd4f32aeSBjoern A. Zeeb 			.cal_offset = 128 * 1024,
224dd4f32aeSBjoern A. Zeeb 		},
225dd4f32aeSBjoern A. Zeeb 		.max_radios = 3,
226dd4f32aeSBjoern A. Zeeb 		.bdf_addr = 0x4B0C0000,
227dd4f32aeSBjoern A. Zeeb 		.hw_ops = &qca6390_ops,
228dd4f32aeSBjoern A. Zeeb 		.ring_mask = &ath11k_hw_ring_mask_qca6390,
229dd4f32aeSBjoern A. Zeeb 		.internal_sleep_clock = true,
230dd4f32aeSBjoern A. Zeeb 		.regs = &qca6390_regs,
231dd4f32aeSBjoern A. Zeeb 		.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
232dd4f32aeSBjoern A. Zeeb 		.host_ce_config = ath11k_host_ce_config_qca6390,
233dd4f32aeSBjoern A. Zeeb 		.ce_count = 9,
234dd4f32aeSBjoern A. Zeeb 		.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
235dd4f32aeSBjoern A. Zeeb 		.target_ce_count = 9,
236dd4f32aeSBjoern A. Zeeb 		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
237dd4f32aeSBjoern A. Zeeb 		.svc_to_ce_map_len = 14,
23828348caeSBjoern A. Zeeb 		.ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
239dd4f32aeSBjoern A. Zeeb 		.single_pdev_only = true,
240dd4f32aeSBjoern A. Zeeb 		.rxdma1_enable = false,
241dd4f32aeSBjoern A. Zeeb 		.num_rxmda_per_pdev = 2,
242dd4f32aeSBjoern A. Zeeb 		.rx_mac_buf_ring = true,
243dd4f32aeSBjoern A. Zeeb 		.vdev_start_delay = true,
244dd4f32aeSBjoern A. Zeeb 		.htt_peer_map_v2 = false,
245dd4f32aeSBjoern A. Zeeb 
246dd4f32aeSBjoern A. Zeeb 		.spectral = {
247dd4f32aeSBjoern A. Zeeb 			.fft_sz = 0,
248dd4f32aeSBjoern A. Zeeb 			.fft_pad_sz = 0,
249dd4f32aeSBjoern A. Zeeb 			.summary_pad_sz = 0,
250dd4f32aeSBjoern A. Zeeb 			.fft_hdr_len = 0,
251dd4f32aeSBjoern A. Zeeb 			.max_fft_bins = 0,
25228348caeSBjoern A. Zeeb 			.fragment_160mhz = false,
253dd4f32aeSBjoern A. Zeeb 		},
254dd4f32aeSBjoern A. Zeeb 
255dd4f32aeSBjoern A. Zeeb 		.interface_modes = BIT(NL80211_IFTYPE_STATION) |
256dd4f32aeSBjoern A. Zeeb 					BIT(NL80211_IFTYPE_AP),
257dd4f32aeSBjoern A. Zeeb 		.supports_monitor = false,
258dd4f32aeSBjoern A. Zeeb 		.full_monitor_mode = false,
259dd4f32aeSBjoern A. Zeeb 		.supports_shadow_regs = true,
260dd4f32aeSBjoern A. Zeeb 		.idle_ps = true,
261dd4f32aeSBjoern A. Zeeb 		.supports_sta_ps = true,
26228348caeSBjoern A. Zeeb 		.coldboot_cal_mm = false,
26328348caeSBjoern A. Zeeb 		.coldboot_cal_ftm = false,
26428348caeSBjoern A. Zeeb 		.cbcal_restart_fw = false,
265dd4f32aeSBjoern A. Zeeb 		.fw_mem_mode = 0,
266dd4f32aeSBjoern A. Zeeb 		.num_vdevs = 16 + 1,
267dd4f32aeSBjoern A. Zeeb 		.num_peers = 512,
268dd4f32aeSBjoern A. Zeeb 		.supports_suspend = true,
269dd4f32aeSBjoern A. Zeeb 		.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
27028348caeSBjoern A. Zeeb 		.supports_regdb = false,
271dd4f32aeSBjoern A. Zeeb 		.fix_l1ss = true,
272dd4f32aeSBjoern A. Zeeb 		.credit_flow = true,
273dd4f32aeSBjoern A. Zeeb 		.max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
274dd4f32aeSBjoern A. Zeeb 		.hal_params = &ath11k_hw_hal_params_qca6390,
275dd4f32aeSBjoern A. Zeeb 		.supports_dynamic_smps_6ghz = false,
276dd4f32aeSBjoern A. Zeeb 		.alloc_cacheable_memory = false,
277dd4f32aeSBjoern A. Zeeb 		.supports_rssi_stats = true,
278dd4f32aeSBjoern A. Zeeb 		.fw_wmi_diag_event = true,
27928348caeSBjoern A. Zeeb 		.current_cc_support = true,
28028348caeSBjoern A. Zeeb 		.dbr_debug_support = false,
28128348caeSBjoern A. Zeeb 		.global_reset = true,
28228348caeSBjoern A. Zeeb 		.bios_sar_capa = NULL,
28328348caeSBjoern A. Zeeb 		.m3_fw_support = true,
28428348caeSBjoern A. Zeeb 		.fixed_bdf_addr = false,
28528348caeSBjoern A. Zeeb 		.fixed_mem_region = false,
28628348caeSBjoern A. Zeeb 		.static_window_map = false,
28728348caeSBjoern A. Zeeb 		.hybrid_bus_type = false,
28828348caeSBjoern A. Zeeb 		.fixed_fw_mem = false,
28928348caeSBjoern A. Zeeb 		.support_off_channel_tx = true,
29028348caeSBjoern A. Zeeb 		.supports_multi_bssid = true,
29128348caeSBjoern A. Zeeb 
29228348caeSBjoern A. Zeeb 		.sram_dump = {
29328348caeSBjoern A. Zeeb 			.start = 0x01400000,
29428348caeSBjoern A. Zeeb 			.end = 0x0171ffff,
29528348caeSBjoern A. Zeeb 		},
29628348caeSBjoern A. Zeeb 
29728348caeSBjoern A. Zeeb 		.tcl_ring_retry = true,
29828348caeSBjoern A. Zeeb 		.tx_ring_size = DP_TCL_DATA_RING_SIZE,
29928348caeSBjoern A. Zeeb 		.smp2p_wow_exit = false,
30028348caeSBjoern A. Zeeb 		.support_fw_mac_sequence = true,
301dd4f32aeSBjoern A. Zeeb 	},
302dd4f32aeSBjoern A. Zeeb 	{
303dd4f32aeSBjoern A. Zeeb 		.name = "qcn9074 hw1.0",
304dd4f32aeSBjoern A. Zeeb 		.hw_rev = ATH11K_HW_QCN9074_HW10,
305dd4f32aeSBjoern A. Zeeb 		.fw = {
306dd4f32aeSBjoern A. Zeeb 			.dir = "QCN9074/hw1.0",
307dd4f32aeSBjoern A. Zeeb 			.board_size = 256 * 1024,
308dd4f32aeSBjoern A. Zeeb 			.cal_offset = 128 * 1024,
309dd4f32aeSBjoern A. Zeeb 		},
310dd4f32aeSBjoern A. Zeeb 		.max_radios = 1,
311dd4f32aeSBjoern A. Zeeb 		.single_pdev_only = false,
312dd4f32aeSBjoern A. Zeeb 		.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
313dd4f32aeSBjoern A. Zeeb 		.hw_ops = &qcn9074_ops,
314dd4f32aeSBjoern A. Zeeb 		.ring_mask = &ath11k_hw_ring_mask_qcn9074,
315dd4f32aeSBjoern A. Zeeb 		.internal_sleep_clock = false,
316dd4f32aeSBjoern A. Zeeb 		.regs = &qcn9074_regs,
317dd4f32aeSBjoern A. Zeeb 		.host_ce_config = ath11k_host_ce_config_qcn9074,
318dd4f32aeSBjoern A. Zeeb 		.ce_count = 6,
319dd4f32aeSBjoern A. Zeeb 		.target_ce_config = ath11k_target_ce_config_wlan_qcn9074,
320dd4f32aeSBjoern A. Zeeb 		.target_ce_count = 9,
321dd4f32aeSBjoern A. Zeeb 		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
322dd4f32aeSBjoern A. Zeeb 		.svc_to_ce_map_len = 18,
32328348caeSBjoern A. Zeeb 		.ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
324dd4f32aeSBjoern A. Zeeb 		.rxdma1_enable = true,
325dd4f32aeSBjoern A. Zeeb 		.num_rxmda_per_pdev = 1,
326dd4f32aeSBjoern A. Zeeb 		.rx_mac_buf_ring = false,
327dd4f32aeSBjoern A. Zeeb 		.vdev_start_delay = false,
328dd4f32aeSBjoern A. Zeeb 		.htt_peer_map_v2 = true,
329dd4f32aeSBjoern A. Zeeb 
330dd4f32aeSBjoern A. Zeeb 		.spectral = {
331dd4f32aeSBjoern A. Zeeb 			.fft_sz = 2,
332dd4f32aeSBjoern A. Zeeb 			.fft_pad_sz = 0,
333dd4f32aeSBjoern A. Zeeb 			.summary_pad_sz = 16,
334dd4f32aeSBjoern A. Zeeb 			.fft_hdr_len = 24,
335dd4f32aeSBjoern A. Zeeb 			.max_fft_bins = 1024,
33628348caeSBjoern A. Zeeb 			.fragment_160mhz = false,
337dd4f32aeSBjoern A. Zeeb 		},
338dd4f32aeSBjoern A. Zeeb 
339dd4f32aeSBjoern A. Zeeb 		.interface_modes = BIT(NL80211_IFTYPE_STATION) |
340dd4f32aeSBjoern A. Zeeb 					BIT(NL80211_IFTYPE_AP) |
341dd4f32aeSBjoern A. Zeeb 					BIT(NL80211_IFTYPE_MESH_POINT),
342dd4f32aeSBjoern A. Zeeb 		.supports_monitor = true,
343dd4f32aeSBjoern A. Zeeb 		.full_monitor_mode = true,
344dd4f32aeSBjoern A. Zeeb 		.supports_shadow_regs = false,
345dd4f32aeSBjoern A. Zeeb 		.idle_ps = false,
346dd4f32aeSBjoern A. Zeeb 		.supports_sta_ps = false,
34728348caeSBjoern A. Zeeb 		.coldboot_cal_mm = false,
34828348caeSBjoern A. Zeeb 		.coldboot_cal_ftm = true,
34928348caeSBjoern A. Zeeb 		.cbcal_restart_fw = true,
350dd4f32aeSBjoern A. Zeeb 		.fw_mem_mode = 2,
351dd4f32aeSBjoern A. Zeeb 		.num_vdevs = 8,
352dd4f32aeSBjoern A. Zeeb 		.num_peers = 128,
353dd4f32aeSBjoern A. Zeeb 		.supports_suspend = false,
354dd4f32aeSBjoern A. Zeeb 		.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
355dd4f32aeSBjoern A. Zeeb 		.supports_regdb = false,
356dd4f32aeSBjoern A. Zeeb 		.fix_l1ss = true,
357dd4f32aeSBjoern A. Zeeb 		.credit_flow = false,
358dd4f32aeSBjoern A. Zeeb 		.max_tx_ring = DP_TCL_NUM_RING_MAX,
359dd4f32aeSBjoern A. Zeeb 		.hal_params = &ath11k_hw_hal_params_ipq8074,
360dd4f32aeSBjoern A. Zeeb 		.supports_dynamic_smps_6ghz = true,
361dd4f32aeSBjoern A. Zeeb 		.alloc_cacheable_memory = true,
362dd4f32aeSBjoern A. Zeeb 		.supports_rssi_stats = false,
363dd4f32aeSBjoern A. Zeeb 		.fw_wmi_diag_event = false,
36428348caeSBjoern A. Zeeb 		.current_cc_support = false,
36528348caeSBjoern A. Zeeb 		.dbr_debug_support = true,
36628348caeSBjoern A. Zeeb 		.global_reset = false,
36728348caeSBjoern A. Zeeb 		.bios_sar_capa = NULL,
36828348caeSBjoern A. Zeeb 		.m3_fw_support = true,
36928348caeSBjoern A. Zeeb 		.fixed_bdf_addr = false,
37028348caeSBjoern A. Zeeb 		.fixed_mem_region = false,
37128348caeSBjoern A. Zeeb 		.static_window_map = true,
37228348caeSBjoern A. Zeeb 		.hybrid_bus_type = false,
37328348caeSBjoern A. Zeeb 		.fixed_fw_mem = false,
37428348caeSBjoern A. Zeeb 		.support_off_channel_tx = false,
37528348caeSBjoern A. Zeeb 		.supports_multi_bssid = false,
37628348caeSBjoern A. Zeeb 
37728348caeSBjoern A. Zeeb 		.sram_dump = {},
37828348caeSBjoern A. Zeeb 
37928348caeSBjoern A. Zeeb 		.tcl_ring_retry = true,
38028348caeSBjoern A. Zeeb 		.tx_ring_size = DP_TCL_DATA_RING_SIZE,
38128348caeSBjoern A. Zeeb 		.smp2p_wow_exit = false,
38228348caeSBjoern A. Zeeb 		.support_fw_mac_sequence = false,
383dd4f32aeSBjoern A. Zeeb 	},
384dd4f32aeSBjoern A. Zeeb 	{
385dd4f32aeSBjoern A. Zeeb 		.name = "wcn6855 hw2.0",
386dd4f32aeSBjoern A. Zeeb 		.hw_rev = ATH11K_HW_WCN6855_HW20,
387dd4f32aeSBjoern A. Zeeb 		.fw = {
388dd4f32aeSBjoern A. Zeeb 			.dir = "WCN6855/hw2.0",
389dd4f32aeSBjoern A. Zeeb 			.board_size = 256 * 1024,
390dd4f32aeSBjoern A. Zeeb 			.cal_offset = 128 * 1024,
391dd4f32aeSBjoern A. Zeeb 		},
392dd4f32aeSBjoern A. Zeeb 		.max_radios = 3,
393dd4f32aeSBjoern A. Zeeb 		.bdf_addr = 0x4B0C0000,
394dd4f32aeSBjoern A. Zeeb 		.hw_ops = &wcn6855_ops,
395dd4f32aeSBjoern A. Zeeb 		.ring_mask = &ath11k_hw_ring_mask_qca6390,
396dd4f32aeSBjoern A. Zeeb 		.internal_sleep_clock = true,
397dd4f32aeSBjoern A. Zeeb 		.regs = &wcn6855_regs,
398dd4f32aeSBjoern A. Zeeb 		.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
399dd4f32aeSBjoern A. Zeeb 		.host_ce_config = ath11k_host_ce_config_qca6390,
400dd4f32aeSBjoern A. Zeeb 		.ce_count = 9,
401dd4f32aeSBjoern A. Zeeb 		.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
402dd4f32aeSBjoern A. Zeeb 		.target_ce_count = 9,
403dd4f32aeSBjoern A. Zeeb 		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
404dd4f32aeSBjoern A. Zeeb 		.svc_to_ce_map_len = 14,
40528348caeSBjoern A. Zeeb 		.ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
406dd4f32aeSBjoern A. Zeeb 		.single_pdev_only = true,
407dd4f32aeSBjoern A. Zeeb 		.rxdma1_enable = false,
408dd4f32aeSBjoern A. Zeeb 		.num_rxmda_per_pdev = 2,
409dd4f32aeSBjoern A. Zeeb 		.rx_mac_buf_ring = true,
410dd4f32aeSBjoern A. Zeeb 		.vdev_start_delay = true,
411dd4f32aeSBjoern A. Zeeb 		.htt_peer_map_v2 = false,
412dd4f32aeSBjoern A. Zeeb 
413dd4f32aeSBjoern A. Zeeb 		.spectral = {
414dd4f32aeSBjoern A. Zeeb 			.fft_sz = 0,
415dd4f32aeSBjoern A. Zeeb 			.fft_pad_sz = 0,
416dd4f32aeSBjoern A. Zeeb 			.summary_pad_sz = 0,
417dd4f32aeSBjoern A. Zeeb 			.fft_hdr_len = 0,
418dd4f32aeSBjoern A. Zeeb 			.max_fft_bins = 0,
41928348caeSBjoern A. Zeeb 			.fragment_160mhz = false,
420dd4f32aeSBjoern A. Zeeb 		},
421dd4f32aeSBjoern A. Zeeb 
422dd4f32aeSBjoern A. Zeeb 		.interface_modes = BIT(NL80211_IFTYPE_STATION) |
423dd4f32aeSBjoern A. Zeeb 					BIT(NL80211_IFTYPE_AP),
424dd4f32aeSBjoern A. Zeeb 		.supports_monitor = false,
425dd4f32aeSBjoern A. Zeeb 		.full_monitor_mode = false,
426dd4f32aeSBjoern A. Zeeb 		.supports_shadow_regs = true,
427dd4f32aeSBjoern A. Zeeb 		.idle_ps = true,
428dd4f32aeSBjoern A. Zeeb 		.supports_sta_ps = true,
42928348caeSBjoern A. Zeeb 		.coldboot_cal_mm = false,
43028348caeSBjoern A. Zeeb 		.coldboot_cal_ftm = false,
43128348caeSBjoern A. Zeeb 		.cbcal_restart_fw = false,
432dd4f32aeSBjoern A. Zeeb 		.fw_mem_mode = 0,
433dd4f32aeSBjoern A. Zeeb 		.num_vdevs = 16 + 1,
434dd4f32aeSBjoern A. Zeeb 		.num_peers = 512,
435dd4f32aeSBjoern A. Zeeb 		.supports_suspend = true,
436dd4f32aeSBjoern A. Zeeb 		.hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
437dd4f32aeSBjoern A. Zeeb 		.supports_regdb = true,
438dd4f32aeSBjoern A. Zeeb 		.fix_l1ss = false,
439dd4f32aeSBjoern A. Zeeb 		.credit_flow = true,
440dd4f32aeSBjoern A. Zeeb 		.max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
441dd4f32aeSBjoern A. Zeeb 		.hal_params = &ath11k_hw_hal_params_qca6390,
442dd4f32aeSBjoern A. Zeeb 		.supports_dynamic_smps_6ghz = false,
443dd4f32aeSBjoern A. Zeeb 		.alloc_cacheable_memory = false,
444dd4f32aeSBjoern A. Zeeb 		.supports_rssi_stats = true,
445dd4f32aeSBjoern A. Zeeb 		.fw_wmi_diag_event = true,
44628348caeSBjoern A. Zeeb 		.current_cc_support = true,
44728348caeSBjoern A. Zeeb 		.dbr_debug_support = false,
44828348caeSBjoern A. Zeeb 		.global_reset = true,
44928348caeSBjoern A. Zeeb 		.bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
45028348caeSBjoern A. Zeeb 		.m3_fw_support = true,
45128348caeSBjoern A. Zeeb 		.fixed_bdf_addr = false,
45228348caeSBjoern A. Zeeb 		.fixed_mem_region = false,
45328348caeSBjoern A. Zeeb 		.static_window_map = false,
45428348caeSBjoern A. Zeeb 		.hybrid_bus_type = false,
45528348caeSBjoern A. Zeeb 		.fixed_fw_mem = false,
45628348caeSBjoern A. Zeeb 		.support_off_channel_tx = true,
45728348caeSBjoern A. Zeeb 		.supports_multi_bssid = true,
45828348caeSBjoern A. Zeeb 
45928348caeSBjoern A. Zeeb 		.sram_dump = {
46028348caeSBjoern A. Zeeb 			.start = 0x01400000,
46128348caeSBjoern A. Zeeb 			.end = 0x0177ffff,
46228348caeSBjoern A. Zeeb 		},
46328348caeSBjoern A. Zeeb 
46428348caeSBjoern A. Zeeb 		.tcl_ring_retry = true,
46528348caeSBjoern A. Zeeb 		.tx_ring_size = DP_TCL_DATA_RING_SIZE,
46628348caeSBjoern A. Zeeb 		.smp2p_wow_exit = false,
46728348caeSBjoern A. Zeeb 		.support_fw_mac_sequence = true,
468dd4f32aeSBjoern A. Zeeb 	},
469dd4f32aeSBjoern A. Zeeb 	{
470dd4f32aeSBjoern A. Zeeb 		.name = "wcn6855 hw2.1",
471dd4f32aeSBjoern A. Zeeb 		.hw_rev = ATH11K_HW_WCN6855_HW21,
472dd4f32aeSBjoern A. Zeeb 		.fw = {
473dd4f32aeSBjoern A. Zeeb 			.dir = "WCN6855/hw2.1",
474dd4f32aeSBjoern A. Zeeb 			.board_size = 256 * 1024,
475dd4f32aeSBjoern A. Zeeb 			.cal_offset = 128 * 1024,
476dd4f32aeSBjoern A. Zeeb 		},
477dd4f32aeSBjoern A. Zeeb 		.max_radios = 3,
478dd4f32aeSBjoern A. Zeeb 		.bdf_addr = 0x4B0C0000,
479dd4f32aeSBjoern A. Zeeb 		.hw_ops = &wcn6855_ops,
480dd4f32aeSBjoern A. Zeeb 		.ring_mask = &ath11k_hw_ring_mask_qca6390,
481dd4f32aeSBjoern A. Zeeb 		.internal_sleep_clock = true,
482dd4f32aeSBjoern A. Zeeb 		.regs = &wcn6855_regs,
483dd4f32aeSBjoern A. Zeeb 		.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
484dd4f32aeSBjoern A. Zeeb 		.host_ce_config = ath11k_host_ce_config_qca6390,
485dd4f32aeSBjoern A. Zeeb 		.ce_count = 9,
486dd4f32aeSBjoern A. Zeeb 		.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
487dd4f32aeSBjoern A. Zeeb 		.target_ce_count = 9,
488dd4f32aeSBjoern A. Zeeb 		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
489dd4f32aeSBjoern A. Zeeb 		.svc_to_ce_map_len = 14,
490dd4f32aeSBjoern A. Zeeb 		.single_pdev_only = true,
491dd4f32aeSBjoern A. Zeeb 		.rxdma1_enable = false,
492dd4f32aeSBjoern A. Zeeb 		.num_rxmda_per_pdev = 2,
493dd4f32aeSBjoern A. Zeeb 		.rx_mac_buf_ring = true,
494dd4f32aeSBjoern A. Zeeb 		.vdev_start_delay = true,
495dd4f32aeSBjoern A. Zeeb 		.htt_peer_map_v2 = false,
496dd4f32aeSBjoern A. Zeeb 
497dd4f32aeSBjoern A. Zeeb 		.spectral = {
498dd4f32aeSBjoern A. Zeeb 			.fft_sz = 0,
499dd4f32aeSBjoern A. Zeeb 			.fft_pad_sz = 0,
500dd4f32aeSBjoern A. Zeeb 			.summary_pad_sz = 0,
501dd4f32aeSBjoern A. Zeeb 			.fft_hdr_len = 0,
502dd4f32aeSBjoern A. Zeeb 			.max_fft_bins = 0,
50328348caeSBjoern A. Zeeb 			.fragment_160mhz = false,
504dd4f32aeSBjoern A. Zeeb 		},
505dd4f32aeSBjoern A. Zeeb 
506dd4f32aeSBjoern A. Zeeb 		.interface_modes = BIT(NL80211_IFTYPE_STATION) |
507dd4f32aeSBjoern A. Zeeb 					BIT(NL80211_IFTYPE_AP),
508dd4f32aeSBjoern A. Zeeb 		.supports_monitor = false,
509dd4f32aeSBjoern A. Zeeb 		.supports_shadow_regs = true,
510dd4f32aeSBjoern A. Zeeb 		.idle_ps = true,
511dd4f32aeSBjoern A. Zeeb 		.supports_sta_ps = true,
51228348caeSBjoern A. Zeeb 		.coldboot_cal_mm = false,
51328348caeSBjoern A. Zeeb 		.coldboot_cal_ftm = false,
51428348caeSBjoern A. Zeeb 		.cbcal_restart_fw = false,
515dd4f32aeSBjoern A. Zeeb 		.fw_mem_mode = 0,
516dd4f32aeSBjoern A. Zeeb 		.num_vdevs = 16 + 1,
517dd4f32aeSBjoern A. Zeeb 		.num_peers = 512,
518dd4f32aeSBjoern A. Zeeb 		.supports_suspend = true,
519dd4f32aeSBjoern A. Zeeb 		.hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
520dd4f32aeSBjoern A. Zeeb 		.supports_regdb = true,
521dd4f32aeSBjoern A. Zeeb 		.fix_l1ss = false,
522dd4f32aeSBjoern A. Zeeb 		.credit_flow = true,
523dd4f32aeSBjoern A. Zeeb 		.max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
524dd4f32aeSBjoern A. Zeeb 		.hal_params = &ath11k_hw_hal_params_qca6390,
525dd4f32aeSBjoern A. Zeeb 		.supports_dynamic_smps_6ghz = false,
526dd4f32aeSBjoern A. Zeeb 		.alloc_cacheable_memory = false,
527dd4f32aeSBjoern A. Zeeb 		.supports_rssi_stats = true,
528dd4f32aeSBjoern A. Zeeb 		.fw_wmi_diag_event = true,
52928348caeSBjoern A. Zeeb 		.current_cc_support = true,
53028348caeSBjoern A. Zeeb 		.dbr_debug_support = false,
53128348caeSBjoern A. Zeeb 		.global_reset = true,
53228348caeSBjoern A. Zeeb 		.bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
53328348caeSBjoern A. Zeeb 		.m3_fw_support = true,
53428348caeSBjoern A. Zeeb 		.fixed_bdf_addr = false,
53528348caeSBjoern A. Zeeb 		.fixed_mem_region = false,
53628348caeSBjoern A. Zeeb 		.static_window_map = false,
53728348caeSBjoern A. Zeeb 		.hybrid_bus_type = false,
53828348caeSBjoern A. Zeeb 		.fixed_fw_mem = false,
53928348caeSBjoern A. Zeeb 		.support_off_channel_tx = true,
54028348caeSBjoern A. Zeeb 		.supports_multi_bssid = true,
54128348caeSBjoern A. Zeeb 
54228348caeSBjoern A. Zeeb 		.sram_dump = {
54328348caeSBjoern A. Zeeb 			.start = 0x01400000,
54428348caeSBjoern A. Zeeb 			.end = 0x0177ffff,
54528348caeSBjoern A. Zeeb 		},
54628348caeSBjoern A. Zeeb 
54728348caeSBjoern A. Zeeb 		.tcl_ring_retry = true,
54828348caeSBjoern A. Zeeb 		.tx_ring_size = DP_TCL_DATA_RING_SIZE,
54928348caeSBjoern A. Zeeb 		.smp2p_wow_exit = false,
55028348caeSBjoern A. Zeeb 		.support_fw_mac_sequence = true,
55128348caeSBjoern A. Zeeb 	},
55228348caeSBjoern A. Zeeb 	{
55328348caeSBjoern A. Zeeb 		.name = "wcn6750 hw1.0",
55428348caeSBjoern A. Zeeb 		.hw_rev = ATH11K_HW_WCN6750_HW10,
55528348caeSBjoern A. Zeeb 		.fw = {
55628348caeSBjoern A. Zeeb 			.dir = "WCN6750/hw1.0",
55728348caeSBjoern A. Zeeb 			.board_size = 256 * 1024,
55828348caeSBjoern A. Zeeb 			.cal_offset = 128 * 1024,
55928348caeSBjoern A. Zeeb 		},
56028348caeSBjoern A. Zeeb 		.max_radios = 1,
56128348caeSBjoern A. Zeeb 		.bdf_addr = 0x4B0C0000,
56228348caeSBjoern A. Zeeb 		.hw_ops = &wcn6750_ops,
56328348caeSBjoern A. Zeeb 		.ring_mask = &ath11k_hw_ring_mask_wcn6750,
56428348caeSBjoern A. Zeeb 		.internal_sleep_clock = false,
56528348caeSBjoern A. Zeeb 		.regs = &wcn6750_regs,
56628348caeSBjoern A. Zeeb 		.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
56728348caeSBjoern A. Zeeb 		.host_ce_config = ath11k_host_ce_config_qca6390,
56828348caeSBjoern A. Zeeb 		.ce_count = 9,
56928348caeSBjoern A. Zeeb 		.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
57028348caeSBjoern A. Zeeb 		.target_ce_count = 9,
57128348caeSBjoern A. Zeeb 		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
57228348caeSBjoern A. Zeeb 		.svc_to_ce_map_len = 14,
57328348caeSBjoern A. Zeeb 		.ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
57428348caeSBjoern A. Zeeb 		.single_pdev_only = true,
57528348caeSBjoern A. Zeeb 		.rxdma1_enable = false,
57628348caeSBjoern A. Zeeb 		.num_rxmda_per_pdev = 1,
57728348caeSBjoern A. Zeeb 		.rx_mac_buf_ring = true,
57828348caeSBjoern A. Zeeb 		.vdev_start_delay = true,
57928348caeSBjoern A. Zeeb 		.htt_peer_map_v2 = false,
58028348caeSBjoern A. Zeeb 
58128348caeSBjoern A. Zeeb 		.spectral = {
58228348caeSBjoern A. Zeeb 			.fft_sz = 0,
58328348caeSBjoern A. Zeeb 			.fft_pad_sz = 0,
58428348caeSBjoern A. Zeeb 			.summary_pad_sz = 0,
58528348caeSBjoern A. Zeeb 			.fft_hdr_len = 0,
58628348caeSBjoern A. Zeeb 			.max_fft_bins = 0,
58728348caeSBjoern A. Zeeb 			.fragment_160mhz = false,
58828348caeSBjoern A. Zeeb 		},
58928348caeSBjoern A. Zeeb 
59028348caeSBjoern A. Zeeb 		.interface_modes = BIT(NL80211_IFTYPE_STATION) |
59128348caeSBjoern A. Zeeb 					BIT(NL80211_IFTYPE_AP),
59228348caeSBjoern A. Zeeb 		.supports_monitor = false,
59328348caeSBjoern A. Zeeb 		.supports_shadow_regs = true,
59428348caeSBjoern A. Zeeb 		.idle_ps = true,
59528348caeSBjoern A. Zeeb 		.supports_sta_ps = true,
59628348caeSBjoern A. Zeeb 		.coldboot_cal_mm = true,
59728348caeSBjoern A. Zeeb 		.coldboot_cal_ftm = true,
59828348caeSBjoern A. Zeeb 		.cbcal_restart_fw = false,
59928348caeSBjoern A. Zeeb 		.fw_mem_mode = 0,
60028348caeSBjoern A. Zeeb 		.num_vdevs = 16 + 1,
60128348caeSBjoern A. Zeeb 		.num_peers = 512,
60228348caeSBjoern A. Zeeb 		.supports_suspend = false,
60328348caeSBjoern A. Zeeb 		.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
60428348caeSBjoern A. Zeeb 		.supports_regdb = true,
60528348caeSBjoern A. Zeeb 		.fix_l1ss = false,
60628348caeSBjoern A. Zeeb 		.credit_flow = true,
60728348caeSBjoern A. Zeeb 		.max_tx_ring = DP_TCL_NUM_RING_MAX,
60828348caeSBjoern A. Zeeb 		.hal_params = &ath11k_hw_hal_params_wcn6750,
60928348caeSBjoern A. Zeeb 		.supports_dynamic_smps_6ghz = false,
61028348caeSBjoern A. Zeeb 		.alloc_cacheable_memory = false,
61128348caeSBjoern A. Zeeb 		.supports_rssi_stats = true,
61228348caeSBjoern A. Zeeb 		.fw_wmi_diag_event = false,
61328348caeSBjoern A. Zeeb 		.current_cc_support = true,
61428348caeSBjoern A. Zeeb 		.dbr_debug_support = false,
61528348caeSBjoern A. Zeeb 		.global_reset = false,
61628348caeSBjoern A. Zeeb 		.bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
61728348caeSBjoern A. Zeeb 		.m3_fw_support = false,
61828348caeSBjoern A. Zeeb 		.fixed_bdf_addr = false,
61928348caeSBjoern A. Zeeb 		.fixed_mem_region = false,
62028348caeSBjoern A. Zeeb 		.static_window_map = true,
62128348caeSBjoern A. Zeeb 		.hybrid_bus_type = true,
62228348caeSBjoern A. Zeeb 		.fixed_fw_mem = true,
62328348caeSBjoern A. Zeeb 		.support_off_channel_tx = true,
62428348caeSBjoern A. Zeeb 		.supports_multi_bssid = true,
62528348caeSBjoern A. Zeeb 
62628348caeSBjoern A. Zeeb 		.sram_dump = {},
62728348caeSBjoern A. Zeeb 
62828348caeSBjoern A. Zeeb 		.tcl_ring_retry = false,
62928348caeSBjoern A. Zeeb 		.tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750,
63028348caeSBjoern A. Zeeb 		.smp2p_wow_exit = true,
63128348caeSBjoern A. Zeeb 		.support_fw_mac_sequence = true,
63228348caeSBjoern A. Zeeb 	},
63328348caeSBjoern A. Zeeb 	{
63428348caeSBjoern A. Zeeb 		.hw_rev = ATH11K_HW_IPQ5018_HW10,
63528348caeSBjoern A. Zeeb 		.name = "ipq5018 hw1.0",
63628348caeSBjoern A. Zeeb 		.fw = {
63728348caeSBjoern A. Zeeb 			.dir = "IPQ5018/hw1.0",
63828348caeSBjoern A. Zeeb 			.board_size = 256 * 1024,
63928348caeSBjoern A. Zeeb 			.cal_offset = 128 * 1024,
64028348caeSBjoern A. Zeeb 		},
64128348caeSBjoern A. Zeeb 		.max_radios = MAX_RADIOS_5018,
64228348caeSBjoern A. Zeeb 		.bdf_addr = 0x4BA00000,
64328348caeSBjoern A. Zeeb 		/* hal_desc_sz and hw ops are similar to qcn9074 */
64428348caeSBjoern A. Zeeb 		.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
64528348caeSBjoern A. Zeeb 		.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
64628348caeSBjoern A. Zeeb 		.ring_mask = &ath11k_hw_ring_mask_ipq8074,
64728348caeSBjoern A. Zeeb 		.credit_flow = false,
64828348caeSBjoern A. Zeeb 		.max_tx_ring = 1,
64928348caeSBjoern A. Zeeb 		.spectral = {
65028348caeSBjoern A. Zeeb 			.fft_sz = 2,
65128348caeSBjoern A. Zeeb 			.fft_pad_sz = 0,
65228348caeSBjoern A. Zeeb 			.summary_pad_sz = 16,
65328348caeSBjoern A. Zeeb 			.fft_hdr_len = 24,
65428348caeSBjoern A. Zeeb 			.max_fft_bins = 1024,
65528348caeSBjoern A. Zeeb 		},
65628348caeSBjoern A. Zeeb 		.internal_sleep_clock = false,
65728348caeSBjoern A. Zeeb 		.regs = &ipq5018_regs,
65828348caeSBjoern A. Zeeb 		.hw_ops = &ipq5018_ops,
65928348caeSBjoern A. Zeeb 		.host_ce_config = ath11k_host_ce_config_qcn9074,
66028348caeSBjoern A. Zeeb 		.ce_count = CE_CNT_5018,
66128348caeSBjoern A. Zeeb 		.target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
66228348caeSBjoern A. Zeeb 		.target_ce_count = TARGET_CE_CNT_5018,
66328348caeSBjoern A. Zeeb 		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018,
66428348caeSBjoern A. Zeeb 		.svc_to_ce_map_len = SVC_CE_MAP_LEN_5018,
66528348caeSBjoern A. Zeeb 		.ce_ie_addr = &ath11k_ce_ie_addr_ipq5018,
66628348caeSBjoern A. Zeeb 		.ce_remap = &ath11k_ce_remap_ipq5018,
66728348caeSBjoern A. Zeeb 		.rxdma1_enable = true,
66828348caeSBjoern A. Zeeb 		.num_rxmda_per_pdev = RXDMA_PER_PDEV_5018,
66928348caeSBjoern A. Zeeb 		.rx_mac_buf_ring = false,
67028348caeSBjoern A. Zeeb 		.vdev_start_delay = false,
67128348caeSBjoern A. Zeeb 		.htt_peer_map_v2 = true,
67228348caeSBjoern A. Zeeb 		.interface_modes = BIT(NL80211_IFTYPE_STATION) |
67328348caeSBjoern A. Zeeb 			BIT(NL80211_IFTYPE_AP) |
67428348caeSBjoern A. Zeeb 			BIT(NL80211_IFTYPE_MESH_POINT),
67528348caeSBjoern A. Zeeb 		.supports_monitor = false,
67628348caeSBjoern A. Zeeb 		.supports_sta_ps = false,
67728348caeSBjoern A. Zeeb 		.supports_shadow_regs = false,
67828348caeSBjoern A. Zeeb 		.fw_mem_mode = 0,
67928348caeSBjoern A. Zeeb 		.num_vdevs = 16 + 1,
68028348caeSBjoern A. Zeeb 		.num_peers = 512,
68128348caeSBjoern A. Zeeb 		.supports_regdb = false,
68228348caeSBjoern A. Zeeb 		.idle_ps = false,
68328348caeSBjoern A. Zeeb 		.supports_suspend = false,
68428348caeSBjoern A. Zeeb 		.hal_params = &ath11k_hw_hal_params_ipq8074,
68528348caeSBjoern A. Zeeb 		.single_pdev_only = false,
68628348caeSBjoern A. Zeeb 		.coldboot_cal_mm = true,
68728348caeSBjoern A. Zeeb 		.coldboot_cal_ftm = true,
68828348caeSBjoern A. Zeeb 		.cbcal_restart_fw = true,
68928348caeSBjoern A. Zeeb 		.fix_l1ss = true,
69028348caeSBjoern A. Zeeb 		.supports_dynamic_smps_6ghz = false,
69128348caeSBjoern A. Zeeb 		.alloc_cacheable_memory = true,
69228348caeSBjoern A. Zeeb 		.supports_rssi_stats = false,
69328348caeSBjoern A. Zeeb 		.fw_wmi_diag_event = false,
69428348caeSBjoern A. Zeeb 		.current_cc_support = false,
69528348caeSBjoern A. Zeeb 		.dbr_debug_support = true,
69628348caeSBjoern A. Zeeb 		.global_reset = false,
69728348caeSBjoern A. Zeeb 		.bios_sar_capa = NULL,
69828348caeSBjoern A. Zeeb 		.m3_fw_support = false,
69928348caeSBjoern A. Zeeb 		.fixed_bdf_addr = true,
70028348caeSBjoern A. Zeeb 		.fixed_mem_region = true,
70128348caeSBjoern A. Zeeb 		.static_window_map = false,
70228348caeSBjoern A. Zeeb 		.hybrid_bus_type = false,
70328348caeSBjoern A. Zeeb 		.fixed_fw_mem = false,
70428348caeSBjoern A. Zeeb 		.support_off_channel_tx = false,
70528348caeSBjoern A. Zeeb 		.supports_multi_bssid = false,
70628348caeSBjoern A. Zeeb 
70728348caeSBjoern A. Zeeb 		.sram_dump = {},
70828348caeSBjoern A. Zeeb 
70928348caeSBjoern A. Zeeb 		.tcl_ring_retry = true,
71028348caeSBjoern A. Zeeb 		.tx_ring_size = DP_TCL_DATA_RING_SIZE,
71128348caeSBjoern A. Zeeb 		.smp2p_wow_exit = false,
71228348caeSBjoern A. Zeeb 		.support_fw_mac_sequence = false,
713dd4f32aeSBjoern A. Zeeb 	},
714dd4f32aeSBjoern A. Zeeb };
715dd4f32aeSBjoern A. Zeeb 
ath11k_core_get_single_pdev(struct ath11k_base * ab)71628348caeSBjoern A. Zeeb static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab)
71728348caeSBjoern A. Zeeb {
71828348caeSBjoern A. Zeeb 	WARN_ON(!ab->hw_params.single_pdev_only);
71928348caeSBjoern A. Zeeb 
72028348caeSBjoern A. Zeeb 	return &ab->pdevs[0];
72128348caeSBjoern A. Zeeb }
72228348caeSBjoern A. Zeeb 
ath11k_fw_stats_pdevs_free(struct list_head * head)72328348caeSBjoern A. Zeeb void ath11k_fw_stats_pdevs_free(struct list_head *head)
72428348caeSBjoern A. Zeeb {
72528348caeSBjoern A. Zeeb 	struct ath11k_fw_stats_pdev *i, *tmp;
72628348caeSBjoern A. Zeeb 
72728348caeSBjoern A. Zeeb 	list_for_each_entry_safe(i, tmp, head, list) {
72828348caeSBjoern A. Zeeb 		list_del(&i->list);
72928348caeSBjoern A. Zeeb 		kfree(i);
73028348caeSBjoern A. Zeeb 	}
73128348caeSBjoern A. Zeeb }
73228348caeSBjoern A. Zeeb 
ath11k_fw_stats_vdevs_free(struct list_head * head)73328348caeSBjoern A. Zeeb void ath11k_fw_stats_vdevs_free(struct list_head *head)
73428348caeSBjoern A. Zeeb {
73528348caeSBjoern A. Zeeb 	struct ath11k_fw_stats_vdev *i, *tmp;
73628348caeSBjoern A. Zeeb 
73728348caeSBjoern A. Zeeb 	list_for_each_entry_safe(i, tmp, head, list) {
73828348caeSBjoern A. Zeeb 		list_del(&i->list);
73928348caeSBjoern A. Zeeb 		kfree(i);
74028348caeSBjoern A. Zeeb 	}
74128348caeSBjoern A. Zeeb }
74228348caeSBjoern A. Zeeb 
ath11k_fw_stats_bcn_free(struct list_head * head)74328348caeSBjoern A. Zeeb void ath11k_fw_stats_bcn_free(struct list_head *head)
74428348caeSBjoern A. Zeeb {
74528348caeSBjoern A. Zeeb 	struct ath11k_fw_stats_bcn *i, *tmp;
74628348caeSBjoern A. Zeeb 
74728348caeSBjoern A. Zeeb 	list_for_each_entry_safe(i, tmp, head, list) {
74828348caeSBjoern A. Zeeb 		list_del(&i->list);
74928348caeSBjoern A. Zeeb 		kfree(i);
75028348caeSBjoern A. Zeeb 	}
75128348caeSBjoern A. Zeeb }
75228348caeSBjoern A. Zeeb 
ath11k_fw_stats_init(struct ath11k * ar)75328348caeSBjoern A. Zeeb void ath11k_fw_stats_init(struct ath11k *ar)
75428348caeSBjoern A. Zeeb {
75528348caeSBjoern A. Zeeb 	INIT_LIST_HEAD(&ar->fw_stats.pdevs);
75628348caeSBjoern A. Zeeb 	INIT_LIST_HEAD(&ar->fw_stats.vdevs);
75728348caeSBjoern A. Zeeb 	INIT_LIST_HEAD(&ar->fw_stats.bcn);
75828348caeSBjoern A. Zeeb 
75928348caeSBjoern A. Zeeb 	init_completion(&ar->fw_stats_complete);
76028348caeSBjoern A. Zeeb }
76128348caeSBjoern A. Zeeb 
ath11k_fw_stats_free(struct ath11k_fw_stats * stats)76228348caeSBjoern A. Zeeb void ath11k_fw_stats_free(struct ath11k_fw_stats *stats)
76328348caeSBjoern A. Zeeb {
76428348caeSBjoern A. Zeeb 	ath11k_fw_stats_pdevs_free(&stats->pdevs);
76528348caeSBjoern A. Zeeb 	ath11k_fw_stats_vdevs_free(&stats->vdevs);
76628348caeSBjoern A. Zeeb 	ath11k_fw_stats_bcn_free(&stats->bcn);
76728348caeSBjoern A. Zeeb }
76828348caeSBjoern A. Zeeb 
ath11k_core_coldboot_cal_support(struct ath11k_base * ab)76928348caeSBjoern A. Zeeb bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab)
77028348caeSBjoern A. Zeeb {
77128348caeSBjoern A. Zeeb 	if (!ath11k_cold_boot_cal)
77228348caeSBjoern A. Zeeb 		return false;
77328348caeSBjoern A. Zeeb 
77428348caeSBjoern A. Zeeb 	if (ath11k_ftm_mode)
77528348caeSBjoern A. Zeeb 		return ab->hw_params.coldboot_cal_ftm;
77628348caeSBjoern A. Zeeb 
77728348caeSBjoern A. Zeeb 	else
77828348caeSBjoern A. Zeeb 		return ab->hw_params.coldboot_cal_mm;
77928348caeSBjoern A. Zeeb }
78028348caeSBjoern A. Zeeb 
ath11k_core_suspend(struct ath11k_base * ab)781dd4f32aeSBjoern A. Zeeb int ath11k_core_suspend(struct ath11k_base *ab)
782dd4f32aeSBjoern A. Zeeb {
783dd4f32aeSBjoern A. Zeeb 	int ret;
78428348caeSBjoern A. Zeeb 	struct ath11k_pdev *pdev;
78528348caeSBjoern A. Zeeb 	struct ath11k *ar;
786dd4f32aeSBjoern A. Zeeb 
787dd4f32aeSBjoern A. Zeeb 	if (!ab->hw_params.supports_suspend)
788dd4f32aeSBjoern A. Zeeb 		return -EOPNOTSUPP;
789dd4f32aeSBjoern A. Zeeb 
79028348caeSBjoern A. Zeeb 	/* so far single_pdev_only chips have supports_suspend as true
79128348caeSBjoern A. Zeeb 	 * and only the first pdev is valid.
792dd4f32aeSBjoern A. Zeeb 	 */
79328348caeSBjoern A. Zeeb 	pdev = ath11k_core_get_single_pdev(ab);
79428348caeSBjoern A. Zeeb 	ar = pdev->ar;
79528348caeSBjoern A. Zeeb 	if (!ar || ar->state != ATH11K_STATE_OFF)
79628348caeSBjoern A. Zeeb 		return 0;
797dd4f32aeSBjoern A. Zeeb 
798dd4f32aeSBjoern A. Zeeb 	ret = ath11k_dp_rx_pktlog_stop(ab, true);
799dd4f32aeSBjoern A. Zeeb 	if (ret) {
800dd4f32aeSBjoern A. Zeeb 		ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
801dd4f32aeSBjoern A. Zeeb 			    ret);
802dd4f32aeSBjoern A. Zeeb 		return ret;
803dd4f32aeSBjoern A. Zeeb 	}
804dd4f32aeSBjoern A. Zeeb 
80528348caeSBjoern A. Zeeb 	ret = ath11k_mac_wait_tx_complete(ar);
80628348caeSBjoern A. Zeeb 	if (ret) {
80728348caeSBjoern A. Zeeb 		ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
80828348caeSBjoern A. Zeeb 		return ret;
80928348caeSBjoern A. Zeeb 	}
81028348caeSBjoern A. Zeeb 
811dd4f32aeSBjoern A. Zeeb 	ret = ath11k_wow_enable(ab);
812dd4f32aeSBjoern A. Zeeb 	if (ret) {
813dd4f32aeSBjoern A. Zeeb 		ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret);
814dd4f32aeSBjoern A. Zeeb 		return ret;
815dd4f32aeSBjoern A. Zeeb 	}
816dd4f32aeSBjoern A. Zeeb 
817dd4f32aeSBjoern A. Zeeb 	ret = ath11k_dp_rx_pktlog_stop(ab, false);
818dd4f32aeSBjoern A. Zeeb 	if (ret) {
819dd4f32aeSBjoern A. Zeeb 		ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
820dd4f32aeSBjoern A. Zeeb 			    ret);
821dd4f32aeSBjoern A. Zeeb 		return ret;
822dd4f32aeSBjoern A. Zeeb 	}
823dd4f32aeSBjoern A. Zeeb 
824dd4f32aeSBjoern A. Zeeb 	ath11k_ce_stop_shadow_timers(ab);
825dd4f32aeSBjoern A. Zeeb 	ath11k_dp_stop_shadow_timers(ab);
826dd4f32aeSBjoern A. Zeeb 
827dd4f32aeSBjoern A. Zeeb 	ath11k_hif_irq_disable(ab);
828dd4f32aeSBjoern A. Zeeb 	ath11k_hif_ce_irq_disable(ab);
829dd4f32aeSBjoern A. Zeeb 
830dd4f32aeSBjoern A. Zeeb 	ret = ath11k_hif_suspend(ab);
831dd4f32aeSBjoern A. Zeeb 	if (ret) {
832dd4f32aeSBjoern A. Zeeb 		ath11k_warn(ab, "failed to suspend hif: %d\n", ret);
833dd4f32aeSBjoern A. Zeeb 		return ret;
834dd4f32aeSBjoern A. Zeeb 	}
835dd4f32aeSBjoern A. Zeeb 
836dd4f32aeSBjoern A. Zeeb 	return 0;
837dd4f32aeSBjoern A. Zeeb }
838dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_suspend);
839dd4f32aeSBjoern A. Zeeb 
ath11k_core_resume(struct ath11k_base * ab)840dd4f32aeSBjoern A. Zeeb int ath11k_core_resume(struct ath11k_base *ab)
841dd4f32aeSBjoern A. Zeeb {
842dd4f32aeSBjoern A. Zeeb 	int ret;
84328348caeSBjoern A. Zeeb 	struct ath11k_pdev *pdev;
84428348caeSBjoern A. Zeeb 	struct ath11k *ar;
845dd4f32aeSBjoern A. Zeeb 
846dd4f32aeSBjoern A. Zeeb 	if (!ab->hw_params.supports_suspend)
847dd4f32aeSBjoern A. Zeeb 		return -EOPNOTSUPP;
848dd4f32aeSBjoern A. Zeeb 
84928348caeSBjoern A. Zeeb 	/* so far signle_pdev_only chips have supports_suspend as true
85028348caeSBjoern A. Zeeb 	 * and only the first pdev is valid.
85128348caeSBjoern A. Zeeb 	 */
85228348caeSBjoern A. Zeeb 	pdev = ath11k_core_get_single_pdev(ab);
85328348caeSBjoern A. Zeeb 	ar = pdev->ar;
85428348caeSBjoern A. Zeeb 	if (!ar || ar->state != ATH11K_STATE_OFF)
85528348caeSBjoern A. Zeeb 		return 0;
85628348caeSBjoern A. Zeeb 
857dd4f32aeSBjoern A. Zeeb 	ret = ath11k_hif_resume(ab);
858dd4f32aeSBjoern A. Zeeb 	if (ret) {
859dd4f32aeSBjoern A. Zeeb 		ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret);
860dd4f32aeSBjoern A. Zeeb 		return ret;
861dd4f32aeSBjoern A. Zeeb 	}
862dd4f32aeSBjoern A. Zeeb 
863dd4f32aeSBjoern A. Zeeb 	ath11k_hif_ce_irq_enable(ab);
864dd4f32aeSBjoern A. Zeeb 	ath11k_hif_irq_enable(ab);
865dd4f32aeSBjoern A. Zeeb 
866dd4f32aeSBjoern A. Zeeb 	ret = ath11k_dp_rx_pktlog_start(ab);
867dd4f32aeSBjoern A. Zeeb 	if (ret) {
868dd4f32aeSBjoern A. Zeeb 		ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
869dd4f32aeSBjoern A. Zeeb 			    ret);
870dd4f32aeSBjoern A. Zeeb 		return ret;
871dd4f32aeSBjoern A. Zeeb 	}
872dd4f32aeSBjoern A. Zeeb 
873dd4f32aeSBjoern A. Zeeb 	ret = ath11k_wow_wakeup(ab);
874dd4f32aeSBjoern A. Zeeb 	if (ret) {
875dd4f32aeSBjoern A. Zeeb 		ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret);
876dd4f32aeSBjoern A. Zeeb 		return ret;
877dd4f32aeSBjoern A. Zeeb 	}
878dd4f32aeSBjoern A. Zeeb 
879dd4f32aeSBjoern A. Zeeb 	return 0;
880dd4f32aeSBjoern A. Zeeb }
881dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_resume);
882dd4f32aeSBjoern A. Zeeb 
ath11k_core_check_cc_code_bdfext(const struct dmi_header * hdr,void * data)88328348caeSBjoern A. Zeeb static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data)
88428348caeSBjoern A. Zeeb {
88528348caeSBjoern A. Zeeb 	struct ath11k_base *ab = data;
88628348caeSBjoern A. Zeeb 	const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC;
88728348caeSBjoern A. Zeeb #if defined(__linux__)
88828348caeSBjoern A. Zeeb 	struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr;
88928348caeSBjoern A. Zeeb #elif defined(__FreeBSD__)
89028348caeSBjoern A. Zeeb 	const struct ath11k_smbios_bdf *smbios = (const struct ath11k_smbios_bdf *)hdr;
89128348caeSBjoern A. Zeeb #endif
89228348caeSBjoern A. Zeeb 	ssize_t copied;
89328348caeSBjoern A. Zeeb 	size_t len;
89428348caeSBjoern A. Zeeb 	int i;
89528348caeSBjoern A. Zeeb 
89628348caeSBjoern A. Zeeb 	if (ab->qmi.target.bdf_ext[0] != '\0')
89728348caeSBjoern A. Zeeb 		return;
89828348caeSBjoern A. Zeeb 
89928348caeSBjoern A. Zeeb 	if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE)
90028348caeSBjoern A. Zeeb 		return;
90128348caeSBjoern A. Zeeb 
90228348caeSBjoern A. Zeeb 	if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) {
90328348caeSBjoern A. Zeeb 		ath11k_dbg(ab, ATH11K_DBG_BOOT,
90428348caeSBjoern A. Zeeb 			   "wrong smbios bdf ext type length (%d).\n",
90528348caeSBjoern A. Zeeb 			   hdr->length);
90628348caeSBjoern A. Zeeb 		return;
90728348caeSBjoern A. Zeeb 	}
90828348caeSBjoern A. Zeeb 
90928348caeSBjoern A. Zeeb 	spin_lock_bh(&ab->base_lock);
91028348caeSBjoern A. Zeeb 
91128348caeSBjoern A. Zeeb 	switch (smbios->country_code_flag) {
91228348caeSBjoern A. Zeeb 	case ATH11K_SMBIOS_CC_ISO:
91328348caeSBjoern A. Zeeb 		ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
91428348caeSBjoern A. Zeeb 		ab->new_alpha2[1] = smbios->cc_code & 0xff;
91528348caeSBjoern A. Zeeb 		ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n",
91628348caeSBjoern A. Zeeb 			   ab->new_alpha2[0], ab->new_alpha2[1]);
91728348caeSBjoern A. Zeeb 		break;
91828348caeSBjoern A. Zeeb 	case ATH11K_SMBIOS_CC_WW:
91928348caeSBjoern A. Zeeb 		ab->new_alpha2[0] = '0';
92028348caeSBjoern A. Zeeb 		ab->new_alpha2[1] = '0';
92128348caeSBjoern A. Zeeb 		ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n");
92228348caeSBjoern A. Zeeb 		break;
92328348caeSBjoern A. Zeeb 	default:
92428348caeSBjoern A. Zeeb 		ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n",
92528348caeSBjoern A. Zeeb 			   smbios->country_code_flag);
92628348caeSBjoern A. Zeeb 		break;
92728348caeSBjoern A. Zeeb 	}
92828348caeSBjoern A. Zeeb 
92928348caeSBjoern A. Zeeb 	spin_unlock_bh(&ab->base_lock);
93028348caeSBjoern A. Zeeb 
93128348caeSBjoern A. Zeeb 	if (!smbios->bdf_enabled) {
93228348caeSBjoern A. Zeeb 		ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n");
93328348caeSBjoern A. Zeeb 		return;
93428348caeSBjoern A. Zeeb 	}
93528348caeSBjoern A. Zeeb 
93628348caeSBjoern A. Zeeb 	/* Only one string exists (per spec) */
93728348caeSBjoern A. Zeeb 	if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) {
93828348caeSBjoern A. Zeeb 		ath11k_dbg(ab, ATH11K_DBG_BOOT,
93928348caeSBjoern A. Zeeb 			   "bdf variant magic does not match.\n");
94028348caeSBjoern A. Zeeb 		return;
94128348caeSBjoern A. Zeeb 	}
94228348caeSBjoern A. Zeeb 
94328348caeSBjoern A. Zeeb 	len = min_t(size_t,
94428348caeSBjoern A. Zeeb 		    strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext));
94528348caeSBjoern A. Zeeb 	for (i = 0; i < len; i++) {
94628348caeSBjoern A. Zeeb 		if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) {
94728348caeSBjoern A. Zeeb 			ath11k_dbg(ab, ATH11K_DBG_BOOT,
94828348caeSBjoern A. Zeeb 				   "bdf variant name contains non ascii chars.\n");
94928348caeSBjoern A. Zeeb 			return;
95028348caeSBjoern A. Zeeb 		}
95128348caeSBjoern A. Zeeb 	}
95228348caeSBjoern A. Zeeb 
95328348caeSBjoern A. Zeeb 	/* Copy extension name without magic prefix */
95428348caeSBjoern A. Zeeb 	copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic),
95528348caeSBjoern A. Zeeb 			 sizeof(ab->qmi.target.bdf_ext));
95628348caeSBjoern A. Zeeb 	if (copied < 0) {
95728348caeSBjoern A. Zeeb 		ath11k_dbg(ab, ATH11K_DBG_BOOT,
95828348caeSBjoern A. Zeeb 			   "bdf variant string is longer than the buffer can accommodate\n");
95928348caeSBjoern A. Zeeb 		return;
96028348caeSBjoern A. Zeeb 	}
96128348caeSBjoern A. Zeeb 
96228348caeSBjoern A. Zeeb 	ath11k_dbg(ab, ATH11K_DBG_BOOT,
96328348caeSBjoern A. Zeeb 		   "found and validated bdf variant smbios_type 0x%x bdf %s\n",
96428348caeSBjoern A. Zeeb 		   ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext);
96528348caeSBjoern A. Zeeb }
96628348caeSBjoern A. Zeeb 
ath11k_core_check_smbios(struct ath11k_base * ab)96728348caeSBjoern A. Zeeb int ath11k_core_check_smbios(struct ath11k_base *ab)
96828348caeSBjoern A. Zeeb {
96928348caeSBjoern A. Zeeb 	ab->qmi.target.bdf_ext[0] = '\0';
97028348caeSBjoern A. Zeeb 	dmi_walk(ath11k_core_check_cc_code_bdfext, ab);
97128348caeSBjoern A. Zeeb 
97228348caeSBjoern A. Zeeb 	if (ab->qmi.target.bdf_ext[0] == '\0')
97328348caeSBjoern A. Zeeb 		return -ENODATA;
97428348caeSBjoern A. Zeeb 
97528348caeSBjoern A. Zeeb 	return 0;
97628348caeSBjoern A. Zeeb }
97728348caeSBjoern A. Zeeb 
ath11k_core_check_dt(struct ath11k_base * ab)978dd4f32aeSBjoern A. Zeeb int ath11k_core_check_dt(struct ath11k_base *ab)
979dd4f32aeSBjoern A. Zeeb {
980dd4f32aeSBjoern A. Zeeb #if defined(__linux__)
981dd4f32aeSBjoern A. Zeeb 	size_t max_len = sizeof(ab->qmi.target.bdf_ext);
982dd4f32aeSBjoern A. Zeeb 	const char *variant = NULL;
983dd4f32aeSBjoern A. Zeeb 	struct device_node *node;
984dd4f32aeSBjoern A. Zeeb 
985dd4f32aeSBjoern A. Zeeb 	node = ab->dev->of_node;
986dd4f32aeSBjoern A. Zeeb 	if (!node)
987dd4f32aeSBjoern A. Zeeb 		return -ENOENT;
988dd4f32aeSBjoern A. Zeeb 
989dd4f32aeSBjoern A. Zeeb 	of_property_read_string(node, "qcom,ath11k-calibration-variant",
990dd4f32aeSBjoern A. Zeeb 				&variant);
991dd4f32aeSBjoern A. Zeeb 	if (!variant)
992dd4f32aeSBjoern A. Zeeb 		return -ENODATA;
993dd4f32aeSBjoern A. Zeeb 
994dd4f32aeSBjoern A. Zeeb 	if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0)
995dd4f32aeSBjoern A. Zeeb 		ath11k_dbg(ab, ATH11K_DBG_BOOT,
996dd4f32aeSBjoern A. Zeeb 			   "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
997dd4f32aeSBjoern A. Zeeb 			    variant);
998dd4f32aeSBjoern A. Zeeb 
999dd4f32aeSBjoern A. Zeeb 	return 0;
1000dd4f32aeSBjoern A. Zeeb #elif defined(__FreeBSD__)
1001dd4f32aeSBjoern A. Zeeb 	return -ENOENT;
1002dd4f32aeSBjoern A. Zeeb #endif
1003dd4f32aeSBjoern A. Zeeb }
1004dd4f32aeSBjoern A. Zeeb 
__ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len,bool with_variant,bool bus_type_mode)100528348caeSBjoern A. Zeeb static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
100628348caeSBjoern A. Zeeb 					   size_t name_len, bool with_variant,
100728348caeSBjoern A. Zeeb 					   bool bus_type_mode)
1008dd4f32aeSBjoern A. Zeeb {
1009dd4f32aeSBjoern A. Zeeb 	/* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
1010dd4f32aeSBjoern A. Zeeb 	char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 };
1011dd4f32aeSBjoern A. Zeeb 
101228348caeSBjoern A. Zeeb 	if (with_variant && ab->qmi.target.bdf_ext[0] != '\0')
1013dd4f32aeSBjoern A. Zeeb 		scnprintf(variant, sizeof(variant), ",variant=%s",
1014dd4f32aeSBjoern A. Zeeb 			  ab->qmi.target.bdf_ext);
1015dd4f32aeSBjoern A. Zeeb 
1016dd4f32aeSBjoern A. Zeeb 	switch (ab->id.bdf_search) {
1017dd4f32aeSBjoern A. Zeeb 	case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
101828348caeSBjoern A. Zeeb 		if (bus_type_mode)
101928348caeSBjoern A. Zeeb 			scnprintf(name, name_len,
102028348caeSBjoern A. Zeeb 				  "bus=%s",
102128348caeSBjoern A. Zeeb 				  ath11k_bus_str(ab->hif.bus));
102228348caeSBjoern A. Zeeb 		else
1023dd4f32aeSBjoern A. Zeeb 			scnprintf(name, name_len,
1024dd4f32aeSBjoern A. Zeeb 				  "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
1025dd4f32aeSBjoern A. Zeeb 				  ath11k_bus_str(ab->hif.bus),
1026dd4f32aeSBjoern A. Zeeb 				  ab->id.vendor, ab->id.device,
1027dd4f32aeSBjoern A. Zeeb 				  ab->id.subsystem_vendor,
1028dd4f32aeSBjoern A. Zeeb 				  ab->id.subsystem_device,
1029dd4f32aeSBjoern A. Zeeb 				  ab->qmi.target.chip_id,
1030dd4f32aeSBjoern A. Zeeb 				  ab->qmi.target.board_id,
1031dd4f32aeSBjoern A. Zeeb 				  variant);
1032dd4f32aeSBjoern A. Zeeb 		break;
1033dd4f32aeSBjoern A. Zeeb 	default:
1034dd4f32aeSBjoern A. Zeeb 		scnprintf(name, name_len,
1035dd4f32aeSBjoern A. Zeeb 			  "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s",
1036dd4f32aeSBjoern A. Zeeb 			  ath11k_bus_str(ab->hif.bus),
1037dd4f32aeSBjoern A. Zeeb 			  ab->qmi.target.chip_id,
1038dd4f32aeSBjoern A. Zeeb 			  ab->qmi.target.board_id, variant);
1039dd4f32aeSBjoern A. Zeeb 		break;
1040dd4f32aeSBjoern A. Zeeb 	}
1041dd4f32aeSBjoern A. Zeeb 
104228348caeSBjoern A. Zeeb 	ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name);
1043dd4f32aeSBjoern A. Zeeb 
1044dd4f32aeSBjoern A. Zeeb 	return 0;
1045dd4f32aeSBjoern A. Zeeb }
1046dd4f32aeSBjoern A. Zeeb 
ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len)104728348caeSBjoern A. Zeeb static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
104828348caeSBjoern A. Zeeb 					 size_t name_len)
104928348caeSBjoern A. Zeeb {
105028348caeSBjoern A. Zeeb 	return __ath11k_core_create_board_name(ab, name, name_len, true, false);
105128348caeSBjoern A. Zeeb }
105228348caeSBjoern A. Zeeb 
ath11k_core_create_fallback_board_name(struct ath11k_base * ab,char * name,size_t name_len)105328348caeSBjoern A. Zeeb static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
105428348caeSBjoern A. Zeeb 						  size_t name_len)
105528348caeSBjoern A. Zeeb {
105628348caeSBjoern A. Zeeb 	return __ath11k_core_create_board_name(ab, name, name_len, false, false);
105728348caeSBjoern A. Zeeb }
105828348caeSBjoern A. Zeeb 
ath11k_core_create_bus_type_board_name(struct ath11k_base * ab,char * name,size_t name_len)105928348caeSBjoern A. Zeeb static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name,
106028348caeSBjoern A. Zeeb 						  size_t name_len)
106128348caeSBjoern A. Zeeb {
106228348caeSBjoern A. Zeeb 	return __ath11k_core_create_board_name(ab, name, name_len, false, true);
106328348caeSBjoern A. Zeeb }
106428348caeSBjoern A. Zeeb 
ath11k_core_firmware_request(struct ath11k_base * ab,const char * file)1065dd4f32aeSBjoern A. Zeeb const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1066dd4f32aeSBjoern A. Zeeb 						    const char *file)
1067dd4f32aeSBjoern A. Zeeb {
1068dd4f32aeSBjoern A. Zeeb 	const struct firmware *fw;
1069dd4f32aeSBjoern A. Zeeb 	char path[100];
1070dd4f32aeSBjoern A. Zeeb 	int ret;
1071dd4f32aeSBjoern A. Zeeb 
1072dd4f32aeSBjoern A. Zeeb 	if (file == NULL)
1073dd4f32aeSBjoern A. Zeeb 		return ERR_PTR(-ENOENT);
1074dd4f32aeSBjoern A. Zeeb 
1075dd4f32aeSBjoern A. Zeeb 	ath11k_core_create_firmware_path(ab, file, path, sizeof(path));
1076dd4f32aeSBjoern A. Zeeb 
1077dd4f32aeSBjoern A. Zeeb 	ret = firmware_request_nowarn(&fw, path, ab->dev);
1078dd4f32aeSBjoern A. Zeeb 	if (ret)
1079dd4f32aeSBjoern A. Zeeb 		return ERR_PTR(ret);
1080dd4f32aeSBjoern A. Zeeb 
108128348caeSBjoern A. Zeeb 	ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n",
1082dd4f32aeSBjoern A. Zeeb 		   path, fw->size);
1083dd4f32aeSBjoern A. Zeeb 
1084dd4f32aeSBjoern A. Zeeb 	return fw;
1085dd4f32aeSBjoern A. Zeeb }
1086dd4f32aeSBjoern A. Zeeb 
ath11k_core_free_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1087dd4f32aeSBjoern A. Zeeb void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1088dd4f32aeSBjoern A. Zeeb {
1089dd4f32aeSBjoern A. Zeeb 	if (!IS_ERR(bd->fw))
1090dd4f32aeSBjoern A. Zeeb 		release_firmware(bd->fw);
1091dd4f32aeSBjoern A. Zeeb 
1092dd4f32aeSBjoern A. Zeeb 	memset(bd, 0, sizeof(*bd));
1093dd4f32aeSBjoern A. Zeeb }
1094dd4f32aeSBjoern A. Zeeb 
ath11k_core_parse_bd_ie_board(struct ath11k_base * ab,struct ath11k_board_data * bd,const void * buf,size_t buf_len,const char * boardname,int ie_id,int name_id,int data_id)1095dd4f32aeSBjoern A. Zeeb static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
1096dd4f32aeSBjoern A. Zeeb 					 struct ath11k_board_data *bd,
1097dd4f32aeSBjoern A. Zeeb #if defined(__linux__)
1098dd4f32aeSBjoern A. Zeeb 					 const void *buf, size_t buf_len,
1099dd4f32aeSBjoern A. Zeeb #elif defined(__FreeBSD__)
1100dd4f32aeSBjoern A. Zeeb 					 const u8 *buf, size_t buf_len,
1101dd4f32aeSBjoern A. Zeeb #endif
1102dd4f32aeSBjoern A. Zeeb 					 const char *boardname,
110328348caeSBjoern A. Zeeb 					 int ie_id,
110428348caeSBjoern A. Zeeb 					 int name_id,
110528348caeSBjoern A. Zeeb 					 int data_id)
1106dd4f32aeSBjoern A. Zeeb {
1107dd4f32aeSBjoern A. Zeeb 	const struct ath11k_fw_ie *hdr;
1108dd4f32aeSBjoern A. Zeeb 	bool name_match_found;
1109dd4f32aeSBjoern A. Zeeb 	int ret, board_ie_id;
1110dd4f32aeSBjoern A. Zeeb 	size_t board_ie_len;
1111dd4f32aeSBjoern A. Zeeb 	const void *board_ie_data;
1112dd4f32aeSBjoern A. Zeeb 
1113dd4f32aeSBjoern A. Zeeb 	name_match_found = false;
1114dd4f32aeSBjoern A. Zeeb 
111528348caeSBjoern A. Zeeb 	/* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */
1116dd4f32aeSBjoern A. Zeeb 	while (buf_len > sizeof(struct ath11k_fw_ie)) {
1117dd4f32aeSBjoern A. Zeeb #if defined(__linux__)
1118dd4f32aeSBjoern A. Zeeb 		hdr = buf;
1119dd4f32aeSBjoern A. Zeeb #elif defined(__FreeBSD__)
1120dd4f32aeSBjoern A. Zeeb 		hdr = (const struct ath11k_fw_ie *)buf;
1121dd4f32aeSBjoern A. Zeeb #endif
1122dd4f32aeSBjoern A. Zeeb 		board_ie_id = le32_to_cpu(hdr->id);
1123dd4f32aeSBjoern A. Zeeb 		board_ie_len = le32_to_cpu(hdr->len);
1124dd4f32aeSBjoern A. Zeeb 		board_ie_data = hdr->data;
1125dd4f32aeSBjoern A. Zeeb 
1126dd4f32aeSBjoern A. Zeeb 		buf_len -= sizeof(*hdr);
1127dd4f32aeSBjoern A. Zeeb 		buf += sizeof(*hdr);
1128dd4f32aeSBjoern A. Zeeb 
1129dd4f32aeSBjoern A. Zeeb 		if (buf_len < ALIGN(board_ie_len, 4)) {
113028348caeSBjoern A. Zeeb 			ath11k_err(ab, "invalid %s length: %zu < %zu\n",
113128348caeSBjoern A. Zeeb 				   ath11k_bd_ie_type_str(ie_id),
1132dd4f32aeSBjoern A. Zeeb 				   buf_len, ALIGN(board_ie_len, 4));
1133dd4f32aeSBjoern A. Zeeb 			ret = -EINVAL;
1134dd4f32aeSBjoern A. Zeeb 			goto out;
1135dd4f32aeSBjoern A. Zeeb 		}
1136dd4f32aeSBjoern A. Zeeb 
113728348caeSBjoern A. Zeeb 		if (board_ie_id == name_id) {
1138dd4f32aeSBjoern A. Zeeb 			ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "",
1139dd4f32aeSBjoern A. Zeeb 					board_ie_data, board_ie_len);
1140dd4f32aeSBjoern A. Zeeb 
1141dd4f32aeSBjoern A. Zeeb 			if (board_ie_len != strlen(boardname))
114228348caeSBjoern A. Zeeb 				goto next;
1143dd4f32aeSBjoern A. Zeeb 
1144dd4f32aeSBjoern A. Zeeb 			ret = memcmp(board_ie_data, boardname, strlen(boardname));
1145dd4f32aeSBjoern A. Zeeb 			if (ret)
114628348caeSBjoern A. Zeeb 				goto next;
1147dd4f32aeSBjoern A. Zeeb 
1148dd4f32aeSBjoern A. Zeeb 			name_match_found = true;
1149dd4f32aeSBjoern A. Zeeb 			ath11k_dbg(ab, ATH11K_DBG_BOOT,
115028348caeSBjoern A. Zeeb 				   "found match %s for name '%s'",
115128348caeSBjoern A. Zeeb 				   ath11k_bd_ie_type_str(ie_id),
1152dd4f32aeSBjoern A. Zeeb 				   boardname);
115328348caeSBjoern A. Zeeb 		} else if (board_ie_id == data_id) {
1154dd4f32aeSBjoern A. Zeeb 			if (!name_match_found)
1155dd4f32aeSBjoern A. Zeeb 				/* no match found */
115628348caeSBjoern A. Zeeb 				goto next;
1157dd4f32aeSBjoern A. Zeeb 
1158dd4f32aeSBjoern A. Zeeb 			ath11k_dbg(ab, ATH11K_DBG_BOOT,
115928348caeSBjoern A. Zeeb 				   "found %s for '%s'",
116028348caeSBjoern A. Zeeb 				   ath11k_bd_ie_type_str(ie_id),
116128348caeSBjoern A. Zeeb 				   boardname);
1162dd4f32aeSBjoern A. Zeeb 
1163dd4f32aeSBjoern A. Zeeb 			bd->data = board_ie_data;
1164dd4f32aeSBjoern A. Zeeb 			bd->len = board_ie_len;
1165dd4f32aeSBjoern A. Zeeb 
1166dd4f32aeSBjoern A. Zeeb 			ret = 0;
1167dd4f32aeSBjoern A. Zeeb 			goto out;
116828348caeSBjoern A. Zeeb 		} else {
116928348caeSBjoern A. Zeeb 			ath11k_warn(ab, "unknown %s id found: %d\n",
117028348caeSBjoern A. Zeeb 				    ath11k_bd_ie_type_str(ie_id),
1171dd4f32aeSBjoern A. Zeeb 				    board_ie_id);
1172dd4f32aeSBjoern A. Zeeb 		}
117328348caeSBjoern A. Zeeb next:
1174dd4f32aeSBjoern A. Zeeb 		/* jump over the padding */
1175dd4f32aeSBjoern A. Zeeb 		board_ie_len = ALIGN(board_ie_len, 4);
1176dd4f32aeSBjoern A. Zeeb 
1177dd4f32aeSBjoern A. Zeeb 		buf_len -= board_ie_len;
1178dd4f32aeSBjoern A. Zeeb 		buf += board_ie_len;
1179dd4f32aeSBjoern A. Zeeb 	}
1180dd4f32aeSBjoern A. Zeeb 
1181dd4f32aeSBjoern A. Zeeb 	/* no match found */
1182dd4f32aeSBjoern A. Zeeb 	ret = -ENOENT;
1183dd4f32aeSBjoern A. Zeeb 
1184dd4f32aeSBjoern A. Zeeb out:
1185dd4f32aeSBjoern A. Zeeb 	return ret;
1186dd4f32aeSBjoern A. Zeeb }
1187dd4f32aeSBjoern A. Zeeb 
ath11k_core_fetch_board_data_api_n(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * boardname,int ie_id_match,int name_id,int data_id)1188dd4f32aeSBjoern A. Zeeb static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
1189dd4f32aeSBjoern A. Zeeb 					      struct ath11k_board_data *bd,
119028348caeSBjoern A. Zeeb 					      const char *boardname,
119128348caeSBjoern A. Zeeb 					      int ie_id_match,
119228348caeSBjoern A. Zeeb 					      int name_id,
119328348caeSBjoern A. Zeeb 					      int data_id)
1194dd4f32aeSBjoern A. Zeeb {
1195dd4f32aeSBjoern A. Zeeb 	size_t len, magic_len;
1196dd4f32aeSBjoern A. Zeeb 	const u8 *data;
1197dd4f32aeSBjoern A. Zeeb 	char *filename, filepath[100];
1198dd4f32aeSBjoern A. Zeeb 	size_t ie_len;
1199dd4f32aeSBjoern A. Zeeb #if defined(__linux__)
1200dd4f32aeSBjoern A. Zeeb 	struct ath11k_fw_ie *hdr;
1201dd4f32aeSBjoern A. Zeeb #elif defined(__FreeBSD__)
1202dd4f32aeSBjoern A. Zeeb 	const struct ath11k_fw_ie *hdr;
1203dd4f32aeSBjoern A. Zeeb #endif
1204dd4f32aeSBjoern A. Zeeb 	int ret, ie_id;
1205dd4f32aeSBjoern A. Zeeb 
1206dd4f32aeSBjoern A. Zeeb 	filename = ATH11K_BOARD_API2_FILE;
1207dd4f32aeSBjoern A. Zeeb 
1208dd4f32aeSBjoern A. Zeeb 	if (!bd->fw)
1209dd4f32aeSBjoern A. Zeeb 		bd->fw = ath11k_core_firmware_request(ab, filename);
1210dd4f32aeSBjoern A. Zeeb 
1211dd4f32aeSBjoern A. Zeeb 	if (IS_ERR(bd->fw))
1212dd4f32aeSBjoern A. Zeeb 		return PTR_ERR(bd->fw);
1213dd4f32aeSBjoern A. Zeeb 
1214dd4f32aeSBjoern A. Zeeb 	data = bd->fw->data;
1215dd4f32aeSBjoern A. Zeeb 	len = bd->fw->size;
1216dd4f32aeSBjoern A. Zeeb 
1217dd4f32aeSBjoern A. Zeeb 	ath11k_core_create_firmware_path(ab, filename,
1218dd4f32aeSBjoern A. Zeeb 					 filepath, sizeof(filepath));
1219dd4f32aeSBjoern A. Zeeb 
1220dd4f32aeSBjoern A. Zeeb 	/* magic has extra null byte padded */
1221dd4f32aeSBjoern A. Zeeb 	magic_len = strlen(ATH11K_BOARD_MAGIC) + 1;
1222dd4f32aeSBjoern A. Zeeb 	if (len < magic_len) {
1223dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n",
1224dd4f32aeSBjoern A. Zeeb 			   filepath, len);
1225dd4f32aeSBjoern A. Zeeb 		ret = -EINVAL;
1226dd4f32aeSBjoern A. Zeeb 		goto err;
1227dd4f32aeSBjoern A. Zeeb 	}
1228dd4f32aeSBjoern A. Zeeb 
1229dd4f32aeSBjoern A. Zeeb 	if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) {
1230dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "found invalid board magic\n");
1231dd4f32aeSBjoern A. Zeeb 		ret = -EINVAL;
1232dd4f32aeSBjoern A. Zeeb 		goto err;
1233dd4f32aeSBjoern A. Zeeb 	}
1234dd4f32aeSBjoern A. Zeeb 
1235dd4f32aeSBjoern A. Zeeb 	/* magic is padded to 4 bytes */
1236dd4f32aeSBjoern A. Zeeb 	magic_len = ALIGN(magic_len, 4);
1237dd4f32aeSBjoern A. Zeeb 	if (len < magic_len) {
1238dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n",
1239dd4f32aeSBjoern A. Zeeb 			   filepath, len);
1240dd4f32aeSBjoern A. Zeeb 		ret = -EINVAL;
1241dd4f32aeSBjoern A. Zeeb 		goto err;
1242dd4f32aeSBjoern A. Zeeb 	}
1243dd4f32aeSBjoern A. Zeeb 
1244dd4f32aeSBjoern A. Zeeb 	data += magic_len;
1245dd4f32aeSBjoern A. Zeeb 	len -= magic_len;
1246dd4f32aeSBjoern A. Zeeb 
1247dd4f32aeSBjoern A. Zeeb 	while (len > sizeof(struct ath11k_fw_ie)) {
1248dd4f32aeSBjoern A. Zeeb #if defined(__linux__)
1249dd4f32aeSBjoern A. Zeeb 		hdr = (struct ath11k_fw_ie *)data;
1250dd4f32aeSBjoern A. Zeeb #elif defined(__FreeBSD__)
1251dd4f32aeSBjoern A. Zeeb 		hdr = (const struct ath11k_fw_ie *)data;
1252dd4f32aeSBjoern A. Zeeb #endif
1253dd4f32aeSBjoern A. Zeeb 		ie_id = le32_to_cpu(hdr->id);
1254dd4f32aeSBjoern A. Zeeb 		ie_len = le32_to_cpu(hdr->len);
1255dd4f32aeSBjoern A. Zeeb 
1256dd4f32aeSBjoern A. Zeeb 		len -= sizeof(*hdr);
1257dd4f32aeSBjoern A. Zeeb 		data = hdr->data;
1258dd4f32aeSBjoern A. Zeeb 
1259dd4f32aeSBjoern A. Zeeb 		if (len < ALIGN(ie_len, 4)) {
1260dd4f32aeSBjoern A. Zeeb 			ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1261dd4f32aeSBjoern A. Zeeb 				   ie_id, ie_len, len);
1262dd4f32aeSBjoern A. Zeeb 			ret = -EINVAL;
1263dd4f32aeSBjoern A. Zeeb 			goto err;
1264dd4f32aeSBjoern A. Zeeb 		}
1265dd4f32aeSBjoern A. Zeeb 
126628348caeSBjoern A. Zeeb 		if (ie_id == ie_id_match) {
1267dd4f32aeSBjoern A. Zeeb 			ret = ath11k_core_parse_bd_ie_board(ab, bd, data,
1268dd4f32aeSBjoern A. Zeeb 							    ie_len,
1269dd4f32aeSBjoern A. Zeeb 							    boardname,
127028348caeSBjoern A. Zeeb 							    ie_id_match,
127128348caeSBjoern A. Zeeb 							    name_id,
127228348caeSBjoern A. Zeeb 							    data_id);
1273dd4f32aeSBjoern A. Zeeb 			if (ret == -ENOENT)
1274dd4f32aeSBjoern A. Zeeb 				/* no match found, continue */
127528348caeSBjoern A. Zeeb 				goto next;
1276dd4f32aeSBjoern A. Zeeb 			else if (ret)
1277dd4f32aeSBjoern A. Zeeb 				/* there was an error, bail out */
1278dd4f32aeSBjoern A. Zeeb 				goto err;
1279dd4f32aeSBjoern A. Zeeb 			/* either found or error, so stop searching */
1280dd4f32aeSBjoern A. Zeeb 			goto out;
1281dd4f32aeSBjoern A. Zeeb 		}
128228348caeSBjoern A. Zeeb next:
1283dd4f32aeSBjoern A. Zeeb 		/* jump over the padding */
1284dd4f32aeSBjoern A. Zeeb 		ie_len = ALIGN(ie_len, 4);
1285dd4f32aeSBjoern A. Zeeb 
1286dd4f32aeSBjoern A. Zeeb 		len -= ie_len;
1287dd4f32aeSBjoern A. Zeeb 		data += ie_len;
1288dd4f32aeSBjoern A. Zeeb 	}
1289dd4f32aeSBjoern A. Zeeb 
1290dd4f32aeSBjoern A. Zeeb out:
1291dd4f32aeSBjoern A. Zeeb 	if (!bd->data || !bd->len) {
129228348caeSBjoern A. Zeeb 		ath11k_dbg(ab, ATH11K_DBG_BOOT,
129328348caeSBjoern A. Zeeb 			   "failed to fetch %s for %s from %s\n",
129428348caeSBjoern A. Zeeb 			   ath11k_bd_ie_type_str(ie_id_match),
1295dd4f32aeSBjoern A. Zeeb 			   boardname, filepath);
1296dd4f32aeSBjoern A. Zeeb 		ret = -ENODATA;
1297dd4f32aeSBjoern A. Zeeb 		goto err;
1298dd4f32aeSBjoern A. Zeeb 	}
1299dd4f32aeSBjoern A. Zeeb 
1300dd4f32aeSBjoern A. Zeeb 	return 0;
1301dd4f32aeSBjoern A. Zeeb 
1302dd4f32aeSBjoern A. Zeeb err:
1303dd4f32aeSBjoern A. Zeeb 	ath11k_core_free_bdf(ab, bd);
1304dd4f32aeSBjoern A. Zeeb 	return ret;
1305dd4f32aeSBjoern A. Zeeb }
1306dd4f32aeSBjoern A. Zeeb 
ath11k_core_fetch_board_data_api_1(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * name)1307dd4f32aeSBjoern A. Zeeb int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1308dd4f32aeSBjoern A. Zeeb 				       struct ath11k_board_data *bd,
1309dd4f32aeSBjoern A. Zeeb 				       const char *name)
1310dd4f32aeSBjoern A. Zeeb {
1311dd4f32aeSBjoern A. Zeeb 	bd->fw = ath11k_core_firmware_request(ab, name);
1312dd4f32aeSBjoern A. Zeeb 
1313dd4f32aeSBjoern A. Zeeb 	if (IS_ERR(bd->fw))
1314dd4f32aeSBjoern A. Zeeb 		return PTR_ERR(bd->fw);
1315dd4f32aeSBjoern A. Zeeb 
1316dd4f32aeSBjoern A. Zeeb 	bd->data = bd->fw->data;
1317dd4f32aeSBjoern A. Zeeb 	bd->len = bd->fw->size;
1318dd4f32aeSBjoern A. Zeeb 
1319dd4f32aeSBjoern A. Zeeb 	return 0;
1320dd4f32aeSBjoern A. Zeeb }
1321dd4f32aeSBjoern A. Zeeb 
1322dd4f32aeSBjoern A. Zeeb #define BOARD_NAME_SIZE 200
ath11k_core_fetch_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1323dd4f32aeSBjoern A. Zeeb int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1324dd4f32aeSBjoern A. Zeeb {
132528348caeSBjoern A. Zeeb 	char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE];
132628348caeSBjoern A. Zeeb 	char *filename, filepath[100];
1327dd4f32aeSBjoern A. Zeeb 	int ret;
1328dd4f32aeSBjoern A. Zeeb 
132928348caeSBjoern A. Zeeb 	filename = ATH11K_BOARD_API2_FILE;
133028348caeSBjoern A. Zeeb 
133128348caeSBjoern A. Zeeb 	ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname));
1332dd4f32aeSBjoern A. Zeeb 	if (ret) {
1333dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to create board name: %d", ret);
1334dd4f32aeSBjoern A. Zeeb 		return ret;
1335dd4f32aeSBjoern A. Zeeb 	}
1336dd4f32aeSBjoern A. Zeeb 
1337dd4f32aeSBjoern A. Zeeb 	ab->bd_api = 2;
133828348caeSBjoern A. Zeeb 	ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
133928348caeSBjoern A. Zeeb 						 ATH11K_BD_IE_BOARD,
134028348caeSBjoern A. Zeeb 						 ATH11K_BD_IE_BOARD_NAME,
134128348caeSBjoern A. Zeeb 						 ATH11K_BD_IE_BOARD_DATA);
134228348caeSBjoern A. Zeeb 	if (!ret)
134328348caeSBjoern A. Zeeb 		goto success;
134428348caeSBjoern A. Zeeb 
134528348caeSBjoern A. Zeeb 	ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname,
134628348caeSBjoern A. Zeeb 						     sizeof(fallback_boardname));
134728348caeSBjoern A. Zeeb 	if (ret) {
134828348caeSBjoern A. Zeeb 		ath11k_err(ab, "failed to create fallback board name: %d", ret);
134928348caeSBjoern A. Zeeb 		return ret;
135028348caeSBjoern A. Zeeb 	}
135128348caeSBjoern A. Zeeb 
135228348caeSBjoern A. Zeeb 	ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname,
135328348caeSBjoern A. Zeeb 						 ATH11K_BD_IE_BOARD,
135428348caeSBjoern A. Zeeb 						 ATH11K_BD_IE_BOARD_NAME,
135528348caeSBjoern A. Zeeb 						 ATH11K_BD_IE_BOARD_DATA);
1356dd4f32aeSBjoern A. Zeeb 	if (!ret)
1357dd4f32aeSBjoern A. Zeeb 		goto success;
1358dd4f32aeSBjoern A. Zeeb 
1359dd4f32aeSBjoern A. Zeeb 	ab->bd_api = 1;
1360dd4f32aeSBjoern A. Zeeb 	ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE);
1361dd4f32aeSBjoern A. Zeeb 	if (ret) {
136228348caeSBjoern A. Zeeb 		ath11k_core_create_firmware_path(ab, filename,
136328348caeSBjoern A. Zeeb 						 filepath, sizeof(filepath));
136428348caeSBjoern A. Zeeb 		ath11k_err(ab, "failed to fetch board data for %s from %s\n",
136528348caeSBjoern A. Zeeb 			   boardname, filepath);
136628348caeSBjoern A. Zeeb 		if (memcmp(boardname, fallback_boardname, strlen(boardname)))
136728348caeSBjoern A. Zeeb 			ath11k_err(ab, "failed to fetch board data for %s from %s\n",
136828348caeSBjoern A. Zeeb 				   fallback_boardname, filepath);
136928348caeSBjoern A. Zeeb 
137028348caeSBjoern A. Zeeb 		ath11k_err(ab, "failed to fetch board.bin from %s\n",
1371dd4f32aeSBjoern A. Zeeb 			   ab->hw_params.fw.dir);
1372dd4f32aeSBjoern A. Zeeb 		return ret;
1373dd4f32aeSBjoern A. Zeeb 	}
1374dd4f32aeSBjoern A. Zeeb 
1375dd4f32aeSBjoern A. Zeeb success:
1376dd4f32aeSBjoern A. Zeeb 	ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api);
1377dd4f32aeSBjoern A. Zeeb 	return 0;
1378dd4f32aeSBjoern A. Zeeb }
1379dd4f32aeSBjoern A. Zeeb 
ath11k_core_fetch_regdb(struct ath11k_base * ab,struct ath11k_board_data * bd)1380dd4f32aeSBjoern A. Zeeb int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
1381dd4f32aeSBjoern A. Zeeb {
138228348caeSBjoern A. Zeeb 	char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE];
1383dd4f32aeSBjoern A. Zeeb 	int ret;
1384dd4f32aeSBjoern A. Zeeb 
138528348caeSBjoern A. Zeeb 	ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
138628348caeSBjoern A. Zeeb 	if (ret) {
138728348caeSBjoern A. Zeeb 		ath11k_dbg(ab, ATH11K_DBG_BOOT,
138828348caeSBjoern A. Zeeb 			   "failed to create board name for regdb: %d", ret);
138928348caeSBjoern A. Zeeb 		goto exit;
139028348caeSBjoern A. Zeeb 	}
139128348caeSBjoern A. Zeeb 
139228348caeSBjoern A. Zeeb 	ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
139328348caeSBjoern A. Zeeb 						 ATH11K_BD_IE_REGDB,
139428348caeSBjoern A. Zeeb 						 ATH11K_BD_IE_REGDB_NAME,
139528348caeSBjoern A. Zeeb 						 ATH11K_BD_IE_REGDB_DATA);
139628348caeSBjoern A. Zeeb 	if (!ret)
139728348caeSBjoern A. Zeeb 		goto exit;
139828348caeSBjoern A. Zeeb 
139928348caeSBjoern A. Zeeb 	ret = ath11k_core_create_bus_type_board_name(ab, default_boardname,
140028348caeSBjoern A. Zeeb 						     BOARD_NAME_SIZE);
140128348caeSBjoern A. Zeeb 	if (ret) {
140228348caeSBjoern A. Zeeb 		ath11k_dbg(ab, ATH11K_DBG_BOOT,
140328348caeSBjoern A. Zeeb 			   "failed to create default board name for regdb: %d", ret);
140428348caeSBjoern A. Zeeb 		goto exit;
140528348caeSBjoern A. Zeeb 	}
140628348caeSBjoern A. Zeeb 
140728348caeSBjoern A. Zeeb 	ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname,
140828348caeSBjoern A. Zeeb 						 ATH11K_BD_IE_REGDB,
140928348caeSBjoern A. Zeeb 						 ATH11K_BD_IE_REGDB_NAME,
141028348caeSBjoern A. Zeeb 						 ATH11K_BD_IE_REGDB_DATA);
141128348caeSBjoern A. Zeeb 	if (!ret)
141228348caeSBjoern A. Zeeb 		goto exit;
141328348caeSBjoern A. Zeeb 
1414dd4f32aeSBjoern A. Zeeb 	ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
1415dd4f32aeSBjoern A. Zeeb 	if (ret)
1416dd4f32aeSBjoern A. Zeeb 		ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
1417dd4f32aeSBjoern A. Zeeb 			   ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir);
1418dd4f32aeSBjoern A. Zeeb 
141928348caeSBjoern A. Zeeb exit:
142028348caeSBjoern A. Zeeb 	if (!ret)
142128348caeSBjoern A. Zeeb 		ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n");
142228348caeSBjoern A. Zeeb 
1423dd4f32aeSBjoern A. Zeeb 	return ret;
1424dd4f32aeSBjoern A. Zeeb }
1425dd4f32aeSBjoern A. Zeeb 
ath11k_core_stop(struct ath11k_base * ab)1426dd4f32aeSBjoern A. Zeeb static void ath11k_core_stop(struct ath11k_base *ab)
1427dd4f32aeSBjoern A. Zeeb {
1428dd4f32aeSBjoern A. Zeeb 	if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
1429dd4f32aeSBjoern A. Zeeb 		ath11k_qmi_firmware_stop(ab);
1430dd4f32aeSBjoern A. Zeeb 
1431dd4f32aeSBjoern A. Zeeb 	ath11k_hif_stop(ab);
1432dd4f32aeSBjoern A. Zeeb 	ath11k_wmi_detach(ab);
1433dd4f32aeSBjoern A. Zeeb 	ath11k_dp_pdev_reo_cleanup(ab);
1434dd4f32aeSBjoern A. Zeeb 
1435dd4f32aeSBjoern A. Zeeb 	/* De-Init of components as needed */
1436dd4f32aeSBjoern A. Zeeb }
1437dd4f32aeSBjoern A. Zeeb 
ath11k_core_soc_create(struct ath11k_base * ab)1438dd4f32aeSBjoern A. Zeeb static int ath11k_core_soc_create(struct ath11k_base *ab)
1439dd4f32aeSBjoern A. Zeeb {
1440dd4f32aeSBjoern A. Zeeb 	int ret;
1441dd4f32aeSBjoern A. Zeeb 
144228348caeSBjoern A. Zeeb 	if (ath11k_ftm_mode) {
144328348caeSBjoern A. Zeeb 		ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM;
144428348caeSBjoern A. Zeeb 		ath11k_info(ab, "Booting in factory test mode\n");
144528348caeSBjoern A. Zeeb 	}
144628348caeSBjoern A. Zeeb 
1447dd4f32aeSBjoern A. Zeeb 	ret = ath11k_qmi_init_service(ab);
1448dd4f32aeSBjoern A. Zeeb 	if (ret) {
1449dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to initialize qmi :%d\n", ret);
1450dd4f32aeSBjoern A. Zeeb 		return ret;
1451dd4f32aeSBjoern A. Zeeb 	}
1452dd4f32aeSBjoern A. Zeeb 
1453dd4f32aeSBjoern A. Zeeb 	ret = ath11k_debugfs_soc_create(ab);
1454dd4f32aeSBjoern A. Zeeb 	if (ret) {
1455dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to create ath11k debugfs\n");
1456dd4f32aeSBjoern A. Zeeb 		goto err_qmi_deinit;
1457dd4f32aeSBjoern A. Zeeb 	}
1458dd4f32aeSBjoern A. Zeeb 
1459dd4f32aeSBjoern A. Zeeb 	ret = ath11k_hif_power_up(ab);
1460dd4f32aeSBjoern A. Zeeb 	if (ret) {
1461dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to power up :%d\n", ret);
1462dd4f32aeSBjoern A. Zeeb 		goto err_debugfs_reg;
1463dd4f32aeSBjoern A. Zeeb 	}
1464dd4f32aeSBjoern A. Zeeb 
1465dd4f32aeSBjoern A. Zeeb 	return 0;
1466dd4f32aeSBjoern A. Zeeb 
1467dd4f32aeSBjoern A. Zeeb err_debugfs_reg:
1468dd4f32aeSBjoern A. Zeeb 	ath11k_debugfs_soc_destroy(ab);
1469dd4f32aeSBjoern A. Zeeb err_qmi_deinit:
1470dd4f32aeSBjoern A. Zeeb 	ath11k_qmi_deinit_service(ab);
1471dd4f32aeSBjoern A. Zeeb 	return ret;
1472dd4f32aeSBjoern A. Zeeb }
1473dd4f32aeSBjoern A. Zeeb 
ath11k_core_soc_destroy(struct ath11k_base * ab)1474dd4f32aeSBjoern A. Zeeb static void ath11k_core_soc_destroy(struct ath11k_base *ab)
1475dd4f32aeSBjoern A. Zeeb {
1476dd4f32aeSBjoern A. Zeeb 	ath11k_debugfs_soc_destroy(ab);
1477dd4f32aeSBjoern A. Zeeb 	ath11k_dp_free(ab);
1478dd4f32aeSBjoern A. Zeeb 	ath11k_reg_free(ab);
1479dd4f32aeSBjoern A. Zeeb 	ath11k_qmi_deinit_service(ab);
1480dd4f32aeSBjoern A. Zeeb }
1481dd4f32aeSBjoern A. Zeeb 
ath11k_core_pdev_create(struct ath11k_base * ab)1482dd4f32aeSBjoern A. Zeeb static int ath11k_core_pdev_create(struct ath11k_base *ab)
1483dd4f32aeSBjoern A. Zeeb {
1484dd4f32aeSBjoern A. Zeeb 	int ret;
1485dd4f32aeSBjoern A. Zeeb 
1486dd4f32aeSBjoern A. Zeeb 	ret = ath11k_debugfs_pdev_create(ab);
1487dd4f32aeSBjoern A. Zeeb 	if (ret) {
1488dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret);
1489dd4f32aeSBjoern A. Zeeb 		return ret;
1490dd4f32aeSBjoern A. Zeeb 	}
1491dd4f32aeSBjoern A. Zeeb 
1492dd4f32aeSBjoern A. Zeeb 	ret = ath11k_dp_pdev_alloc(ab);
1493dd4f32aeSBjoern A. Zeeb 	if (ret) {
1494dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to attach DP pdev: %d\n", ret);
149528348caeSBjoern A. Zeeb 		goto err_pdev_debug;
149628348caeSBjoern A. Zeeb 	}
149728348caeSBjoern A. Zeeb 
149828348caeSBjoern A. Zeeb 	ret = ath11k_mac_register(ab);
149928348caeSBjoern A. Zeeb 	if (ret) {
150028348caeSBjoern A. Zeeb 		ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret);
150128348caeSBjoern A. Zeeb 		goto err_dp_pdev_free;
1502dd4f32aeSBjoern A. Zeeb 	}
1503dd4f32aeSBjoern A. Zeeb 
1504dd4f32aeSBjoern A. Zeeb 	ret = ath11k_thermal_register(ab);
1505dd4f32aeSBjoern A. Zeeb 	if (ret) {
1506dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "could not register thermal device: %d\n",
1507dd4f32aeSBjoern A. Zeeb 			   ret);
150828348caeSBjoern A. Zeeb 		goto err_mac_unregister;
1509dd4f32aeSBjoern A. Zeeb 	}
1510dd4f32aeSBjoern A. Zeeb 
1511dd4f32aeSBjoern A. Zeeb 	ret = ath11k_spectral_init(ab);
1512dd4f32aeSBjoern A. Zeeb 	if (ret) {
1513dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to init spectral %d\n", ret);
1514dd4f32aeSBjoern A. Zeeb 		goto err_thermal_unregister;
1515dd4f32aeSBjoern A. Zeeb 	}
1516dd4f32aeSBjoern A. Zeeb 
1517dd4f32aeSBjoern A. Zeeb 	return 0;
1518dd4f32aeSBjoern A. Zeeb 
1519dd4f32aeSBjoern A. Zeeb err_thermal_unregister:
1520dd4f32aeSBjoern A. Zeeb 	ath11k_thermal_unregister(ab);
1521dd4f32aeSBjoern A. Zeeb err_mac_unregister:
1522dd4f32aeSBjoern A. Zeeb 	ath11k_mac_unregister(ab);
152328348caeSBjoern A. Zeeb err_dp_pdev_free:
152428348caeSBjoern A. Zeeb 	ath11k_dp_pdev_free(ab);
1525dd4f32aeSBjoern A. Zeeb err_pdev_debug:
1526dd4f32aeSBjoern A. Zeeb 	ath11k_debugfs_pdev_destroy(ab);
1527dd4f32aeSBjoern A. Zeeb 
1528dd4f32aeSBjoern A. Zeeb 	return ret;
1529dd4f32aeSBjoern A. Zeeb }
1530dd4f32aeSBjoern A. Zeeb 
ath11k_core_pdev_destroy(struct ath11k_base * ab)1531dd4f32aeSBjoern A. Zeeb static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
1532dd4f32aeSBjoern A. Zeeb {
1533dd4f32aeSBjoern A. Zeeb 	ath11k_spectral_deinit(ab);
1534dd4f32aeSBjoern A. Zeeb 	ath11k_thermal_unregister(ab);
1535dd4f32aeSBjoern A. Zeeb 	ath11k_mac_unregister(ab);
1536dd4f32aeSBjoern A. Zeeb 	ath11k_hif_irq_disable(ab);
1537dd4f32aeSBjoern A. Zeeb 	ath11k_dp_pdev_free(ab);
1538dd4f32aeSBjoern A. Zeeb 	ath11k_debugfs_pdev_destroy(ab);
1539dd4f32aeSBjoern A. Zeeb }
1540dd4f32aeSBjoern A. Zeeb 
ath11k_core_start(struct ath11k_base * ab)154128348caeSBjoern A. Zeeb static int ath11k_core_start(struct ath11k_base *ab)
1542dd4f32aeSBjoern A. Zeeb {
1543dd4f32aeSBjoern A. Zeeb 	int ret;
1544dd4f32aeSBjoern A. Zeeb 
1545dd4f32aeSBjoern A. Zeeb 	ret = ath11k_wmi_attach(ab);
1546dd4f32aeSBjoern A. Zeeb 	if (ret) {
1547dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to attach wmi: %d\n", ret);
154828348caeSBjoern A. Zeeb 		return ret;
1549dd4f32aeSBjoern A. Zeeb 	}
1550dd4f32aeSBjoern A. Zeeb 
1551dd4f32aeSBjoern A. Zeeb 	ret = ath11k_htc_init(ab);
1552dd4f32aeSBjoern A. Zeeb 	if (ret) {
1553dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to init htc: %d\n", ret);
1554dd4f32aeSBjoern A. Zeeb 		goto err_wmi_detach;
1555dd4f32aeSBjoern A. Zeeb 	}
1556dd4f32aeSBjoern A. Zeeb 
1557dd4f32aeSBjoern A. Zeeb 	ret = ath11k_hif_start(ab);
1558dd4f32aeSBjoern A. Zeeb 	if (ret) {
1559dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to start HIF: %d\n", ret);
1560dd4f32aeSBjoern A. Zeeb 		goto err_wmi_detach;
1561dd4f32aeSBjoern A. Zeeb 	}
1562dd4f32aeSBjoern A. Zeeb 
1563dd4f32aeSBjoern A. Zeeb 	ret = ath11k_htc_wait_target(&ab->htc);
1564dd4f32aeSBjoern A. Zeeb 	if (ret) {
1565dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to connect to HTC: %d\n", ret);
1566dd4f32aeSBjoern A. Zeeb 		goto err_hif_stop;
1567dd4f32aeSBjoern A. Zeeb 	}
1568dd4f32aeSBjoern A. Zeeb 
1569dd4f32aeSBjoern A. Zeeb 	ret = ath11k_dp_htt_connect(&ab->dp);
1570dd4f32aeSBjoern A. Zeeb 	if (ret) {
1571dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to connect to HTT: %d\n", ret);
1572dd4f32aeSBjoern A. Zeeb 		goto err_hif_stop;
1573dd4f32aeSBjoern A. Zeeb 	}
1574dd4f32aeSBjoern A. Zeeb 
1575dd4f32aeSBjoern A. Zeeb 	ret = ath11k_wmi_connect(ab);
1576dd4f32aeSBjoern A. Zeeb 	if (ret) {
1577dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to connect wmi: %d\n", ret);
1578dd4f32aeSBjoern A. Zeeb 		goto err_hif_stop;
1579dd4f32aeSBjoern A. Zeeb 	}
1580dd4f32aeSBjoern A. Zeeb 
1581dd4f32aeSBjoern A. Zeeb 	ret = ath11k_htc_start(&ab->htc);
1582dd4f32aeSBjoern A. Zeeb 	if (ret) {
1583dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to start HTC: %d\n", ret);
1584dd4f32aeSBjoern A. Zeeb 		goto err_hif_stop;
1585dd4f32aeSBjoern A. Zeeb 	}
1586dd4f32aeSBjoern A. Zeeb 
1587dd4f32aeSBjoern A. Zeeb 	ret = ath11k_wmi_wait_for_service_ready(ab);
1588dd4f32aeSBjoern A. Zeeb 	if (ret) {
1589dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to receive wmi service ready event: %d\n",
1590dd4f32aeSBjoern A. Zeeb 			   ret);
1591dd4f32aeSBjoern A. Zeeb 		goto err_hif_stop;
1592dd4f32aeSBjoern A. Zeeb 	}
1593dd4f32aeSBjoern A. Zeeb 
1594dd4f32aeSBjoern A. Zeeb 	ret = ath11k_mac_allocate(ab);
1595dd4f32aeSBjoern A. Zeeb 	if (ret) {
1596dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n",
1597dd4f32aeSBjoern A. Zeeb 			   ret);
1598dd4f32aeSBjoern A. Zeeb 		goto err_hif_stop;
1599dd4f32aeSBjoern A. Zeeb 	}
1600dd4f32aeSBjoern A. Zeeb 
1601dd4f32aeSBjoern A. Zeeb 	ath11k_dp_pdev_pre_alloc(ab);
1602dd4f32aeSBjoern A. Zeeb 
1603dd4f32aeSBjoern A. Zeeb 	ret = ath11k_dp_pdev_reo_setup(ab);
1604dd4f32aeSBjoern A. Zeeb 	if (ret) {
1605dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret);
1606dd4f32aeSBjoern A. Zeeb 		goto err_mac_destroy;
1607dd4f32aeSBjoern A. Zeeb 	}
1608dd4f32aeSBjoern A. Zeeb 
1609dd4f32aeSBjoern A. Zeeb 	ret = ath11k_wmi_cmd_init(ab);
1610dd4f32aeSBjoern A. Zeeb 	if (ret) {
1611dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret);
1612dd4f32aeSBjoern A. Zeeb 		goto err_reo_cleanup;
1613dd4f32aeSBjoern A. Zeeb 	}
1614dd4f32aeSBjoern A. Zeeb 
1615dd4f32aeSBjoern A. Zeeb 	ret = ath11k_wmi_wait_for_unified_ready(ab);
1616dd4f32aeSBjoern A. Zeeb 	if (ret) {
1617dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to receive wmi unified ready event: %d\n",
1618dd4f32aeSBjoern A. Zeeb 			   ret);
1619dd4f32aeSBjoern A. Zeeb 		goto err_reo_cleanup;
1620dd4f32aeSBjoern A. Zeeb 	}
1621dd4f32aeSBjoern A. Zeeb 
1622dd4f32aeSBjoern A. Zeeb 	/* put hardware to DBS mode */
162328348caeSBjoern A. Zeeb 	if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) {
1624dd4f32aeSBjoern A. Zeeb 		ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS);
1625dd4f32aeSBjoern A. Zeeb 		if (ret) {
1626dd4f32aeSBjoern A. Zeeb 			ath11k_err(ab, "failed to send dbs mode: %d\n", ret);
1627dd4f32aeSBjoern A. Zeeb 			goto err_hif_stop;
1628dd4f32aeSBjoern A. Zeeb 		}
1629dd4f32aeSBjoern A. Zeeb 	}
1630dd4f32aeSBjoern A. Zeeb 
1631dd4f32aeSBjoern A. Zeeb 	ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab);
1632dd4f32aeSBjoern A. Zeeb 	if (ret) {
1633dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to send htt version request message: %d\n",
1634dd4f32aeSBjoern A. Zeeb 			   ret);
1635dd4f32aeSBjoern A. Zeeb 		goto err_reo_cleanup;
1636dd4f32aeSBjoern A. Zeeb 	}
1637dd4f32aeSBjoern A. Zeeb 
1638dd4f32aeSBjoern A. Zeeb 	return 0;
1639dd4f32aeSBjoern A. Zeeb 
1640dd4f32aeSBjoern A. Zeeb err_reo_cleanup:
1641dd4f32aeSBjoern A. Zeeb 	ath11k_dp_pdev_reo_cleanup(ab);
1642dd4f32aeSBjoern A. Zeeb err_mac_destroy:
1643dd4f32aeSBjoern A. Zeeb 	ath11k_mac_destroy(ab);
1644dd4f32aeSBjoern A. Zeeb err_hif_stop:
1645dd4f32aeSBjoern A. Zeeb 	ath11k_hif_stop(ab);
1646dd4f32aeSBjoern A. Zeeb err_wmi_detach:
1647dd4f32aeSBjoern A. Zeeb 	ath11k_wmi_detach(ab);
1648dd4f32aeSBjoern A. Zeeb 
1649dd4f32aeSBjoern A. Zeeb 	return ret;
1650dd4f32aeSBjoern A. Zeeb }
1651dd4f32aeSBjoern A. Zeeb 
ath11k_core_start_firmware(struct ath11k_base * ab,enum ath11k_firmware_mode mode)165228348caeSBjoern A. Zeeb static int ath11k_core_start_firmware(struct ath11k_base *ab,
165328348caeSBjoern A. Zeeb 				      enum ath11k_firmware_mode mode)
1654dd4f32aeSBjoern A. Zeeb {
165528348caeSBjoern A. Zeeb 	int ret;
1656dd4f32aeSBjoern A. Zeeb 
165728348caeSBjoern A. Zeeb 	ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
165828348caeSBjoern A. Zeeb 				    &ab->qmi.ce_cfg.shadow_reg_v2_len);
1659dd4f32aeSBjoern A. Zeeb 
166028348caeSBjoern A. Zeeb 	ret = ath11k_qmi_firmware_start(ab, mode);
166128348caeSBjoern A. Zeeb 	if (ret) {
166228348caeSBjoern A. Zeeb 		ath11k_err(ab, "failed to send firmware start: %d\n", ret);
1663dd4f32aeSBjoern A. Zeeb 		return ret;
1664dd4f32aeSBjoern A. Zeeb 	}
1665dd4f32aeSBjoern A. Zeeb 
1666dd4f32aeSBjoern A. Zeeb 	return ret;
1667dd4f32aeSBjoern A. Zeeb }
1668dd4f32aeSBjoern A. Zeeb 
ath11k_core_qmi_firmware_ready(struct ath11k_base * ab)1669dd4f32aeSBjoern A. Zeeb int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
1670dd4f32aeSBjoern A. Zeeb {
1671dd4f32aeSBjoern A. Zeeb 	int ret;
1672dd4f32aeSBjoern A. Zeeb 
167328348caeSBjoern A. Zeeb 	ret = ath11k_core_start_firmware(ab, ab->fw_mode);
167428348caeSBjoern A. Zeeb 	if (ret) {
167528348caeSBjoern A. Zeeb 		ath11k_err(ab, "failed to start firmware: %d\n", ret);
167628348caeSBjoern A. Zeeb 		return ret;
167728348caeSBjoern A. Zeeb 	}
167828348caeSBjoern A. Zeeb 
1679dd4f32aeSBjoern A. Zeeb 	ret = ath11k_ce_init_pipes(ab);
1680dd4f32aeSBjoern A. Zeeb 	if (ret) {
1681dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to initialize CE: %d\n", ret);
168228348caeSBjoern A. Zeeb 		goto err_firmware_stop;
1683dd4f32aeSBjoern A. Zeeb 	}
1684dd4f32aeSBjoern A. Zeeb 
1685dd4f32aeSBjoern A. Zeeb 	ret = ath11k_dp_alloc(ab);
1686dd4f32aeSBjoern A. Zeeb 	if (ret) {
1687dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to init DP: %d\n", ret);
168828348caeSBjoern A. Zeeb 		goto err_firmware_stop;
1689dd4f32aeSBjoern A. Zeeb 	}
1690dd4f32aeSBjoern A. Zeeb 
1691dd4f32aeSBjoern A. Zeeb 	switch (ath11k_crypto_mode) {
1692dd4f32aeSBjoern A. Zeeb 	case ATH11K_CRYPT_MODE_SW:
1693dd4f32aeSBjoern A. Zeeb 		set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1694dd4f32aeSBjoern A. Zeeb 		set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1695dd4f32aeSBjoern A. Zeeb 		break;
1696dd4f32aeSBjoern A. Zeeb 	case ATH11K_CRYPT_MODE_HW:
1697dd4f32aeSBjoern A. Zeeb 		clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1698dd4f32aeSBjoern A. Zeeb 		clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1699dd4f32aeSBjoern A. Zeeb 		break;
1700dd4f32aeSBjoern A. Zeeb 	default:
1701dd4f32aeSBjoern A. Zeeb 		ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode);
1702dd4f32aeSBjoern A. Zeeb 		return -EINVAL;
1703dd4f32aeSBjoern A. Zeeb 	}
1704dd4f32aeSBjoern A. Zeeb 
1705dd4f32aeSBjoern A. Zeeb 	if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW)
1706dd4f32aeSBjoern A. Zeeb 		set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1707dd4f32aeSBjoern A. Zeeb 
1708dd4f32aeSBjoern A. Zeeb 	mutex_lock(&ab->core_lock);
170928348caeSBjoern A. Zeeb 	ret = ath11k_core_start(ab);
1710dd4f32aeSBjoern A. Zeeb 	if (ret) {
1711dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to start core: %d\n", ret);
1712dd4f32aeSBjoern A. Zeeb 		goto err_dp_free;
1713dd4f32aeSBjoern A. Zeeb 	}
1714dd4f32aeSBjoern A. Zeeb 
1715dd4f32aeSBjoern A. Zeeb 	ret = ath11k_core_pdev_create(ab);
1716dd4f32aeSBjoern A. Zeeb 	if (ret) {
1717dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to create pdev core: %d\n", ret);
1718dd4f32aeSBjoern A. Zeeb 		goto err_core_stop;
1719dd4f32aeSBjoern A. Zeeb 	}
1720dd4f32aeSBjoern A. Zeeb 	ath11k_hif_irq_enable(ab);
1721dd4f32aeSBjoern A. Zeeb 	mutex_unlock(&ab->core_lock);
1722dd4f32aeSBjoern A. Zeeb 
1723dd4f32aeSBjoern A. Zeeb 	return 0;
1724dd4f32aeSBjoern A. Zeeb 
1725dd4f32aeSBjoern A. Zeeb err_core_stop:
1726dd4f32aeSBjoern A. Zeeb 	ath11k_core_stop(ab);
1727dd4f32aeSBjoern A. Zeeb 	ath11k_mac_destroy(ab);
1728dd4f32aeSBjoern A. Zeeb err_dp_free:
1729dd4f32aeSBjoern A. Zeeb 	ath11k_dp_free(ab);
1730dd4f32aeSBjoern A. Zeeb 	mutex_unlock(&ab->core_lock);
173128348caeSBjoern A. Zeeb err_firmware_stop:
173228348caeSBjoern A. Zeeb 	ath11k_qmi_firmware_stop(ab);
173328348caeSBjoern A. Zeeb 
1734dd4f32aeSBjoern A. Zeeb 	return ret;
1735dd4f32aeSBjoern A. Zeeb }
1736dd4f32aeSBjoern A. Zeeb 
ath11k_core_reconfigure_on_crash(struct ath11k_base * ab)1737dd4f32aeSBjoern A. Zeeb static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
1738dd4f32aeSBjoern A. Zeeb {
1739dd4f32aeSBjoern A. Zeeb 	int ret;
1740dd4f32aeSBjoern A. Zeeb 
1741dd4f32aeSBjoern A. Zeeb 	mutex_lock(&ab->core_lock);
1742dd4f32aeSBjoern A. Zeeb 	ath11k_thermal_unregister(ab);
1743dd4f32aeSBjoern A. Zeeb 	ath11k_hif_irq_disable(ab);
1744dd4f32aeSBjoern A. Zeeb 	ath11k_dp_pdev_free(ab);
1745dd4f32aeSBjoern A. Zeeb 	ath11k_spectral_deinit(ab);
1746dd4f32aeSBjoern A. Zeeb 	ath11k_hif_stop(ab);
1747dd4f32aeSBjoern A. Zeeb 	ath11k_wmi_detach(ab);
1748dd4f32aeSBjoern A. Zeeb 	ath11k_dp_pdev_reo_cleanup(ab);
1749dd4f32aeSBjoern A. Zeeb 	mutex_unlock(&ab->core_lock);
1750dd4f32aeSBjoern A. Zeeb 
1751dd4f32aeSBjoern A. Zeeb 	ath11k_dp_free(ab);
1752dd4f32aeSBjoern A. Zeeb 	ath11k_hal_srng_deinit(ab);
1753dd4f32aeSBjoern A. Zeeb 
1754dd4f32aeSBjoern A. Zeeb 	ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
1755dd4f32aeSBjoern A. Zeeb 
1756dd4f32aeSBjoern A. Zeeb 	ret = ath11k_hal_srng_init(ab);
1757dd4f32aeSBjoern A. Zeeb 	if (ret)
1758dd4f32aeSBjoern A. Zeeb 		return ret;
1759dd4f32aeSBjoern A. Zeeb 
1760dd4f32aeSBjoern A. Zeeb 	clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags);
1761dd4f32aeSBjoern A. Zeeb 
1762dd4f32aeSBjoern A. Zeeb 	ret = ath11k_core_qmi_firmware_ready(ab);
1763dd4f32aeSBjoern A. Zeeb 	if (ret)
1764dd4f32aeSBjoern A. Zeeb 		goto err_hal_srng_deinit;
1765dd4f32aeSBjoern A. Zeeb 
1766dd4f32aeSBjoern A. Zeeb 	clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags);
1767dd4f32aeSBjoern A. Zeeb 
1768dd4f32aeSBjoern A. Zeeb 	return 0;
1769dd4f32aeSBjoern A. Zeeb 
1770dd4f32aeSBjoern A. Zeeb err_hal_srng_deinit:
1771dd4f32aeSBjoern A. Zeeb 	ath11k_hal_srng_deinit(ab);
1772dd4f32aeSBjoern A. Zeeb 	return ret;
1773dd4f32aeSBjoern A. Zeeb }
1774dd4f32aeSBjoern A. Zeeb 
ath11k_core_halt(struct ath11k * ar)1775dd4f32aeSBjoern A. Zeeb void ath11k_core_halt(struct ath11k *ar)
1776dd4f32aeSBjoern A. Zeeb {
1777dd4f32aeSBjoern A. Zeeb 	struct ath11k_base *ab = ar->ab;
1778dd4f32aeSBjoern A. Zeeb 
1779dd4f32aeSBjoern A. Zeeb 	lockdep_assert_held(&ar->conf_mutex);
1780dd4f32aeSBjoern A. Zeeb 
1781dd4f32aeSBjoern A. Zeeb 	ar->num_created_vdevs = 0;
1782dd4f32aeSBjoern A. Zeeb 	ar->allocated_vdev_map = 0;
1783dd4f32aeSBjoern A. Zeeb 
1784dd4f32aeSBjoern A. Zeeb 	ath11k_mac_scan_finish(ar);
1785dd4f32aeSBjoern A. Zeeb 	ath11k_mac_peer_cleanup_all(ar);
1786dd4f32aeSBjoern A. Zeeb 	cancel_delayed_work_sync(&ar->scan.timeout);
1787dd4f32aeSBjoern A. Zeeb 	cancel_work_sync(&ar->regd_update_work);
1788dd4f32aeSBjoern A. Zeeb 	cancel_work_sync(&ab->update_11d_work);
1789dd4f32aeSBjoern A. Zeeb 
1790dd4f32aeSBjoern A. Zeeb 	rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
1791dd4f32aeSBjoern A. Zeeb 	synchronize_rcu();
1792dd4f32aeSBjoern A. Zeeb 	INIT_LIST_HEAD(&ar->arvifs);
1793dd4f32aeSBjoern A. Zeeb 	idr_init(&ar->txmgmt_idr);
1794dd4f32aeSBjoern A. Zeeb }
1795dd4f32aeSBjoern A. Zeeb 
ath11k_update_11d(struct work_struct * work)1796dd4f32aeSBjoern A. Zeeb static void ath11k_update_11d(struct work_struct *work)
1797dd4f32aeSBjoern A. Zeeb {
1798dd4f32aeSBjoern A. Zeeb 	struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
1799dd4f32aeSBjoern A. Zeeb 	struct ath11k *ar;
1800dd4f32aeSBjoern A. Zeeb 	struct ath11k_pdev *pdev;
1801dd4f32aeSBjoern A. Zeeb 	struct wmi_set_current_country_params set_current_param = {};
1802dd4f32aeSBjoern A. Zeeb 	int ret, i;
1803dd4f32aeSBjoern A. Zeeb 
1804dd4f32aeSBjoern A. Zeeb 	spin_lock_bh(&ab->base_lock);
1805dd4f32aeSBjoern A. Zeeb 	memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2);
1806dd4f32aeSBjoern A. Zeeb 	spin_unlock_bh(&ab->base_lock);
1807dd4f32aeSBjoern A. Zeeb 
1808dd4f32aeSBjoern A. Zeeb 	ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n",
1809dd4f32aeSBjoern A. Zeeb 		   set_current_param.alpha2[0],
1810dd4f32aeSBjoern A. Zeeb 		   set_current_param.alpha2[1]);
1811dd4f32aeSBjoern A. Zeeb 
1812dd4f32aeSBjoern A. Zeeb 	for (i = 0; i < ab->num_radios; i++) {
1813dd4f32aeSBjoern A. Zeeb 		pdev = &ab->pdevs[i];
1814dd4f32aeSBjoern A. Zeeb 		ar = pdev->ar;
1815dd4f32aeSBjoern A. Zeeb 
181628348caeSBjoern A. Zeeb 		memcpy(&ar->alpha2, &set_current_param.alpha2, 2);
1817dd4f32aeSBjoern A. Zeeb 		ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param);
1818dd4f32aeSBjoern A. Zeeb 		if (ret)
1819dd4f32aeSBjoern A. Zeeb 			ath11k_warn(ar->ab,
1820dd4f32aeSBjoern A. Zeeb 				    "pdev id %d failed set current country code: %d\n",
1821dd4f32aeSBjoern A. Zeeb 				    i, ret);
1822dd4f32aeSBjoern A. Zeeb 	}
1823dd4f32aeSBjoern A. Zeeb }
1824dd4f32aeSBjoern A. Zeeb 
ath11k_core_pre_reconfigure_recovery(struct ath11k_base * ab)182528348caeSBjoern A. Zeeb void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
1826dd4f32aeSBjoern A. Zeeb {
1827dd4f32aeSBjoern A. Zeeb 	struct ath11k *ar;
1828dd4f32aeSBjoern A. Zeeb 	struct ath11k_pdev *pdev;
182928348caeSBjoern A. Zeeb 	int i;
1830dd4f32aeSBjoern A. Zeeb 
1831dd4f32aeSBjoern A. Zeeb 	spin_lock_bh(&ab->base_lock);
1832dd4f32aeSBjoern A. Zeeb 	ab->stats.fw_crash_counter++;
1833dd4f32aeSBjoern A. Zeeb 	spin_unlock_bh(&ab->base_lock);
1834dd4f32aeSBjoern A. Zeeb 
1835dd4f32aeSBjoern A. Zeeb 	for (i = 0; i < ab->num_radios; i++) {
1836dd4f32aeSBjoern A. Zeeb 		pdev = &ab->pdevs[i];
1837dd4f32aeSBjoern A. Zeeb 		ar = pdev->ar;
183828348caeSBjoern A. Zeeb 		if (!ar || ar->state == ATH11K_STATE_OFF ||
183928348caeSBjoern A. Zeeb 		    ar->state == ATH11K_STATE_FTM)
1840dd4f32aeSBjoern A. Zeeb 			continue;
1841dd4f32aeSBjoern A. Zeeb 
1842dd4f32aeSBjoern A. Zeeb 		ieee80211_stop_queues(ar->hw);
1843dd4f32aeSBjoern A. Zeeb 		ath11k_mac_drain_tx(ar);
184428348caeSBjoern A. Zeeb 		ar->state_11d = ATH11K_11D_IDLE;
184528348caeSBjoern A. Zeeb 		complete(&ar->completed_11d_scan);
1846dd4f32aeSBjoern A. Zeeb 		complete(&ar->scan.started);
184728348caeSBjoern A. Zeeb 		complete_all(&ar->scan.completed);
184828348caeSBjoern A. Zeeb 		complete(&ar->scan.on_channel);
1849dd4f32aeSBjoern A. Zeeb 		complete(&ar->peer_assoc_done);
1850dd4f32aeSBjoern A. Zeeb 		complete(&ar->peer_delete_done);
1851dd4f32aeSBjoern A. Zeeb 		complete(&ar->install_key_done);
1852dd4f32aeSBjoern A. Zeeb 		complete(&ar->vdev_setup_done);
1853dd4f32aeSBjoern A. Zeeb 		complete(&ar->vdev_delete_done);
1854dd4f32aeSBjoern A. Zeeb 		complete(&ar->bss_survey_done);
1855dd4f32aeSBjoern A. Zeeb 		complete(&ar->thermal.wmi_sync);
1856dd4f32aeSBjoern A. Zeeb 
1857dd4f32aeSBjoern A. Zeeb 		wake_up(&ar->dp.tx_empty_waitq);
1858dd4f32aeSBjoern A. Zeeb 		idr_for_each(&ar->txmgmt_idr,
1859dd4f32aeSBjoern A. Zeeb 			     ath11k_mac_tx_mgmt_pending_free, ar);
1860dd4f32aeSBjoern A. Zeeb 		idr_destroy(&ar->txmgmt_idr);
1861dd4f32aeSBjoern A. Zeeb 		wake_up(&ar->txmgmt_empty_waitq);
186228348caeSBjoern A. Zeeb 
186328348caeSBjoern A. Zeeb 		ar->monitor_vdev_id = -1;
186428348caeSBjoern A. Zeeb 		clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags);
186528348caeSBjoern A. Zeeb 		clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);
1866dd4f32aeSBjoern A. Zeeb 	}
1867dd4f32aeSBjoern A. Zeeb 
1868dd4f32aeSBjoern A. Zeeb 	wake_up(&ab->wmi_ab.tx_credits_wq);
1869dd4f32aeSBjoern A. Zeeb 	wake_up(&ab->peer_mapping_wq);
1870dd4f32aeSBjoern A. Zeeb 
187128348caeSBjoern A. Zeeb 	reinit_completion(&ab->driver_recovery);
1872dd4f32aeSBjoern A. Zeeb }
1873dd4f32aeSBjoern A. Zeeb 
ath11k_core_post_reconfigure_recovery(struct ath11k_base * ab)187428348caeSBjoern A. Zeeb static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
187528348caeSBjoern A. Zeeb {
187628348caeSBjoern A. Zeeb 	struct ath11k *ar;
187728348caeSBjoern A. Zeeb 	struct ath11k_pdev *pdev;
187828348caeSBjoern A. Zeeb 	int i;
187928348caeSBjoern A. Zeeb 
1880dd4f32aeSBjoern A. Zeeb 	for (i = 0; i < ab->num_radios; i++) {
1881dd4f32aeSBjoern A. Zeeb 		pdev = &ab->pdevs[i];
1882dd4f32aeSBjoern A. Zeeb 		ar = pdev->ar;
1883dd4f32aeSBjoern A. Zeeb 		if (!ar || ar->state == ATH11K_STATE_OFF)
1884dd4f32aeSBjoern A. Zeeb 			continue;
1885dd4f32aeSBjoern A. Zeeb 
1886dd4f32aeSBjoern A. Zeeb 		mutex_lock(&ar->conf_mutex);
1887dd4f32aeSBjoern A. Zeeb 
1888dd4f32aeSBjoern A. Zeeb 		switch (ar->state) {
1889dd4f32aeSBjoern A. Zeeb 		case ATH11K_STATE_ON:
1890dd4f32aeSBjoern A. Zeeb 			ar->state = ATH11K_STATE_RESTARTING;
1891dd4f32aeSBjoern A. Zeeb 			ath11k_core_halt(ar);
1892dd4f32aeSBjoern A. Zeeb 			ieee80211_restart_hw(ar->hw);
1893dd4f32aeSBjoern A. Zeeb 			break;
1894dd4f32aeSBjoern A. Zeeb 		case ATH11K_STATE_OFF:
1895dd4f32aeSBjoern A. Zeeb 			ath11k_warn(ab,
1896dd4f32aeSBjoern A. Zeeb 				    "cannot restart radio %d that hasn't been started\n",
1897dd4f32aeSBjoern A. Zeeb 				    i);
1898dd4f32aeSBjoern A. Zeeb 			break;
1899dd4f32aeSBjoern A. Zeeb 		case ATH11K_STATE_RESTARTING:
1900dd4f32aeSBjoern A. Zeeb 			break;
1901dd4f32aeSBjoern A. Zeeb 		case ATH11K_STATE_RESTARTED:
1902dd4f32aeSBjoern A. Zeeb 			ar->state = ATH11K_STATE_WEDGED;
1903dd4f32aeSBjoern A. Zeeb 			fallthrough;
1904dd4f32aeSBjoern A. Zeeb 		case ATH11K_STATE_WEDGED:
1905dd4f32aeSBjoern A. Zeeb 			ath11k_warn(ab,
1906dd4f32aeSBjoern A. Zeeb 				    "device is wedged, will not restart radio %d\n", i);
1907dd4f32aeSBjoern A. Zeeb 			break;
190828348caeSBjoern A. Zeeb 		case ATH11K_STATE_FTM:
190928348caeSBjoern A. Zeeb 			ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
191028348caeSBjoern A. Zeeb 				   "fw mode reset done radio %d\n", i);
191128348caeSBjoern A. Zeeb 			break;
1912dd4f32aeSBjoern A. Zeeb 		}
191328348caeSBjoern A. Zeeb 
1914dd4f32aeSBjoern A. Zeeb 		mutex_unlock(&ar->conf_mutex);
1915dd4f32aeSBjoern A. Zeeb 	}
1916dd4f32aeSBjoern A. Zeeb 	complete(&ab->driver_recovery);
1917dd4f32aeSBjoern A. Zeeb }
1918dd4f32aeSBjoern A. Zeeb 
ath11k_core_restart(struct work_struct * work)191928348caeSBjoern A. Zeeb static void ath11k_core_restart(struct work_struct *work)
192028348caeSBjoern A. Zeeb {
192128348caeSBjoern A. Zeeb 	struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
192228348caeSBjoern A. Zeeb 	int ret;
192328348caeSBjoern A. Zeeb 
192428348caeSBjoern A. Zeeb 	ret = ath11k_core_reconfigure_on_crash(ab);
192528348caeSBjoern A. Zeeb 	if (ret) {
192628348caeSBjoern A. Zeeb 		ath11k_err(ab, "failed to reconfigure driver on crash recovery\n");
192728348caeSBjoern A. Zeeb 		return;
192828348caeSBjoern A. Zeeb 	}
192928348caeSBjoern A. Zeeb 
193028348caeSBjoern A. Zeeb 	if (ab->is_reset)
193128348caeSBjoern A. Zeeb 		complete_all(&ab->reconfigure_complete);
193228348caeSBjoern A. Zeeb 
193328348caeSBjoern A. Zeeb 	if (!ab->is_reset)
193428348caeSBjoern A. Zeeb 		ath11k_core_post_reconfigure_recovery(ab);
193528348caeSBjoern A. Zeeb }
193628348caeSBjoern A. Zeeb 
ath11k_core_reset(struct work_struct * work)193728348caeSBjoern A. Zeeb static void ath11k_core_reset(struct work_struct *work)
193828348caeSBjoern A. Zeeb {
193928348caeSBjoern A. Zeeb 	struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work);
194028348caeSBjoern A. Zeeb 	int reset_count, fail_cont_count;
194128348caeSBjoern A. Zeeb 	long time_left;
194228348caeSBjoern A. Zeeb 
194328348caeSBjoern A. Zeeb 	if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) {
194428348caeSBjoern A. Zeeb 		ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags);
194528348caeSBjoern A. Zeeb 		return;
194628348caeSBjoern A. Zeeb 	}
194728348caeSBjoern A. Zeeb 
194828348caeSBjoern A. Zeeb 	/* Sometimes the recovery will fail and then the next all recovery fail,
194928348caeSBjoern A. Zeeb 	 * this is to avoid infinite recovery since it can not recovery success.
195028348caeSBjoern A. Zeeb 	 */
195128348caeSBjoern A. Zeeb 	fail_cont_count = atomic_read(&ab->fail_cont_count);
195228348caeSBjoern A. Zeeb 
195328348caeSBjoern A. Zeeb 	if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL)
195428348caeSBjoern A. Zeeb 		return;
195528348caeSBjoern A. Zeeb 
195628348caeSBjoern A. Zeeb 	if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST &&
195728348caeSBjoern A. Zeeb 	    time_before(jiffies, ab->reset_fail_timeout))
195828348caeSBjoern A. Zeeb 		return;
195928348caeSBjoern A. Zeeb 
196028348caeSBjoern A. Zeeb 	reset_count = atomic_inc_return(&ab->reset_count);
196128348caeSBjoern A. Zeeb 
196228348caeSBjoern A. Zeeb 	if (reset_count > 1) {
196328348caeSBjoern A. Zeeb 		/* Sometimes it happened another reset worker before the previous one
196428348caeSBjoern A. Zeeb 		 * completed, then the second reset worker will destroy the previous one,
196528348caeSBjoern A. Zeeb 		 * thus below is to avoid that.
196628348caeSBjoern A. Zeeb 		 */
196728348caeSBjoern A. Zeeb 		ath11k_warn(ab, "already resetting count %d\n", reset_count);
196828348caeSBjoern A. Zeeb 
196928348caeSBjoern A. Zeeb 		reinit_completion(&ab->reset_complete);
197028348caeSBjoern A. Zeeb 		time_left = wait_for_completion_timeout(&ab->reset_complete,
197128348caeSBjoern A. Zeeb 							ATH11K_RESET_TIMEOUT_HZ);
197228348caeSBjoern A. Zeeb 
197328348caeSBjoern A. Zeeb 		if (time_left) {
197428348caeSBjoern A. Zeeb 			ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n");
197528348caeSBjoern A. Zeeb 			atomic_dec(&ab->reset_count);
197628348caeSBjoern A. Zeeb 			return;
197728348caeSBjoern A. Zeeb 		}
197828348caeSBjoern A. Zeeb 
197928348caeSBjoern A. Zeeb 		ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ;
198028348caeSBjoern A. Zeeb 		/* Record the continuous recovery fail count when recovery failed*/
198128348caeSBjoern A. Zeeb 		atomic_inc(&ab->fail_cont_count);
198228348caeSBjoern A. Zeeb 	}
198328348caeSBjoern A. Zeeb 
198428348caeSBjoern A. Zeeb 	ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n");
198528348caeSBjoern A. Zeeb 
198628348caeSBjoern A. Zeeb 	ab->is_reset = true;
198728348caeSBjoern A. Zeeb 	atomic_set(&ab->recovery_count, 0);
198828348caeSBjoern A. Zeeb 	reinit_completion(&ab->recovery_start);
198928348caeSBjoern A. Zeeb 	atomic_set(&ab->recovery_start_count, 0);
199028348caeSBjoern A. Zeeb 
199128348caeSBjoern A. Zeeb 	ath11k_core_pre_reconfigure_recovery(ab);
199228348caeSBjoern A. Zeeb 
199328348caeSBjoern A. Zeeb 	reinit_completion(&ab->reconfigure_complete);
199428348caeSBjoern A. Zeeb 	ath11k_core_post_reconfigure_recovery(ab);
199528348caeSBjoern A. Zeeb 
199628348caeSBjoern A. Zeeb 	ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n");
199728348caeSBjoern A. Zeeb 
199828348caeSBjoern A. Zeeb 	time_left = wait_for_completion_timeout(&ab->recovery_start,
199928348caeSBjoern A. Zeeb 						ATH11K_RECOVER_START_TIMEOUT_HZ);
200028348caeSBjoern A. Zeeb 
200128348caeSBjoern A. Zeeb 	ath11k_hif_power_down(ab);
200228348caeSBjoern A. Zeeb 	ath11k_hif_power_up(ab);
200328348caeSBjoern A. Zeeb 
200428348caeSBjoern A. Zeeb 	ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n");
200528348caeSBjoern A. Zeeb }
200628348caeSBjoern A. Zeeb 
ath11k_init_hw_params(struct ath11k_base * ab)2007dd4f32aeSBjoern A. Zeeb static int ath11k_init_hw_params(struct ath11k_base *ab)
2008dd4f32aeSBjoern A. Zeeb {
2009dd4f32aeSBjoern A. Zeeb 	const struct ath11k_hw_params *hw_params = NULL;
2010dd4f32aeSBjoern A. Zeeb 	int i;
2011dd4f32aeSBjoern A. Zeeb 
2012dd4f32aeSBjoern A. Zeeb 	for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) {
2013dd4f32aeSBjoern A. Zeeb 		hw_params = &ath11k_hw_params[i];
2014dd4f32aeSBjoern A. Zeeb 
2015dd4f32aeSBjoern A. Zeeb 		if (hw_params->hw_rev == ab->hw_rev)
2016dd4f32aeSBjoern A. Zeeb 			break;
2017dd4f32aeSBjoern A. Zeeb 	}
2018dd4f32aeSBjoern A. Zeeb 
2019dd4f32aeSBjoern A. Zeeb 	if (i == ARRAY_SIZE(ath11k_hw_params)) {
2020dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
2021dd4f32aeSBjoern A. Zeeb 		return -EINVAL;
2022dd4f32aeSBjoern A. Zeeb 	}
2023dd4f32aeSBjoern A. Zeeb 
2024dd4f32aeSBjoern A. Zeeb 	ab->hw_params = *hw_params;
2025dd4f32aeSBjoern A. Zeeb 
2026dd4f32aeSBjoern A. Zeeb 	ath11k_info(ab, "%s\n", ab->hw_params.name);
2027dd4f32aeSBjoern A. Zeeb 
2028dd4f32aeSBjoern A. Zeeb 	return 0;
2029dd4f32aeSBjoern A. Zeeb }
2030dd4f32aeSBjoern A. Zeeb 
ath11k_core_pre_init(struct ath11k_base * ab)2031dd4f32aeSBjoern A. Zeeb int ath11k_core_pre_init(struct ath11k_base *ab)
2032dd4f32aeSBjoern A. Zeeb {
2033dd4f32aeSBjoern A. Zeeb 	int ret;
2034dd4f32aeSBjoern A. Zeeb 
2035dd4f32aeSBjoern A. Zeeb 	ret = ath11k_init_hw_params(ab);
2036dd4f32aeSBjoern A. Zeeb 	if (ret) {
2037dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to get hw params: %d\n", ret);
2038dd4f32aeSBjoern A. Zeeb 		return ret;
2039dd4f32aeSBjoern A. Zeeb 	}
2040dd4f32aeSBjoern A. Zeeb 
2041dd4f32aeSBjoern A. Zeeb 	return 0;
2042dd4f32aeSBjoern A. Zeeb }
2043dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_pre_init);
2044dd4f32aeSBjoern A. Zeeb 
ath11k_core_init(struct ath11k_base * ab)2045dd4f32aeSBjoern A. Zeeb int ath11k_core_init(struct ath11k_base *ab)
2046dd4f32aeSBjoern A. Zeeb {
2047dd4f32aeSBjoern A. Zeeb 	int ret;
2048dd4f32aeSBjoern A. Zeeb 
2049dd4f32aeSBjoern A. Zeeb 	ret = ath11k_core_soc_create(ab);
2050dd4f32aeSBjoern A. Zeeb 	if (ret) {
2051dd4f32aeSBjoern A. Zeeb 		ath11k_err(ab, "failed to create soc core: %d\n", ret);
2052dd4f32aeSBjoern A. Zeeb 		return ret;
2053dd4f32aeSBjoern A. Zeeb 	}
2054dd4f32aeSBjoern A. Zeeb 
2055dd4f32aeSBjoern A. Zeeb 	return 0;
2056dd4f32aeSBjoern A. Zeeb }
2057dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_init);
2058dd4f32aeSBjoern A. Zeeb 
ath11k_core_deinit(struct ath11k_base * ab)2059dd4f32aeSBjoern A. Zeeb void ath11k_core_deinit(struct ath11k_base *ab)
2060dd4f32aeSBjoern A. Zeeb {
2061dd4f32aeSBjoern A. Zeeb 	mutex_lock(&ab->core_lock);
2062dd4f32aeSBjoern A. Zeeb 
2063dd4f32aeSBjoern A. Zeeb 	ath11k_core_pdev_destroy(ab);
2064dd4f32aeSBjoern A. Zeeb 	ath11k_core_stop(ab);
2065dd4f32aeSBjoern A. Zeeb 
2066dd4f32aeSBjoern A. Zeeb 	mutex_unlock(&ab->core_lock);
2067dd4f32aeSBjoern A. Zeeb 
2068dd4f32aeSBjoern A. Zeeb 	ath11k_hif_power_down(ab);
2069dd4f32aeSBjoern A. Zeeb 	ath11k_mac_destroy(ab);
2070dd4f32aeSBjoern A. Zeeb 	ath11k_core_soc_destroy(ab);
2071dd4f32aeSBjoern A. Zeeb }
2072dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_deinit);
2073dd4f32aeSBjoern A. Zeeb 
ath11k_core_free(struct ath11k_base * ab)2074dd4f32aeSBjoern A. Zeeb void ath11k_core_free(struct ath11k_base *ab)
2075dd4f32aeSBjoern A. Zeeb {
207628348caeSBjoern A. Zeeb 	destroy_workqueue(ab->workqueue_aux);
2077dd4f32aeSBjoern A. Zeeb 	destroy_workqueue(ab->workqueue);
2078dd4f32aeSBjoern A. Zeeb 
2079dd4f32aeSBjoern A. Zeeb 	kfree(ab);
2080dd4f32aeSBjoern A. Zeeb }
2081dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_free);
2082dd4f32aeSBjoern A. Zeeb 
ath11k_core_alloc(struct device * dev,size_t priv_size,enum ath11k_bus bus)2083dd4f32aeSBjoern A. Zeeb struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
208428348caeSBjoern A. Zeeb 				      enum ath11k_bus bus)
2085dd4f32aeSBjoern A. Zeeb {
2086dd4f32aeSBjoern A. Zeeb 	struct ath11k_base *ab;
2087dd4f32aeSBjoern A. Zeeb 
2088dd4f32aeSBjoern A. Zeeb 	ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
2089dd4f32aeSBjoern A. Zeeb 	if (!ab)
2090dd4f32aeSBjoern A. Zeeb 		return NULL;
2091dd4f32aeSBjoern A. Zeeb 
2092dd4f32aeSBjoern A. Zeeb 	init_completion(&ab->driver_recovery);
2093dd4f32aeSBjoern A. Zeeb 
2094dd4f32aeSBjoern A. Zeeb 	ab->workqueue = create_singlethread_workqueue("ath11k_wq");
2095dd4f32aeSBjoern A. Zeeb 	if (!ab->workqueue)
2096dd4f32aeSBjoern A. Zeeb 		goto err_sc_free;
2097dd4f32aeSBjoern A. Zeeb 
209828348caeSBjoern A. Zeeb 	ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq");
209928348caeSBjoern A. Zeeb 	if (!ab->workqueue_aux)
210028348caeSBjoern A. Zeeb 		goto err_free_wq;
210128348caeSBjoern A. Zeeb 
2102dd4f32aeSBjoern A. Zeeb 	mutex_init(&ab->core_lock);
210328348caeSBjoern A. Zeeb 	mutex_init(&ab->tbl_mtx_lock);
2104dd4f32aeSBjoern A. Zeeb 	spin_lock_init(&ab->base_lock);
2105dd4f32aeSBjoern A. Zeeb 	mutex_init(&ab->vdev_id_11d_lock);
210628348caeSBjoern A. Zeeb 	init_completion(&ab->reset_complete);
210728348caeSBjoern A. Zeeb 	init_completion(&ab->reconfigure_complete);
210828348caeSBjoern A. Zeeb 	init_completion(&ab->recovery_start);
2109dd4f32aeSBjoern A. Zeeb 
2110dd4f32aeSBjoern A. Zeeb 	INIT_LIST_HEAD(&ab->peers);
2111dd4f32aeSBjoern A. Zeeb 	init_waitqueue_head(&ab->peer_mapping_wq);
2112dd4f32aeSBjoern A. Zeeb 	init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
2113dd4f32aeSBjoern A. Zeeb 	init_waitqueue_head(&ab->qmi.cold_boot_waitq);
2114dd4f32aeSBjoern A. Zeeb 	INIT_WORK(&ab->restart_work, ath11k_core_restart);
2115dd4f32aeSBjoern A. Zeeb 	INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
211628348caeSBjoern A. Zeeb 	INIT_WORK(&ab->reset_work, ath11k_core_reset);
2117dd4f32aeSBjoern A. Zeeb 	timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
2118dd4f32aeSBjoern A. Zeeb 	init_completion(&ab->htc_suspend);
2119dd4f32aeSBjoern A. Zeeb 	init_completion(&ab->wow.wakeup_completed);
2120dd4f32aeSBjoern A. Zeeb 
2121dd4f32aeSBjoern A. Zeeb 	ab->dev = dev;
2122dd4f32aeSBjoern A. Zeeb 	ab->hif.bus = bus;
2123dd4f32aeSBjoern A. Zeeb 
2124dd4f32aeSBjoern A. Zeeb 	return ab;
2125dd4f32aeSBjoern A. Zeeb 
212628348caeSBjoern A. Zeeb err_free_wq:
212728348caeSBjoern A. Zeeb 	destroy_workqueue(ab->workqueue);
2128dd4f32aeSBjoern A. Zeeb err_sc_free:
2129dd4f32aeSBjoern A. Zeeb 	kfree(ab);
2130dd4f32aeSBjoern A. Zeeb 	return NULL;
2131dd4f32aeSBjoern A. Zeeb }
2132dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_alloc);
2133dd4f32aeSBjoern A. Zeeb 
2134dd4f32aeSBjoern A. Zeeb MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards.");
2135dd4f32aeSBjoern A. Zeeb MODULE_LICENSE("Dual BSD/GPL");
2136