1bfcc09ddSBjoern A. Zeeb /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2bfcc09ddSBjoern A. Zeeb /* 3bfcc09ddSBjoern A. Zeeb * Copyright (C) 2017 Intel Deutschland GmbH 49af1bba4SBjoern A. Zeeb * Copyright (C) 2018-2020, 2022 Intel Corporation 5bfcc09ddSBjoern A. Zeeb */ 6bfcc09ddSBjoern A. Zeeb #ifndef __iwl_context_info_file_h__ 7bfcc09ddSBjoern A. Zeeb #define __iwl_context_info_file_h__ 8bfcc09ddSBjoern A. Zeeb 9bfcc09ddSBjoern A. Zeeb /* maximmum number of DRAM map entries supported by FW */ 10bfcc09ddSBjoern A. Zeeb #define IWL_MAX_DRAM_ENTRY 64 11bfcc09ddSBjoern A. Zeeb #define CSR_CTXT_INFO_BA 0x40 12bfcc09ddSBjoern A. Zeeb 13bfcc09ddSBjoern A. Zeeb /** 14bfcc09ddSBjoern A. Zeeb * enum iwl_context_info_flags - Context information control flags 15bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting 16bfcc09ddSBjoern A. Zeeb * the init done for driver command that configures several system modes 17bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug 18bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump 19bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_RB_CB_SIZE: mask of the RBD Cyclic Buffer Size 20bfcc09ddSBjoern A. Zeeb * exponent, the actual size is 2**value, valid sizes are 8-2048. 21bfcc09ddSBjoern A. Zeeb * The value is four bits long. Maximum valid exponent is 12 22bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the 23bfcc09ddSBjoern A. Zeeb * default is short format - not supported by the driver) 24bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_RB_SIZE: RB size mask 25bfcc09ddSBjoern A. Zeeb * (values are IWL_CTXT_INFO_RB_SIZE_*K) 26bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size 27bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size 28bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size 29bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size 30bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size 31bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size 32bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size 33bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size 34bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size 35bfcc09ddSBjoern A. Zeeb * @IWL_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size 36bfcc09ddSBjoern A. Zeeb */ 37bfcc09ddSBjoern A. Zeeb enum iwl_context_info_flags { 38bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_AUTO_FUNC_INIT = 0x0001, 39bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_EARLY_DEBUG = 0x0002, 40bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_ENABLE_CDMP = 0x0004, 41bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_RB_CB_SIZE = 0x00f0, 42bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_TFD_FORMAT_LONG = 0x0100, 43bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_RB_SIZE = 0x1e00, 44bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_RB_SIZE_1K = 0x1, 45bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_RB_SIZE_2K = 0x2, 46bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_RB_SIZE_4K = 0x4, 47bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_RB_SIZE_8K = 0x8, 48bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_RB_SIZE_12K = 0x9, 49bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_RB_SIZE_16K = 0xa, 50bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_RB_SIZE_20K = 0xb, 51bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_RB_SIZE_24K = 0xc, 52bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_RB_SIZE_28K = 0xd, 53bfcc09ddSBjoern A. Zeeb IWL_CTXT_INFO_RB_SIZE_32K = 0xe, 54bfcc09ddSBjoern A. Zeeb }; 55bfcc09ddSBjoern A. Zeeb 56bfcc09ddSBjoern A. Zeeb /* 57bfcc09ddSBjoern A. Zeeb * struct iwl_context_info_version - version structure 58bfcc09ddSBjoern A. Zeeb * @mac_id: SKU and revision id 59bfcc09ddSBjoern A. Zeeb * @version: context information version id 60bfcc09ddSBjoern A. Zeeb * @size: the size of the context information in DWs 61bfcc09ddSBjoern A. Zeeb */ 62bfcc09ddSBjoern A. Zeeb struct iwl_context_info_version { 63bfcc09ddSBjoern A. Zeeb __le16 mac_id; 64bfcc09ddSBjoern A. Zeeb __le16 version; 65bfcc09ddSBjoern A. Zeeb __le16 size; 66bfcc09ddSBjoern A. Zeeb __le16 reserved; 67bfcc09ddSBjoern A. Zeeb } __packed; 68bfcc09ddSBjoern A. Zeeb 69bfcc09ddSBjoern A. Zeeb /* 70bfcc09ddSBjoern A. Zeeb * struct iwl_context_info_control - version structure 71bfcc09ddSBjoern A. Zeeb * @control_flags: context information flags see &enum iwl_context_info_flags 72bfcc09ddSBjoern A. Zeeb */ 73bfcc09ddSBjoern A. Zeeb struct iwl_context_info_control { 74bfcc09ddSBjoern A. Zeeb __le32 control_flags; 75bfcc09ddSBjoern A. Zeeb __le32 reserved; 76bfcc09ddSBjoern A. Zeeb } __packed; 77bfcc09ddSBjoern A. Zeeb 78bfcc09ddSBjoern A. Zeeb /* 79bfcc09ddSBjoern A. Zeeb * struct iwl_context_info_dram - images DRAM map 80bfcc09ddSBjoern A. Zeeb * each entry in the map represents a DRAM chunk of up to 32 KB 81bfcc09ddSBjoern A. Zeeb * @umac_img: UMAC image DRAM map 82bfcc09ddSBjoern A. Zeeb * @lmac_img: LMAC image DRAM map 83bfcc09ddSBjoern A. Zeeb * @virtual_img: paged image DRAM map 84bfcc09ddSBjoern A. Zeeb */ 85bfcc09ddSBjoern A. Zeeb struct iwl_context_info_dram { 86bfcc09ddSBjoern A. Zeeb __le64 umac_img[IWL_MAX_DRAM_ENTRY]; 87bfcc09ddSBjoern A. Zeeb __le64 lmac_img[IWL_MAX_DRAM_ENTRY]; 88bfcc09ddSBjoern A. Zeeb __le64 virtual_img[IWL_MAX_DRAM_ENTRY]; 89bfcc09ddSBjoern A. Zeeb } __packed; 90bfcc09ddSBjoern A. Zeeb 91bfcc09ddSBjoern A. Zeeb /* 92bfcc09ddSBjoern A. Zeeb * struct iwl_context_info_rbd_cfg - RBDs configuration 93bfcc09ddSBjoern A. Zeeb * @free_rbd_addr: default queue free RB CB base address 94bfcc09ddSBjoern A. Zeeb * @used_rbd_addr: default queue used RB CB base address 95bfcc09ddSBjoern A. Zeeb * @status_wr_ptr: default queue used RB status write pointer 96bfcc09ddSBjoern A. Zeeb */ 97bfcc09ddSBjoern A. Zeeb struct iwl_context_info_rbd_cfg { 98bfcc09ddSBjoern A. Zeeb __le64 free_rbd_addr; 99bfcc09ddSBjoern A. Zeeb __le64 used_rbd_addr; 100bfcc09ddSBjoern A. Zeeb __le64 status_wr_ptr; 101bfcc09ddSBjoern A. Zeeb } __packed; 102bfcc09ddSBjoern A. Zeeb 103bfcc09ddSBjoern A. Zeeb /* 104bfcc09ddSBjoern A. Zeeb * struct iwl_context_info_hcmd_cfg - command queue configuration 105bfcc09ddSBjoern A. Zeeb * @cmd_queue_addr: address of command queue 106bfcc09ddSBjoern A. Zeeb * @cmd_queue_size: number of entries 107bfcc09ddSBjoern A. Zeeb */ 108bfcc09ddSBjoern A. Zeeb struct iwl_context_info_hcmd_cfg { 109bfcc09ddSBjoern A. Zeeb __le64 cmd_queue_addr; 110bfcc09ddSBjoern A. Zeeb u8 cmd_queue_size; 111bfcc09ddSBjoern A. Zeeb u8 reserved[7]; 112bfcc09ddSBjoern A. Zeeb } __packed; 113bfcc09ddSBjoern A. Zeeb 114bfcc09ddSBjoern A. Zeeb /* 115bfcc09ddSBjoern A. Zeeb * struct iwl_context_info_dump_cfg - Core Dump configuration 116bfcc09ddSBjoern A. Zeeb * @core_dump_addr: core dump (debug DRAM address) start address 117bfcc09ddSBjoern A. Zeeb * @core_dump_size: size, in DWs 118bfcc09ddSBjoern A. Zeeb */ 119bfcc09ddSBjoern A. Zeeb struct iwl_context_info_dump_cfg { 120bfcc09ddSBjoern A. Zeeb __le64 core_dump_addr; 121bfcc09ddSBjoern A. Zeeb __le32 core_dump_size; 122bfcc09ddSBjoern A. Zeeb __le32 reserved; 123bfcc09ddSBjoern A. Zeeb } __packed; 124bfcc09ddSBjoern A. Zeeb 125bfcc09ddSBjoern A. Zeeb /* 126bfcc09ddSBjoern A. Zeeb * struct iwl_context_info_pnvm_cfg - platform NVM data configuration 127bfcc09ddSBjoern A. Zeeb * @platform_nvm_addr: Platform NVM data start address 128bfcc09ddSBjoern A. Zeeb * @platform_nvm_size: size in DWs 129bfcc09ddSBjoern A. Zeeb */ 130bfcc09ddSBjoern A. Zeeb struct iwl_context_info_pnvm_cfg { 131bfcc09ddSBjoern A. Zeeb __le64 platform_nvm_addr; 132bfcc09ddSBjoern A. Zeeb __le32 platform_nvm_size; 133bfcc09ddSBjoern A. Zeeb __le32 reserved; 134bfcc09ddSBjoern A. Zeeb } __packed; 135bfcc09ddSBjoern A. Zeeb 136bfcc09ddSBjoern A. Zeeb /* 137bfcc09ddSBjoern A. Zeeb * struct iwl_context_info_early_dbg_cfg - early debug configuration for 138bfcc09ddSBjoern A. Zeeb * dumping DRAM addresses 139bfcc09ddSBjoern A. Zeeb * @early_debug_addr: early debug start address 140bfcc09ddSBjoern A. Zeeb * @early_debug_size: size in DWs 141bfcc09ddSBjoern A. Zeeb */ 142bfcc09ddSBjoern A. Zeeb struct iwl_context_info_early_dbg_cfg { 143bfcc09ddSBjoern A. Zeeb __le64 early_debug_addr; 144bfcc09ddSBjoern A. Zeeb __le32 early_debug_size; 145bfcc09ddSBjoern A. Zeeb __le32 reserved; 146bfcc09ddSBjoern A. Zeeb } __packed; 147bfcc09ddSBjoern A. Zeeb 148bfcc09ddSBjoern A. Zeeb /* 149bfcc09ddSBjoern A. Zeeb * struct iwl_context_info - device INIT configuration 150bfcc09ddSBjoern A. Zeeb * @version: version information of context info and HW 151bfcc09ddSBjoern A. Zeeb * @control: control flags of FH configurations 152bfcc09ddSBjoern A. Zeeb * @rbd_cfg: default RX queue configuration 153bfcc09ddSBjoern A. Zeeb * @hcmd_cfg: command queue configuration 154bfcc09ddSBjoern A. Zeeb * @dump_cfg: core dump data 155bfcc09ddSBjoern A. Zeeb * @edbg_cfg: early debug configuration 156bfcc09ddSBjoern A. Zeeb * @pnvm_cfg: platform nvm configuration 157bfcc09ddSBjoern A. Zeeb * @dram: firmware image addresses in DRAM 158bfcc09ddSBjoern A. Zeeb */ 159bfcc09ddSBjoern A. Zeeb struct iwl_context_info { 160bfcc09ddSBjoern A. Zeeb struct iwl_context_info_version version; 161bfcc09ddSBjoern A. Zeeb struct iwl_context_info_control control; 162bfcc09ddSBjoern A. Zeeb __le64 reserved0; 163bfcc09ddSBjoern A. Zeeb struct iwl_context_info_rbd_cfg rbd_cfg; 164bfcc09ddSBjoern A. Zeeb struct iwl_context_info_hcmd_cfg hcmd_cfg; 165bfcc09ddSBjoern A. Zeeb __le32 reserved1[4]; 166bfcc09ddSBjoern A. Zeeb struct iwl_context_info_dump_cfg dump_cfg; 167bfcc09ddSBjoern A. Zeeb struct iwl_context_info_early_dbg_cfg edbg_cfg; 168bfcc09ddSBjoern A. Zeeb struct iwl_context_info_pnvm_cfg pnvm_cfg; 169bfcc09ddSBjoern A. Zeeb __le32 reserved2[16]; 170bfcc09ddSBjoern A. Zeeb struct iwl_context_info_dram dram; 171bfcc09ddSBjoern A. Zeeb __le32 reserved3[16]; 172bfcc09ddSBjoern A. Zeeb } __packed; 173bfcc09ddSBjoern A. Zeeb 174bfcc09ddSBjoern A. Zeeb int iwl_pcie_ctxt_info_init(struct iwl_trans *trans, const struct fw_img *fw); 175bfcc09ddSBjoern A. Zeeb void iwl_pcie_ctxt_info_free(struct iwl_trans *trans); 176bfcc09ddSBjoern A. Zeeb void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans); 177bfcc09ddSBjoern A. Zeeb int iwl_pcie_init_fw_sec(struct iwl_trans *trans, 178bfcc09ddSBjoern A. Zeeb const struct fw_img *fw, 179bfcc09ddSBjoern A. Zeeb struct iwl_context_info_dram *ctxt_dram); 1809af1bba4SBjoern A. Zeeb void *iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans, 1819af1bba4SBjoern A. Zeeb size_t size, 1829af1bba4SBjoern A. Zeeb dma_addr_t *phys); 183bfcc09ddSBjoern A. Zeeb int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans, 184bfcc09ddSBjoern A. Zeeb const void *data, u32 len, 185bfcc09ddSBjoern A. Zeeb struct iwl_dram_data *dram); 186bfcc09ddSBjoern A. Zeeb 187bfcc09ddSBjoern A. Zeeb #endif /* __iwl_context_info_file_h__ */ 188